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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 5f54c8b2d4fad95d1f8ecbe023ebe6038e6d3760 / . / arch / arm / mach-omap2 / cm.h
blob: e833984cc85e6fc8cfa1a4045351cee19a404449 [file] [log] [blame]
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]1/*
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]2 * OMAP2+ Clock Management prototypes
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]3 *
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600[diff] [blame]4 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
Rajendra Nayak9b472672009-12-08 18:24:50 -0700[diff] [blame]5 * Copyright (C) 2007-2009 Nokia Corporation
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]6 *
7 * Written by Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]13#ifndef __ARCH_ASM_MACH_OMAP2_CM_H
14#define __ARCH_ASM_MACH_OMAP2_CM_H
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]15
Benoit Coussond9e66252010-05-20 12:31:08 -0600[diff] [blame]16/*
17 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the
18 * PRCM to request that a module exit the inactive state in the case of
19 * OMAP2 & 3.
20 * In the case of OMAP4 this is the max duration in microseconds for the
21 * module to reach the functionnal state from an inactive state.
22 */
23#define MAX_MODULE_READY_TIME 2000
24
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600[diff] [blame]25# ifndef __ASSEMBLER__
Tero Kristo6c0afb52017-02-09 11:24:37 +0200[diff] [blame]26#include <linux/clk/ti.h>
Tero Kristo90129332017-05-31 18:00:00 +0300[diff] [blame]27
28#include "prcm-common.h"
29
30extern struct omap_domain_base cm_base;
31extern struct omap_domain_base cm2_base;
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600[diff] [blame]32extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
33# endif
34
Paul Walmsleyb8f15b72012-06-17 11:57:53 -0600[diff] [blame]35/*
36 * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for
37 * the PRCM to request that a module enter the inactive state in the
38 * case of OMAP2 & 3. In the case of OMAP4 this is the max duration
39 * in microseconds for the module to reach the inactive state from
40 * a functional state.
41 * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during
42 * kernel init.
43 */
44#define MAX_MODULE_DISABLE_TIME 5000
45
Paul Walmsley21325b252012-10-21 01:01:12 -0600[diff] [blame]46# ifndef __ASSEMBLER__
47
48/**
49 * struct cm_ll_data - fn ptrs to per-SoC CM function implementations
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]50 * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl
51 * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl
Tero Kristoa8ae5af2014-10-27 08:39:23 -0700[diff] [blame]52 * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl
Tero Kristo128603f2014-10-27 08:39:24 -0700[diff] [blame]53 * @module_enable: ptr to the SoC CM-specific module_enable impl
54 * @module_disable: ptr to the SoC CM-specific module_disable impl
Paul Walmsley21325b252012-10-21 01:01:12 -0600[diff] [blame]55 */
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]56struct cm_ll_data {
Tero Kristo6c0afb52017-02-09 11:24:37 +0200[diff] [blame]57 int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]58 u8 *idlest_reg_id);
Tero Kristo021b6ff2014-10-27 08:39:23 -0700[diff] [blame]59 int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
60 u8 idlest_shift);
Tero Kristoa8ae5af2014-10-27 08:39:23 -0700[diff] [blame]61 int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg,
62 u8 idlest_shift);
Tero Kristo128603f2014-10-27 08:39:24 -0700[diff] [blame]63 void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
64 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]65};
66
Tero Kristo6c0afb52017-02-09 11:24:37 +0200[diff] [blame]67extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600[diff] [blame]68 u8 *idlest_reg_id);
Tero Kristo021b6ff2014-10-27 08:39:23 -0700[diff] [blame]69int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
70 u8 idlest_shift);
Tero Kristoa8ae5af2014-10-27 08:39:23 -0700[diff] [blame]71int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg,
72 u8 idlest_shift);
Tero Kristo128603f2014-10-27 08:39:24 -0700[diff] [blame]73int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
74int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
Paul Walmsley21325b252012-10-21 01:01:12 -0600[diff] [blame]75extern int cm_register(struct cm_ll_data *cld);
76extern int cm_unregister(struct cm_ll_data *cld);
Tero Kristofe874142014-03-12 18:33:45 +0200[diff] [blame]77int omap_cm_init(void);
Tero Kristo5970ca22014-11-11 16:51:52 +0200[diff] [blame]78int omap2_cm_base_init(void);
Paul Walmsley21325b252012-10-21 01:01:12 -0600[diff] [blame]79
80# endif
81
Paul Walmsley69d88a02008-03-18 10:02:50 +0200[diff] [blame]82#endif