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Fabio Estevam3c1d6632018-04-22 21:02:11 -03001// SPDX-License-Identifier: GPL-2.0
2//
3// sgtl5000.c -- SGTL5000 ALSA SoC Audio driver
4//
5// Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08006
7#include <linux/module.h>
8#include <linux/moduleparam.h>
9#include <linux/init.h>
10#include <linux/delay.h>
11#include <linux/slab.h>
12#include <linux/pm.h>
13#include <linux/i2c.h>
14#include <linux/clk.h>
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +020015#include <linux/log2.h>
Fabio Estevame5d80e82013-05-04 15:39:34 -030016#include <linux/regmap.h>
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +080017#include <linux/regulator/driver.h>
18#include <linux/regulator/machine.h>
19#include <linux/regulator/consumer.h>
Shawn Guo58e49422011-07-22 00:28:51 +080020#include <linux/of_device.h>
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +080021#include <sound/core.h>
22#include <sound/tlv.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +080028
29#include "sgtl5000.h"
30
31#define SGTL5000_DAP_REG_OFFSET 0x0100
32#define SGTL5000_MAX_REG_OFFSET 0x013A
33
Wolfram Sang151798f2011-08-02 19:42:19 +020034/* default value of sgtl5000 registers */
Fabio Estevame5d80e82013-05-04 15:39:34 -030035static const struct reg_default sgtl5000_reg_defaults[] = {
Fabio Estevam29aa37c2014-05-26 10:34:20 -030036 { SGTL5000_CHIP_DIG_POWER, 0x0000 },
Fabio Estevame5d80e82013-05-04 15:39:34 -030037 { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
Fabio Estevam016fcab2013-07-04 20:01:02 -030038 { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
Fabio Estevam29aa37c2014-05-26 10:34:20 -030039 { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
Fabio Estevame5d80e82013-05-04 15:39:34 -030040 { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
41 { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
Fabio Estevam29aa37c2014-05-26 10:34:20 -030042 { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
Fabio Estevame5d80e82013-05-04 15:39:34 -030043 { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
44 { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
Fabio Estevam29aa37c2014-05-26 10:34:20 -030045 { SGTL5000_CHIP_REF_CTRL, 0x0000 },
46 { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
47 { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
Fabio Estevame5d80e82013-05-04 15:39:34 -030048 { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
Fabio Estevame5d80e82013-05-04 15:39:34 -030049 { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
Fabio Estevam29aa37c2014-05-26 10:34:20 -030050 { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
51 { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
52 { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
53 { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
54 { SGTL5000_DAP_CTRL, 0x0000 },
55 { SGTL5000_DAP_PEQ, 0x0000 },
Fabio Estevame5d80e82013-05-04 15:39:34 -030056 { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
57 { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
Fabio Estevam29aa37c2014-05-26 10:34:20 -030058 { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
Fabio Estevame5d80e82013-05-04 15:39:34 -030059 { SGTL5000_DAP_SURROUND, 0x0040 },
60 { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
61 { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
62 { SGTL5000_DAP_EQ_BASS_BAND2, 0x002f },
63 { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
64 { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
65 { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
Fabio Estevam29aa37c2014-05-26 10:34:20 -030066 { SGTL5000_DAP_MIX_CHAN, 0x0000 },
Fabio Estevame5d80e82013-05-04 15:39:34 -030067 { SGTL5000_DAP_AVC_CTRL, 0x0510 },
68 { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
69 { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
70 { SGTL5000_DAP_AVC_DECAY, 0x0050 },
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +080071};
72
Richard Leitnera7295262017-06-14 10:36:12 +020073/* AVC: Threshold dB -> register: pre-calculated values */
74static const u16 avc_thr_db2reg[97] = {
75 0x5168, 0x488E, 0x40AA, 0x39A1, 0x335D, 0x2DC7, 0x28CC, 0x245D, 0x2068,
76 0x1CE2, 0x19BE, 0x16F1, 0x1472, 0x1239, 0x103E, 0x0E7A, 0x0CE6, 0x0B7F,
77 0x0A3F, 0x0922, 0x0824, 0x0741, 0x0677, 0x05C3, 0x0522, 0x0493, 0x0414,
78 0x03A2, 0x033D, 0x02E3, 0x0293, 0x024B, 0x020B, 0x01D2, 0x019F, 0x0172,
79 0x014A, 0x0126, 0x0106, 0x00E9, 0x00D0, 0x00B9, 0x00A5, 0x0093, 0x0083,
80 0x0075, 0x0068, 0x005D, 0x0052, 0x0049, 0x0041, 0x003A, 0x0034, 0x002E,
81 0x0029, 0x0025, 0x0021, 0x001D, 0x001A, 0x0017, 0x0014, 0x0012, 0x0010,
82 0x000E, 0x000D, 0x000B, 0x000A, 0x0009, 0x0008, 0x0007, 0x0006, 0x0005,
83 0x0005, 0x0004, 0x0004, 0x0003, 0x0003, 0x0002, 0x0002, 0x0002, 0x0002,
84 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0000, 0x0000, 0x0000,
85 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000};
86
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +080087/* regulator supplies for sgtl5000, VDDD is an optional external supply */
88enum sgtl5000_regulator_supplies {
89 VDDA,
90 VDDIO,
91 VDDD,
92 SGTL5000_SUPPLY_NUM
93};
94
95/* vddd is optional supply */
96static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
97 "VDDA",
98 "VDDIO",
99 "VDDD"
100};
101
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800102#define LDO_VOLTAGE 1200000
Eric Nelson3d632cc2016-06-07 01:14:50 +0200103#define LINREG_VDDD ((1600 - LDO_VOLTAGE / 1000) / 50)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800104
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +0200105enum sgtl5000_micbias_resistor {
106 SGTL5000_MICBIAS_OFF = 0,
107 SGTL5000_MICBIAS_2K = 2,
108 SGTL5000_MICBIAS_4K = 4,
109 SGTL5000_MICBIAS_8K = 8,
110};
111
Fabio Estevam570c70a2017-04-05 11:32:34 -0300112enum {
113 I2S_LRCLK_STRENGTH_DISABLE,
114 I2S_LRCLK_STRENGTH_LOW,
115 I2S_LRCLK_STRENGTH_MEDIUM,
116 I2S_LRCLK_STRENGTH_HIGH,
117};
118
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800119/* sgtl5000 private structure in codec */
120struct sgtl5000_priv {
121 int sysclk; /* sysclk rate */
122 int master; /* i2s master or not */
123 int fmt; /* i2s data format */
124 struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
Eric Nelson940adb22016-06-07 01:14:48 +0200125 int num_supplies;
Fabio Estevame5d80e82013-05-04 15:39:34 -0300126 struct regmap *regmap;
Fabio Estevam9e13f342013-06-09 22:07:46 -0300127 struct clk *mclk;
Shawn Guo252e91f2013-12-13 14:43:02 +0800128 int revision;
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +0200129 u8 micbias_resistor;
Jean-Michel Hautbois87357792014-10-14 08:43:12 +0200130 u8 micbias_voltage;
Fabio Estevam570c70a2017-04-05 11:32:34 -0300131 u8 lrclk_strength;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800132};
133
134/*
135 * mic_bias power on/off share the same register bits with
136 * output impedance of mic bias, when power on mic bias, we
137 * need reclaim it to impedance value.
138 * 0x0 = Powered off
139 * 0x1 = 2Kohm
140 * 0x2 = 4Kohm
141 * 0x3 = 8Kohm
142 */
143static int mic_bias_event(struct snd_soc_dapm_widget *w,
144 struct snd_kcontrol *kcontrol, int event)
145{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000146 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
147 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +0200148
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800149 switch (event) {
150 case SND_SOC_DAPM_POST_PMU:
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +0200151 /* change mic bias resistor */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000152 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +0200153 SGTL5000_BIAS_R_MASK,
154 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800155 break;
156
157 case SND_SOC_DAPM_PRE_PMD:
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000158 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
Axel Lindc56c5a82011-10-19 11:00:42 +0800159 SGTL5000_BIAS_R_MASK, 0);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800160 break;
161 }
162 return 0;
163}
164
165/*
Zeng Zhaomingf0cdcf32012-03-30 00:13:02 +0800166 * As manual described, ADC/DAC only works when VAG powerup,
167 * So enabled VAG before ADC/DAC up.
168 * In power down case, we need wait 400ms when vag fully ramped down.
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800169 */
Zeng Zhaomingf0cdcf32012-03-30 00:13:02 +0800170static int power_vag_event(struct snd_soc_dapm_widget *w,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800171 struct snd_kcontrol *kcontrol, int event)
172{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000173 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
Lothar Waßmannf091f3f2013-07-31 16:44:29 +0200174 const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
175
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800176 switch (event) {
Marek Vasutdd4d2d62013-05-28 20:55:56 +0200177 case SND_SOC_DAPM_POST_PMU:
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000178 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800179 SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
Jean-Michel Hautboisc803cc22015-12-17 11:07:23 +0100180 msleep(400);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800181 break;
182
Marek Vasutdd4d2d62013-05-28 20:55:56 +0200183 case SND_SOC_DAPM_PRE_PMD:
Lothar Waßmannf091f3f2013-07-31 16:44:29 +0200184 /*
185 * Don't clear VAG_POWERUP, when both DAC and ADC are
186 * operational to prevent inadvertently starving the
187 * other one of them.
188 */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000189 if ((snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER) &
Lothar Waßmannf091f3f2013-07-31 16:44:29 +0200190 mask) != mask) {
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000191 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
Lothar Waßmannf091f3f2013-07-31 16:44:29 +0200192 SGTL5000_VAG_POWERUP, 0);
193 msleep(400);
194 }
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800195 break;
196 default:
197 break;
198 }
199
200 return 0;
201}
202
203/* input sources for ADC */
204static const char *adc_mux_text[] = {
205 "MIC_IN", "LINE_IN"
206};
207
Takashi Iwaic8ed6502014-02-18 10:16:31 +0100208static SOC_ENUM_SINGLE_DECL(adc_enum,
209 SGTL5000_CHIP_ANA_CTRL, 2,
210 adc_mux_text);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800211
212static const struct snd_kcontrol_new adc_mux =
213SOC_DAPM_ENUM("Capture Mux", adc_enum);
214
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100215/* input sources for headphone */
216static const char *hp_mux_text[] = {
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800217 "DAC", "LINE_IN"
218};
219
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100220static SOC_ENUM_SINGLE_DECL(hp_enum,
Takashi Iwaic8ed6502014-02-18 10:16:31 +0100221 SGTL5000_CHIP_ANA_CTRL, 6,
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100222 hp_mux_text);
223
224static const struct snd_kcontrol_new hp_mux =
225SOC_DAPM_ENUM("Headphone Mux", hp_enum);
226
227/* input sources for DAC */
228static const char *dac_mux_text[] = {
229 "ADC", "I2S", "Rsvrd", "DAP"
230};
231
232static SOC_ENUM_SINGLE_DECL(dac_enum,
233 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAC_SEL_SHIFT,
Takashi Iwaic8ed6502014-02-18 10:16:31 +0100234 dac_mux_text);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800235
236static const struct snd_kcontrol_new dac_mux =
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100237SOC_DAPM_ENUM("Digital Input Mux", dac_enum);
238
239/* input sources for DAP */
240static const char *dap_mux_text[] = {
241 "ADC", "I2S"
242};
243
244static SOC_ENUM_SINGLE_DECL(dap_enum,
245 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_SEL_SHIFT,
246 dap_mux_text);
247
248static const struct snd_kcontrol_new dap_mux =
249SOC_DAPM_ENUM("DAP Mux", dap_enum);
250
251/* input sources for DAP mix */
252static const char *dapmix_mux_text[] = {
253 "ADC", "I2S"
254};
255
256static SOC_ENUM_SINGLE_DECL(dapmix_enum,
257 SGTL5000_CHIP_SSS_CTRL, SGTL5000_DAP_MIX_SEL_SHIFT,
258 dapmix_mux_text);
259
260static const struct snd_kcontrol_new dapmix_mux =
261SOC_DAPM_ENUM("DAP MIX Mux", dapmix_enum);
262
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800263
264static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
265 SND_SOC_DAPM_INPUT("LINE_IN"),
266 SND_SOC_DAPM_INPUT("MIC_IN"),
267
268 SND_SOC_DAPM_OUTPUT("HP_OUT"),
269 SND_SOC_DAPM_OUTPUT("LINE_OUT"),
270
Mark Brown8fc8ec92012-03-28 20:51:43 +0100271 SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
272 mic_bias_event,
273 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800274
Zeng Zhaomingf0cdcf32012-03-30 00:13:02 +0800275 SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
276 SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800277
278 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100279 SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &hp_mux),
280 SND_SOC_DAPM_MUX("Digital Input Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
281 SND_SOC_DAPM_MUX("DAP Mux", SGTL5000_DAP_CTRL, 0, 0, &dap_mux),
282 SND_SOC_DAPM_MUX("DAP MIX Mux", SGTL5000_DAP_CTRL, 4, 0, &dapmix_mux),
283 SND_SOC_DAPM_MIXER("DAP", SGTL5000_CHIP_DIG_POWER, 4, 0, NULL, 0),
284
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800285
286 /* aif for i2s input */
287 SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
288 0, SGTL5000_CHIP_DIG_POWER,
289 0, 0),
290
291 /* aif for i2s output */
292 SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
293 0, SGTL5000_CHIP_DIG_POWER,
294 1, 0),
295
Zeng Zhaomingf0cdcf32012-03-30 00:13:02 +0800296 SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800297 SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
Marek Vasutdd4d2d62013-05-28 20:55:56 +0200298
299 SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
300 SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800301};
302
303/* routes for sgtl5000 */
Fabio Estevam89989632012-01-22 14:49:42 -0200304static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800305 {"Capture Mux", "LINE_IN", "LINE_IN"}, /* line_in --> adc_mux */
306 {"Capture Mux", "MIC_IN", "MIC_IN"}, /* mic_in --> adc_mux */
307
308 {"ADC", NULL, "Capture Mux"}, /* adc_mux --> adc */
309 {"AIFOUT", NULL, "ADC"}, /* adc --> i2s_out */
310
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100311 {"DAP Mux", "ADC", "ADC"}, /* adc --> DAP mux */
312 {"DAP Mux", NULL, "AIFIN"}, /* i2s --> DAP mux */
313 {"DAP", NULL, "DAP Mux"}, /* DAP mux --> dap */
314
315 {"DAP MIX Mux", "ADC", "ADC"}, /* adc --> DAP MIX mux */
316 {"DAP MIX Mux", NULL, "AIFIN"}, /* i2s --> DAP MIX mux */
317 {"DAP", NULL, "DAP MIX Mux"}, /* DAP MIX mux --> dap */
318
319 {"Digital Input Mux", "ADC", "ADC"}, /* adc --> audio mux */
320 {"Digital Input Mux", NULL, "AIFIN"}, /* i2s --> audio mux */
321 {"Digital Input Mux", NULL, "DAP"}, /* dap --> audio mux */
322 {"DAC", NULL, "Digital Input Mux"}, /* audio mux --> dac */
323
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800324 {"Headphone Mux", "DAC", "DAC"}, /* dac --> hp_mux */
325 {"LO", NULL, "DAC"}, /* dac --> line_out */
326
327 {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
328 {"HP", NULL, "Headphone Mux"}, /* hp_mux --> hp */
329
330 {"LINE_OUT", NULL, "LO"},
331 {"HP_OUT", NULL, "HP"},
332};
333
334/* custom function to fetch info of PCM playback volume */
335static int dac_info_volsw(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_info *uinfo)
337{
338 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
339 uinfo->count = 2;
340 uinfo->value.integer.min = 0;
341 uinfo->value.integer.max = 0xfc - 0x3c;
342 return 0;
343}
344
345/*
346 * custom function to get of PCM playback volume
347 *
348 * dac volume register
349 * 15-------------8-7--------------0
350 * | R channel vol | L channel vol |
351 * -------------------------------
352 *
353 * PCM volume with 0.5017 dB steps from 0 to -90 dB
354 *
355 * register values map to dB
356 * 0x3B and less = Reserved
357 * 0x3C = 0 dB
358 * 0x3D = -0.5 dB
359 * 0xF0 = -90 dB
360 * 0xFC and greater = Muted
361 *
362 * register value map to userspace value
363 *
364 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
365 * ------------------------------
366 * userspace value 0xc0 0
367 */
368static int dac_get_volsw(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000371 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800372 int reg;
373 int l;
374 int r;
375
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000376 reg = snd_soc_component_read32(component, SGTL5000_CHIP_DAC_VOL);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800377
378 /* get left channel volume */
379 l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
380
381 /* get right channel volume */
382 r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
383
384 /* make sure value fall in (0x3c,0xfc) */
385 l = clamp(l, 0x3c, 0xfc);
386 r = clamp(r, 0x3c, 0xfc);
387
388 /* invert it and map to userspace value */
389 l = 0xfc - l;
390 r = 0xfc - r;
391
392 ucontrol->value.integer.value[0] = l;
393 ucontrol->value.integer.value[1] = r;
394
395 return 0;
396}
397
398/*
399 * custom function to put of PCM playback volume
400 *
401 * dac volume register
402 * 15-------------8-7--------------0
403 * | R channel vol | L channel vol |
404 * -------------------------------
405 *
406 * PCM volume with 0.5017 dB steps from 0 to -90 dB
407 *
408 * register values map to dB
409 * 0x3B and less = Reserved
410 * 0x3C = 0 dB
411 * 0x3D = -0.5 dB
412 * 0xF0 = -90 dB
413 * 0xFC and greater = Muted
414 *
415 * userspace value map to register value
416 *
417 * userspace value 0xc0 0
418 * ------------------------------
419 * register value 0x3c(0dB) 0xf0(-90dB)0xfc
420 */
421static int dac_put_volsw(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000424 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800425 int reg;
426 int l;
427 int r;
428
429 l = ucontrol->value.integer.value[0];
430 r = ucontrol->value.integer.value[1];
431
432 /* make sure userspace volume fall in (0, 0xfc-0x3c) */
433 l = clamp(l, 0, 0xfc - 0x3c);
434 r = clamp(r, 0, 0xfc - 0x3c);
435
436 /* invert it, get the value can be set to register */
437 l = 0xfc - l;
438 r = 0xfc - r;
439
440 /* shift to get the register value */
441 reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
442 r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
443
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000444 snd_soc_component_write(component, SGTL5000_CHIP_DAC_VOL, reg);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800445
446 return 0;
447}
448
Richard Leitnera7295262017-06-14 10:36:12 +0200449/*
450 * custom function to get AVC threshold
451 *
452 * The threshold dB is calculated by rearranging the calculation from the
453 * avc_put_threshold function: register_value = 10^(dB/20) * 0.636 * 2^15 ==>
454 * dB = ( fls(register_value) - 14.347 ) * 6.02
455 *
Fabio Estevam51e78692018-04-22 21:02:10 -0300456 * As this calculation is expensive and the threshold dB values may not exceed
Richard Leitnera7295262017-06-14 10:36:12 +0200457 * 0 to 96 we use pre-calculated values.
458 */
459static int avc_get_threshold(struct snd_kcontrol *kcontrol,
460 struct snd_ctl_elem_value *ucontrol)
461{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000462 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Richard Leitnera7295262017-06-14 10:36:12 +0200463 int db, i;
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000464 u16 reg = snd_soc_component_read32(component, SGTL5000_DAP_AVC_THRESHOLD);
Richard Leitnera7295262017-06-14 10:36:12 +0200465
466 /* register value 0 => -96dB */
467 if (!reg) {
468 ucontrol->value.integer.value[0] = 96;
469 ucontrol->value.integer.value[1] = 96;
470 return 0;
471 }
472
473 /* get dB from register value (rounded down) */
474 for (i = 0; avc_thr_db2reg[i] > reg; i++)
475 ;
476 db = i;
477
478 ucontrol->value.integer.value[0] = db;
479 ucontrol->value.integer.value[1] = db;
480
481 return 0;
482}
483
484/*
485 * custom function to put AVC threshold
486 *
487 * The register value is calculated by following formula:
488 * register_value = 10^(dB/20) * 0.636 * 2^15
Fabio Estevam51e78692018-04-22 21:02:10 -0300489 * As this calculation is expensive and the threshold dB values may not exceed
Richard Leitnera7295262017-06-14 10:36:12 +0200490 * 0 to 96 we use pre-calculated values.
491 */
492static int avc_put_threshold(struct snd_kcontrol *kcontrol,
493 struct snd_ctl_elem_value *ucontrol)
494{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000495 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
Richard Leitnera7295262017-06-14 10:36:12 +0200496 int db;
497 u16 reg;
498
499 db = (int)ucontrol->value.integer.value[0];
500 if (db < 0 || db > 96)
501 return -EINVAL;
502 reg = avc_thr_db2reg[db];
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000503 snd_soc_component_write(component, SGTL5000_DAP_AVC_THRESHOLD, reg);
Richard Leitnera7295262017-06-14 10:36:12 +0200504
505 return 0;
506}
507
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800508static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
509
510/* tlv for mic gain, 0db 20db 30db 40db */
Lars-Peter Clausen53eb1ca2015-08-02 17:19:53 +0200511static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800512 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
Lars-Peter Clausen53eb1ca2015-08-02 17:19:53 +0200513 1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
514);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800515
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100516/* tlv for DAP channels, 0% - 100% - 200% */
517static const DECLARE_TLV_DB_SCALE(dap_volume, 0, 1, 0);
518
Michal Oleszczyk92a27422018-02-19 10:03:46 +0100519/* tlv for bass bands, -11.75db to 12.0db, step .25db */
520static const DECLARE_TLV_DB_SCALE(bass_band, -1175, 25, 0);
521
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800522/* tlv for hp volume, -51.5db to 12.0db, step .5db */
523static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
524
Kalle Kankare0593d462016-07-12 10:41:18 +0200525/* tlv for lineout volume, 31 steps of .5db each */
526static const DECLARE_TLV_DB_SCALE(lineout_volume, -1550, 50, 0);
527
Richard Leitnera7295262017-06-14 10:36:12 +0200528/* tlv for dap avc max gain, 0db, 6db, 12db */
529static const DECLARE_TLV_DB_SCALE(avc_max_gain, 0, 600, 0);
530
531/* tlv for dap avc threshold, */
532static const DECLARE_TLV_DB_MINMAX(avc_threshold, 0, 9600);
533
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800534static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
535 /* SOC_DOUBLE_S8_TLV with invert */
536 {
537 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
538 .name = "PCM Playback Volume",
539 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
540 SNDRV_CTL_ELEM_ACCESS_READWRITE,
541 .info = dac_info_volsw,
542 .get = dac_get_volsw,
543 .put = dac_put_volsw,
544 },
545
546 SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
547 SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
548 SGTL5000_CHIP_ANA_ADC_CTRL,
Lothar Waßmann65f2b222013-07-31 16:44:30 +0200549 8, 1, 0, capture_6db_attenuate),
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800550 SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
551
552 SOC_DOUBLE_TLV("Headphone Playback Volume",
553 SGTL5000_CHIP_ANA_HP_CTRL,
554 0, 8,
555 0x7f, 1,
556 headphone_volume),
Richard Leitner904a9872016-08-31 09:26:31 +0200557 SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
558 4, 1, 1),
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800559 SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
560 5, 1, 0),
561
562 SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
Fabio Estevamb50684d2012-12-23 15:45:31 -0200563 0, 3, 0, mic_gain_tlv),
Kalle Kankare0593d462016-07-12 10:41:18 +0200564
565 SOC_DOUBLE_TLV("Lineout Playback Volume",
566 SGTL5000_CHIP_LINE_OUT_VOL,
567 SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
568 SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
569 0x1f, 1,
570 lineout_volume),
Richard Leitner904a9872016-08-31 09:26:31 +0200571 SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
Richard Leitnera7295262017-06-14 10:36:12 +0200572
Michal Oleszczyk7f7d5232018-02-19 10:03:45 +0100573 SOC_SINGLE_TLV("DAP Main channel", SGTL5000_DAP_MAIN_CHAN,
574 0, 0xffff, 0, dap_volume),
575
576 SOC_SINGLE_TLV("DAP Mix channel", SGTL5000_DAP_MIX_CHAN,
577 0, 0xffff, 0, dap_volume),
Richard Leitnera7295262017-06-14 10:36:12 +0200578 /* Automatic Volume Control (DAP AVC) */
579 SOC_SINGLE("AVC Switch", SGTL5000_DAP_AVC_CTRL, 0, 1, 0),
580 SOC_SINGLE("AVC Hard Limiter Switch", SGTL5000_DAP_AVC_CTRL, 5, 1, 0),
581 SOC_SINGLE_TLV("AVC Max Gain Volume", SGTL5000_DAP_AVC_CTRL, 12, 2, 0,
582 avc_max_gain),
583 SOC_SINGLE("AVC Integrator Response", SGTL5000_DAP_AVC_CTRL, 8, 3, 0),
584 SOC_SINGLE_EXT_TLV("AVC Threshold Volume", SGTL5000_DAP_AVC_THRESHOLD,
585 0, 96, 0, avc_get_threshold, avc_put_threshold,
586 avc_threshold),
Michal Oleszczyk92a27422018-02-19 10:03:46 +0100587
588 SOC_SINGLE_TLV("BASS 0", SGTL5000_DAP_EQ_BASS_BAND0,
589 0, 0x5F, 0, bass_band),
590
591 SOC_SINGLE_TLV("BASS 1", SGTL5000_DAP_EQ_BASS_BAND1,
592 0, 0x5F, 0, bass_band),
593
594 SOC_SINGLE_TLV("BASS 2", SGTL5000_DAP_EQ_BASS_BAND2,
595 0, 0x5F, 0, bass_band),
596
597 SOC_SINGLE_TLV("BASS 3", SGTL5000_DAP_EQ_BASS_BAND3,
598 0, 0x5F, 0, bass_band),
599
600 SOC_SINGLE_TLV("BASS 4", SGTL5000_DAP_EQ_BASS_BAND4,
601 0, 0x5F, 0, bass_band),
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800602};
603
604/* mute the codec used by alsa core */
605static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
606{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000607 struct snd_soc_component *component = codec_dai->component;
Michal Oleszczykc5489f92018-02-02 13:10:29 +0100608 u16 i2s_pwr = SGTL5000_I2S_IN_POWERUP;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800609
Michal Oleszczykc5489f92018-02-02 13:10:29 +0100610 /*
611 * During 'digital mute' do not mute DAC
612 * because LINE_IN would be muted aswell. We want to mute
613 * only I2S block - this can be done by powering it off
614 */
Mark Brown58fadc12018-02-14 15:39:30 +0000615 snd_soc_component_update_bits(component, SGTL5000_CHIP_DIG_POWER,
Michal Oleszczykc5489f92018-02-02 13:10:29 +0100616 i2s_pwr, mute ? 0 : i2s_pwr);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800617
618 return 0;
619}
620
621/* set codec format */
622static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
623{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000624 struct snd_soc_component *component = codec_dai->component;
625 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800626 u16 i2sctl = 0;
627
628 sgtl5000->master = 0;
629 /*
630 * i2s clock and frame master setting.
631 * ONLY support:
632 * - clock and frame slave,
633 * - clock and frame master
634 */
635 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
636 case SND_SOC_DAIFMT_CBS_CFS:
637 break;
638 case SND_SOC_DAIFMT_CBM_CFM:
639 i2sctl |= SGTL5000_I2S_MASTER;
640 sgtl5000->master = 1;
641 break;
642 default:
643 return -EINVAL;
644 }
645
646 /* setting i2s data format */
647 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
648 case SND_SOC_DAIFMT_DSP_A:
Filip Brozovic9ee802e2015-01-30 12:58:24 +0100649 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800650 break;
651 case SND_SOC_DAIFMT_DSP_B:
Filip Brozovic9ee802e2015-01-30 12:58:24 +0100652 i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800653 i2sctl |= SGTL5000_I2S_LRALIGN;
654 break;
655 case SND_SOC_DAIFMT_I2S:
Filip Brozovic9ee802e2015-01-30 12:58:24 +0100656 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800657 break;
658 case SND_SOC_DAIFMT_RIGHT_J:
Filip Brozovic9ee802e2015-01-30 12:58:24 +0100659 i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800660 i2sctl |= SGTL5000_I2S_LRPOL;
661 break;
662 case SND_SOC_DAIFMT_LEFT_J:
Filip Brozovic9ee802e2015-01-30 12:58:24 +0100663 i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800664 i2sctl |= SGTL5000_I2S_LRALIGN;
665 break;
666 default:
667 return -EINVAL;
668 }
669
670 sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
671
672 /* Clock inversion */
673 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
674 case SND_SOC_DAIFMT_NB_NF:
675 break;
676 case SND_SOC_DAIFMT_IB_NF:
677 i2sctl |= SGTL5000_I2S_SCLK_INV;
678 break;
679 default:
680 return -EINVAL;
681 }
682
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000683 snd_soc_component_write(component, SGTL5000_CHIP_I2S_CTRL, i2sctl);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800684
685 return 0;
686}
687
688/* set codec sysclk */
689static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
690 int clk_id, unsigned int freq, int dir)
691{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000692 struct snd_soc_component *component = codec_dai->component;
693 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800694
695 switch (clk_id) {
696 case SGTL5000_SYSCLK:
697 sgtl5000->sysclk = freq;
698 break;
699 default:
700 return -EINVAL;
701 }
702
703 return 0;
704}
705
706/*
707 * set clock according to i2s frame clock,
Fabio Estevam7f6d75d2014-10-07 10:50:56 -0300708 * sgtl5000 provides 2 clock sources:
709 * 1. sys_mclk: sample freq can only be configured to
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800710 * 1/256, 1/384, 1/512 of sys_mclk.
Fabio Estevam7f6d75d2014-10-07 10:50:56 -0300711 * 2. pll: can derive any audio clocks.
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800712 *
713 * clock setting rules:
Fabio Estevam7f6d75d2014-10-07 10:50:56 -0300714 * 1. in slave mode, only sys_mclk can be used
715 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
716 * and above.
717 * 3. usage of sys_mclk is preferred over pll to save power.
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800718 */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000719static int sgtl5000_set_clock(struct snd_soc_component *component, int frame_rate)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800720{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000721 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800722 int clk_ctl = 0;
723 int sys_fs; /* sample freq */
724
725 /*
726 * sample freq should be divided by frame clock,
Fabio Estevam7f6d75d2014-10-07 10:50:56 -0300727 * if frame clock is lower than 44.1 kHz, sample freq should be set to
728 * 32 kHz or 44.1 kHz.
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800729 */
730 switch (frame_rate) {
731 case 8000:
732 case 16000:
733 sys_fs = 32000;
734 break;
735 case 11025:
736 case 22050:
737 sys_fs = 44100;
738 break;
739 default:
740 sys_fs = frame_rate;
741 break;
742 }
743
744 /* set divided factor of frame clock */
745 switch (sys_fs / frame_rate) {
746 case 4:
747 clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
748 break;
749 case 2:
750 clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
751 break;
752 case 1:
753 clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
754 break;
755 default:
756 return -EINVAL;
757 }
758
759 /* set the sys_fs according to frame rate */
760 switch (sys_fs) {
761 case 32000:
762 clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
763 break;
764 case 44100:
765 clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
766 break;
767 case 48000:
768 clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
769 break;
770 case 96000:
771 clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
772 break;
773 default:
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000774 dev_err(component->dev, "frame rate %d not supported\n",
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800775 frame_rate);
776 return -EINVAL;
777 }
778
779 /*
780 * calculate the divider of mclk/sample_freq,
Fabio Estevam7f6d75d2014-10-07 10:50:56 -0300781 * factor of freq = 96 kHz can only be 256, since mclk is in the range
782 * of 8 MHz - 27 MHz
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800783 */
Fabio Estevam2a4cfd12014-11-27 13:02:01 -0200784 switch (sgtl5000->sysclk / frame_rate) {
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800785 case 256:
786 clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
787 SGTL5000_MCLK_FREQ_SHIFT;
788 break;
789 case 384:
790 clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
791 SGTL5000_MCLK_FREQ_SHIFT;
792 break;
793 case 512:
794 clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
795 SGTL5000_MCLK_FREQ_SHIFT;
796 break;
797 default:
Fabio Estevam7f6d75d2014-10-07 10:50:56 -0300798 /* if mclk does not satisfy the divider, use pll */
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800799 if (sgtl5000->master) {
800 clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
801 SGTL5000_MCLK_FREQ_SHIFT;
802 } else {
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000803 dev_err(component->dev,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800804 "PLL not supported in slave mode\n");
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000805 dev_err(component->dev, "%d ratio is not supported. "
Fabio Estevamfa558d02014-10-02 16:16:50 -0300806 "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
Fabio Estevam2a4cfd12014-11-27 13:02:01 -0200807 sgtl5000->sysclk / frame_rate);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800808 return -EINVAL;
809 }
810 }
811
812 /* if using pll, please check manual 6.4.2 for detail */
813 if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
814 u64 out, t;
815 int div2;
816 int pll_ctl;
817 unsigned int in, int_div, frac_div;
818
819 if (sgtl5000->sysclk > 17000000) {
820 div2 = 1;
821 in = sgtl5000->sysclk / 2;
822 } else {
823 div2 = 0;
824 in = sgtl5000->sysclk;
825 }
826 if (sys_fs == 44100)
827 out = 180633600;
828 else
829 out = 196608000;
830 t = do_div(out, in);
831 int_div = out;
832 t *= 2048;
833 do_div(t, in);
834 frac_div = t;
835 pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
836 frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
837
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000838 snd_soc_component_write(component, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800839 if (div2)
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000840 snd_soc_component_update_bits(component,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800841 SGTL5000_CHIP_CLK_TOP_CTRL,
842 SGTL5000_INPUT_FREQ_DIV2,
843 SGTL5000_INPUT_FREQ_DIV2);
844 else
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000845 snd_soc_component_update_bits(component,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800846 SGTL5000_CHIP_CLK_TOP_CTRL,
847 SGTL5000_INPUT_FREQ_DIV2,
848 0);
849
850 /* power up pll */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000851 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800852 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
853 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
Oskar Schirmere06e4c22013-08-05 07:36:02 +0000854
855 /* if using pll, clk_ctrl must be set after pll power up */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000856 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800857 } else {
Oskar Schirmere06e4c22013-08-05 07:36:02 +0000858 /* otherwise, clk_ctrl must be set before pll power down */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000859 snd_soc_component_write(component, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
Oskar Schirmere06e4c22013-08-05 07:36:02 +0000860
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800861 /* power down pll */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000862 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800863 SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
864 0);
865 }
866
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800867 return 0;
868}
869
870/*
871 * Set PCM DAI bit size and sample rate.
872 * input: params_rate, params_fmt
873 */
874static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
875 struct snd_pcm_hw_params *params,
876 struct snd_soc_dai *dai)
877{
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000878 struct snd_soc_component *component = dai->component;
879 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800880 int channels = params_channels(params);
881 int i2s_ctl = 0;
882 int stereo;
883 int ret;
884
885 /* sysclk should already set */
886 if (!sgtl5000->sysclk) {
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000887 dev_err(component->dev, "%s: set sysclk first!\n", __func__);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800888 return -EFAULT;
889 }
890
891 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
892 stereo = SGTL5000_DAC_STEREO;
893 else
894 stereo = SGTL5000_ADC_STEREO;
895
896 /* set mono to save power */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000897 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER, stereo,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800898 channels == 1 ? 0 : stereo);
899
900 /* set codec clock base on lrclk */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000901 ret = sgtl5000_set_clock(component, params_rate(params));
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800902 if (ret)
903 return ret;
904
905 /* set i2s data format */
Mark Browndacc2ae2014-07-31 12:46:05 +0100906 switch (params_width(params)) {
907 case 16:
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800908 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
909 return -EINVAL;
910 i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
911 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
912 SGTL5000_I2S_SCLKFREQ_SHIFT;
913 break;
Mark Browndacc2ae2014-07-31 12:46:05 +0100914 case 20:
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800915 i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
916 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
917 SGTL5000_I2S_SCLKFREQ_SHIFT;
918 break;
Mark Browndacc2ae2014-07-31 12:46:05 +0100919 case 24:
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800920 i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
921 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
922 SGTL5000_I2S_SCLKFREQ_SHIFT;
923 break;
Mark Browndacc2ae2014-07-31 12:46:05 +0100924 case 32:
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800925 if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
926 return -EINVAL;
927 i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
928 i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
929 SGTL5000_I2S_SCLKFREQ_SHIFT;
930 break;
931 default:
932 return -EINVAL;
933 }
934
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000935 snd_soc_component_update_bits(component, SGTL5000_CHIP_I2S_CTRL,
Axel Lin33cb92c2011-10-21 09:54:43 +0800936 SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
937 i2s_ctl);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800938
939 return 0;
940}
941
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800942/*
943 * set dac bias
944 * common state changes:
945 * startup:
946 * off --> standby --> prepare --> on
947 * standby --> prepare --> on
948 *
949 * stop:
950 * on --> prepare --> standby
951 */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000952static int sgtl5000_set_bias_level(struct snd_soc_component *component,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800953 enum snd_soc_bias_level level)
954{
Mark Brown27a4b3f2018-02-16 15:29:19 +0000955 struct sgtl5000_priv *sgtl = snd_soc_component_get_drvdata(component);
Fabio Estevama8992972018-02-16 11:58:54 -0200956 int ret;
957
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800958 switch (level) {
959 case SND_SOC_BIAS_ON:
960 case SND_SOC_BIAS_PREPARE:
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800961 case SND_SOC_BIAS_STANDBY:
Fabio Estevama8992972018-02-16 11:58:54 -0200962 regcache_cache_only(sgtl->regmap, false);
963 ret = regcache_sync(sgtl->regmap);
964 if (ret) {
965 regcache_cache_only(sgtl->regmap, true);
966 return ret;
967 }
968
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000969 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
Eric Nelson8419caa2016-06-07 01:14:52 +0200970 SGTL5000_REFTOP_POWERUP,
971 SGTL5000_REFTOP_POWERUP);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800972 break;
973 case SND_SOC_BIAS_OFF:
Fabio Estevama8992972018-02-16 11:58:54 -0200974 regcache_cache_only(sgtl->regmap, true);
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +0000975 snd_soc_component_update_bits(component, SGTL5000_CHIP_ANA_POWER,
Eric Nelson8419caa2016-06-07 01:14:52 +0200976 SGTL5000_REFTOP_POWERUP, 0);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800977 break;
978 }
979
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800980 return 0;
981}
982
983#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
984 SNDRV_PCM_FMTBIT_S20_3LE |\
985 SNDRV_PCM_FMTBIT_S24_LE |\
986 SNDRV_PCM_FMTBIT_S32_LE)
987
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100988static const struct snd_soc_dai_ops sgtl5000_ops = {
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800989 .hw_params = sgtl5000_pcm_hw_params,
990 .digital_mute = sgtl5000_digital_mute,
991 .set_fmt = sgtl5000_set_dai_fmt,
992 .set_sysclk = sgtl5000_set_dai_sysclk,
993};
994
995static struct snd_soc_dai_driver sgtl5000_dai = {
996 .name = "sgtl5000",
997 .playback = {
998 .stream_name = "Playback",
999 .channels_min = 1,
1000 .channels_max = 2,
1001 /*
1002 * only support 8~48K + 96K,
1003 * TODO modify hw_param to support more
1004 */
1005 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1006 .formats = SGTL5000_FORMATS,
1007 },
1008 .capture = {
1009 .stream_name = "Capture",
1010 .channels_min = 1,
1011 .channels_max = 2,
1012 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1013 .formats = SGTL5000_FORMATS,
1014 },
1015 .ops = &sgtl5000_ops,
1016 .symmetric_rates = 1,
1017};
1018
Fabio Estevame5d80e82013-05-04 15:39:34 -03001019static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001020{
1021 switch (reg) {
1022 case SGTL5000_CHIP_ID:
1023 case SGTL5000_CHIP_ADCDAC_CTRL:
1024 case SGTL5000_CHIP_ANA_STATUS:
Fabio Estevame5d80e82013-05-04 15:39:34 -03001025 return true;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001026 }
1027
Fabio Estevame5d80e82013-05-04 15:39:34 -03001028 return false;
1029}
1030
1031static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1032{
1033 switch (reg) {
1034 case SGTL5000_CHIP_ID:
1035 case SGTL5000_CHIP_DIG_POWER:
1036 case SGTL5000_CHIP_CLK_CTRL:
1037 case SGTL5000_CHIP_I2S_CTRL:
1038 case SGTL5000_CHIP_SSS_CTRL:
1039 case SGTL5000_CHIP_ADCDAC_CTRL:
1040 case SGTL5000_CHIP_DAC_VOL:
1041 case SGTL5000_CHIP_PAD_STRENGTH:
1042 case SGTL5000_CHIP_ANA_ADC_CTRL:
1043 case SGTL5000_CHIP_ANA_HP_CTRL:
1044 case SGTL5000_CHIP_ANA_CTRL:
1045 case SGTL5000_CHIP_LINREG_CTRL:
1046 case SGTL5000_CHIP_REF_CTRL:
1047 case SGTL5000_CHIP_MIC_CTRL:
1048 case SGTL5000_CHIP_LINE_OUT_CTRL:
1049 case SGTL5000_CHIP_LINE_OUT_VOL:
1050 case SGTL5000_CHIP_ANA_POWER:
1051 case SGTL5000_CHIP_PLL_CTRL:
1052 case SGTL5000_CHIP_CLK_TOP_CTRL:
1053 case SGTL5000_CHIP_ANA_STATUS:
1054 case SGTL5000_CHIP_SHORT_CTRL:
1055 case SGTL5000_CHIP_ANA_TEST2:
1056 case SGTL5000_DAP_CTRL:
1057 case SGTL5000_DAP_PEQ:
1058 case SGTL5000_DAP_BASS_ENHANCE:
1059 case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1060 case SGTL5000_DAP_AUDIO_EQ:
1061 case SGTL5000_DAP_SURROUND:
1062 case SGTL5000_DAP_FLT_COEF_ACCESS:
1063 case SGTL5000_DAP_COEF_WR_B0_MSB:
1064 case SGTL5000_DAP_COEF_WR_B0_LSB:
1065 case SGTL5000_DAP_EQ_BASS_BAND0:
1066 case SGTL5000_DAP_EQ_BASS_BAND1:
1067 case SGTL5000_DAP_EQ_BASS_BAND2:
1068 case SGTL5000_DAP_EQ_BASS_BAND3:
1069 case SGTL5000_DAP_EQ_BASS_BAND4:
1070 case SGTL5000_DAP_MAIN_CHAN:
1071 case SGTL5000_DAP_MIX_CHAN:
1072 case SGTL5000_DAP_AVC_CTRL:
1073 case SGTL5000_DAP_AVC_THRESHOLD:
1074 case SGTL5000_DAP_AVC_ATTACK:
1075 case SGTL5000_DAP_AVC_DECAY:
1076 case SGTL5000_DAP_COEF_WR_B1_MSB:
1077 case SGTL5000_DAP_COEF_WR_B1_LSB:
1078 case SGTL5000_DAP_COEF_WR_B2_MSB:
1079 case SGTL5000_DAP_COEF_WR_B2_LSB:
1080 case SGTL5000_DAP_COEF_WR_A1_MSB:
1081 case SGTL5000_DAP_COEF_WR_A1_LSB:
1082 case SGTL5000_DAP_COEF_WR_A2_MSB:
1083 case SGTL5000_DAP_COEF_WR_A2_LSB:
1084 return true;
1085
1086 default:
1087 return false;
1088 }
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001089}
1090
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001091/*
Alexander Stein1f39d932015-04-16 14:51:57 +02001092 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1093 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1094 * The calculatation was done for all possible register values which
1095 * is the array index and the following formula: 10^((idx−15)/40) * 100
1096 */
1097static const u8 vol_quot_table[] = {
1098 42, 45, 47, 50, 53, 56, 60, 63,
1099 67, 71, 75, 79, 84, 89, 94, 100,
1100 106, 112, 119, 126, 133, 141, 150, 158,
1101 168, 178, 188, 200, 211, 224, 237, 251
1102};
1103
1104/*
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001105 * sgtl5000 has 3 internal power supplies:
1106 * 1. VAG, normally set to vdda/2
Fabio Estevam7f6d75d2014-10-07 10:50:56 -03001107 * 2. charge pump, set to different value
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001108 * according to voltage of vdda and vddio
1109 * 3. line out VAG, normally set to vddio/2
1110 *
1111 * and should be set according to:
1112 * 1. vddd provided by external or not
1113 * 2. vdda and vddio voltage value. > 3.1v or not
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001114 */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001115static int sgtl5000_set_power_regs(struct snd_soc_component *component)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001116{
1117 int vddd;
1118 int vdda;
1119 int vddio;
1120 u16 ana_pwr;
1121 u16 lreg_ctrl;
1122 int vag;
Alexander Steind2b7c2a2015-04-16 14:51:56 +02001123 int lo_vag;
Alexander Stein1f39d932015-04-16 14:51:57 +02001124 int vol_quot;
1125 int lo_vol;
1126 size_t i;
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001127 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001128
1129 vdda = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1130 vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
Eric Nelson940adb22016-06-07 01:14:48 +02001131 vddd = (sgtl5000->num_supplies > VDDD)
1132 ? regulator_get_voltage(sgtl5000->supplies[VDDD].consumer)
1133 : LDO_VOLTAGE;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001134
1135 vdda = vdda / 1000;
1136 vddio = vddio / 1000;
1137 vddd = vddd / 1000;
1138
1139 if (vdda <= 0 || vddio <= 0 || vddd < 0) {
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001140 dev_err(component->dev, "regulator voltage not set correctly\n");
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001141
1142 return -EINVAL;
1143 }
1144
1145 /* according to datasheet, maximum voltage of supplies */
1146 if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001147 dev_err(component->dev,
Fabio Estevamcf1ee982011-12-28 09:55:15 -02001148 "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001149 vdda, vddio, vddd);
1150
1151 return -EINVAL;
1152 }
1153
1154 /* reset value */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001155 ana_pwr = snd_soc_component_read32(component, SGTL5000_CHIP_ANA_POWER);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001156 ana_pwr |= SGTL5000_DAC_STEREO |
1157 SGTL5000_ADC_STEREO |
1158 SGTL5000_REFTOP_POWERUP;
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001159 lreg_ctrl = snd_soc_component_read32(component, SGTL5000_CHIP_LINREG_CTRL);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001160
1161 if (vddio < 3100 && vdda < 3100) {
1162 /* enable internal oscillator used for charge pump */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001163 snd_soc_component_update_bits(component, SGTL5000_CHIP_CLK_TOP_CTRL,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001164 SGTL5000_INT_OSC_EN,
1165 SGTL5000_INT_OSC_EN);
1166 /* Enable VDDC charge pump */
1167 ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1168 } else if (vddio >= 3100 && vdda >= 3100) {
Eric Nelsonc7d910b2015-02-27 08:06:45 -07001169 ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001170 /* VDDC use VDDIO rail */
1171 lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1172 lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1173 SGTL5000_VDDC_MAN_ASSN_SHIFT;
1174 }
1175
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001176 snd_soc_component_write(component, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001177
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001178 snd_soc_component_write(component, SGTL5000_CHIP_ANA_POWER, ana_pwr);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001179
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001180 /*
1181 * set ADC/DAC VAG to vdda / 2,
1182 * should stay in range (0.8v, 1.575v)
1183 */
1184 vag = vdda / 2;
1185 if (vag <= SGTL5000_ANA_GND_BASE)
1186 vag = 0;
1187 else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1188 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1189 vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1190 else
1191 vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1192
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001193 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
Axel Lin33cb92c2011-10-21 09:54:43 +08001194 SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001195
1196 /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
Alexander Steind2b7c2a2015-04-16 14:51:56 +02001197 lo_vag = vddio / 2;
1198 if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1199 lo_vag = 0;
1200 else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001201 SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
Alexander Steind2b7c2a2015-04-16 14:51:56 +02001202 lo_vag = SGTL5000_LINE_OUT_GND_MAX;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001203 else
Alexander Steind2b7c2a2015-04-16 14:51:56 +02001204 lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001205 SGTL5000_LINE_OUT_GND_STP;
1206
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001207 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_CTRL,
Axel Lin33cb92c2011-10-21 09:54:43 +08001208 SGTL5000_LINE_OUT_CURRENT_MASK |
1209 SGTL5000_LINE_OUT_GND_MASK,
Alexander Steind2b7c2a2015-04-16 14:51:56 +02001210 lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001211 SGTL5000_LINE_OUT_CURRENT_360u <<
1212 SGTL5000_LINE_OUT_CURRENT_SHIFT);
1213
Alexander Stein1f39d932015-04-16 14:51:57 +02001214 /*
1215 * Set lineout output level in range (0..31)
1216 * the same value is used for right and left channel
1217 *
1218 * Searching for a suitable index solving this formula:
1219 * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1220 */
Colin Ian King9ab708a2018-09-06 11:41:52 +01001221 vol_quot = lo_vag ? (vag * 100) / lo_vag : 0;
Alexander Stein1f39d932015-04-16 14:51:57 +02001222 lo_vol = 0;
1223 for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1224 if (vol_quot >= vol_quot_table[i])
1225 lo_vol = i;
1226 else
1227 break;
1228 }
1229
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001230 snd_soc_component_update_bits(component, SGTL5000_CHIP_LINE_OUT_VOL,
Alexander Stein1f39d932015-04-16 14:51:57 +02001231 SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1232 SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1233 lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1234 lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1235
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001236 return 0;
1237}
1238
Eric Nelson940adb22016-06-07 01:14:48 +02001239static int sgtl5000_enable_regulators(struct i2c_client *client)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001240{
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001241 int ret;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001242 int i;
1243 int external_vddd = 0;
Shawn Guo11db0da2013-12-13 14:43:03 +08001244 struct regulator *vddd;
Eric Nelson940adb22016-06-07 01:14:48 +02001245 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001246
1247 for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1248 sgtl5000->supplies[i].supply = supply_names[i];
1249
Eric Nelson940adb22016-06-07 01:14:48 +02001250 vddd = regulator_get_optional(&client->dev, "VDDD");
1251 if (IS_ERR(vddd)) {
1252 /* See if it's just not registered yet */
1253 if (PTR_ERR(vddd) == -EPROBE_DEFER)
1254 return -EPROBE_DEFER;
1255 } else {
1256 external_vddd = 1;
1257 regulator_put(vddd);
Shawn Guo11db0da2013-12-13 14:43:03 +08001258 }
1259
Eric Nelson940adb22016-06-07 01:14:48 +02001260 sgtl5000->num_supplies = ARRAY_SIZE(sgtl5000->supplies)
1261 - 1 + external_vddd;
1262 ret = regulator_bulk_get(&client->dev, sgtl5000->num_supplies,
Shawn Guo11db0da2013-12-13 14:43:03 +08001263 sgtl5000->supplies);
1264 if (ret)
Eric Nelson940adb22016-06-07 01:14:48 +02001265 return ret;
Shawn Guo11db0da2013-12-13 14:43:03 +08001266
Eric Nelson940adb22016-06-07 01:14:48 +02001267 ret = regulator_bulk_enable(sgtl5000->num_supplies,
1268 sgtl5000->supplies);
1269 if (!ret)
1270 usleep_range(10, 20);
1271 else
1272 regulator_bulk_free(sgtl5000->num_supplies,
1273 sgtl5000->supplies);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001274
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001275 return ret;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001276}
1277
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001278static int sgtl5000_probe(struct snd_soc_component *component)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001279{
1280 int ret;
Fabio Estevam570c70a2017-04-05 11:32:34 -03001281 u16 reg;
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001282 struct sgtl5000_priv *sgtl5000 = snd_soc_component_get_drvdata(component);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001283
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001284 /* power up sgtl5000 */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001285 ret = sgtl5000_set_power_regs(component);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001286 if (ret)
1287 goto err;
1288
1289 /* enable small pop, introduce 400ms delay in turning off */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001290 snd_soc_component_update_bits(component, SGTL5000_CHIP_REF_CTRL,
Fabio Estevamc251ea72014-11-14 02:14:47 -02001291 SGTL5000_SMALL_POP, 1);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001292
1293 /* disable short cut detector */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001294 snd_soc_component_write(component, SGTL5000_CHIP_SHORT_CTRL, 0);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001295
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001296 snd_soc_component_write(component, SGTL5000_CHIP_DIG_POWER,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001297 SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1298
1299 /* enable dac volume ramp by default */
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001300 snd_soc_component_write(component, SGTL5000_CHIP_ADCDAC_CTRL,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001301 SGTL5000_DAC_VOL_RAMP_EN |
1302 SGTL5000_DAC_MUTE_RIGHT |
1303 SGTL5000_DAC_MUTE_LEFT);
1304
Fabio Estevam570c70a2017-04-05 11:32:34 -03001305 reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f);
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001306 snd_soc_component_write(component, SGTL5000_CHIP_PAD_STRENGTH, reg);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001307
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001308 snd_soc_component_write(component, SGTL5000_CHIP_ANA_CTRL,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001309 SGTL5000_HP_ZCD_EN |
1310 SGTL5000_ADC_ZCD_EN);
1311
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001312 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +02001313 SGTL5000_BIAS_R_MASK,
1314 sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001315
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001316 snd_soc_component_update_bits(component, SGTL5000_CHIP_MIC_CTRL,
Gianluca Renzie256da82015-09-25 21:33:41 +02001317 SGTL5000_BIAS_VOLT_MASK,
1318 sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001319 /*
Michal Oleszczyk92a27422018-02-19 10:03:46 +01001320 * enable DAP Graphic EQ
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001321 * TODO:
Michal Oleszczyk92a27422018-02-19 10:03:46 +01001322 * Add control for changing between PEQ/Tone Control/GEQ
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001323 */
Michal Oleszczyk92a27422018-02-19 10:03:46 +01001324 snd_soc_component_write(component, SGTL5000_DAP_AUDIO_EQ, SGTL5000_DAP_SEL_GEQ);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001325
Michal Oleszczykc5489f92018-02-02 13:10:29 +01001326 /* Unmute DAC after start */
Mark Brown58fadc12018-02-14 15:39:30 +00001327 snd_soc_component_update_bits(component, SGTL5000_CHIP_ADCDAC_CTRL,
Michal Oleszczykc5489f92018-02-02 13:10:29 +01001328 SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT, 0);
1329
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001330 return 0;
1331
1332err:
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001333 return ret;
1334}
1335
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001336static const struct snd_soc_component_driver sgtl5000_driver = {
1337 .probe = sgtl5000_probe,
1338 .set_bias_level = sgtl5000_set_bias_level,
1339 .controls = sgtl5000_snd_controls,
1340 .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1341 .dapm_widgets = sgtl5000_dapm_widgets,
1342 .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1343 .dapm_routes = sgtl5000_dapm_routes,
1344 .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1345 .suspend_bias_off = 1,
1346 .idle_bias_on = 1,
1347 .use_pmdown_time = 1,
1348 .endianness = 1,
1349 .non_legacy_dai_naming = 1,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001350};
1351
Fabio Estevame5d80e82013-05-04 15:39:34 -03001352static const struct regmap_config sgtl5000_regmap = {
1353 .reg_bits = 16,
1354 .val_bits = 16,
Fabio Estevamcb23e852013-07-04 20:01:01 -03001355 .reg_stride = 2,
Fabio Estevame5d80e82013-05-04 15:39:34 -03001356
1357 .max_register = SGTL5000_MAX_REG_OFFSET,
1358 .volatile_reg = sgtl5000_volatile,
1359 .readable_reg = sgtl5000_readable,
1360
1361 .cache_type = REGCACHE_RBTREE,
1362 .reg_defaults = sgtl5000_reg_defaults,
1363 .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1364};
1365
Fabio Estevamaf8ee112013-05-09 21:15:47 -03001366/*
1367 * Write all the default values from sgtl5000_reg_defaults[] array into the
1368 * sgtl5000 registers, to make sure we always start with the sane registers
1369 * values as stated in the datasheet.
1370 *
1371 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1372 * we follow this approach to guarantee we always start from the default values
1373 * and avoid problems like, not being able to probe after an audio playback
1374 * followed by a system reset or a 'reboot' command in Linux
1375 */
Eric Nelsonf219b162016-06-07 01:14:49 +02001376static void sgtl5000_fill_defaults(struct i2c_client *client)
Fabio Estevamaf8ee112013-05-09 21:15:47 -03001377{
Eric Nelsonf219b162016-06-07 01:14:49 +02001378 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
Fabio Estevamaf8ee112013-05-09 21:15:47 -03001379 int i, ret, val, index;
1380
1381 for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1382 val = sgtl5000_reg_defaults[i].def;
1383 index = sgtl5000_reg_defaults[i].reg;
1384 ret = regmap_write(sgtl5000->regmap, index, val);
1385 if (ret)
Eric Nelsonf219b162016-06-07 01:14:49 +02001386 dev_err(&client->dev,
1387 "%s: error %d setting reg 0x%02x to 0x%04x\n",
1388 __func__, ret, index, val);
Fabio Estevamaf8ee112013-05-09 21:15:47 -03001389 }
Fabio Estevamaf8ee112013-05-09 21:15:47 -03001390}
1391
Bill Pemberton7a79e942012-12-07 09:26:37 -05001392static int sgtl5000_i2c_probe(struct i2c_client *client,
1393 const struct i2c_device_id *id)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001394{
1395 struct sgtl5000_priv *sgtl5000;
Fabio Estevamb871f1a2013-05-09 21:15:46 -03001396 int ret, reg, rev;
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +02001397 struct device_node *np = client->dev.of_node;
1398 u32 value;
Eric Nelson3d632cc2016-06-07 01:14:50 +02001399 u16 ana_pwr;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001400
Fabio Estevam3f7256f2014-10-24 13:01:25 -02001401 sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001402 if (!sgtl5000)
1403 return -ENOMEM;
1404
Eric Nelson940adb22016-06-07 01:14:48 +02001405 i2c_set_clientdata(client, sgtl5000);
1406
1407 ret = sgtl5000_enable_regulators(client);
1408 if (ret)
1409 return ret;
1410
Fabio Estevame5d80e82013-05-04 15:39:34 -03001411 sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1412 if (IS_ERR(sgtl5000->regmap)) {
1413 ret = PTR_ERR(sgtl5000->regmap);
1414 dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
Eric Nelson940adb22016-06-07 01:14:48 +02001415 goto disable_regs;
Fabio Estevame5d80e82013-05-04 15:39:34 -03001416 }
1417
Fabio Estevam9e13f342013-06-09 22:07:46 -03001418 sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1419 if (IS_ERR(sgtl5000->mclk)) {
1420 ret = PTR_ERR(sgtl5000->mclk);
Shawn Guo46a59052013-07-16 09:17:27 +08001421 /* Defer the probe to see if the clk will be provided later */
1422 if (ret == -ENOENT)
Eric Nelson940adb22016-06-07 01:14:48 +02001423 ret = -EPROBE_DEFER;
Fabio Estevam8af57482018-01-17 13:48:54 -02001424
1425 if (ret != -EPROBE_DEFER)
1426 dev_err(&client->dev, "Failed to get mclock: %d\n",
1427 ret);
Eric Nelson940adb22016-06-07 01:14:48 +02001428 goto disable_regs;
Fabio Estevam9e13f342013-06-09 22:07:46 -03001429 }
1430
1431 ret = clk_prepare_enable(sgtl5000->mclk);
Eric Nelson940adb22016-06-07 01:14:48 +02001432 if (ret) {
1433 dev_err(&client->dev, "Error enabling clock %d\n", ret);
1434 goto disable_regs;
1435 }
Fabio Estevam9e13f342013-06-09 22:07:46 -03001436
Eric Nelson58cc9c92015-01-30 14:07:55 -07001437 /* Need 8 clocks before I2C accesses */
1438 udelay(1);
1439
Fabio Estevamb871f1a2013-05-09 21:15:46 -03001440 /* read chip information */
1441 ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
Eric Nelson940adb22016-06-07 01:14:48 +02001442 if (ret) {
1443 dev_err(&client->dev, "Error reading chip id %d\n", ret);
Fabio Estevam9e13f342013-06-09 22:07:46 -03001444 goto disable_clk;
Eric Nelson940adb22016-06-07 01:14:48 +02001445 }
Fabio Estevamb871f1a2013-05-09 21:15:46 -03001446
1447 if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1448 SGTL5000_PARTID_PART_ID) {
1449 dev_err(&client->dev,
1450 "Device with ID register %x is not a sgtl5000\n", reg);
Fabio Estevam9e13f342013-06-09 22:07:46 -03001451 ret = -ENODEV;
1452 goto disable_clk;
Fabio Estevamb871f1a2013-05-09 21:15:46 -03001453 }
1454
1455 rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1456 dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
Shawn Guo252e91f2013-12-13 14:43:02 +08001457 sgtl5000->revision = rev;
Fabio Estevamb871f1a2013-05-09 21:15:46 -03001458
Eric Nelson08dea162016-06-07 01:14:51 +02001459 /* reconfigure the clocks in case we're using the PLL */
1460 ret = regmap_write(sgtl5000->regmap,
1461 SGTL5000_CHIP_CLK_CTRL,
1462 SGTL5000_CHIP_CLK_CTRL_DEFAULT);
1463 if (ret)
1464 dev_err(&client->dev,
1465 "Error %d initializing CHIP_CLK_CTRL\n", ret);
1466
Eric Nelson940adb22016-06-07 01:14:48 +02001467 /* Follow section 2.2.1.1 of AN3663 */
Eric Nelson3d632cc2016-06-07 01:14:50 +02001468 ana_pwr = SGTL5000_ANA_POWER_DEFAULT;
Eric Nelson940adb22016-06-07 01:14:48 +02001469 if (sgtl5000->num_supplies <= VDDD) {
1470 /* internal VDDD at 1.2V */
Eric Nelson3d632cc2016-06-07 01:14:50 +02001471 ret = regmap_update_bits(sgtl5000->regmap,
1472 SGTL5000_CHIP_LINREG_CTRL,
1473 SGTL5000_LINREG_VDDD_MASK,
1474 LINREG_VDDD);
1475 if (ret)
1476 dev_err(&client->dev,
1477 "Error %d setting LINREG_VDDD\n", ret);
1478
1479 ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
1480 dev_info(&client->dev,
Fabio Estevamda689e02018-01-18 09:45:28 -02001481 "Using internal LDO instead of VDDD: check ER1 erratum\n");
Eric Nelson940adb22016-06-07 01:14:48 +02001482 } else {
1483 /* using external LDO for VDDD
1484 * Clear startup powerup and simple powerup
1485 * bits to save power
1486 */
Eric Nelson3d632cc2016-06-07 01:14:50 +02001487 ana_pwr &= ~(SGTL5000_STARTUP_POWERUP
1488 | SGTL5000_LINREG_SIMPLE_POWERUP);
Eric Nelson940adb22016-06-07 01:14:48 +02001489 dev_dbg(&client->dev, "Using external VDDD\n");
1490 }
Eric Nelson3d632cc2016-06-07 01:14:50 +02001491 ret = regmap_write(sgtl5000->regmap, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1492 if (ret)
1493 dev_err(&client->dev,
1494 "Error %d setting CHIP_ANA_POWER to %04x\n",
1495 ret, ana_pwr);
Eric Nelson940adb22016-06-07 01:14:48 +02001496
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +02001497 if (np) {
1498 if (!of_property_read_u32(np,
1499 "micbias-resistor-k-ohms", &value)) {
1500 switch (value) {
1501 case SGTL5000_MICBIAS_OFF:
1502 sgtl5000->micbias_resistor = 0;
1503 break;
1504 case SGTL5000_MICBIAS_2K:
1505 sgtl5000->micbias_resistor = 1;
1506 break;
1507 case SGTL5000_MICBIAS_4K:
1508 sgtl5000->micbias_resistor = 2;
1509 break;
1510 case SGTL5000_MICBIAS_8K:
1511 sgtl5000->micbias_resistor = 3;
1512 break;
1513 default:
1514 sgtl5000->micbias_resistor = 2;
1515 dev_err(&client->dev,
1516 "Unsuitable MicBias resistor\n");
1517 }
1518 } else {
1519 /* default is 4Kohms */
1520 sgtl5000->micbias_resistor = 2;
1521 }
Jean-Michel Hautbois87357792014-10-14 08:43:12 +02001522 if (!of_property_read_u32(np,
1523 "micbias-voltage-m-volts", &value)) {
1524 /* 1250mV => 0 */
1525 /* steps of 250mV */
1526 if ((value >= 1250) && (value <= 3000))
1527 sgtl5000->micbias_voltage = (value / 250) - 5;
1528 else {
1529 sgtl5000->micbias_voltage = 0;
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +02001530 dev_err(&client->dev,
Gianluca Renzifb97d752015-09-25 21:33:42 +02001531 "Unsuitable MicBias voltage\n");
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +02001532 }
1533 } else {
Jean-Michel Hautbois87357792014-10-14 08:43:12 +02001534 sgtl5000->micbias_voltage = 0;
Jean-Michel Hautboisbd0593f2014-10-14 08:43:11 +02001535 }
1536 }
1537
Fabio Estevam570c70a2017-04-05 11:32:34 -03001538 sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
1539 if (!of_property_read_u32(np, "lrclk-strength", &value)) {
1540 if (value > I2S_LRCLK_STRENGTH_HIGH)
1541 value = I2S_LRCLK_STRENGTH_LOW;
1542 sgtl5000->lrclk_strength = value;
1543 }
1544
Fabio Estevamaf8ee112013-05-09 21:15:47 -03001545 /* Ensure sgtl5000 will start with sane register values */
Eric Nelsonf219b162016-06-07 01:14:49 +02001546 sgtl5000_fill_defaults(client);
Fabio Estevamaf8ee112013-05-09 21:15:47 -03001547
Kuninori Morimoto2f8b3182018-01-29 04:37:53 +00001548 ret = devm_snd_soc_register_component(&client->dev,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001549 &sgtl5000_driver, &sgtl5000_dai, 1);
Fabio Estevam9e13f342013-06-09 22:07:46 -03001550 if (ret)
1551 goto disable_clk;
1552
1553 return 0;
1554
1555disable_clk:
1556 clk_disable_unprepare(sgtl5000->mclk);
Eric Nelson940adb22016-06-07 01:14:48 +02001557
1558disable_regs:
1559 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1560 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1561
Fabio Estevam512fa7c2011-12-28 11:30:11 -02001562 return ret;
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001563}
1564
Bill Pemberton7a79e942012-12-07 09:26:37 -05001565static int sgtl5000_i2c_remove(struct i2c_client *client)
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001566{
Fabio Estevam7c647af2013-06-10 10:24:41 -03001567 struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001568
Fabio Estevam9e13f342013-06-09 22:07:46 -03001569 clk_disable_unprepare(sgtl5000->mclk);
Eric Nelson940adb22016-06-07 01:14:48 +02001570 regulator_bulk_disable(sgtl5000->num_supplies, sgtl5000->supplies);
1571 regulator_bulk_free(sgtl5000->num_supplies, sgtl5000->supplies);
1572
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001573 return 0;
1574}
1575
1576static const struct i2c_device_id sgtl5000_id[] = {
1577 {"sgtl5000", 0},
1578 {},
1579};
1580
1581MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1582
Shawn Guo58e49422011-07-22 00:28:51 +08001583static const struct of_device_id sgtl5000_dt_ids[] = {
1584 { .compatible = "fsl,sgtl5000", },
1585 { /* sentinel */ }
1586};
Axel Lin4c54c6d2011-08-11 22:19:16 +08001587MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
Shawn Guo58e49422011-07-22 00:28:51 +08001588
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001589static struct i2c_driver sgtl5000_i2c_driver = {
1590 .driver = {
1591 .name = "sgtl5000",
Shawn Guo58e49422011-07-22 00:28:51 +08001592 .of_match_table = sgtl5000_dt_ids,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001593 },
1594 .probe = sgtl5000_i2c_probe,
Bill Pemberton7a79e942012-12-07 09:26:37 -05001595 .remove = sgtl5000_i2c_remove,
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001596 .id_table = sgtl5000_id,
1597};
1598
Mark Brown67d45092012-04-03 22:35:18 +01001599module_i2c_driver(sgtl5000_i2c_driver);
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001600
1601MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
Zeng Zhaomingf7cb8a42012-01-16 15:18:11 +08001602MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001603MODULE_LICENSE("GPL");