| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Clocks for ux500 platforms |
| 3 | * |
| 4 | * Copyright (C) 2012 ST-Ericsson SA |
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> |
| 6 | * |
| 7 | * License terms: GNU General Public License (GPL) version 2 |
| 8 | */ |
| 9 | |
| 10 | #ifndef __UX500_CLK_H |
| 11 | #define __UX500_CLK_H |
| 12 | |
| 13 | #include <linux/clk.h> |
| Ulf Hansson | 5b82d03 | 2013-04-03 14:26:57 +0200 | [diff] [blame^] | 14 | #include <linux/device.h> |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 15 | |
| 16 | struct clk *clk_reg_prcc_pclk(const char *name, |
| 17 | const char *parent_name, |
| 18 | unsigned int phy_base, |
| 19 | u32 cg_sel, |
| 20 | unsigned long flags); |
| 21 | |
| 22 | struct clk *clk_reg_prcc_kclk(const char *name, |
| 23 | const char *parent_name, |
| 24 | unsigned int phy_base, |
| 25 | u32 cg_sel, |
| 26 | unsigned long flags); |
| 27 | |
| 28 | struct clk *clk_reg_prcmu_scalable(const char *name, |
| 29 | const char *parent_name, |
| 30 | u8 cg_sel, |
| 31 | unsigned long rate, |
| 32 | unsigned long flags); |
| 33 | |
| 34 | struct clk *clk_reg_prcmu_gate(const char *name, |
| 35 | const char *parent_name, |
| 36 | u8 cg_sel, |
| 37 | unsigned long flags); |
| 38 | |
| Ulf Hansson | a816d25 | 2012-10-10 13:42:27 +0200 | [diff] [blame] | 39 | struct clk *clk_reg_prcmu_scalable_rate(const char *name, |
| 40 | const char *parent_name, |
| 41 | u8 cg_sel, |
| 42 | unsigned long rate, |
| 43 | unsigned long flags); |
| 44 | |
| Ulf Hansson | 70b1fce | 2012-08-31 14:21:29 +0200 | [diff] [blame] | 45 | struct clk *clk_reg_prcmu_rate(const char *name, |
| 46 | const char *parent_name, |
| 47 | u8 cg_sel, |
| 48 | unsigned long flags); |
| 49 | |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 50 | struct clk *clk_reg_prcmu_opp_gate(const char *name, |
| 51 | const char *parent_name, |
| 52 | u8 cg_sel, |
| 53 | unsigned long flags); |
| 54 | |
| Ulf Hansson | b0ea0fc | 2012-09-24 16:43:18 +0200 | [diff] [blame] | 55 | struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, |
| 56 | const char *parent_name, |
| 57 | u8 cg_sel, |
| 58 | unsigned long rate, |
| 59 | unsigned long flags); |
| 60 | |
| Ulf Hansson | 5b82d03 | 2013-04-03 14:26:57 +0200 | [diff] [blame^] | 61 | struct clk *clk_reg_sysctrl_gate(struct device *dev, |
| 62 | const char *name, |
| 63 | const char *parent_name, |
| 64 | u16 reg_sel, |
| 65 | u8 reg_mask, |
| 66 | u8 reg_bits, |
| 67 | unsigned long enable_delay_us, |
| 68 | unsigned long flags); |
| 69 | |
| 70 | struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, |
| 71 | const char *name, |
| 72 | const char *parent_name, |
| 73 | u16 reg_sel, |
| 74 | u8 reg_mask, |
| 75 | u8 reg_bits, |
| 76 | unsigned long rate, |
| 77 | unsigned long enable_delay_us, |
| 78 | unsigned long flags); |
| 79 | |
| 80 | struct clk *clk_reg_sysctrl_set_parent(struct device *dev, |
| 81 | const char *name, |
| 82 | const char **parent_names, |
| 83 | u8 num_parents, |
| 84 | u16 *reg_sel, |
| 85 | u8 *reg_mask, |
| 86 | u8 *reg_bits, |
| 87 | unsigned long flags); |
| 88 | |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 89 | #endif /* __UX500_CLK_H */ |