Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 557c7ffa2f283166fa863aaa415757f5f485aa62 / . / drivers / clk / sunxi-ng / ccu-sun8i-r40.c
blob: 897490800102f3612b79d9c6e37efed0e74ef08e [file] [log] [blame]
Thomas Gleixner9c92ab62019-05-29 07:17:56 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]2/*
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]4 */
5
6#include <linux/clk-provider.h>
Stephen Boyd62e59c42019-04-18 15:20:22 -0700[diff] [blame]7#include <linux/io.h>
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]8#include <linux/platform_device.h>
9#include <linux/regmap.h>
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]10
11#include "ccu_common.h"
12#include "ccu_reset.h"
13
14#include "ccu_div.h"
15#include "ccu_gate.h"
16#include "ccu_mp.h"
17#include "ccu_mult.h"
18#include "ccu_nk.h"
19#include "ccu_nkm.h"
20#include "ccu_nkmp.h"
21#include "ccu_nm.h"
22#include "ccu_phase.h"
23
24#include "ccu-sun8i-r40.h"
25
26/* TODO: The result of N*K is required to be in [10, 88] range. */
27static struct ccu_nkmp pll_cpu_clk = {
28 .enable = BIT(31),
29 .lock = BIT(28),
30 .n = _SUNXI_CCU_MULT(8, 5),
31 .k = _SUNXI_CCU_MULT(4, 2),
32 .m = _SUNXI_CCU_DIV(0, 2),
33 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
34 .common = {
35 .reg = 0x000,
36 .hw.init = CLK_HW_INIT("pll-cpu",
37 "osc24M",
38 &ccu_nkmp_ops,
39 CLK_SET_RATE_UNGATE),
40 },
41};
42
43/*
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45 * the base (2x, 4x and 8x), and one variable divider (the one true
46 * pll audio).
47 *
48 * We don't have any need for the variable divider for now, so we just
49 * hardcode it to match with the clock names
50 */
51#define SUN8I_R40_PLL_AUDIO_REG 0x008
52
53static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
54 "osc24M", 0x008,
55 8, 7, /* N */
56 0, 5, /* M */
57 BIT(31), /* gate */
58 BIT(28), /* lock */
59 CLK_SET_RATE_UNGATE);
60
Jernej Skrabecb16fb662018-08-09 18:52:15 +0200[diff] [blame]61static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
62 "osc24M", 0x0010,
63 192000000, /* Minimum rate */
64 1008000000, /* Maximum rate */
65 8, 7, /* N */
66 0, 4, /* M */
67 BIT(24), /* frac enable */
68 BIT(25), /* frac select */
69 270000000, /* frac rate 0 */
70 297000000, /* frac rate 1 */
71 BIT(31), /* gate */
72 BIT(28), /* lock */
73 CLK_SET_RATE_UNGATE);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]74
75/* TODO: The result of N/M is required to be in [8, 25] range. */
76static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
77 "osc24M", 0x0018,
78 8, 7, /* N */
79 0, 4, /* M */
80 BIT(24), /* frac enable */
81 BIT(25), /* frac select */
82 270000000, /* frac rate 0 */
83 297000000, /* frac rate 1 */
84 BIT(31), /* gate */
85 BIT(28), /* lock */
86 CLK_SET_RATE_UNGATE);
87
88/* TODO: The result of N*K is required to be in [10, 77] range. */
89static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
90 "osc24M", 0x020,
91 8, 5, /* N */
92 4, 2, /* K */
93 0, 2, /* M */
94 BIT(31), /* gate */
95 BIT(28), /* lock */
96 CLK_SET_RATE_UNGATE);
97
98/* TODO: The result of N*K is required to be in [21, 58] range. */
99static struct ccu_nk pll_periph0_clk = {
100 .enable = BIT(31),
101 .lock = BIT(28),
102 .n = _SUNXI_CCU_MULT(8, 5),
103 .k = _SUNXI_CCU_MULT(4, 2),
104 .fixed_post_div = 2,
105 .common = {
106 .reg = 0x028,
107 .features = CCU_FEATURE_FIXED_POSTDIV,
108 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
109 &ccu_nk_ops,
110 CLK_SET_RATE_UNGATE),
111 },
112};
113
114static struct ccu_div pll_periph0_sata_clk = {
115 .enable = BIT(24),
116 .div = _SUNXI_CCU_DIV(0, 2),
117 /*
118 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
119 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
120 * 6/2 = 3.
121 */
122 .fixed_post_div = 3,
123 .common = {
124 .reg = 0x028,
125 .features = CCU_FEATURE_FIXED_POSTDIV,
126 .hw.init = CLK_HW_INIT("pll-periph0-sata",
127 "pll-periph0",
128 &ccu_div_ops, 0),
129 },
130};
131
132/* TODO: The result of N*K is required to be in [21, 58] range. */
133static struct ccu_nk pll_periph1_clk = {
134 .enable = BIT(31),
135 .lock = BIT(28),
136 .n = _SUNXI_CCU_MULT(8, 5),
137 .k = _SUNXI_CCU_MULT(4, 2),
138 .fixed_post_div = 2,
139 .common = {
140 .reg = 0x02c,
141 .features = CCU_FEATURE_FIXED_POSTDIV,
142 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
143 &ccu_nk_ops,
144 CLK_SET_RATE_UNGATE),
145 },
146};
147
Jernej Skrabecb16fb662018-08-09 18:52:15 +0200[diff] [blame]148static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
149 "osc24M", 0x030,
150 192000000, /* Minimum rate */
151 1008000000, /* Maximum rate */
152 8, 7, /* N */
153 0, 4, /* M */
154 BIT(24), /* frac enable */
155 BIT(25), /* frac select */
156 270000000, /* frac rate 0 */
157 297000000, /* frac rate 1 */
158 BIT(31), /* gate */
159 BIT(28), /* lock */
160 CLK_SET_RATE_UNGATE);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]161
162static struct ccu_nkm pll_sata_clk = {
163 .enable = BIT(31),
164 .lock = BIT(28),
165 .n = _SUNXI_CCU_MULT(8, 5),
166 .k = _SUNXI_CCU_MULT(4, 2),
167 .m = _SUNXI_CCU_DIV(0, 2),
168 .fixed_post_div = 6,
169 .common = {
170 .reg = 0x034,
171 .features = CCU_FEATURE_FIXED_POSTDIV,
172 .hw.init = CLK_HW_INIT("pll-sata", "osc24M",
173 &ccu_nkm_ops,
174 CLK_SET_RATE_UNGATE),
175 },
176};
177
178static const char * const pll_sata_out_parents[] = { "pll-sata",
179 "pll-periph0-sata" };
180static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
181 pll_sata_out_parents, 0x034,
182 30, 1, /* mux */
183 BIT(14), /* gate */
184 CLK_SET_RATE_PARENT);
185
186/* TODO: The result of N/M is required to be in [8, 25] range. */
187static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
188 "osc24M", 0x038,
189 8, 7, /* N */
190 0, 4, /* M */
191 BIT(24), /* frac enable */
192 BIT(25), /* frac select */
193 270000000, /* frac rate 0 */
194 297000000, /* frac rate 1 */
195 BIT(31), /* gate */
196 BIT(28), /* lock */
197 CLK_SET_RATE_UNGATE);
198
199/*
200 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
201 *
202 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
203 * integer / fractional clock with switchable multipliers and dividers.
204 * This is not supported here. We hardcode the PLL to MIPI mode.
205 *
206 * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
207 * which cannot be implemented now.
208 */
209#define SUN8I_R40_PLL_MIPI_REG 0x040
210
211static const char * const pll_mipi_parents[] = { "pll-video0" };
212static struct ccu_nkm pll_mipi_clk = {
213 .enable = BIT(31) | BIT(23) | BIT(22),
214 .lock = BIT(28),
215 .n = _SUNXI_CCU_MULT(8, 4),
216 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
217 .m = _SUNXI_CCU_DIV(0, 4),
218 .mux = _SUNXI_CCU_MUX(21, 1),
219 .common = {
220 .reg = 0x040,
221 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
222 pll_mipi_parents,
223 &ccu_nkm_ops,
224 CLK_SET_RATE_UNGATE)
225 },
226};
227
228/* TODO: The result of N/M is required to be in [8, 25] range. */
229static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
230 "osc24M", 0x048,
231 8, 7, /* N */
232 0, 4, /* M */
233 BIT(24), /* frac enable */
234 BIT(25), /* frac select */
235 270000000, /* frac rate 0 */
236 297000000, /* frac rate 1 */
237 BIT(31), /* gate */
238 BIT(28), /* lock */
239 CLK_SET_RATE_UNGATE);
240
241/* TODO: The N factor is required to be in [16, 75] range. */
242static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
243 "osc24M", 0x04c,
244 8, 7, /* N */
245 0, 2, /* M */
246 BIT(31), /* gate */
247 BIT(28), /* lock */
248 CLK_SET_RATE_UNGATE);
249
250static const char * const cpu_parents[] = { "osc32k", "osc24M",
251 "pll-cpu", "pll-cpu" };
252static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
253 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
254
255static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
256
257static const char * const ahb1_parents[] = { "osc32k", "osc24M",
258 "axi", "pll-periph0" };
259static const struct ccu_mux_var_prediv ahb1_predivs[] = {
260 { .index = 3, .shift = 6, .width = 2 },
261};
262static struct ccu_div ahb1_clk = {
263 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
264
265 .mux = {
266 .shift = 12,
267 .width = 2,
268
269 .var_predivs = ahb1_predivs,
270 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
271 },
272
273 .common = {
274 .reg = 0x054,
275 .features = CCU_FEATURE_VARIABLE_PREDIV,
276 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
277 ahb1_parents,
278 &ccu_div_ops,
279 0),
280 },
281};
282
283static struct clk_div_table apb1_div_table[] = {
284 { .val = 0, .div = 2 },
285 { .val = 1, .div = 2 },
286 { .val = 2, .div = 4 },
287 { .val = 3, .div = 8 },
288 { /* Sentinel */ },
289};
290static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
291 0x054, 8, 2, apb1_div_table, 0);
292
293static const char * const apb2_parents[] = { "osc32k", "osc24M",
294 "pll-periph0-2x",
295 "pll-periph0-2x" };
296static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
297 0, 5, /* M */
298 16, 2, /* P */
299 24, 2, /* mux */
300 0);
301
302static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
303 0x060, BIT(1), 0);
304static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
305 0x060, BIT(5), 0);
306static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
307 0x060, BIT(6), 0);
308static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
309 0x060, BIT(8), 0);
310static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
311 0x060, BIT(9), 0);
312static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
313 0x060, BIT(10), 0);
314static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
315 0x060, BIT(11), 0);
316static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
317 0x060, BIT(13), 0);
318static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
319 0x060, BIT(14), 0);
320static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
321 0x060, BIT(17), 0);
322static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
323 0x060, BIT(18), 0);
324static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
325 0x060, BIT(19), 0);
326static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
327 0x060, BIT(20), 0);
328static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
329 0x060, BIT(21), 0);
330static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
331 0x060, BIT(22), 0);
332static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
333 0x060, BIT(23), 0);
334static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
335 0x060, BIT(24), 0);
336static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
337 0x060, BIT(25), 0);
338static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
339 0x060, BIT(26), 0);
340static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
341 0x060, BIT(27), 0);
342static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
343 0x060, BIT(28), 0);
344static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
345 0x060, BIT(29), 0);
346static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
347 0x060, BIT(30), 0);
348static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
349 0x060, BIT(31), 0);
350
351static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
352 0x064, BIT(0), 0);
353static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
354 0x064, BIT(2), 0);
355static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
356 0x064, BIT(5), 0);
357static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
358 0x064, BIT(8), 0);
359static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
360 0x064, BIT(9), 0);
361static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
362 0x064, BIT(10), 0);
363static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
364 0x064, BIT(11), 0);
365static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
366 0x064, BIT(12), 0);
367static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
368 0x064, BIT(13), 0);
369static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
370 0x064, BIT(14), 0);
371static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
372 0x064, BIT(15), 0);
373static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
374 0x064, BIT(17), 0);
375static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
376 0x064, BIT(20), 0);
377static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
378 0x064, BIT(21), 0);
379static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
380 0x064, BIT(22), 0);
381static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
382 0x064, BIT(23), 0);
383static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
384 0x064, BIT(24), 0);
385static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
386 0x064, BIT(25), 0);
387static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
388 0x064, BIT(26), 0);
389static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
390 0x064, BIT(27), 0);
391static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
392 0x064, BIT(28), 0);
393static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
394 0x064, BIT(29), 0);
395static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
396 0x064, BIT(30), 0);
397
398static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
399 0x068, BIT(0), 0);
400static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
401 0x068, BIT(1), 0);
402static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
403 0x068, BIT(2), 0);
404static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
405 0x068, BIT(5), 0);
406static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
407 0x068, BIT(6), 0);
408static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
409 0x068, BIT(7), 0);
410static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
411 0x068, BIT(8), 0);
412static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
413 0x068, BIT(10), 0);
414static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
415 0x068, BIT(12), 0);
416static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
417 0x068, BIT(13), 0);
418static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
419 0x068, BIT(14), 0);
420
421static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
422 0x06c, BIT(0), 0);
423static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
424 0x06c, BIT(1), 0);
425static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
426 0x06c, BIT(2), 0);
427static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
428 0x06c, BIT(3), 0);
429/*
430 * In datasheet here's "Reserved", however the gate exists in BSP soucre
431 * code.
432 */
433static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
434 0x06c, BIT(4), 0);
435static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
436 0x06c, BIT(5), 0);
437static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
438 0x06c, BIT(6), 0);
439static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
440 0x06c, BIT(7), 0);
441static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
442 0x06c, BIT(15), 0);
443static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
444 0x06c, BIT(16), 0);
445static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
446 0x06c, BIT(17), 0);
447static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
448 0x06c, BIT(18), 0);
449static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
450 0x06c, BIT(19), 0);
451static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
452 0x06c, BIT(20), 0);
453static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
454 0x06c, BIT(21), 0);
455static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
456 0x06c, BIT(22), 0);
457static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
458 0x06c, BIT(23), 0);
459
460static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
461 0x070, BIT(7), 0);
462
463static const char * const ths_parents[] = { "osc24M" };
464static struct ccu_div ths_clk = {
465 .enable = BIT(31),
466 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
467 .mux = _SUNXI_CCU_MUX(24, 2),
468 .common = {
469 .reg = 0x074,
470 .hw.init = CLK_HW_INIT_PARENTS("ths",
471 ths_parents,
472 &ccu_div_ops,
473 0),
474 },
475};
476
477static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
478 "pll-periph1" };
479static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
480 0, 4, /* M */
481 16, 2, /* P */
482 24, 2, /* mux */
483 BIT(31), /* gate */
484 0);
485
486static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
487 0, 4, /* M */
488 16, 2, /* P */
489 24, 2, /* mux */
490 BIT(31), /* gate */
491 0);
492
493static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
494 0, 4, /* M */
495 16, 2, /* P */
496 24, 2, /* mux */
497 BIT(31), /* gate */
498 0);
499
500static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
501 0, 4, /* M */
502 16, 2, /* P */
503 24, 2, /* mux */
504 BIT(31), /* gate */
505 0);
506
507static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
508 0, 4, /* M */
509 16, 2, /* P */
510 24, 2, /* mux */
511 BIT(31), /* gate */
512 0);
513
514static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
515static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
516 0, 4, /* M */
517 16, 2, /* P */
518 24, 4, /* mux */
519 BIT(31), /* gate */
520 0);
521
522static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
523 "pll-periph1-2x" };
524static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
525 0, 4, /* M */
526 16, 2, /* P */
527 24, 2, /* mux */
528 BIT(31), /* gate */
529 0);
530
531static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
532 0, 4, /* M */
533 16, 2, /* P */
534 24, 2, /* mux */
535 BIT(31), /* gate */
536 0);
537
538static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
539 0, 4, /* M */
540 16, 2, /* P */
541 24, 2, /* mux */
542 BIT(31), /* gate */
543 0);
544
545static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
546 0, 4, /* M */
547 16, 2, /* P */
548 24, 2, /* mux */
549 BIT(31), /* gate */
550 0);
551
552static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
553 0, 4, /* M */
554 16, 2, /* P */
555 24, 2, /* mux */
556 BIT(31), /* gate */
557 0);
558
559static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
560 "pll-audio-2x", "pll-audio" };
561static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
562 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
563
564static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
565 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
566
567static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
568 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
569
570static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
571 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
572
573static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
574 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
575
576static const char * const keypad_parents[] = { "osc24M", "osc32k" };
577static const u8 keypad_table[] = { 0, 2 };
578static struct ccu_mp keypad_clk = {
579 .enable = BIT(31),
580 .m = _SUNXI_CCU_DIV(0, 5),
581 .p = _SUNXI_CCU_DIV(16, 2),
582 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
583 .common = {
584 .reg = 0x0c4,
585 .hw.init = CLK_HW_INIT_PARENTS("keypad",
586 keypad_parents,
587 &ccu_mp_ops,
588 0),
589 }
590};
591
592static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
593static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
594 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
595
596/*
597 * There are 3 OHCI 12M clock source selection bits in this register.
598 * We will force them to 0 (12M divided from 48M).
599 */
600#define SUN8I_R40_USB_CLK_REG 0x0cc
601
602static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
603 0x0cc, BIT(8), 0);
604static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
605 0x0cc, BIT(9), 0);
606static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
607 0x0cc, BIT(10), 0);
608static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
609 0x0cc, BIT(16), 0);
610static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
611 0x0cc, BIT(17), 0);
612static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
613 0x0cc, BIT(18), 0);
614
615static const char * const ir_parents[] = { "osc24M", "pll-periph0",
616 "pll-periph1", "osc32k" };
617static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
618 0, 4, /* M */
619 16, 2, /* P */
620 24, 2, /* mux */
621 BIT(31), /* gate */
622 0);
623
624static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
625 0, 4, /* M */
626 16, 2, /* P */
627 24, 2, /* mux */
628 BIT(31), /* gate */
629 0);
630
631static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
632static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
633 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
634
635static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
636 0x100, BIT(0), 0);
637static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
638 0x100, BIT(1), 0);
639static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
640 0x100, BIT(2), 0);
641static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
642 0x100, BIT(3), 0);
643static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
644 0x100, BIT(4), 0);
645static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
646 0x100, BIT(5), 0);
647static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
648 0x100, BIT(6), 0);
649
650static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
651static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
Jernej Skrabecfb4aa0f2018-06-25 14:02:42 +0200[diff] [blame]652 0x104, 0, 4, 24, 3, BIT(31),
653 CLK_SET_RATE_PARENT);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]654static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
655 0x108, 0, 4, 24, 3, BIT(31), 0);
656
657static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
658 "pll-video0-2x", "pll-video1-2x",
659 "pll-mipi" };
660static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
661 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
662static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
663 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
664static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
Jernej Skrabecfb4aa0f2018-06-25 14:02:42 +0200[diff] [blame]665 0x118, 0, 4, 24, 3, BIT(31),
666 CLK_SET_RATE_PARENT);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]667static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
Jernej Skrabecfb4aa0f2018-06-25 14:02:42 +0200[diff] [blame]668 0x11c, 0, 4, 24, 3, BIT(31),
669 CLK_SET_RATE_PARENT);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]670
671static const char * const deinterlace_parents[] = { "pll-periph0",
672 "pll-periph1" };
673static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
674 deinterlace_parents, 0x124, 0, 4, 24, 3,
675 BIT(31), 0);
676
677static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
678 "pll-periph1" };
679static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
680 0x130, 0, 5, 8, 3, BIT(15), 0);
681
682static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
683static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
684 0x134, 16, 4, 24, 3, BIT(31), 0);
685
686static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
687 0x134, 0, 5, 8, 3, BIT(15), 0);
688
689static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
690 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
691
692static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
693 0x140, BIT(31), CLK_SET_RATE_PARENT);
694static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
695 0x144, BIT(31), 0);
696
697static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
698static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
Jernej Skrabecfb4aa0f2018-06-25 14:02:42 +0200[diff] [blame]699 0x150, 0, 4, 24, 2, BIT(31),
700 CLK_SET_RATE_PARENT);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]701
702static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
703 0x154, BIT(31), 0);
704
705/*
706 * In the SoC's user manual, the P factor is mentioned, but not used in
707 * the frequency formula.
708 *
709 * Here the factor is included, according to the BSP kernel source,
710 * which contains the P factor of this clock.
711 */
712static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
713 "pll-ddr0" };
714static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
715 0, 4, /* M */
716 16, 2, /* P */
717 24, 2, /* mux */
718 BIT(31), /* gate */
719 CLK_IS_CRITICAL);
720
721static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
722 "pll-periph0" };
723static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
724 0x168, 0, 4, 8, 2, BIT(15), 0);
725
726static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
727 0x180, 0, 4, 24, 3, BIT(31), 0);
728static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
729 0x184, 0, 4, 24, 3, BIT(31), 0);
730
731static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
732 "pll-video0-2x", "pll-video1-2x" };
733static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
734 0x188, 0, 4, 24, 3, BIT(31), 0);
735static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
736 0x18c, 0, 4, 24, 3, BIT(31), 0);
737static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
738 0x190, 0, 4, 24, 3, BIT(31), 0);
739static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
740 0x194, 0, 4, 24, 3, BIT(31), 0);
741
742static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
743 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
744
745static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
746static const struct ccu_mux_fixed_prediv out_predivs[] = {
747 { .index = 0, .div = 750, },
748};
749
750static struct ccu_mp outa_clk = {
751 .enable = BIT(31),
752 .m = _SUNXI_CCU_DIV(8, 5),
753 .p = _SUNXI_CCU_DIV(20, 2),
754 .mux = {
755 .shift = 24,
756 .width = 2,
757 .fixed_predivs = out_predivs,
758 .n_predivs = ARRAY_SIZE(out_predivs),
759 },
760 .common = {
761 .reg = 0x1f0,
762 .features = CCU_FEATURE_FIXED_PREDIV,
763 .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents,
764 &ccu_mp_ops, 0),
765 }
766};
767
768static struct ccu_mp outb_clk = {
769 .enable = BIT(31),
770 .m = _SUNXI_CCU_DIV(8, 5),
771 .p = _SUNXI_CCU_DIV(20, 2),
772 .mux = {
773 .shift = 24,
774 .width = 2,
775 .fixed_predivs = out_predivs,
776 .n_predivs = ARRAY_SIZE(out_predivs),
777 },
778 .common = {
779 .reg = 0x1f4,
780 .features = CCU_FEATURE_FIXED_PREDIV,
781 .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents,
782 &ccu_mp_ops, 0),
783 }
784};
785
786static struct ccu_common *sun8i_r40_ccu_clks[] = {
787 &pll_cpu_clk.common,
788 &pll_audio_base_clk.common,
789 &pll_video0_clk.common,
790 &pll_ve_clk.common,
791 &pll_ddr0_clk.common,
792 &pll_periph0_clk.common,
793 &pll_periph0_sata_clk.common,
794 &pll_periph1_clk.common,
795 &pll_video1_clk.common,
796 &pll_sata_clk.common,
797 &pll_sata_out_clk.common,
798 &pll_gpu_clk.common,
799 &pll_mipi_clk.common,
800 &pll_de_clk.common,
801 &pll_ddr1_clk.common,
802 &cpu_clk.common,
803 &axi_clk.common,
804 &ahb1_clk.common,
805 &apb1_clk.common,
806 &apb2_clk.common,
807 &bus_mipi_dsi_clk.common,
808 &bus_ce_clk.common,
809 &bus_dma_clk.common,
810 &bus_mmc0_clk.common,
811 &bus_mmc1_clk.common,
812 &bus_mmc2_clk.common,
813 &bus_mmc3_clk.common,
814 &bus_nand_clk.common,
815 &bus_dram_clk.common,
816 &bus_emac_clk.common,
817 &bus_ts_clk.common,
818 &bus_hstimer_clk.common,
819 &bus_spi0_clk.common,
820 &bus_spi1_clk.common,
821 &bus_spi2_clk.common,
822 &bus_spi3_clk.common,
823 &bus_sata_clk.common,
824 &bus_otg_clk.common,
825 &bus_ehci0_clk.common,
826 &bus_ehci1_clk.common,
827 &bus_ehci2_clk.common,
828 &bus_ohci0_clk.common,
829 &bus_ohci1_clk.common,
830 &bus_ohci2_clk.common,
831 &bus_ve_clk.common,
832 &bus_mp_clk.common,
833 &bus_deinterlace_clk.common,
834 &bus_csi0_clk.common,
835 &bus_csi1_clk.common,
836 &bus_hdmi0_clk.common,
837 &bus_hdmi1_clk.common,
838 &bus_de_clk.common,
839 &bus_tve0_clk.common,
840 &bus_tve1_clk.common,
841 &bus_tve_top_clk.common,
842 &bus_gmac_clk.common,
843 &bus_gpu_clk.common,
844 &bus_tvd0_clk.common,
845 &bus_tvd1_clk.common,
846 &bus_tvd2_clk.common,
847 &bus_tvd3_clk.common,
848 &bus_tvd_top_clk.common,
849 &bus_tcon_lcd0_clk.common,
850 &bus_tcon_lcd1_clk.common,
851 &bus_tcon_tv0_clk.common,
852 &bus_tcon_tv1_clk.common,
853 &bus_tcon_top_clk.common,
854 &bus_codec_clk.common,
855 &bus_spdif_clk.common,
856 &bus_ac97_clk.common,
857 &bus_pio_clk.common,
858 &bus_ir0_clk.common,
859 &bus_ir1_clk.common,
860 &bus_ths_clk.common,
861 &bus_keypad_clk.common,
862 &bus_i2s0_clk.common,
863 &bus_i2s1_clk.common,
864 &bus_i2s2_clk.common,
865 &bus_i2c0_clk.common,
866 &bus_i2c1_clk.common,
867 &bus_i2c2_clk.common,
868 &bus_i2c3_clk.common,
869 &bus_can_clk.common,
870 &bus_scr_clk.common,
871 &bus_ps20_clk.common,
872 &bus_ps21_clk.common,
873 &bus_i2c4_clk.common,
874 &bus_uart0_clk.common,
875 &bus_uart1_clk.common,
876 &bus_uart2_clk.common,
877 &bus_uart3_clk.common,
878 &bus_uart4_clk.common,
879 &bus_uart5_clk.common,
880 &bus_uart6_clk.common,
881 &bus_uart7_clk.common,
882 &bus_dbg_clk.common,
883 &ths_clk.common,
884 &nand_clk.common,
885 &mmc0_clk.common,
886 &mmc1_clk.common,
887 &mmc2_clk.common,
888 &mmc3_clk.common,
889 &ts_clk.common,
890 &ce_clk.common,
891 &spi0_clk.common,
892 &spi1_clk.common,
893 &spi2_clk.common,
894 &spi3_clk.common,
895 &i2s0_clk.common,
896 &i2s1_clk.common,
897 &i2s2_clk.common,
898 &ac97_clk.common,
899 &spdif_clk.common,
900 &keypad_clk.common,
901 &sata_clk.common,
902 &usb_phy0_clk.common,
903 &usb_phy1_clk.common,
904 &usb_phy2_clk.common,
905 &usb_ohci0_clk.common,
906 &usb_ohci1_clk.common,
907 &usb_ohci2_clk.common,
908 &ir0_clk.common,
909 &ir1_clk.common,
910 &dram_clk.common,
911 &dram_ve_clk.common,
912 &dram_csi0_clk.common,
913 &dram_csi1_clk.common,
914 &dram_ts_clk.common,
915 &dram_tvd_clk.common,
916 &dram_mp_clk.common,
917 &dram_deinterlace_clk.common,
918 &de_clk.common,
919 &mp_clk.common,
920 &tcon_lcd0_clk.common,
921 &tcon_lcd1_clk.common,
922 &tcon_tv0_clk.common,
923 &tcon_tv1_clk.common,
924 &deinterlace_clk.common,
925 &csi1_mclk_clk.common,
926 &csi_sclk_clk.common,
927 &csi0_mclk_clk.common,
928 &ve_clk.common,
929 &codec_clk.common,
930 &avs_clk.common,
931 &hdmi_clk.common,
932 &hdmi_slow_clk.common,
933 &mbus_clk.common,
934 &dsi_dphy_clk.common,
935 &tve0_clk.common,
936 &tve1_clk.common,
937 &tvd0_clk.common,
938 &tvd1_clk.common,
939 &tvd2_clk.common,
940 &tvd3_clk.common,
941 &gpu_clk.common,
942 &outa_clk.common,
943 &outb_clk.common,
944};
945
946/* Fixed Factor clocks */
Chen-Yu Tsai3fccf2e2019-05-03 18:07:52 +0800[diff] [blame]947static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
948
949static const struct clk_hw *clk_parent_pll_audio[] = {
950 &pll_audio_base_clk.common.hw
951};
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]952
953/* We hardcode the divider to 4 for now */
Chen-Yu Tsai3fccf2e2019-05-03 18:07:52 +0800[diff] [blame]954static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
955 clk_parent_pll_audio,
956 4, 1, CLK_SET_RATE_PARENT);
957static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
958 clk_parent_pll_audio,
959 2, 1, CLK_SET_RATE_PARENT);
960static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
961 clk_parent_pll_audio,
962 1, 1, CLK_SET_RATE_PARENT);
963static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
964 clk_parent_pll_audio,
965 1, 2, CLK_SET_RATE_PARENT);
966static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
967 &pll_periph0_clk.common.hw,
968 1, 2, 0);
969static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
970 &pll_periph1_clk.common.hw,
971 1, 2, 0);
972static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
973 &pll_video0_clk.common.hw,
974 1, 2, 0);
975static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
976 &pll_video1_clk.common.hw,
977 1, 2, 0);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]978
979static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
980 .hws = {
981 [CLK_OSC_12M] = &osc12M_clk.hw,
982 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
983 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
984 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
985 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
986 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
987 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
988 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
989 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
990 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
991 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
992 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
993 [CLK_PLL_PERIPH0_SATA] = &pll_periph0_sata_clk.common.hw,
994 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
995 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
996 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
997 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
998 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
999 [CLK_PLL_SATA] = &pll_sata_clk.common.hw,
1000 [CLK_PLL_SATA_OUT] = &pll_sata_out_clk.common.hw,
1001 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
1002 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
1003 [CLK_PLL_DE] = &pll_de_clk.common.hw,
1004 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
1005 [CLK_CPU] = &cpu_clk.common.hw,
1006 [CLK_AXI] = &axi_clk.common.hw,
1007 [CLK_AHB1] = &ahb1_clk.common.hw,
1008 [CLK_APB1] = &apb1_clk.common.hw,
1009 [CLK_APB2] = &apb2_clk.common.hw,
1010 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
1011 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
1012 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
1013 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
1014 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
1015 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
1016 [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw,
1017 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
1018 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
1019 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
1020 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
1021 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
1022 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1023 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1024 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
1025 [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
1026 [CLK_BUS_SATA] = &bus_sata_clk.common.hw,
1027 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1028 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1029 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1030 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
1031 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1032 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1033 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
1034 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
1035 [CLK_BUS_MP] = &bus_mp_clk.common.hw,
1036 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
1037 [CLK_BUS_CSI0] = &bus_csi0_clk.common.hw,
1038 [CLK_BUS_CSI1] = &bus_csi1_clk.common.hw,
1039 [CLK_BUS_HDMI0] = &bus_hdmi0_clk.common.hw,
1040 [CLK_BUS_HDMI1] = &bus_hdmi1_clk.common.hw,
1041 [CLK_BUS_DE] = &bus_de_clk.common.hw,
1042 [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw,
1043 [CLK_BUS_TVE1] = &bus_tve1_clk.common.hw,
1044 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
1045 [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
1046 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
1047 [CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw,
1048 [CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw,
1049 [CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw,
1050 [CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw,
1051 [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
1052 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1053 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
1054 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
1055 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
1056 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
1057 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
1058 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1059 [CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
1060 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
1061 [CLK_BUS_IR0] = &bus_ir0_clk.common.hw,
1062 [CLK_BUS_IR1] = &bus_ir1_clk.common.hw,
1063 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1064 [CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw,
1065 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
1066 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
1067 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
1068 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1069 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1070 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1071 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1072 [CLK_BUS_CAN] = &bus_can_clk.common.hw,
1073 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
1074 [CLK_BUS_PS20] = &bus_ps20_clk.common.hw,
1075 [CLK_BUS_PS21] = &bus_ps21_clk.common.hw,
1076 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
1077 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
1078 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1079 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1080 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1081 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
1082 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
1083 [CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
1084 [CLK_BUS_UART7] = &bus_uart7_clk.common.hw,
1085 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
1086 [CLK_THS] = &ths_clk.common.hw,
1087 [CLK_NAND] = &nand_clk.common.hw,
1088 [CLK_MMC0] = &mmc0_clk.common.hw,
1089 [CLK_MMC1] = &mmc1_clk.common.hw,
1090 [CLK_MMC2] = &mmc2_clk.common.hw,
1091 [CLK_MMC3] = &mmc3_clk.common.hw,
1092 [CLK_TS] = &ts_clk.common.hw,
1093 [CLK_CE] = &ce_clk.common.hw,
1094 [CLK_SPI0] = &spi0_clk.common.hw,
1095 [CLK_SPI1] = &spi1_clk.common.hw,
1096 [CLK_SPI2] = &spi2_clk.common.hw,
1097 [CLK_SPI3] = &spi3_clk.common.hw,
1098 [CLK_I2S0] = &i2s0_clk.common.hw,
1099 [CLK_I2S1] = &i2s1_clk.common.hw,
1100 [CLK_I2S2] = &i2s2_clk.common.hw,
1101 [CLK_AC97] = &ac97_clk.common.hw,
1102 [CLK_SPDIF] = &spdif_clk.common.hw,
1103 [CLK_KEYPAD] = &keypad_clk.common.hw,
1104 [CLK_SATA] = &sata_clk.common.hw,
1105 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1106 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1107 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1108 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1109 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1110 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1111 [CLK_IR0] = &ir0_clk.common.hw,
1112 [CLK_IR1] = &ir1_clk.common.hw,
1113 [CLK_DRAM] = &dram_clk.common.hw,
1114 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1115 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1116 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1117 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1118 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1119 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1120 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
1121 [CLK_DE] = &de_clk.common.hw,
1122 [CLK_MP] = &mp_clk.common.hw,
1123 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1124 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
1125 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
1126 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
1127 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
1128 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1129 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1130 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1131 [CLK_VE] = &ve_clk.common.hw,
1132 [CLK_CODEC] = &codec_clk.common.hw,
1133 [CLK_AVS] = &avs_clk.common.hw,
1134 [CLK_HDMI] = &hdmi_clk.common.hw,
1135 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
1136 [CLK_MBUS] = &mbus_clk.common.hw,
1137 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
1138 [CLK_TVE0] = &tve0_clk.common.hw,
1139 [CLK_TVE1] = &tve1_clk.common.hw,
1140 [CLK_TVD0] = &tvd0_clk.common.hw,
1141 [CLK_TVD1] = &tvd1_clk.common.hw,
1142 [CLK_TVD2] = &tvd2_clk.common.hw,
1143 [CLK_TVD3] = &tvd3_clk.common.hw,
1144 [CLK_GPU] = &gpu_clk.common.hw,
1145 [CLK_OUTA] = &outa_clk.common.hw,
1146 [CLK_OUTB] = &outb_clk.common.hw,
1147 },
1148 .num = CLK_NUMBER,
1149};
1150
1151static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
1152 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1153 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1154 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1155
1156 [RST_DRAM] = { 0x0f4, BIT(31) },
1157 [RST_MBUS] = { 0x0fc, BIT(31) },
1158
1159 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
1160 [RST_BUS_CE] = { 0x2c0, BIT(5) },
1161 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
1162 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
1163 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
1164 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
1165 [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
1166 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
1167 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
1168 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
1169 [RST_BUS_TS] = { 0x2c0, BIT(18) },
1170 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
1171 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
1172 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
1173 [RST_BUS_SPI2] = { 0x2c0, BIT(22) },
1174 [RST_BUS_SPI3] = { 0x2c0, BIT(23) },
1175 [RST_BUS_SATA] = { 0x2c0, BIT(24) },
1176 [RST_BUS_OTG] = { 0x2c0, BIT(25) },
1177 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
1178 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
1179 [RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
1180 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
1181 [RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
1182 [RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
1183
1184 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1185 [RST_BUS_MP] = { 0x2c4, BIT(2) },
1186 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1187 [RST_BUS_CSI0] = { 0x2c4, BIT(8) },
1188 [RST_BUS_CSI1] = { 0x2c4, BIT(9) },
1189 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1190 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1191 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1192 [RST_BUS_TVE0] = { 0x2c4, BIT(13) },
1193 [RST_BUS_TVE1] = { 0x2c4, BIT(14) },
1194 [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
1195 [RST_BUS_GMAC] = { 0x2c4, BIT(17) },
1196 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1197 [RST_BUS_TVD0] = { 0x2c4, BIT(21) },
1198 [RST_BUS_TVD1] = { 0x2c4, BIT(22) },
1199 [RST_BUS_TVD2] = { 0x2c4, BIT(23) },
1200 [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
1201 [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
1202 [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) },
1203 [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) },
1204 [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) },
1205 [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) },
1206 [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
1207 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1208
1209 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
1210
1211 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1212 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1213 [RST_BUS_AC97] = { 0x2d0, BIT(2) },
1214 [RST_BUS_IR0] = { 0x2d0, BIT(6) },
1215 [RST_BUS_IR1] = { 0x2d0, BIT(7) },
1216 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1217 [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
1218 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1219 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1220 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1221
1222 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1223 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1224 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1225 [RST_BUS_I2C3] = { 0x2d8, BIT(3) },
1226 [RST_BUS_CAN] = { 0x2d8, BIT(4) },
1227 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
1228 [RST_BUS_PS20] = { 0x2d8, BIT(6) },
1229 [RST_BUS_PS21] = { 0x2d8, BIT(7) },
1230 [RST_BUS_I2C4] = { 0x2d8, BIT(15) },
1231 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1232 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1233 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1234 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1235 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
1236 [RST_BUS_UART5] = { 0x2d8, BIT(21) },
1237 [RST_BUS_UART6] = { 0x2d8, BIT(22) },
1238 [RST_BUS_UART7] = { 0x2d8, BIT(23) },
1239};
1240
1241static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
1242 .ccu_clks = sun8i_r40_ccu_clks,
1243 .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks),
1244
1245 .hw_clks = &sun8i_r40_hw_clks,
1246
1247 .resets = sun8i_r40_ccu_resets,
1248 .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
1249};
1250
1251static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
1252 .common = &pll_cpu_clk.common,
1253 /* copy from pll_cpu_clk */
1254 .enable = BIT(31),
1255 .lock = BIT(28),
1256};
1257
1258static struct ccu_mux_nb sun8i_r40_cpu_nb = {
1259 .common = &cpu_clk.common,
1260 .cm = &cpu_clk.mux,
1261 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1262 .bypass_index = 1, /* index of 24 MHz oscillator */
1263};
1264
Icenowy Zheng17de4c852018-05-02 00:12:14 +0800[diff] [blame]1265/*
1266 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1267 * GMAC configuration register.
1268 * Only this register is allowed to be written, in order to
1269 * prevent overriding critical clock configuration.
1270 */
1271
1272#define SUN8I_R40_GMAC_CFG_REG 0x164
1273static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
1274 unsigned int reg)
1275{
1276 if (reg == SUN8I_R40_GMAC_CFG_REG)
1277 return true;
1278 return false;
1279}
1280
1281static struct regmap_config sun8i_r40_ccu_regmap_config = {
1282 .reg_bits = 32,
1283 .val_bits = 32,
1284 .reg_stride = 4,
1285 .max_register = 0x320, /* PLL_LOCK_CTRL_REG */
1286
1287 /* other devices have no business accessing other registers */
1288 .readable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1289 .writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1290};
1291
Chen-Yu Tsai01a7ea72018-11-28 17:30:07 +0800[diff] [blame]1292#define SUN8I_R40_SYS_32K_CLK_REG 0x310
1293#define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
1294
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]1295static int sun8i_r40_ccu_probe(struct platform_device *pdev)
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]1296{
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]1297 struct resource *res;
Icenowy Zheng17de4c852018-05-02 00:12:14 +0800[diff] [blame]1298 struct regmap *regmap;
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]1299 void __iomem *reg;
1300 u32 val;
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]1301 int ret;
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]1302
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]1303 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1304 reg = devm_ioremap_resource(&pdev->dev, res);
1305 if (IS_ERR(reg))
1306 return PTR_ERR(reg);
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]1307
1308 /* Force the PLL-Audio-1x divider to 4 */
1309 val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
1310 val &= ~GENMASK(19, 16);
1311 writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
1312
1313 /* Force PLL-MIPI to MIPI mode */
1314 val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
1315 val &= ~BIT(16);
1316 writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
1317
1318 /* Force OHCI 12M parent to 12M divided from 48M */
1319 val = readl(reg + SUN8I_R40_USB_CLK_REG);
1320 val &= ~GENMASK(25, 20);
1321 writel(val, reg + SUN8I_R40_USB_CLK_REG);
1322
Chen-Yu Tsai01a7ea72018-11-28 17:30:07 +0800[diff] [blame]1323 /*
1324 * Force SYS 32k (otherwise known as LOSC throughout the CCU)
1325 * clock parent to LOSC output from RTC module instead of the
1326 * CCU's internal RC oscillator divided output.
1327 */
1328 writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
1329 reg + SUN8I_R40_SYS_32K_CLK_REG);
1330
Icenowy Zheng17de4c852018-05-02 00:12:14 +0800[diff] [blame]1331 regmap = devm_regmap_init_mmio(&pdev->dev, reg,
1332 &sun8i_r40_ccu_regmap_config);
1333 if (IS_ERR(regmap))
1334 return PTR_ERR(regmap);
1335
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]1336 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_r40_ccu_desc);
1337 if (ret)
1338 return ret;
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]1339
1340 /* Gate then ungate PLL CPU after any rate changes */
1341 ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
1342
1343 /* Reparent CPU during PLL CPU rate changes */
1344 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1345 &sun8i_r40_cpu_nb);
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]1346
1347 return 0;
Icenowy Zhengcd030a72017-08-15 13:55:29 +0800[diff] [blame]1348}
Icenowy Zhengc3bf29f2018-05-02 00:12:13 +0800[diff] [blame]1349
1350static const struct of_device_id sun8i_r40_ccu_ids[] = {
1351 { .compatible = "allwinner,sun8i-r40-ccu" },
1352 { }
1353};
1354
1355static struct platform_driver sun8i_r40_ccu_driver = {
1356 .probe = sun8i_r40_ccu_probe,
1357 .driver = {
1358 .name = "sun8i-r40-ccu",
1359 .of_match_table = sun8i_r40_ccu_ids,
1360 },
1361};
1362builtin_platform_driver(sun8i_r40_ccu_driver);