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Thomas Gleixner2b27bdc2019-05-29 16:57:50 -07001// SPDX-License-Identifier: GPL-2.0-only
Peter Ujfalusif9f8c042012-09-14 17:30:27 +03002/*
3* TWL6040 clock module driver for OMAP4 McPDM functional clock
4*
5* Copyright (C) 2012 Texas Instruments Inc.
6* Peter Ujfalusi <peter.ujfalusi@ti.com>
Peter Ujfalusif9f8c042012-09-14 17:30:27 +03007*/
8
Peter Ujfalusif9f8c042012-09-14 17:30:27 +03009#include <linux/module.h>
10#include <linux/slab.h>
11#include <linux/platform_device.h>
12#include <linux/mfd/twl6040.h>
13#include <linux/clk-provider.h>
14
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030015struct twl6040_pdmclk {
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030016 struct twl6040 *twl6040;
17 struct device *dev;
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030018 struct clk_hw pdmclk_hw;
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030019 int enabled;
20};
21
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030022static int twl6040_pdmclk_is_prepared(struct clk_hw *hw)
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030023{
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030024 struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
25 pdmclk_hw);
26
27 return pdmclk->enabled;
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030028}
29
Tony Lindgren5ae51d62019-02-11 14:59:07 -080030static int twl6040_pdmclk_reset_one_clock(struct twl6040_pdmclk *pdmclk,
31 unsigned int reg)
32{
33 const u8 reset_mask = TWL6040_HPLLRST; /* Same for HPPLL and LPPLL */
34 int ret;
35
36 ret = twl6040_set_bits(pdmclk->twl6040, reg, reset_mask);
37 if (ret < 0)
38 return ret;
39
40 ret = twl6040_clear_bits(pdmclk->twl6040, reg, reset_mask);
41 if (ret < 0)
42 return ret;
43
44 return 0;
45}
46
47/*
48 * TWL6040A2 Phoenix Audio IC erratum #6: "PDM Clock Generation Issue At
49 * Cold Temperature". This affects cold boot and deeper idle states it
50 * seems. The workaround consists of resetting HPPLL and LPPLL.
51 */
52static int twl6040_pdmclk_quirk_reset_clocks(struct twl6040_pdmclk *pdmclk)
53{
54 int ret;
55
56 ret = twl6040_pdmclk_reset_one_clock(pdmclk, TWL6040_REG_HPPLLCTL);
57 if (ret)
58 return ret;
59
60 ret = twl6040_pdmclk_reset_one_clock(pdmclk, TWL6040_REG_LPPLLCTL);
61 if (ret)
62 return ret;
63
64 return 0;
65}
66
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030067static int twl6040_pdmclk_prepare(struct clk_hw *hw)
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030068{
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030069 struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
70 pdmclk_hw);
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030071 int ret;
72
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030073 ret = twl6040_power(pdmclk->twl6040, 1);
Tony Lindgren5ae51d62019-02-11 14:59:07 -080074 if (ret)
75 return ret;
76
77 ret = twl6040_pdmclk_quirk_reset_clocks(pdmclk);
78 if (ret)
79 goto out_err;
80
81 pdmclk->enabled = 1;
82
83 return 0;
84
85out_err:
86 dev_err(pdmclk->dev, "%s: error %i\n", __func__, ret);
87 twl6040_power(pdmclk->twl6040, 0);
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030088
89 return ret;
90}
91
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030092static void twl6040_pdmclk_unprepare(struct clk_hw *hw)
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030093{
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030094 struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
95 pdmclk_hw);
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030096 int ret;
97
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +030098 ret = twl6040_power(pdmclk->twl6040, 0);
Peter Ujfalusif9f8c042012-09-14 17:30:27 +030099 if (!ret)
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300100 pdmclk->enabled = 0;
101
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300102}
103
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300104static unsigned long twl6040_pdmclk_recalc_rate(struct clk_hw *hw,
105 unsigned long parent_rate)
106{
107 struct twl6040_pdmclk *pdmclk = container_of(hw, struct twl6040_pdmclk,
108 pdmclk_hw);
109
110 return twl6040_get_sysclk(pdmclk->twl6040);
111}
112
113static const struct clk_ops twl6040_pdmclk_ops = {
114 .is_prepared = twl6040_pdmclk_is_prepared,
115 .prepare = twl6040_pdmclk_prepare,
116 .unprepare = twl6040_pdmclk_unprepare,
117 .recalc_rate = twl6040_pdmclk_recalc_rate,
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300118};
119
Bhumika Goyal07770662017-08-18 15:38:17 +0530120static const struct clk_init_data twl6040_pdmclk_init = {
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300121 .name = "pdmclk",
122 .ops = &twl6040_pdmclk_ops,
123 .flags = CLK_GET_RATE_NOCACHE,
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300124};
125
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300126static int twl6040_pdmclk_probe(struct platform_device *pdev)
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300127{
128 struct twl6040 *twl6040 = dev_get_drvdata(pdev->dev.parent);
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300129 struct twl6040_pdmclk *clkdata;
Stephen Boydf5b37152016-06-01 16:15:30 -0700130 int ret;
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300131
132 clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
133 if (!clkdata)
134 return -ENOMEM;
135
136 clkdata->dev = &pdev->dev;
137 clkdata->twl6040 = twl6040;
138
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300139 clkdata->pdmclk_hw.init = &twl6040_pdmclk_init;
Stephen Boydf5b37152016-06-01 16:15:30 -0700140 ret = devm_clk_hw_register(&pdev->dev, &clkdata->pdmclk_hw);
141 if (ret)
142 return ret;
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300143
Jingoo Hanc0431032013-05-24 10:11:46 +0900144 platform_set_drvdata(pdev, clkdata);
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300145
Matti Vaittinen654dea62018-12-04 13:38:32 +0200146 return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
147 &clkdata->pdmclk_hw);
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300148}
149
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300150static struct platform_driver twl6040_pdmclk_driver = {
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300151 .driver = {
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300152 .name = "twl6040-pdmclk",
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300153 },
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300154 .probe = twl6040_pdmclk_probe,
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300155};
156
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300157module_platform_driver(twl6040_pdmclk_driver);
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300158
159MODULE_DESCRIPTION("TWL6040 clock driver for McPDM functional clock");
160MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
Peter Ujfalusi7e37deb2016-05-30 11:55:11 +0300161MODULE_ALIAS("platform:twl6040-pdmclk");
Peter Ujfalusif9f8c042012-09-14 17:30:27 +0300162MODULE_LICENSE("GPL");