| Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.h |
| 3 | * |
| 4 | * Copyright (C) 2005 Texas Instruments Inc. |
| 5 | * Richard Woodruff <r-woodruff2@ti.com> |
| 6 | * Created for OMAP2. |
| 7 | * |
| 8 | * Copyright (C) 2004 Nokia corporation |
| 9 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 10 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
| 11 | * |
| 12 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 13 | * Copyright (C) 2007 Nokia Corporation |
| 14 | * Paul Walmsley |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
| 21 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 22 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H |
| 23 | |
| 24 | #include <asm/arch/clock.h> |
| 25 | |
| 26 | int omap2_clk_enable(struct clk *clk); |
| 27 | void omap2_clk_disable(struct clk *clk); |
| 28 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
| 29 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); |
| 30 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); |
| 31 | |
| 32 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 33 | void omap2_clk_disable_unused(struct clk *clk); |
| 34 | #else |
| 35 | #define omap2_clk_disable_unused NULL |
| 36 | #endif |
| 37 | |
| 38 | void omap2_clksel_recalc(struct clk *clk); |
| 39 | void omap2_init_clksel_parent(struct clk *clk); |
| 40 | u32 omap2_clksel_get_divisor(struct clk *clk); |
| 41 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, |
| 42 | u32 *new_div); |
| 43 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); |
| 44 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); |
| 45 | void omap2_fixed_divisor_recalc(struct clk *clk); |
| 46 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
| 47 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); |
| 48 | u32 omap2_get_dpll_rate(struct clk *clk); |
| 49 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
| 50 | |
| 51 | extern u8 cpu_mask; |
| 52 | |
| 53 | /* clksel_rate data common to 24xx/343x */ |
| 54 | static const struct clksel_rate gpt_32k_rates[] = { |
| 55 | { .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, |
| 56 | { .div = 0 } |
| 57 | }; |
| 58 | |
| 59 | static const struct clksel_rate gpt_sys_rates[] = { |
| 60 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, |
| 61 | { .div = 0 } |
| 62 | }; |
| 63 | |
| 64 | static const struct clksel_rate gfx_l3_rates[] = { |
| 65 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X }, |
| 66 | { .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, |
| 67 | { .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X }, |
| 68 | { .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X }, |
| 69 | { .div = 0 } |
| 70 | }; |
| 71 | |
| 72 | |
| 73 | #endif |