blob: e00f89e645f9112f50e3294e7c2d21489032000f [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Peter De Schrijveradd29e62011-10-12 14:53:05 +03003/include/ "tegra20.dtsi"
4
5/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +00006 model = "NVIDIA Tegra20 Ventana evaluation board";
Peter De Schrijveradd29e62011-10-12 14:53:05 +03007 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030011 };
12
Stephen Warren97d55202013-01-02 14:53:21 -070013 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060025 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060026 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma", "gme";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gmb", "spia",
44 "spib", "spic";
45 nvidia,function = "gmi";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp", "lm1";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
Stephen Warrenecc295b2012-03-15 16:27:36 -060079 dta {
80 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
81 nvidia,function = "vi";
82 };
83 dtf {
84 nvidia,pins = "dtf";
85 nvidia,function = "i2c3";
86 };
87 gmc {
88 nvidia,pins = "gmc";
89 nvidia,function = "uartd";
90 };
91 gmd {
92 nvidia,pins = "gmd";
93 nvidia,function = "sflash";
94 };
95 gpu {
96 nvidia,pins = "gpu";
97 nvidia,function = "pwm";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv", "slxa", "slxk";
105 nvidia,function = "pcie";
106 };
107 hdint {
Mark Zhangcf6334642012-10-25 14:52:30 +0800108 nvidia,pins = "hdint";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uartb";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
121 "kbce", "kbcf";
122 nvidia,function = "kbc";
123 };
124 lcsn {
125 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
126 "lsdi", "lvp0";
127 nvidia,function = "rsvd4";
128 };
129 ld0 {
130 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
131 "ld5", "ld6", "ld7", "ld8", "ld9",
132 "ld10", "ld11", "ld12", "ld13", "ld14",
133 "ld15", "ld16", "ld17", "ldi", "lhp0",
134 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
135 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
136 "lspi", "lvp1", "lvs";
137 nvidia,function = "displaya";
138 };
Mark Zhangcf6334642012-10-25 14:52:30 +0800139 owc {
140 nvidia,pins = "owc", "spdi", "spdo", "uac";
141 nvidia,function = "rsvd2";
142 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600143 pmc {
144 nvidia,pins = "pmc";
145 nvidia,function = "pwr_on";
146 };
147 rm {
148 nvidia,pins = "rm";
149 nvidia,function = "i2c1";
150 };
151 sdb {
152 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
153 nvidia,function = "sdio3";
154 };
155 sdio1 {
156 nvidia,pins = "sdio1";
157 nvidia,function = "sdio1";
158 };
159 slxd {
160 nvidia,pins = "slxd";
161 nvidia,function = "spdif";
162 };
163 spid {
164 nvidia,pins = "spid", "spie", "spif";
165 nvidia,function = "spi1";
166 };
167 spig {
168 nvidia,pins = "spig", "spih";
169 nvidia,function = "spi2_alt";
170 };
171 uaa {
172 nvidia,pins = "uaa", "uab", "uda";
173 nvidia,function = "ulpi";
174 };
175 uad {
176 nvidia,pins = "uad";
177 nvidia,function = "irda";
178 };
179 uca {
180 nvidia,pins = "uca", "ucb";
181 nvidia,function = "uartc";
182 };
183 conf_ata {
184 nvidia,pins = "ata", "atb", "atc", "atd",
185 "cdev1", "cdev2", "dap1", "dap2",
186 "dap4", "ddc", "dtf", "gma", "gmc",
187 "gme", "gpu", "gpu7", "i2cp", "irrx",
188 "irtx", "pta", "rm", "sdc", "sdd",
189 "slxc", "slxd", "slxk", "spdi", "spdo",
190 "uac", "uad", "uca", "ucb", "uda";
191 nvidia,pull = <0>;
192 nvidia,tristate = <0>;
193 };
194 conf_ate {
195 nvidia,pins = "ate", "csus", "dap3", "gmd",
196 "gpv", "owc", "spia", "spib", "spic",
197 "spid", "spie", "spig";
198 nvidia,pull = <0>;
199 nvidia,tristate = <1>;
200 };
201 conf_ck32 {
202 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
203 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
204 nvidia,pull = <0>;
205 };
206 conf_crtp {
207 nvidia,pins = "crtp", "gmb", "slxa", "spih";
208 nvidia,pull = <2>;
209 nvidia,tristate = <1>;
210 };
211 conf_dta {
212 nvidia,pins = "dta", "dtb", "dtc", "dtd";
213 nvidia,pull = <1>;
214 nvidia,tristate = <0>;
215 };
216 conf_dte {
217 nvidia,pins = "dte", "spif";
218 nvidia,pull = <1>;
219 nvidia,tristate = <1>;
220 };
221 conf_hdint {
222 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
223 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
224 nvidia,tristate = <1>;
225 };
226 conf_kbca {
227 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
228 "kbce", "kbcf", "sdio1", "uaa", "uab";
229 nvidia,pull = <2>;
230 nvidia,tristate = <0>;
231 };
232 conf_lc {
233 nvidia,pins = "lc", "ls";
234 nvidia,pull = <2>;
235 };
236 conf_ld0 {
237 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
238 "ld5", "ld6", "ld7", "ld8", "ld9",
239 "ld10", "ld11", "ld12", "ld13", "ld14",
240 "ld15", "ld16", "ld17", "ldi", "lhp0",
241 "lhp1", "lhp2", "lhs", "lm0", "lpp",
242 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
243 "lvp1", "lvs", "pmc", "sdb";
244 nvidia,tristate = <0>;
245 };
246 conf_ld17_0 {
247 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
248 "ld23_22";
249 nvidia,pull = <1>;
250 };
Wei Nic7294292012-09-21 16:54:58 +0800251 drive_sdio1 {
252 nvidia,pins = "drive_sdio1";
253 nvidia,high-speed-mode = <0>;
254 nvidia,schmitt = <1>;
255 nvidia,low-power-mode = <3>;
256 nvidia,pull-down-strength = <31>;
257 nvidia,pull-up-strength = <31>;
258 nvidia,slew-rate-rising = <3>;
259 nvidia,slew-rate-falling = <3>;
260 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600261 };
Mark Zhangcf6334642012-10-25 14:52:30 +0800262
263 state_i2cmux_ddc: pinmux_i2cmux_ddc {
264 ddc {
265 nvidia,pins = "ddc";
266 nvidia,function = "i2c2";
267 };
268 pta {
269 nvidia,pins = "pta";
270 nvidia,function = "rsvd4";
271 };
272 };
273
274 state_i2cmux_pta: pinmux_i2cmux_pta {
275 ddc {
276 nvidia,pins = "ddc";
277 nvidia,function = "rsvd4";
278 };
279 pta {
280 nvidia,pins = "pta";
281 nvidia,function = "i2c2";
282 };
283 };
284
285 state_i2cmux_idle: pinmux_i2cmux_idle {
286 ddc {
287 nvidia,pins = "ddc";
288 nvidia,function = "rsvd4";
289 };
290 pta {
291 nvidia,pins = "pta";
292 nvidia,function = "rsvd4";
293 };
294 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600295 };
296
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600297 i2s@70002800 {
298 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600299 };
300
301 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600302 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600303 };
304
Stephen Warren88950f3b2011-11-21 14:44:09 -0700305 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600306 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700307 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700308
309 wm8903: wm8903@1a {
310 compatible = "wlf,wm8903";
311 reg = <0x1a>;
312 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600313 interrupts = <187 0x04>;
Stephen Warren797acf72012-01-11 16:09:57 -0700314
315 gpio-controller;
316 #gpio-cells = <2>;
317
318 micdet-cfg = <0>;
319 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600320 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700321 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530322
323 /* ALS and proximity sensor */
324 isl29018@44 {
325 compatible = "isil,isl29018";
326 reg = <0x44>;
327 interrupt-parent = <&gpio>;
328 interrupts = <202 0x04>; /*gpio PZ2 */
329 };
Stephen Warren88950f3b2011-11-21 14:44:09 -0700330 };
331
332 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600333 status = "okay";
Stephen Warren97d55202013-01-02 14:53:21 -0700334 clock-frequency = <100000>;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700335 };
336
Mark Zhangcf6334642012-10-25 14:52:30 +0800337 i2cmux {
338 compatible = "i2c-mux-pinctrl";
339 #address-cells = <1>;
340 #size-cells = <0>;
341
342 i2c-parent = <&{/i2c@7000c400}>;
343
344 pinctrl-names = "ddc", "pta", "idle";
345 pinctrl-0 = <&state_i2cmux_ddc>;
346 pinctrl-1 = <&state_i2cmux_pta>;
347 pinctrl-2 = <&state_i2cmux_idle>;
348
Stephen Warren97d55202013-01-02 14:53:21 -0700349 hdmi_ddc: i2c@0 {
Mark Zhangcf6334642012-10-25 14:52:30 +0800350 reg = <0>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 };
354
355 i2c@1 {
356 reg = <1>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 };
360 };
361
Stephen Warren88950f3b2011-11-21 14:44:09 -0700362 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600363 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700364 clock-frequency = <400000>;
365 };
366
367 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600368 status = "okay";
Stephen Warren88950f3b2011-11-21 14:44:09 -0700369 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600370
371 pmic: tps6586x@34 {
372 compatible = "ti,tps6586x";
373 reg = <0x34>;
374 interrupts = <0 86 0x4>;
375
Stephen Warren44b12ef2012-09-11 11:42:26 -0600376 ti,system-power-controller;
377
Stephen Warren017a0102012-06-20 16:53:41 -0600378 #gpio-cells = <2>;
379 gpio-controller;
380
381 sys-supply = <&vdd_5v0_reg>;
382 vin-sm0-supply = <&sys_reg>;
383 vin-sm1-supply = <&sys_reg>;
384 vin-sm2-supply = <&sys_reg>;
385 vinldo01-supply = <&sm2_reg>;
386 vinldo23-supply = <&sm2_reg>;
387 vinldo4-supply = <&sm2_reg>;
388 vinldo678-supply = <&sm2_reg>;
389 vinldo9-supply = <&sm2_reg>;
390
391 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600392 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600393 regulator-name = "vdd_sys";
394 regulator-always-on;
395 };
396
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600397 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600398 regulator-name = "vdd_sm0,vdd_core";
399 regulator-min-microvolt = <1200000>;
400 regulator-max-microvolt = <1200000>;
401 regulator-always-on;
402 };
403
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600404 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600405 regulator-name = "vdd_sm1,vdd_cpu";
406 regulator-min-microvolt = <1000000>;
407 regulator-max-microvolt = <1000000>;
408 regulator-always-on;
409 };
410
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600411 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600412 regulator-name = "vdd_sm2,vin_ldo*";
413 regulator-min-microvolt = <3700000>;
414 regulator-max-microvolt = <3700000>;
415 regulator-always-on;
416 };
417
418 /* LDO0 is not connected to anything */
419
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600420 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600421 regulator-name = "vdd_ldo1,avdd_pll*";
422 regulator-min-microvolt = <1100000>;
423 regulator-max-microvolt = <1100000>;
424 regulator-always-on;
425 };
426
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600427 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600428 regulator-name = "vdd_ldo2,vdd_rtc";
429 regulator-min-microvolt = <1200000>;
430 regulator-max-microvolt = <1200000>;
431 };
432
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600433 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600434 regulator-name = "vdd_ldo3,avdd_usb*";
435 regulator-min-microvolt = <3300000>;
436 regulator-max-microvolt = <3300000>;
437 regulator-always-on;
438 };
439
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600440 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600441 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
442 regulator-min-microvolt = <1800000>;
443 regulator-max-microvolt = <1800000>;
444 regulator-always-on;
445 };
446
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600447 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600448 regulator-name = "vdd_ldo5,vcore_mmc";
449 regulator-min-microvolt = <2850000>;
450 regulator-max-microvolt = <2850000>;
451 regulator-always-on;
452 };
453
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600454 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600455 regulator-name = "vdd_ldo6,avdd_vdac";
456 regulator-min-microvolt = <1800000>;
457 regulator-max-microvolt = <1800000>;
458 };
459
Stephen Warren97d55202013-01-02 14:53:21 -0700460 hdmi_vdd_reg: ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600461 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
462 regulator-min-microvolt = <3300000>;
463 regulator-max-microvolt = <3300000>;
464 };
465
Stephen Warren97d55202013-01-02 14:53:21 -0700466 hdmi_pll_reg: ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600467 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
468 regulator-min-microvolt = <1800000>;
469 regulator-max-microvolt = <1800000>;
470 };
471
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600472 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600473 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
474 regulator-min-microvolt = <2850000>;
475 regulator-max-microvolt = <2850000>;
476 regulator-always-on;
477 };
478
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600479 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600480 regulator-name = "vdd_rtc_out,vdd_cell";
481 regulator-min-microvolt = <3300000>;
482 regulator-max-microvolt = <3300000>;
483 regulator-always-on;
484 };
485 };
486 };
Thierry Redingee9f7262012-11-09 23:01:21 +0100487
488 temperature-sensor@4c {
489 compatible = "onnn,nct1008";
490 reg = <0x4c>;
491 };
Stephen Warren017a0102012-06-20 16:53:41 -0600492 };
493
494 pmc {
495 nvidia,invert-interrupt;
Joseph Loa44a0192013-04-03 19:31:52 +0800496 nvidia,suspend-mode = <2>;
497 nvidia,cpu-pwr-good-time = <2000>;
498 nvidia,cpu-pwr-off-time = <100>;
499 nvidia,core-pwr-good-time = <3845 3845>;
500 nvidia,core-pwr-off-time = <458>;
501 nvidia,sys-clock-req-active-high;
Stephen Warren88950f3b2011-11-21 14:44:09 -0700502 };
503
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600504 usb@c5000000 {
505 status = "okay";
506 };
507
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530508 usb-phy@c5000000 {
509 status = "okay";
510 };
511
Stephen Warrenc04abb32012-05-11 17:03:26 -0600512 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600513 status = "okay";
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530514 nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
515 };
516
517 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530518 status = "okay";
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530519 nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600520 };
521
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600522 usb@c5008000 {
523 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600524 };
525
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530526 usb-phy@c5008000 {
527 status = "okay";
528 };
529
Wei Nic7294292012-09-21 16:54:58 +0800530 sdhci@c8000000 {
531 status = "okay";
532 power-gpios = <&gpio 86 0>; /* gpio PK6 */
533 bus-width = <4>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600534 keep-power-in-suspend;
Wei Nic7294292012-09-21 16:54:58 +0800535 };
536
Stephen Warrenc04abb32012-05-11 17:03:26 -0600537 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600538 status = "okay";
Joseph Lo908ab932013-02-22 11:23:39 +0800539 cd-gpios = <&gpio 69 1>; /* gpio PI5 */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600540 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
541 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200542 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600543 };
544
545 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600546 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200547 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600548 non-removable;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600549 };
550
Joseph Lo7021d122013-04-03 19:31:27 +0800551 clocks {
552 compatible = "simple-bus";
553 #address-cells = <1>;
554 #size-cells = <0>;
555
556 clk32k_in: clock {
557 compatible = "fixed-clock";
558 reg=<0>;
559 #clock-cells = <0>;
560 clock-frequency = <32768>;
561 };
562 };
563
Joseph Lo5741a252013-04-03 19:31:48 +0800564 gpio-keys {
565 compatible = "gpio-keys";
566
567 power {
568 label = "Power";
569 gpios = <&gpio 170 1>; /* gpio PV2, active low */
570 linux,code = <116>; /* KEY_POWER */
571 gpio-key,wakeup;
572 };
573 };
574
Stephen Warren017a0102012-06-20 16:53:41 -0600575 regulators {
576 compatible = "simple-bus";
577 #address-cells = <1>;
578 #size-cells = <0>;
579
580 vdd_5v0_reg: regulator@0 {
581 compatible = "regulator-fixed";
582 reg = <0>;
583 regulator-name = "vdd_5v0";
584 regulator-min-microvolt = <5000000>;
585 regulator-max-microvolt = <5000000>;
586 regulator-always-on;
587 };
588
589 regulator@1 {
590 compatible = "regulator-fixed";
591 reg = <1>;
592 regulator-name = "vdd_1v5";
593 regulator-min-microvolt = <1500000>;
594 regulator-max-microvolt = <1500000>;
595 gpio = <&pmic 0 0>;
596 };
597
598 regulator@2 {
599 compatible = "regulator-fixed";
600 reg = <2>;
601 regulator-name = "vdd_1v2";
602 regulator-min-microvolt = <1200000>;
603 regulator-max-microvolt = <1200000>;
604 gpio = <&pmic 1 0>;
605 enable-active-high;
606 };
607
608 regulator@3 {
609 compatible = "regulator-fixed";
610 reg = <3>;
611 regulator-name = "vdd_pnl";
612 regulator-min-microvolt = <2800000>;
613 regulator-max-microvolt = <2800000>;
614 gpio = <&gpio 22 0>; /* gpio PC6 */
615 enable-active-high;
616 };
617
618 regulator@4 {
619 compatible = "regulator-fixed";
620 reg = <4>;
621 regulator-name = "vdd_bl";
622 regulator-min-microvolt = <2800000>;
623 regulator-max-microvolt = <2800000>;
624 gpio = <&gpio 176 0>; /* gpio PW0 */
625 enable-active-high;
626 };
627 };
628
Stephen Warren797acf72012-01-11 16:09:57 -0700629 sound {
630 compatible = "nvidia,tegra-audio-wm8903-ventana",
631 "nvidia,tegra-audio-wm8903";
632 nvidia,model = "NVIDIA Tegra Ventana";
633
634 nvidia,audio-routing =
635 "Headphone Jack", "HPOUTR",
636 "Headphone Jack", "HPOUTL",
637 "Int Spk", "ROP",
638 "Int Spk", "RON",
639 "Int Spk", "LOP",
640 "Int Spk", "LON",
641 "Mic Jack", "MICBIAS",
642 "IN1L", "Mic Jack";
643
644 nvidia,i2s-controller = <&tegra_i2s1>;
645 nvidia,audio-codec = <&wm8903>;
646
647 nvidia,spkr-en-gpios = <&wm8903 2 0>;
648 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
Stephen Warrenc44e4382012-05-11 16:21:10 -0600649 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
Stephen Warren797acf72012-01-11 16:09:57 -0700650 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600651
Prashant Gaikwad1071b2d2013-04-04 14:35:04 +0530652 clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600653 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warren797acf72012-01-11 16:09:57 -0700654 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300655};