blob: 0371d3d5501a973f2d0a40573377b957974a318b [file] [log] [blame]
Vinod Koul71bb8a12017-12-14 11:19:43 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2// Copyright(c) 2015-17 Intel Corporation.
3
4/*
5 * Soundwire Intel Master Driver
6 */
7
8#include <linux/acpi.h>
Pierre-Louis Bossart79ee6632019-08-21 13:58:20 -05009#include <linux/debugfs.h>
Vinod Koul71bb8a12017-12-14 11:19:43 +053010#include <linux/delay.h>
Paul Gortmaker4abbd782019-04-13 11:12:52 -040011#include <linux/module.h>
Vinod Koul71bb8a12017-12-14 11:19:43 +053012#include <linux/interrupt.h>
Pierre-Louis Bossartdf72b712019-09-16 13:57:38 -050013#include <linux/io.h>
Vinod Koul71bb8a12017-12-14 11:19:43 +053014#include <linux/platform_device.h>
Vinod Koul37a2d222018-04-26 18:38:58 +053015#include <sound/pcm_params.h>
16#include <sound/soc.h>
Vinod Koul71bb8a12017-12-14 11:19:43 +053017#include <linux/soundwire/sdw_registers.h>
18#include <linux/soundwire/sdw.h>
19#include <linux/soundwire/sdw_intel.h>
20#include "cadence_master.h"
Pierre-Louis Bossart79ee6632019-08-21 13:58:20 -050021#include "bus.h"
Vinod Koul71bb8a12017-12-14 11:19:43 +053022#include "intel.h"
23
24/* Intel SHIM Registers Definition */
25#define SDW_SHIM_LCAP 0x0
26#define SDW_SHIM_LCTL 0x4
27#define SDW_SHIM_IPPTR 0x8
28#define SDW_SHIM_SYNC 0xC
29
Pierre-Louis Bossart7cc6e312019-05-01 10:57:39 -050030#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
31#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
32#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
33#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
34#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
35#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
Vinod Koul71bb8a12017-12-14 11:19:43 +053036
Pierre-Louis Bossart7cc6e312019-05-01 10:57:39 -050037#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
38#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
39#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
40#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
41#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
Vinod Koul71bb8a12017-12-14 11:19:43 +053042
43#define SDW_SHIM_WAKEEN 0x190
44#define SDW_SHIM_WAKESTS 0x192
45
46#define SDW_SHIM_LCTL_SPA BIT(0)
47#define SDW_SHIM_LCTL_CPA BIT(8)
48
49#define SDW_SHIM_SYNC_SYNCPRD_VAL 0x176F
50#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
51#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
52#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
53#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
54#define SDW_SHIM_SYNC_SYNCGO BIT(24)
55
56#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
57#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
58#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
59
60#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
61#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
62#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
63#define SDW_SHIM_PCMSYCM_DIR BIT(15)
64
65#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
66#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
67#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
68#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
69
70#define SDW_SHIM_IOCTL_MIF BIT(0)
71#define SDW_SHIM_IOCTL_CO BIT(1)
72#define SDW_SHIM_IOCTL_COE BIT(2)
73#define SDW_SHIM_IOCTL_DO BIT(3)
74#define SDW_SHIM_IOCTL_DOE BIT(4)
75#define SDW_SHIM_IOCTL_BKE BIT(5)
76#define SDW_SHIM_IOCTL_WPDD BIT(6)
77#define SDW_SHIM_IOCTL_CIBD BIT(8)
78#define SDW_SHIM_IOCTL_DIBD BIT(9)
79
80#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
81#define SDW_SHIM_CTMCTL_DODS BIT(1)
82#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
83
84#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
85#define SDW_SHIM_WAKESTS_STATUS BIT(0)
86
87/* Intel ALH Register definitions */
Pierre-Louis Bossart7cc6e312019-05-01 10:57:39 -050088#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
Pierre-Louis Bossart79ee6632019-08-21 13:58:20 -050089#define SDW_ALH_NUM_STREAMS 64
Vinod Koul71bb8a12017-12-14 11:19:43 +053090
91#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
92#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
93#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
94
Pierre-Louis Bossart395713d2019-08-21 13:58:21 -050095#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
96
Vinod Koulc46302e2018-04-26 18:39:05 +053097enum intel_pdi_type {
98 INTEL_PDI_IN = 0,
99 INTEL_PDI_OUT = 1,
100 INTEL_PDI_BD = 2,
101};
102
Vinod Koul71bb8a12017-12-14 11:19:43 +0530103struct sdw_intel {
104 struct sdw_cdns cdns;
105 int instance;
106 struct sdw_intel_link_res *res;
Pierre-Louis Bossart79ee6632019-08-21 13:58:20 -0500107#ifdef CONFIG_DEBUG_FS
108 struct dentry *debugfs;
109#endif
Vinod Koul71bb8a12017-12-14 11:19:43 +0530110};
111
112#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
113
114/*
115 * Read, write helpers for HW registers
116 */
117static inline int intel_readl(void __iomem *base, int offset)
118{
119 return readl(base + offset);
120}
121
122static inline void intel_writel(void __iomem *base, int offset, int value)
123{
124 writel(value, base + offset);
125}
126
127static inline u16 intel_readw(void __iomem *base, int offset)
128{
129 return readw(base + offset);
130}
131
132static inline void intel_writew(void __iomem *base, int offset, u16 value)
133{
134 writew(value, base + offset);
135}
136
137static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
138{
139 int timeout = 10;
140 u32 reg_read;
141
142 writel(value, base + offset);
143 do {
144 reg_read = readl(base + offset);
145 if (!(reg_read & mask))
146 return 0;
147
148 timeout--;
149 udelay(50);
150 } while (timeout != 0);
151
152 return -EAGAIN;
153}
154
155static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
156{
157 int timeout = 10;
158 u32 reg_read;
159
160 writel(value, base + offset);
161 do {
162 reg_read = readl(base + offset);
163 if (reg_read & mask)
164 return 0;
165
166 timeout--;
167 udelay(50);
168 } while (timeout != 0);
169
170 return -EAGAIN;
171}
172
173/*
Pierre-Louis Bossart79ee6632019-08-21 13:58:20 -0500174 * debugfs
175 */
176#ifdef CONFIG_DEBUG_FS
177
178#define RD_BUF (2 * PAGE_SIZE)
179
180static ssize_t intel_sprintf(void __iomem *mem, bool l,
181 char *buf, size_t pos, unsigned int reg)
182{
183 int value;
184
185 if (l)
186 value = intel_readl(mem, reg);
187 else
188 value = intel_readw(mem, reg);
189
190 return scnprintf(buf + pos, RD_BUF - pos, "%4x\t%4x\n", reg, value);
191}
192
193static int intel_reg_show(struct seq_file *s_file, void *data)
194{
195 struct sdw_intel *sdw = s_file->private;
196 void __iomem *s = sdw->res->shim;
197 void __iomem *a = sdw->res->alh;
198 char *buf;
199 ssize_t ret;
200 int i, j;
201 unsigned int links, reg;
202
203 buf = kzalloc(RD_BUF, GFP_KERNEL);
204 if (!buf)
205 return -ENOMEM;
206
207 links = intel_readl(s, SDW_SHIM_LCAP) & GENMASK(2, 0);
208
209 ret = scnprintf(buf, RD_BUF, "Register Value\n");
210 ret += scnprintf(buf + ret, RD_BUF - ret, "\nShim\n");
211
212 for (i = 0; i < links; i++) {
213 reg = SDW_SHIM_LCAP + i * 4;
214 ret += intel_sprintf(s, true, buf, ret, reg);
215 }
216
217 for (i = 0; i < links; i++) {
218 ret += scnprintf(buf + ret, RD_BUF - ret, "\nLink%d\n", i);
219 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLSCAP(i));
220 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS0CM(i));
221 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS1CM(i));
222 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS2CM(i));
223 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTLS3CM(i));
224 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PCMSCAP(i));
225
226 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PCMSyCH registers\n");
227
228 /*
229 * the value 10 is the number of PDIs. We will need a
230 * cleanup to remove hard-coded Intel configurations
231 * from cadence_master.c
232 */
233 for (j = 0; j < 10; j++) {
234 ret += intel_sprintf(s, false, buf, ret,
235 SDW_SHIM_PCMSYCHM(i, j));
236 ret += intel_sprintf(s, false, buf, ret,
237 SDW_SHIM_PCMSYCHC(i, j));
238 }
239 ret += scnprintf(buf + ret, RD_BUF - ret, "\n PDMSCAP, IOCTL, CTMCTL\n");
240
241 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_PDMSCAP(i));
242 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_IOCTL(i));
243 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_CTMCTL(i));
244 }
245
246 ret += scnprintf(buf + ret, RD_BUF - ret, "\nWake registers\n");
247 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKEEN);
248 ret += intel_sprintf(s, false, buf, ret, SDW_SHIM_WAKESTS);
249
250 ret += scnprintf(buf + ret, RD_BUF - ret, "\nALH STRMzCFG\n");
251 for (i = 0; i < SDW_ALH_NUM_STREAMS; i++)
252 ret += intel_sprintf(a, true, buf, ret, SDW_ALH_STRMZCFG(i));
253
254 seq_printf(s_file, "%s", buf);
255 kfree(buf);
256
257 return 0;
258}
259DEFINE_SHOW_ATTRIBUTE(intel_reg);
260
261static void intel_debugfs_init(struct sdw_intel *sdw)
262{
263 struct dentry *root = sdw->cdns.bus.debugfs;
264
265 if (!root)
266 return;
267
268 sdw->debugfs = debugfs_create_dir("intel-sdw", root);
269
270 debugfs_create_file("intel-registers", 0400, sdw->debugfs, sdw,
271 &intel_reg_fops);
272
273 sdw_cdns_debugfs_init(&sdw->cdns, sdw->debugfs);
274}
275
276static void intel_debugfs_exit(struct sdw_intel *sdw)
277{
278 debugfs_remove_recursive(sdw->debugfs);
279}
280#else
281static void intel_debugfs_init(struct sdw_intel *sdw) {}
282static void intel_debugfs_exit(struct sdw_intel *sdw) {}
283#endif /* CONFIG_DEBUG_FS */
284
285/*
Vinod Koul71bb8a12017-12-14 11:19:43 +0530286 * shim ops
287 */
288
289static int intel_link_power_up(struct sdw_intel *sdw)
290{
291 unsigned int link_id = sdw->instance;
292 void __iomem *shim = sdw->res->shim;
293 int spa_mask, cpa_mask;
294 int link_control, ret;
295
296 /* Link power up sequence */
297 link_control = intel_readl(shim, SDW_SHIM_LCTL);
298 spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
299 cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
300 link_control |= spa_mask;
301
302 ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
303 if (ret < 0)
304 return ret;
305
306 sdw->cdns.link_up = true;
307 return 0;
308}
309
310static int intel_shim_init(struct sdw_intel *sdw)
311{
312 void __iomem *shim = sdw->res->shim;
313 unsigned int link_id = sdw->instance;
314 int sync_reg, ret;
315 u16 ioctl = 0, act = 0;
316
317 /* Initialize Shim */
318 ioctl |= SDW_SHIM_IOCTL_BKE;
319 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
320
321 ioctl |= SDW_SHIM_IOCTL_WPDD;
322 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
323
324 ioctl |= SDW_SHIM_IOCTL_DO;
325 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
326
327 ioctl |= SDW_SHIM_IOCTL_DOE;
328 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
329
330 /* Switch to MIP from Glue logic */
331 ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));
332
333 ioctl &= ~(SDW_SHIM_IOCTL_DOE);
334 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
335
336 ioctl &= ~(SDW_SHIM_IOCTL_DO);
337 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
338
339 ioctl |= (SDW_SHIM_IOCTL_MIF);
340 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
341
342 ioctl &= ~(SDW_SHIM_IOCTL_BKE);
343 ioctl &= ~(SDW_SHIM_IOCTL_COE);
344
345 intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
346
347 act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
348 act |= SDW_SHIM_CTMCTL_DACTQE;
349 act |= SDW_SHIM_CTMCTL_DODS;
350 intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
351
352 /* Now set SyncPRD period */
353 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
354 sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
355 SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
356
357 /* Set SyncCPU bit */
358 sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
359 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500360 SDW_SHIM_SYNC_SYNCCPU);
Vinod Koul71bb8a12017-12-14 11:19:43 +0530361 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500362 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
Vinod Koul71bb8a12017-12-14 11:19:43 +0530363
364 return ret;
365}
366
Vinod Koul37a2d222018-04-26 18:38:58 +0530367/*
368 * PDI routines
369 */
370static void intel_pdi_init(struct sdw_intel *sdw,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500371 struct sdw_cdns_stream_config *config)
Vinod Koul37a2d222018-04-26 18:38:58 +0530372{
373 void __iomem *shim = sdw->res->shim;
374 unsigned int link_id = sdw->instance;
375 int pcm_cap, pdm_cap;
376
377 /* PCM Stream Capability */
378 pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
379
380 config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
381 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
382 config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
383 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
384 config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
385 SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
386
Pierre-Louis Bossart121f4362019-05-22 14:47:29 -0500387 dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
388 config->pcm_bd, config->pcm_in, config->pcm_out);
389
Vinod Koul37a2d222018-04-26 18:38:58 +0530390 /* PDM Stream Capability */
391 pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
392
393 config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
394 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
395 config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
396 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
397 config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
398 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
Pierre-Louis Bossart121f4362019-05-22 14:47:29 -0500399
400 dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
401 config->pdm_bd, config->pdm_in, config->pdm_out);
Vinod Koul37a2d222018-04-26 18:38:58 +0530402}
403
404static int
405intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
406{
407 void __iomem *shim = sdw->res->shim;
408 unsigned int link_id = sdw->instance;
409 int count;
410
411 if (pcm) {
412 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
Pierre-Louis Bossart18046332019-08-05 19:55:07 -0500413
414 /*
415 * WORKAROUND: on all existing Intel controllers, pdi
416 * number 2 reports channel count as 1 even though it
417 * supports 8 channels. Performing hardcoding for pdi
418 * number 2.
419 */
420 if (pdi_num == 2)
421 count = 7;
422
Vinod Koul37a2d222018-04-26 18:38:58 +0530423 } else {
424 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
425 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
426 SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
427 }
428
429 /* zero based values for channel count in register */
430 count++;
431
432 return count;
433}
434
435static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500436 struct sdw_cdns_pdi *pdi,
437 unsigned int num_pdi,
438 unsigned int *num_ch, bool pcm)
Vinod Koul37a2d222018-04-26 18:38:58 +0530439{
440 int i, ch_count = 0;
441
442 for (i = 0; i < num_pdi; i++) {
443 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
444 ch_count += pdi->ch_count;
445 pdi++;
446 }
447
448 *num_ch = ch_count;
449 return 0;
450}
451
452static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500453 struct sdw_cdns_streams *stream, bool pcm)
Vinod Koul37a2d222018-04-26 18:38:58 +0530454{
455 intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500456 &stream->num_ch_bd, pcm);
Vinod Koul37a2d222018-04-26 18:38:58 +0530457
458 intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500459 &stream->num_ch_in, pcm);
Vinod Koul37a2d222018-04-26 18:38:58 +0530460
461 intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500462 &stream->num_ch_out, pcm);
Vinod Koul37a2d222018-04-26 18:38:58 +0530463
464 return 0;
465}
466
467static int intel_pdi_ch_update(struct sdw_intel *sdw)
468{
469 /* First update PCM streams followed by PDM streams */
470 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
471 intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
472
473 return 0;
474}
475
476static void
477intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
478{
479 void __iomem *shim = sdw->res->shim;
480 unsigned int link_id = sdw->instance;
481 int pdi_conf = 0;
482
Pierre-Louis Bossartc134f912019-10-22 18:29:48 -0500483 /* the Bulk and PCM streams are not contiguous */
484 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
485 if (pdi->num >= 2)
486 pdi->intel_alh_id += 2;
Vinod Koul37a2d222018-04-26 18:38:58 +0530487
488 /*
489 * Program stream parameters to stream SHIM register
490 * This is applicable for PCM stream only.
491 */
492 if (pdi->type != SDW_STREAM_PCM)
493 return;
494
495 if (pdi->dir == SDW_DATA_DIR_RX)
496 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
497 else
498 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
499
500 pdi_conf |= (pdi->intel_alh_id <<
501 SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
502 pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
503 pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
504
505 intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
506}
507
508static void
509intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
510{
511 void __iomem *alh = sdw->res->alh;
512 unsigned int link_id = sdw->instance;
513 unsigned int conf;
514
Pierre-Louis Bossartc134f912019-10-22 18:29:48 -0500515 /* the Bulk and PCM streams are not contiguous */
516 pdi->intel_alh_id = (link_id * 16) + pdi->num + 3;
517 if (pdi->num >= 2)
518 pdi->intel_alh_id += 2;
Vinod Koul37a2d222018-04-26 18:38:58 +0530519
520 /* Program Stream config ALH register */
521 conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
522
523 conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
524 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
525
526 conf |= ((pdi->ch_count - 1) <<
527 SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
528
529 intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
530}
531
Rander Wang4b206d32019-12-11 19:45:02 -0600532static int intel_params_stream(struct sdw_intel *sdw,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500533 struct snd_pcm_substream *substream,
534 struct snd_soc_dai *dai,
Rander Wang4b206d32019-12-11 19:45:02 -0600535 struct snd_pcm_hw_params *hw_params,
536 int link_id, int alh_stream_id)
Vinod Koulc46302e2018-04-26 18:39:05 +0530537{
Pierre-Louis Bossart05c8afe42019-08-05 19:55:06 -0500538 struct sdw_intel_link_res *res = sdw->res;
Rander Wang4b206d32019-12-11 19:45:02 -0600539 struct sdw_intel_stream_params_data params_data;
Pierre-Louis Bossart05c8afe42019-08-05 19:55:06 -0500540
Rander Wang4b206d32019-12-11 19:45:02 -0600541 params_data.substream = substream;
542 params_data.dai = dai;
543 params_data.hw_params = hw_params;
544 params_data.link_id = link_id;
545 params_data.alh_stream_id = alh_stream_id;
Vinod Koulc46302e2018-04-26 18:39:05 +0530546
Rander Wang4b206d32019-12-11 19:45:02 -0600547 if (res->ops && res->ops->params_stream && res->dev)
548 return res->ops->params_stream(res->dev,
549 &params_data);
Vinod Koulc46302e2018-04-26 18:39:05 +0530550 return -EIO;
551}
552
553/*
Shreyas NC30246e22018-07-27 14:44:17 +0530554 * bank switch routines
555 */
556
557static int intel_pre_bank_switch(struct sdw_bus *bus)
558{
559 struct sdw_cdns *cdns = bus_to_cdns(bus);
560 struct sdw_intel *sdw = cdns_to_intel(cdns);
561 void __iomem *shim = sdw->res->shim;
562 int sync_reg;
563
564 /* Write to register only for multi-link */
565 if (!bus->multi_link)
566 return 0;
567
568 /* Read SYNC register */
569 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
570 sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
571 intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
572
573 return 0;
574}
575
576static int intel_post_bank_switch(struct sdw_bus *bus)
577{
578 struct sdw_cdns *cdns = bus_to_cdns(bus);
579 struct sdw_intel *sdw = cdns_to_intel(cdns);
580 void __iomem *shim = sdw->res->shim;
581 int sync_reg, ret;
582
583 /* Write to register only for multi-link */
584 if (!bus->multi_link)
585 return 0;
586
587 /* Read SYNC register */
588 sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
589
590 /*
591 * post_bank_switch() ops is called from the bus in loop for
592 * all the Masters in the steam with the expectation that
593 * we trigger the bankswitch for the only first Master in the list
594 * and do nothing for the other Masters
595 *
596 * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
597 */
598 if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
599 return 0;
600
601 /*
602 * Set SyncGO bit to synchronously trigger a bank switch for
603 * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
604 * the Masters.
605 */
606 sync_reg |= SDW_SHIM_SYNC_SYNCGO;
607
608 ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500609 SDW_SHIM_SYNC_SYNCGO);
Shreyas NC30246e22018-07-27 14:44:17 +0530610 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500611 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
Shreyas NC30246e22018-07-27 14:44:17 +0530612
613 return ret;
614}
615
616/*
Vinod Koulc46302e2018-04-26 18:39:05 +0530617 * DAI routines
618 */
619
Vinod Koulc46302e2018-04-26 18:39:05 +0530620static int intel_hw_params(struct snd_pcm_substream *substream,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500621 struct snd_pcm_hw_params *params,
622 struct snd_soc_dai *dai)
Vinod Koulc46302e2018-04-26 18:39:05 +0530623{
624 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
625 struct sdw_intel *sdw = cdns_to_intel(cdns);
626 struct sdw_cdns_dma_data *dma;
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500627 struct sdw_cdns_pdi *pdi;
Vinod Koulc46302e2018-04-26 18:39:05 +0530628 struct sdw_stream_config sconfig;
629 struct sdw_port_config *pconfig;
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500630 int ch, dir;
631 int ret;
Vinod Koulc46302e2018-04-26 18:39:05 +0530632 bool pcm = true;
633
634 dma = snd_soc_dai_get_dma_data(dai, substream);
635 if (!dma)
636 return -EIO;
637
638 ch = params_channels(params);
639 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
640 dir = SDW_DATA_DIR_RX;
641 else
642 dir = SDW_DATA_DIR_TX;
643
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500644 if (dma->stream_type == SDW_STREAM_PDM)
Vinod Koulc46302e2018-04-26 18:39:05 +0530645 pcm = false;
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500646
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500647 if (pcm)
Bard Liao1b53385e2019-09-16 14:23:48 -0500648 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pcm, ch, dir, dai->id);
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500649 else
Bard Liao1b53385e2019-09-16 14:23:48 -0500650 pdi = sdw_cdns_alloc_pdi(cdns, &cdns->pdm, ch, dir, dai->id);
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500651
652 if (!pdi) {
653 ret = -EINVAL;
654 goto error;
Vinod Koulc46302e2018-04-26 18:39:05 +0530655 }
656
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500657 /* do run-time configurations for SHIM, ALH and PDI/PORT */
658 intel_pdi_shim_configure(sdw, pdi);
659 intel_pdi_alh_configure(sdw, pdi);
660 sdw_cdns_config_stream(cdns, ch, dir, pdi);
Vinod Koulc46302e2018-04-26 18:39:05 +0530661
Vinod Koulc46302e2018-04-26 18:39:05 +0530662
663 /* Inform DSP about PDI stream number */
Rander Wang4b206d32019-12-11 19:45:02 -0600664 ret = intel_params_stream(sdw, substream, dai, params,
665 sdw->instance,
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500666 pdi->intel_alh_id);
667 if (ret)
668 goto error;
Vinod Koulc46302e2018-04-26 18:39:05 +0530669
670 sconfig.direction = dir;
671 sconfig.ch_count = ch;
672 sconfig.frame_rate = params_rate(params);
673 sconfig.type = dma->stream_type;
674
675 if (dma->stream_type == SDW_STREAM_PDM) {
676 sconfig.frame_rate *= 50;
677 sconfig.bps = 1;
678 } else {
679 sconfig.bps = snd_pcm_format_width(params_format(params));
680 }
681
682 /* Port configuration */
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500683 pconfig = kcalloc(1, sizeof(*pconfig), GFP_KERNEL);
Vinod Koulc46302e2018-04-26 18:39:05 +0530684 if (!pconfig) {
685 ret = -ENOMEM;
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500686 goto error;
Vinod Koulc46302e2018-04-26 18:39:05 +0530687 }
688
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500689 pconfig->num = pdi->num;
690 pconfig->ch_mask = (1 << ch) - 1;
Vinod Koulc46302e2018-04-26 18:39:05 +0530691
692 ret = sdw_stream_add_master(&cdns->bus, &sconfig,
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500693 pconfig, 1, dma->stream);
694 if (ret)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500695 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
Vinod Koulc46302e2018-04-26 18:39:05 +0530696
697 kfree(pconfig);
Pierre-Louis Bossart57a34792019-09-16 14:23:46 -0500698error:
Vinod Koulc46302e2018-04-26 18:39:05 +0530699 return ret;
700}
701
702static int
703intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
704{
705 struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
706 struct sdw_cdns_dma_data *dma;
707 int ret;
708
709 dma = snd_soc_dai_get_dma_data(dai, substream);
710 if (!dma)
711 return -EIO;
712
713 ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
714 if (ret < 0)
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -0500715 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500716 dma->stream->name, ret);
Vinod Koulc46302e2018-04-26 18:39:05 +0530717
Vinod Koulc46302e2018-04-26 18:39:05 +0530718 return ret;
719}
720
Pierre-Louis Bossart183c7682019-08-05 19:55:22 -0500721static void intel_shutdown(struct snd_pcm_substream *substream,
722 struct snd_soc_dai *dai)
723{
724 struct sdw_cdns_dma_data *dma;
725
726 dma = snd_soc_dai_get_dma_data(dai, substream);
727 if (!dma)
728 return;
729
730 snd_soc_dai_set_dma_data(dai, substream, NULL);
731 kfree(dma);
732}
733
Vinod Koulc46302e2018-04-26 18:39:05 +0530734static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500735 void *stream, int direction)
Vinod Koulc46302e2018-04-26 18:39:05 +0530736{
737 return cdns_set_sdw_stream(dai, stream, true, direction);
738}
739
740static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500741 void *stream, int direction)
Vinod Koulc46302e2018-04-26 18:39:05 +0530742{
743 return cdns_set_sdw_stream(dai, stream, false, direction);
744}
745
Julia Lawallb1635592018-10-27 15:34:42 +0200746static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
Vinod Koulc46302e2018-04-26 18:39:05 +0530747 .hw_params = intel_hw_params,
748 .hw_free = intel_hw_free,
Pierre-Louis Bossart183c7682019-08-05 19:55:22 -0500749 .shutdown = intel_shutdown,
Vinod Koulc46302e2018-04-26 18:39:05 +0530750 .set_sdw_stream = intel_pcm_set_sdw_stream,
751};
752
Julia Lawallb1635592018-10-27 15:34:42 +0200753static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
Vinod Koulc46302e2018-04-26 18:39:05 +0530754 .hw_params = intel_hw_params,
755 .hw_free = intel_hw_free,
Pierre-Louis Bossart183c7682019-08-05 19:55:22 -0500756 .shutdown = intel_shutdown,
Vinod Koulc46302e2018-04-26 18:39:05 +0530757 .set_sdw_stream = intel_pdm_set_sdw_stream,
758};
759
760static const struct snd_soc_component_driver dai_component = {
761 .name = "soundwire",
762};
763
764static int intel_create_dai(struct sdw_cdns *cdns,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500765 struct snd_soc_dai_driver *dais,
766 enum intel_pdi_type type,
767 u32 num, u32 off, u32 max_ch, bool pcm)
Vinod Koulc46302e2018-04-26 18:39:05 +0530768{
769 int i;
770
771 if (num == 0)
772 return 0;
773
774 /* TODO: Read supported rates/formats from hardware */
775 for (i = off; i < (off + num); i++) {
776 dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500777 cdns->instance, i);
Vinod Koulc46302e2018-04-26 18:39:05 +0530778 if (!dais[i].name)
779 return -ENOMEM;
780
781 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
Vinod Koulc46302e2018-04-26 18:39:05 +0530782 dais[i].playback.channels_min = 1;
783 dais[i].playback.channels_max = max_ch;
784 dais[i].playback.rates = SNDRV_PCM_RATE_48000;
785 dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
786 }
787
788 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
Srinivas Kandagatla39194122019-06-06 12:23:04 +0100789 dais[i].capture.channels_min = 1;
790 dais[i].capture.channels_max = max_ch;
Vinod Koulc46302e2018-04-26 18:39:05 +0530791 dais[i].capture.rates = SNDRV_PCM_RATE_48000;
792 dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
793 }
794
Vinod Koulc46302e2018-04-26 18:39:05 +0530795 if (pcm)
796 dais[i].ops = &intel_pcm_dai_ops;
797 else
798 dais[i].ops = &intel_pdm_dai_ops;
799 }
800
801 return 0;
802}
803
804static int intel_register_dai(struct sdw_intel *sdw)
805{
806 struct sdw_cdns *cdns = &sdw->cdns;
807 struct sdw_cdns_streams *stream;
808 struct snd_soc_dai_driver *dais;
809 int num_dai, ret, off = 0;
810
811 /* DAIs are created based on total number of PDIs supported */
812 num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
813
814 dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
815 if (!dais)
816 return -ENOMEM;
817
818 /* Create PCM DAIs */
819 stream = &cdns->pcm;
820
Bard Liaocf924962019-09-16 14:23:43 -0500821 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pcm.num_in,
Vinod Koul1215dae2019-05-02 16:29:25 +0530822 off, stream->num_ch_in, true);
Vinod Koulc46302e2018-04-26 18:39:05 +0530823 if (ret)
824 return ret;
825
826 off += cdns->pcm.num_in;
Vinod Koul1215dae2019-05-02 16:29:25 +0530827 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
828 off, stream->num_ch_out, true);
Vinod Koulc46302e2018-04-26 18:39:05 +0530829 if (ret)
830 return ret;
831
832 off += cdns->pcm.num_out;
Vinod Koul1215dae2019-05-02 16:29:25 +0530833 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
834 off, stream->num_ch_bd, true);
Vinod Koulc46302e2018-04-26 18:39:05 +0530835 if (ret)
836 return ret;
837
838 /* Create PDM DAIs */
839 stream = &cdns->pdm;
840 off += cdns->pcm.num_bd;
Vinod Koul1215dae2019-05-02 16:29:25 +0530841 ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
842 off, stream->num_ch_in, false);
Vinod Koulc46302e2018-04-26 18:39:05 +0530843 if (ret)
844 return ret;
845
846 off += cdns->pdm.num_in;
Vinod Koul1215dae2019-05-02 16:29:25 +0530847 ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
848 off, stream->num_ch_out, false);
Vinod Koulc46302e2018-04-26 18:39:05 +0530849 if (ret)
850 return ret;
851
Bard Liaocf924962019-09-16 14:23:43 -0500852 off += cdns->pdm.num_out;
Vinod Koul1215dae2019-05-02 16:29:25 +0530853 ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
854 off, stream->num_ch_bd, false);
Vinod Koulc46302e2018-04-26 18:39:05 +0530855 if (ret)
856 return ret;
857
858 return snd_soc_register_component(cdns->dev, &dai_component,
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500859 dais, num_dai);
Vinod Koulc46302e2018-04-26 18:39:05 +0530860}
861
Pierre-Louis Bossart085f4ac2019-08-05 19:55:16 -0500862static int sdw_master_read_intel_prop(struct sdw_bus *bus)
863{
864 struct sdw_master_prop *prop = &bus->prop;
865 struct fwnode_handle *link;
866 char name[32];
Pierre-Louis Bossart395713d2019-08-21 13:58:21 -0500867 u32 quirk_mask;
Pierre-Louis Bossart085f4ac2019-08-05 19:55:16 -0500868
869 /* Find master handle */
870 snprintf(name, sizeof(name),
871 "mipi-sdw-link-%d-subproperties", bus->link_id);
872
873 link = device_get_named_child_node(bus->dev, name);
874 if (!link) {
875 dev_err(bus->dev, "Master node %s not found\n", name);
876 return -EIO;
877 }
878
879 fwnode_property_read_u32(link,
880 "intel-sdw-ip-clock",
881 &prop->mclk_freq);
Pierre-Louis Bossart395713d2019-08-21 13:58:21 -0500882
883 fwnode_property_read_u32(link,
884 "intel-quirk-mask",
885 &quirk_mask);
886
887 if (quirk_mask & SDW_INTEL_QUIRK_MASK_BUS_DISABLE)
888 prop->hw_disabled = true;
889
Pierre-Louis Bossart085f4ac2019-08-05 19:55:16 -0500890 return 0;
891}
892
Vinod Koul71bb8a12017-12-14 11:19:43 +0530893static int intel_prop_read(struct sdw_bus *bus)
894{
895 /* Initialize with default handler to read all DisCo properties */
896 sdw_master_read_prop(bus);
897
Pierre-Louis Bossart085f4ac2019-08-05 19:55:16 -0500898 /* read Intel-specific properties */
899 sdw_master_read_intel_prop(bus);
900
Vinod Koul71bb8a12017-12-14 11:19:43 +0530901 return 0;
902}
903
Shreyas NCc91605f2018-04-26 18:38:43 +0530904static struct sdw_master_ops sdw_intel_ops = {
905 .read_prop = sdw_master_read_prop,
906 .xfer_msg = cdns_xfer_msg,
907 .xfer_msg_defer = cdns_xfer_msg_defer,
908 .reset_page_addr = cdns_reset_page_addr,
Vinod Koul07abeff2018-04-26 18:38:48 +0530909 .set_bus_conf = cdns_bus_conf,
Shreyas NC30246e22018-07-27 14:44:17 +0530910 .pre_bank_switch = intel_pre_bank_switch,
911 .post_bank_switch = intel_post_bank_switch,
Shreyas NCc91605f2018-04-26 18:38:43 +0530912};
913
Pierre-Louis Bossartdfbe6422019-10-22 18:54:46 -0500914static int intel_init(struct sdw_intel *sdw)
915{
916 /* Initialize shim and controller */
917 intel_link_power_up(sdw);
918 intel_shim_init(sdw);
919
Pierre-Louis Bossart3ccb8552019-10-22 18:54:48 -0500920 return sdw_cdns_init(&sdw->cdns, false);
Pierre-Louis Bossartdfbe6422019-10-22 18:54:46 -0500921}
922
Vinod Koul71bb8a12017-12-14 11:19:43 +0530923/*
924 * probe and init
925 */
926static int intel_probe(struct platform_device *pdev)
927{
Vinod Koul37a2d222018-04-26 18:38:58 +0530928 struct sdw_cdns_stream_config config;
Vinod Koul71bb8a12017-12-14 11:19:43 +0530929 struct sdw_intel *sdw;
930 int ret;
931
932 sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
933 if (!sdw)
934 return -ENOMEM;
935
936 sdw->instance = pdev->id;
937 sdw->res = dev_get_platdata(&pdev->dev);
938 sdw->cdns.dev = &pdev->dev;
939 sdw->cdns.registers = sdw->res->registers;
940 sdw->cdns.instance = sdw->instance;
941 sdw->cdns.msg_count = 0;
942 sdw->cdns.bus.dev = &pdev->dev;
943 sdw->cdns.bus.link_id = pdev->id;
944
945 sdw_cdns_probe(&sdw->cdns);
946
947 /* Set property read ops */
Shreyas NCc91605f2018-04-26 18:38:43 +0530948 sdw_intel_ops.read_prop = intel_prop_read;
949 sdw->cdns.bus.ops = &sdw_intel_ops;
Vinod Koul71bb8a12017-12-14 11:19:43 +0530950
951 platform_set_drvdata(pdev, sdw);
952
953 ret = sdw_add_bus_master(&sdw->cdns.bus);
954 if (ret) {
955 dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
Pierre-Louis Bossart9e3d47f2019-10-22 18:54:47 -0500956 return ret;
Vinod Koul71bb8a12017-12-14 11:19:43 +0530957 }
958
Pierre-Louis Bossart395713d2019-08-21 13:58:21 -0500959 if (sdw->cdns.bus.prop.hw_disabled) {
960 dev_info(&pdev->dev, "SoundWire master %d is disabled, ignoring\n",
961 sdw->cdns.bus.link_id);
962 return 0;
963 }
964
Pierre-Louis Bossartdfbe6422019-10-22 18:54:46 -0500965 /* Initialize shim, controller and Cadence IP */
966 ret = intel_init(sdw);
Vinod Koul71bb8a12017-12-14 11:19:43 +0530967 if (ret)
968 goto err_init;
969
Vinod Koul37a2d222018-04-26 18:38:58 +0530970 /* Read the PDI config and initialize cadence PDI */
971 intel_pdi_init(sdw, &config);
972 ret = sdw_cdns_pdi_init(&sdw->cdns, config);
Vinod Koul71bb8a12017-12-14 11:19:43 +0530973 if (ret)
974 goto err_init;
975
Vinod Koul37a2d222018-04-26 18:38:58 +0530976 intel_pdi_ch_update(sdw);
977
Vinod Koul71bb8a12017-12-14 11:19:43 +0530978 /* Acquire IRQ */
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500979 ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
980 IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
Vinod Koul71bb8a12017-12-14 11:19:43 +0530981 if (ret < 0) {
982 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
Pierre-Louis Bossartd542bc92019-05-01 10:57:38 -0500983 sdw->res->irq);
Vinod Koul71bb8a12017-12-14 11:19:43 +0530984 goto err_init;
985 }
986
Pierre-Louis Bossart9e3d47f2019-10-22 18:54:47 -0500987 ret = sdw_cdns_enable_interrupt(&sdw->cdns, true);
Pierre-Louis Bossart49ea07d2019-10-22 18:54:44 -0500988 if (ret < 0) {
989 dev_err(sdw->cdns.dev, "cannot enable interrupts\n");
990 goto err_init;
991 }
992
993 ret = sdw_cdns_exit_reset(&sdw->cdns);
994 if (ret < 0) {
995 dev_err(sdw->cdns.dev, "unable to exit bus reset sequence\n");
Pierre-Louis Bossart9e3d47f2019-10-22 18:54:47 -0500996 goto err_interrupt;
Pierre-Louis Bossart49ea07d2019-10-22 18:54:44 -0500997 }
998
Vinod Koulc46302e2018-04-26 18:39:05 +0530999 /* Register DAIs */
1000 ret = intel_register_dai(sdw);
1001 if (ret) {
Pierre-Louis Bossart17ed5be2019-05-01 10:57:45 -05001002 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
Vinod Koulc46302e2018-04-26 18:39:05 +05301003 snd_soc_unregister_component(sdw->cdns.dev);
Pierre-Louis Bossart9e3d47f2019-10-22 18:54:47 -05001004 goto err_interrupt;
Vinod Koulc46302e2018-04-26 18:39:05 +05301005 }
1006
Pierre-Louis Bossart79ee6632019-08-21 13:58:20 -05001007 intel_debugfs_init(sdw);
1008
Vinod Koul71bb8a12017-12-14 11:19:43 +05301009 return 0;
1010
Pierre-Louis Bossart9e3d47f2019-10-22 18:54:47 -05001011err_interrupt:
1012 sdw_cdns_enable_interrupt(&sdw->cdns, false);
Vinod Koulc46302e2018-04-26 18:39:05 +05301013 free_irq(sdw->res->irq, sdw);
Vinod Koul71bb8a12017-12-14 11:19:43 +05301014err_init:
1015 sdw_delete_bus_master(&sdw->cdns.bus);
Vinod Koul71bb8a12017-12-14 11:19:43 +05301016 return ret;
1017}
1018
1019static int intel_remove(struct platform_device *pdev)
1020{
1021 struct sdw_intel *sdw;
1022
1023 sdw = platform_get_drvdata(pdev);
1024
Pierre-Louis Bossart395713d2019-08-21 13:58:21 -05001025 if (!sdw->cdns.bus.prop.hw_disabled) {
1026 intel_debugfs_exit(sdw);
Pierre-Louis Bossart9e3d47f2019-10-22 18:54:47 -05001027 sdw_cdns_enable_interrupt(&sdw->cdns, false);
Pierre-Louis Bossart395713d2019-08-21 13:58:21 -05001028 free_irq(sdw->res->irq, sdw);
1029 snd_soc_unregister_component(sdw->cdns.dev);
1030 }
Vinod Koul71bb8a12017-12-14 11:19:43 +05301031 sdw_delete_bus_master(&sdw->cdns.bus);
1032
1033 return 0;
1034}
1035
1036static struct platform_driver sdw_intel_drv = {
1037 .probe = intel_probe,
1038 .remove = intel_remove,
1039 .driver = {
1040 .name = "int-sdw",
1041
1042 },
1043};
1044
1045module_platform_driver(sdw_intel_drv);
1046
1047MODULE_LICENSE("Dual BSD/GPL");
1048MODULE_ALIAS("platform:int-sdw");
1049MODULE_DESCRIPTION("Intel Soundwire Master Driver");