blob: 4069c215328b3e0eb0f34fbd6a4fab197b95cea6 [file] [log] [blame]
Thomas Gleixnercaab2772019-06-03 07:44:50 +02001// SPDX-License-Identifier: GPL-2.0-only
Marc Zyngiercc2d3212014-11-24 14:35:11 +00002/*
Marc Zyngierd7276b82016-12-20 15:11:47 +00003 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
Marc Zyngiercc2d3212014-11-24 14:35:11 +00004 * Author: Marc Zyngier <marc.zyngier@arm.com>
Marc Zyngiercc2d3212014-11-24 14:35:11 +00005 */
6
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02007#include <linux/acpi.h>
Hanjun Guo8d3554b2017-03-07 20:39:59 +08008#include <linux/acpi_iort.h>
Marc Zyngierffedbf02019-11-08 16:57:59 +00009#include <linux/bitfield.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000010#include <linux/bitmap.h>
11#include <linux/cpu.h>
Marc Zyngierc6e2ccb2018-06-26 11:21:11 +010012#include <linux/crash_dump.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000013#include <linux/delay.h>
Robin Murphy44bb7e22016-09-12 17:13:59 +010014#include <linux/dma-iommu.h>
Marc Zyngier3fb68fa2018-07-27 16:21:18 +010015#include <linux/efi.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000016#include <linux/interrupt.h>
Marc Zyngier96806222020-04-10 11:13:26 +010017#include <linux/iopoll.h>
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +020018#include <linux/irqdomain.h>
Marc Zyngier880cb3c2018-05-27 16:14:15 +010019#include <linux/list.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000020#include <linux/log2.h>
Marc Zyngier5e2c9f92018-07-27 16:23:18 +010021#include <linux/memblock.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000022#include <linux/mm.h>
23#include <linux/msi.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_pci.h>
28#include <linux/of_platform.h>
29#include <linux/percpu.h>
30#include <linux/slab.h>
Derek Basehoredba0bc72018-02-28 21:48:18 -080031#include <linux/syscore_ops.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000032
Joel Porquet41a83e062015-07-07 17:11:46 -040033#include <linux/irqchip.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000034#include <linux/irqchip/arm-gic-v3.h>
Marc Zyngierc808eea2016-12-20 09:31:20 +000035#include <linux/irqchip/arm-gic-v4.h>
Marc Zyngiercc2d3212014-11-24 14:35:11 +000036
Marc Zyngiercc2d3212014-11-24 14:35:11 +000037#include <asm/cputype.h>
38#include <asm/exception.h>
39
Robert Richter67510cc2015-09-21 22:58:37 +020040#include "irq-gic-common.h"
41
Robert Richter94100972015-09-21 22:58:38 +020042#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0)
43#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1)
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +020044#define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2)
Marc Zyngiercc2d3212014-11-24 14:35:11 +000045
Marc Zyngierc48ed512014-11-24 14:35:12 +000046#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
Marc Zyngierc440a9d2018-07-27 15:40:13 +010047#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
Marc Zyngierc48ed512014-11-24 14:35:12 +000048
Marc Zyngiera13b0402016-12-19 17:15:24 +000049static u32 lpi_id_bits;
50
51/*
52 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
53 * deal with (one configuration byte per interrupt). PENDBASE has to
54 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
55 */
56#define LPI_NRBITS lpi_id_bits
57#define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K)
58#define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)
59
Julien Thierry2130b782018-08-28 16:51:18 +010060#define LPI_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI
Marc Zyngiera13b0402016-12-19 17:15:24 +000061
Marc Zyngiercc2d3212014-11-24 14:35:11 +000062/*
63 * Collection structure - just an ID, and a redistributor address to
64 * ping. We use one per CPU as a bag of interrupts assigned to this
65 * CPU.
66 */
67struct its_collection {
68 u64 target_address;
69 u16 col_id;
70};
71
72/*
Shanker Donthineni93473592016-06-06 18:17:30 -050073 * The ITS_BASER structure - contains memory information, cached
74 * value of BASER register configuration and ITS page size.
Shanker Donthineni466b7d12016-03-09 22:10:49 -060075 */
76struct its_baser {
77 void *base;
78 u64 val;
79 u32 order;
Shanker Donthineni93473592016-06-06 18:17:30 -050080 u32 psz;
Shanker Donthineni466b7d12016-03-09 22:10:49 -060081};
82
Ard Biesheuvel558b0162017-10-17 17:55:56 +010083struct its_device;
84
Shanker Donthineni466b7d12016-03-09 22:10:49 -060085/*
Marc Zyngiercc2d3212014-11-24 14:35:11 +000086 * The ITS structure - contains most of the infrastructure, with the
Marc Zyngier841514a2015-07-28 14:46:20 +010087 * top-level MSI domain, the command queue, the collections, and the
88 * list of devices writing to it.
Marc Zyngier9791ec72019-01-29 10:02:33 +000089 *
90 * dev_alloc_lock has to be taken for device allocations, while the
91 * spinlock must be taken to parse data structures such as the device
92 * list.
Marc Zyngiercc2d3212014-11-24 14:35:11 +000093 */
94struct its_node {
95 raw_spinlock_t lock;
Marc Zyngier9791ec72019-01-29 10:02:33 +000096 struct mutex dev_alloc_lock;
Marc Zyngiercc2d3212014-11-24 14:35:11 +000097 struct list_head entry;
Marc Zyngiercc2d3212014-11-24 14:35:11 +000098 void __iomem *base;
Marc Zyngier5e46a482020-03-04 20:33:14 +000099 void __iomem *sgir_base;
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +0200100 phys_addr_t phys_base;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000101 struct its_cmd_block *cmd_base;
102 struct its_cmd_block *cmd_write;
Shanker Donthineni466b7d12016-03-09 22:10:49 -0600103 struct its_baser tables[GITS_BASER_NR_REGS];
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000104 struct its_collection *collections;
Ard Biesheuvel558b0162017-10-17 17:55:56 +0100105 struct fwnode_handle *fwnode_handle;
106 u64 (*get_msi_base)(struct its_device *its_dev);
Marc Zyngier0dd57fe2019-11-08 16:57:58 +0000107 u64 typer;
Derek Basehoredba0bc72018-02-28 21:48:18 -0800108 u64 cbaser_save;
109 u32 ctlr_save;
Marc Zyngier5e516842019-12-24 11:10:28 +0000110 u32 mpidr;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000111 struct list_head its_device_list;
112 u64 flags;
Marc Zyngierdebf6d02017-10-08 18:44:42 +0100113 unsigned long list_nr;
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +0200114 int numa_node;
Ard Biesheuvel558b0162017-10-17 17:55:56 +0100115 unsigned int msi_domain_flags;
116 u32 pre_its_base; /* for Socionext Synquacer */
Marc Zyngier5c9a8822017-07-28 21:20:37 +0100117 int vlpi_redist_offset;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000118};
119
Marc Zyngier0dd57fe2019-11-08 16:57:58 +0000120#define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS))
Marc Zyngier5e516842019-12-24 11:10:28 +0000121#define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP))
Marc Zyngier576a8342019-11-08 16:58:00 +0000122#define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1)
Marc Zyngier0dd57fe2019-11-08 16:57:58 +0000123
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000124#define ITS_ITT_ALIGN SZ_256
125
Shanker Donthineni32bd44d2017-10-07 15:43:48 -0500126/* The maximum number of VPEID bits supported by VLPI commands */
Marc Zyngierf2d83402019-12-24 11:10:25 +0000127#define ITS_MAX_VPEID_BITS \
128 ({ \
129 int nvpeid = 16; \
130 if (gic_rdists->has_rvpeid && \
131 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
132 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
133 GICD_TYPER2_VID); \
134 \
135 nvpeid; \
136 })
Shanker Donthineni32bd44d2017-10-07 15:43:48 -0500137#define ITS_MAX_VPEID (1 << (ITS_MAX_VPEID_BITS))
138
Shanker Donthineni2eca0d62016-02-16 18:00:36 -0600139/* Convert page order to size in bytes */
140#define PAGE_ORDER_TO_SIZE(o) (PAGE_SIZE << (o))
141
Marc Zyngier591e5be2015-07-17 10:46:42 +0100142struct event_lpi_map {
143 unsigned long *lpi_map;
144 u16 *col_map;
145 irq_hw_number_t lpi_base;
146 int nr_lpis;
Marc Zyngier11635fa2019-11-08 16:58:05 +0000147 raw_spinlock_t vlpi_lock;
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000148 struct its_vm *vm;
149 struct its_vlpi_map *vlpi_maps;
150 int nr_vlpis;
Marc Zyngier591e5be2015-07-17 10:46:42 +0100151};
152
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000153/*
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000154 * The ITS view of a device - belongs to an ITS, owns an interrupt
155 * translation table, and a list of interrupts. If it some of its
156 * LPIs are injected into a guest (GICv4), the event_map.vm field
157 * indicates which one.
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000158 */
159struct its_device {
160 struct list_head entry;
161 struct its_node *its;
Marc Zyngier591e5be2015-07-17 10:46:42 +0100162 struct event_lpi_map event_map;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000163 void *itt;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000164 u32 nr_ites;
165 u32 device_id;
Marc Zyngier9791ec72019-01-29 10:02:33 +0000166 bool shared;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000167};
168
Marc Zyngier20b3d542016-12-20 15:23:22 +0000169static struct {
170 raw_spinlock_t lock;
171 struct its_device *dev;
172 struct its_vpe **vpes;
173 int next_victim;
174} vpe_proxy;
175
Marc Zyngier2f13ff12020-05-15 17:57:51 +0100176struct cpu_lpi_count {
177 atomic_t managed;
178 atomic_t unmanaged;
179};
180
181static DEFINE_PER_CPU(struct cpu_lpi_count, cpu_lpi_count);
182
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000183static LIST_HEAD(its_nodes);
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +0200184static DEFINE_RAW_SPINLOCK(its_lock);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000185static struct rdists *gic_rdists;
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +0200186static struct irq_domain *its_parent;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000187
Marc Zyngier3dfa5762016-12-19 17:25:54 +0000188static unsigned long its_list_map;
Marc Zyngier3171a472016-12-20 15:17:28 +0000189static u16 vmovp_seq_num;
190static DEFINE_RAW_SPINLOCK(vmovp_lock);
191
Marc Zyngier7d75bbb2016-12-20 13:55:54 +0000192static DEFINE_IDA(its_vpeid_ida);
Marc Zyngier3dfa5762016-12-19 17:25:54 +0000193
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000194#define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
Marc Zyngier11e37d32018-07-27 13:38:54 +0100195#define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000196#define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
Marc Zyngiere643d802016-12-20 15:09:31 +0000197#define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
Marc Zyngier1ac19ca2014-11-24 14:35:14 +0000198
Marc Zyngier009384b2020-03-04 20:33:23 +0000199/*
200 * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
201 * always have vSGIs mapped.
202 */
203static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its)
204{
205 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]);
206}
207
Zenghui Yu84243122019-10-23 03:46:26 +0000208static u16 get_its_list(struct its_vm *vm)
209{
210 struct its_node *its;
211 unsigned long its_list = 0;
212
213 list_for_each_entry(its, &its_nodes, entry) {
Marc Zyngier0dd57fe2019-11-08 16:57:58 +0000214 if (!is_v4(its))
Zenghui Yu84243122019-10-23 03:46:26 +0000215 continue;
216
Marc Zyngier009384b2020-03-04 20:33:23 +0000217 if (require_its_list_vmovp(vm, its))
Zenghui Yu84243122019-10-23 03:46:26 +0000218 __set_bit(its->list_nr, &its_list);
219 }
220
221 return (u16)its_list;
222}
223
Marc Zyngier425c09b2019-11-08 16:57:57 +0000224static inline u32 its_get_event_id(struct irq_data *d)
225{
226 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
227 return d->hwirq - its_dev->event_map.lpi_base;
228}
229
Marc Zyngier591e5be2015-07-17 10:46:42 +0100230static struct its_collection *dev_event_to_col(struct its_device *its_dev,
231 u32 event)
232{
233 struct its_node *its = its_dev->its;
234
235 return its->collections + its_dev->event_map.col_map[event];
236}
237
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +0000238static struct its_vlpi_map *dev_event_to_vlpi_map(struct its_device *its_dev,
239 u32 event)
240{
241 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis))
242 return NULL;
243
244 return &its_dev->event_map.vlpi_maps[event];
245}
246
Marc Zyngierf4a81f52019-12-24 11:10:38 +0000247static struct its_vlpi_map *get_vlpi_map(struct irq_data *d)
248{
249 if (irqd_is_forwarded_to_vcpu(d)) {
250 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
251 u32 event = its_get_event_id(d);
252
253 return dev_event_to_vlpi_map(its_dev, event);
254 }
255
256 return NULL;
257}
258
Marc Zyngierf3a059212020-03-04 20:33:10 +0000259static int vpe_to_cpuid_lock(struct its_vpe *vpe, unsigned long *flags)
Marc Zyngier425c09b2019-11-08 16:57:57 +0000260{
Marc Zyngierf3a059212020-03-04 20:33:10 +0000261 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags);
262 return vpe->col_idx;
263}
264
265static void vpe_to_cpuid_unlock(struct its_vpe *vpe, unsigned long flags)
266{
267 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
268}
269
270static int irq_to_cpuid_lock(struct irq_data *d, unsigned long *flags)
271{
272 struct its_vlpi_map *map = get_vlpi_map(d);
273 int cpu;
274
275 if (map) {
276 cpu = vpe_to_cpuid_lock(map->vpe, flags);
277 } else {
278 /* Physical LPIs are already locked via the irq_desc lock */
279 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
280 cpu = its_dev->event_map.col_map[its_get_event_id(d)];
281 /* Keep GCC quiet... */
282 *flags = 0;
283 }
284
285 return cpu;
286}
287
288static void irq_to_cpuid_unlock(struct irq_data *d, unsigned long flags)
289{
Marc Zyngierf4a81f52019-12-24 11:10:38 +0000290 struct its_vlpi_map *map = get_vlpi_map(d);
Marc Zyngier425c09b2019-11-08 16:57:57 +0000291
Marc Zyngierf4a81f52019-12-24 11:10:38 +0000292 if (map)
Marc Zyngierf3a059212020-03-04 20:33:10 +0000293 vpe_to_cpuid_unlock(map->vpe, flags);
Marc Zyngier425c09b2019-11-08 16:57:57 +0000294}
295
Marc Zyngier83559b42018-06-22 10:52:52 +0100296static struct its_collection *valid_col(struct its_collection *col)
297{
Joe Perches20faba82019-07-09 22:04:18 -0700298 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0)))
Marc Zyngier83559b42018-06-22 10:52:52 +0100299 return NULL;
300
301 return col;
302}
303
Marc Zyngier205e0652018-06-22 10:52:53 +0100304static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
305{
306 if (valid_col(its->collections + vpe->col_idx))
307 return vpe;
308
309 return NULL;
310}
311
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000312/*
313 * ITS command descriptors - parameters to be encoded in a command
314 * block.
315 */
316struct its_cmd_desc {
317 union {
318 struct {
319 struct its_device *dev;
320 u32 event_id;
321 } its_inv_cmd;
322
323 struct {
324 struct its_device *dev;
325 u32 event_id;
Marc Zyngier8d85dce2016-12-19 18:02:13 +0000326 } its_clear_cmd;
327
328 struct {
329 struct its_device *dev;
330 u32 event_id;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000331 } its_int_cmd;
332
333 struct {
334 struct its_device *dev;
335 int valid;
336 } its_mapd_cmd;
337
338 struct {
339 struct its_collection *col;
340 int valid;
341 } its_mapc_cmd;
342
343 struct {
344 struct its_device *dev;
345 u32 phys_id;
346 u32 event_id;
Marc Zyngier6a25ad32016-12-20 15:52:26 +0000347 } its_mapti_cmd;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000348
349 struct {
350 struct its_device *dev;
351 struct its_collection *col;
Marc Zyngier591e5be2015-07-17 10:46:42 +0100352 u32 event_id;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000353 } its_movi_cmd;
354
355 struct {
356 struct its_device *dev;
357 u32 event_id;
358 } its_discard_cmd;
359
360 struct {
361 struct its_collection *col;
362 } its_invall_cmd;
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000363
364 struct {
365 struct its_vpe *vpe;
Marc Zyngiereb781922016-12-20 14:47:05 +0000366 } its_vinvall_cmd;
367
368 struct {
369 struct its_vpe *vpe;
370 struct its_collection *col;
371 bool valid;
372 } its_vmapp_cmd;
373
374 struct {
375 struct its_vpe *vpe;
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000376 struct its_device *dev;
377 u32 virt_id;
378 u32 event_id;
379 bool db_enabled;
380 } its_vmapti_cmd;
381
382 struct {
383 struct its_vpe *vpe;
384 struct its_device *dev;
385 u32 event_id;
386 bool db_enabled;
387 } its_vmovi_cmd;
Marc Zyngier3171a472016-12-20 15:17:28 +0000388
389 struct {
390 struct its_vpe *vpe;
391 struct its_collection *col;
392 u16 seq_num;
393 u16 its_list;
394 } its_vmovp_cmd;
Marc Zyngierd97c97b2019-12-24 11:10:33 +0000395
396 struct {
397 struct its_vpe *vpe;
398 } its_invdb_cmd;
Marc Zyngiere252cf82020-03-04 20:33:16 +0000399
400 struct {
401 struct its_vpe *vpe;
402 u8 sgi;
403 u8 priority;
404 bool enable;
405 bool group;
406 bool clear;
407 } its_vsgi_cmd;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000408 };
409};
410
411/*
412 * The ITS command block, which is what the ITS actually parses.
413 */
414struct its_cmd_block {
Ben Dooks (Codethink)2bbdfcc2019-10-17 12:29:55 +0100415 union {
416 u64 raw_cmd[4];
417 __le64 raw_cmd_le[4];
418 };
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000419};
420
421#define ITS_CMD_QUEUE_SZ SZ_64K
422#define ITS_CMD_QUEUE_NR_ENTRIES (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
423
Marc Zyngier67047f902017-07-28 21:16:58 +0100424typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
425 struct its_cmd_block *,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000426 struct its_cmd_desc *);
427
Marc Zyngier67047f902017-07-28 21:16:58 +0100428typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
429 struct its_cmd_block *,
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000430 struct its_cmd_desc *);
431
Marc Zyngier4d36f132016-12-19 17:11:52 +0000432static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
433{
434 u64 mask = GENMASK_ULL(h, l);
435 *raw_cmd &= ~mask;
436 *raw_cmd |= (val << l) & mask;
437}
438
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000439static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
440{
Marc Zyngier4d36f132016-12-19 17:11:52 +0000441 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000442}
443
444static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
445{
Marc Zyngier4d36f132016-12-19 17:11:52 +0000446 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000447}
448
449static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
450{
Marc Zyngier4d36f132016-12-19 17:11:52 +0000451 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000452}
453
454static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
455{
Marc Zyngier4d36f132016-12-19 17:11:52 +0000456 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000457}
458
459static void its_encode_size(struct its_cmd_block *cmd, u8 size)
460{
Marc Zyngier4d36f132016-12-19 17:11:52 +0000461 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000462}
463
464static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
465{
Shanker Donthineni30ae9612017-10-09 11:46:55 -0500466 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000467}
468
469static void its_encode_valid(struct its_cmd_block *cmd, int valid)
470{
Marc Zyngier4d36f132016-12-19 17:11:52 +0000471 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000472}
473
474static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
475{
Shanker Donthineni30ae9612017-10-09 11:46:55 -0500476 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000477}
478
479static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
480{
Marc Zyngier4d36f132016-12-19 17:11:52 +0000481 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000482}
483
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000484static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
485{
486 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
487}
488
489static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
490{
491 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
492}
493
494static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
495{
496 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
497}
498
499static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
500{
501 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
502}
503
Marc Zyngier3171a472016-12-20 15:17:28 +0000504static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
505{
506 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
507}
508
509static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
510{
511 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
512}
513
Marc Zyngiereb781922016-12-20 14:47:05 +0000514static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
515{
Shanker Donthineni30ae9612017-10-09 11:46:55 -0500516 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
Marc Zyngiereb781922016-12-20 14:47:05 +0000517}
518
519static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
520{
521 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
522}
523
Marc Zyngier64edfaa2019-12-24 11:10:29 +0000524static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa)
525{
526 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16);
527}
528
529static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc)
530{
531 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8);
532}
533
534static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz)
535{
536 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9);
537}
538
539static void its_encode_vmapp_default_db(struct its_cmd_block *cmd,
540 u32 vpe_db_lpi)
541{
542 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0);
543}
544
Marc Zyngierdd3f0502019-12-24 11:10:31 +0000545static void its_encode_vmovp_default_db(struct its_cmd_block *cmd,
546 u32 vpe_db_lpi)
547{
548 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0);
549}
550
551static void its_encode_db(struct its_cmd_block *cmd, bool db)
552{
553 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63);
554}
555
Marc Zyngiere252cf82020-03-04 20:33:16 +0000556static void its_encode_sgi_intid(struct its_cmd_block *cmd, u8 sgi)
557{
558 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32);
559}
560
561static void its_encode_sgi_priority(struct its_cmd_block *cmd, u8 prio)
562{
563 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20);
564}
565
566static void its_encode_sgi_group(struct its_cmd_block *cmd, bool grp)
567{
568 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10);
569}
570
571static void its_encode_sgi_clear(struct its_cmd_block *cmd, bool clr)
572{
573 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9);
574}
575
576static void its_encode_sgi_enable(struct its_cmd_block *cmd, bool en)
577{
578 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8);
579}
580
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000581static inline void its_fixup_cmd(struct its_cmd_block *cmd)
582{
583 /* Let's fixup BE commands */
Ben Dooks (Codethink)2bbdfcc2019-10-17 12:29:55 +0100584 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]);
585 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]);
586 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]);
587 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000588}
589
Marc Zyngier67047f902017-07-28 21:16:58 +0100590static struct its_collection *its_build_mapd_cmd(struct its_node *its,
591 struct its_cmd_block *cmd,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000592 struct its_cmd_desc *desc)
593{
594 unsigned long itt_addr;
Marc Zyngierc8481262014-12-12 10:51:24 +0000595 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000596
597 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
598 itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
599
600 its_encode_cmd(cmd, GITS_CMD_MAPD);
601 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
602 its_encode_size(cmd, size - 1);
603 its_encode_itt(cmd, itt_addr);
604 its_encode_valid(cmd, desc->its_mapd_cmd.valid);
605
606 its_fixup_cmd(cmd);
607
Marc Zyngier591e5be2015-07-17 10:46:42 +0100608 return NULL;
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000609}
610
Marc Zyngier67047f902017-07-28 21:16:58 +0100611static struct its_collection *its_build_mapc_cmd(struct its_node *its,
612 struct its_cmd_block *cmd,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000613 struct its_cmd_desc *desc)
614{
615 its_encode_cmd(cmd, GITS_CMD_MAPC);
616 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
617 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
618 its_encode_valid(cmd, desc->its_mapc_cmd.valid);
619
620 its_fixup_cmd(cmd);
621
622 return desc->its_mapc_cmd.col;
623}
624
Marc Zyngier67047f902017-07-28 21:16:58 +0100625static struct its_collection *its_build_mapti_cmd(struct its_node *its,
626 struct its_cmd_block *cmd,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000627 struct its_cmd_desc *desc)
628{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100629 struct its_collection *col;
630
Marc Zyngier6a25ad32016-12-20 15:52:26 +0000631 col = dev_event_to_col(desc->its_mapti_cmd.dev,
632 desc->its_mapti_cmd.event_id);
Marc Zyngier591e5be2015-07-17 10:46:42 +0100633
Marc Zyngier6a25ad32016-12-20 15:52:26 +0000634 its_encode_cmd(cmd, GITS_CMD_MAPTI);
635 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
636 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
637 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
Marc Zyngier591e5be2015-07-17 10:46:42 +0100638 its_encode_collection(cmd, col->col_id);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000639
640 its_fixup_cmd(cmd);
641
Marc Zyngier83559b42018-06-22 10:52:52 +0100642 return valid_col(col);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000643}
644
Marc Zyngier67047f902017-07-28 21:16:58 +0100645static struct its_collection *its_build_movi_cmd(struct its_node *its,
646 struct its_cmd_block *cmd,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000647 struct its_cmd_desc *desc)
648{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100649 struct its_collection *col;
650
651 col = dev_event_to_col(desc->its_movi_cmd.dev,
652 desc->its_movi_cmd.event_id);
653
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000654 its_encode_cmd(cmd, GITS_CMD_MOVI);
655 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
Marc Zyngier591e5be2015-07-17 10:46:42 +0100656 its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000657 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
658
659 its_fixup_cmd(cmd);
660
Marc Zyngier83559b42018-06-22 10:52:52 +0100661 return valid_col(col);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000662}
663
Marc Zyngier67047f902017-07-28 21:16:58 +0100664static struct its_collection *its_build_discard_cmd(struct its_node *its,
665 struct its_cmd_block *cmd,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000666 struct its_cmd_desc *desc)
667{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100668 struct its_collection *col;
669
670 col = dev_event_to_col(desc->its_discard_cmd.dev,
671 desc->its_discard_cmd.event_id);
672
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000673 its_encode_cmd(cmd, GITS_CMD_DISCARD);
674 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
675 its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
676
677 its_fixup_cmd(cmd);
678
Marc Zyngier83559b42018-06-22 10:52:52 +0100679 return valid_col(col);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000680}
681
Marc Zyngier67047f902017-07-28 21:16:58 +0100682static struct its_collection *its_build_inv_cmd(struct its_node *its,
683 struct its_cmd_block *cmd,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000684 struct its_cmd_desc *desc)
685{
Marc Zyngier591e5be2015-07-17 10:46:42 +0100686 struct its_collection *col;
687
688 col = dev_event_to_col(desc->its_inv_cmd.dev,
689 desc->its_inv_cmd.event_id);
690
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000691 its_encode_cmd(cmd, GITS_CMD_INV);
692 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
693 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
694
695 its_fixup_cmd(cmd);
696
Marc Zyngier83559b42018-06-22 10:52:52 +0100697 return valid_col(col);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000698}
699
Marc Zyngier67047f902017-07-28 21:16:58 +0100700static struct its_collection *its_build_int_cmd(struct its_node *its,
701 struct its_cmd_block *cmd,
Marc Zyngier8d85dce2016-12-19 18:02:13 +0000702 struct its_cmd_desc *desc)
703{
704 struct its_collection *col;
705
706 col = dev_event_to_col(desc->its_int_cmd.dev,
707 desc->its_int_cmd.event_id);
708
709 its_encode_cmd(cmd, GITS_CMD_INT);
710 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
711 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
712
713 its_fixup_cmd(cmd);
714
Marc Zyngier83559b42018-06-22 10:52:52 +0100715 return valid_col(col);
Marc Zyngier8d85dce2016-12-19 18:02:13 +0000716}
717
Marc Zyngier67047f902017-07-28 21:16:58 +0100718static struct its_collection *its_build_clear_cmd(struct its_node *its,
719 struct its_cmd_block *cmd,
Marc Zyngier8d85dce2016-12-19 18:02:13 +0000720 struct its_cmd_desc *desc)
721{
722 struct its_collection *col;
723
724 col = dev_event_to_col(desc->its_clear_cmd.dev,
725 desc->its_clear_cmd.event_id);
726
727 its_encode_cmd(cmd, GITS_CMD_CLEAR);
728 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
729 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
730
731 its_fixup_cmd(cmd);
732
Marc Zyngier83559b42018-06-22 10:52:52 +0100733 return valid_col(col);
Marc Zyngier8d85dce2016-12-19 18:02:13 +0000734}
735
Marc Zyngier67047f902017-07-28 21:16:58 +0100736static struct its_collection *its_build_invall_cmd(struct its_node *its,
737 struct its_cmd_block *cmd,
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000738 struct its_cmd_desc *desc)
739{
740 its_encode_cmd(cmd, GITS_CMD_INVALL);
Zenghui Yu10794522019-12-02 15:10:21 +0800741 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id);
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000742
743 its_fixup_cmd(cmd);
744
745 return NULL;
746}
747
Marc Zyngier67047f902017-07-28 21:16:58 +0100748static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
749 struct its_cmd_block *cmd,
Marc Zyngiereb781922016-12-20 14:47:05 +0000750 struct its_cmd_desc *desc)
751{
752 its_encode_cmd(cmd, GITS_CMD_VINVALL);
753 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);
754
755 its_fixup_cmd(cmd);
756
Marc Zyngier205e0652018-06-22 10:52:53 +0100757 return valid_vpe(its, desc->its_vinvall_cmd.vpe);
Marc Zyngiereb781922016-12-20 14:47:05 +0000758}
759
Marc Zyngier67047f902017-07-28 21:16:58 +0100760static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
761 struct its_cmd_block *cmd,
Marc Zyngiereb781922016-12-20 14:47:05 +0000762 struct its_cmd_desc *desc)
763{
Marc Zyngier64edfaa2019-12-24 11:10:29 +0000764 unsigned long vpt_addr, vconf_addr;
Marc Zyngier5c9a8822017-07-28 21:20:37 +0100765 u64 target;
Marc Zyngier64edfaa2019-12-24 11:10:29 +0000766 bool alloc;
Marc Zyngiereb781922016-12-20 14:47:05 +0000767
768 its_encode_cmd(cmd, GITS_CMD_VMAPP);
769 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
770 its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
Marc Zyngier64edfaa2019-12-24 11:10:29 +0000771
772 if (!desc->its_vmapp_cmd.valid) {
773 if (is_v4_1(its)) {
774 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count);
775 its_encode_alloc(cmd, alloc);
776 }
777
778 goto out;
779 }
780
781 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
782 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
783
Marc Zyngier5c9a8822017-07-28 21:20:37 +0100784 its_encode_target(cmd, target);
Marc Zyngiereb781922016-12-20 14:47:05 +0000785 its_encode_vpt_addr(cmd, vpt_addr);
786 its_encode_vpt_size(cmd, LPI_NRBITS - 1);
787
Marc Zyngier64edfaa2019-12-24 11:10:29 +0000788 if (!is_v4_1(its))
789 goto out;
790
791 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page));
792
793 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count);
794
795 its_encode_alloc(cmd, alloc);
796
797 /* We can only signal PTZ when alloc==1. Why do we have two bits? */
798 its_encode_ptz(cmd, alloc);
799 its_encode_vconf_addr(cmd, vconf_addr);
800 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi);
801
802out:
Marc Zyngiereb781922016-12-20 14:47:05 +0000803 its_fixup_cmd(cmd);
804
Marc Zyngier205e0652018-06-22 10:52:53 +0100805 return valid_vpe(its, desc->its_vmapp_cmd.vpe);
Marc Zyngiereb781922016-12-20 14:47:05 +0000806}
807
Marc Zyngier67047f902017-07-28 21:16:58 +0100808static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
809 struct its_cmd_block *cmd,
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000810 struct its_cmd_desc *desc)
811{
812 u32 db;
813
Marc Zyngier3858d4d2019-12-24 11:10:37 +0000814 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled)
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000815 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
816 else
817 db = 1023;
818
819 its_encode_cmd(cmd, GITS_CMD_VMAPTI);
820 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
821 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
822 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
823 its_encode_db_phys_id(cmd, db);
824 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);
825
826 its_fixup_cmd(cmd);
827
Marc Zyngier205e0652018-06-22 10:52:53 +0100828 return valid_vpe(its, desc->its_vmapti_cmd.vpe);
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000829}
830
Marc Zyngier67047f902017-07-28 21:16:58 +0100831static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
832 struct its_cmd_block *cmd,
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000833 struct its_cmd_desc *desc)
834{
835 u32 db;
836
Marc Zyngier3858d4d2019-12-24 11:10:37 +0000837 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled)
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000838 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
839 else
840 db = 1023;
841
842 its_encode_cmd(cmd, GITS_CMD_VMOVI);
843 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
844 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
845 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
846 its_encode_db_phys_id(cmd, db);
847 its_encode_db_valid(cmd, true);
848
849 its_fixup_cmd(cmd);
850
Marc Zyngier205e0652018-06-22 10:52:53 +0100851 return valid_vpe(its, desc->its_vmovi_cmd.vpe);
Marc Zyngierd011e4e2016-12-20 09:44:41 +0000852}
853
Marc Zyngier67047f902017-07-28 21:16:58 +0100854static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
855 struct its_cmd_block *cmd,
Marc Zyngier3171a472016-12-20 15:17:28 +0000856 struct its_cmd_desc *desc)
857{
Marc Zyngier5c9a8822017-07-28 21:20:37 +0100858 u64 target;
859
860 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
Marc Zyngier3171a472016-12-20 15:17:28 +0000861 its_encode_cmd(cmd, GITS_CMD_VMOVP);
862 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
863 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
864 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
Marc Zyngier5c9a8822017-07-28 21:20:37 +0100865 its_encode_target(cmd, target);
Marc Zyngier3171a472016-12-20 15:17:28 +0000866
Marc Zyngierdd3f0502019-12-24 11:10:31 +0000867 if (is_v4_1(its)) {
868 its_encode_db(cmd, true);
869 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi);
870 }
871
Marc Zyngier3171a472016-12-20 15:17:28 +0000872 its_fixup_cmd(cmd);
873
Marc Zyngier205e0652018-06-22 10:52:53 +0100874 return valid_vpe(its, desc->its_vmovp_cmd.vpe);
Marc Zyngier3171a472016-12-20 15:17:28 +0000875}
876
Marc Zyngier28614692019-11-08 16:58:02 +0000877static struct its_vpe *its_build_vinv_cmd(struct its_node *its,
878 struct its_cmd_block *cmd,
879 struct its_cmd_desc *desc)
880{
881 struct its_vlpi_map *map;
882
883 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev,
884 desc->its_inv_cmd.event_id);
885
886 its_encode_cmd(cmd, GITS_CMD_INV);
887 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
888 its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
889
890 its_fixup_cmd(cmd);
891
892 return valid_vpe(its, map->vpe);
893}
894
Marc Zyngiered0e4aa2019-11-08 16:58:03 +0000895static struct its_vpe *its_build_vint_cmd(struct its_node *its,
896 struct its_cmd_block *cmd,
897 struct its_cmd_desc *desc)
898{
899 struct its_vlpi_map *map;
900
901 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev,
902 desc->its_int_cmd.event_id);
903
904 its_encode_cmd(cmd, GITS_CMD_INT);
905 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
906 its_encode_event_id(cmd, desc->its_int_cmd.event_id);
907
908 its_fixup_cmd(cmd);
909
910 return valid_vpe(its, map->vpe);
911}
912
913static struct its_vpe *its_build_vclear_cmd(struct its_node *its,
914 struct its_cmd_block *cmd,
915 struct its_cmd_desc *desc)
916{
917 struct its_vlpi_map *map;
918
919 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev,
920 desc->its_clear_cmd.event_id);
921
922 its_encode_cmd(cmd, GITS_CMD_CLEAR);
923 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
924 its_encode_event_id(cmd, desc->its_clear_cmd.event_id);
925
926 its_fixup_cmd(cmd);
927
928 return valid_vpe(its, map->vpe);
929}
930
Marc Zyngierd97c97b2019-12-24 11:10:33 +0000931static struct its_vpe *its_build_invdb_cmd(struct its_node *its,
932 struct its_cmd_block *cmd,
933 struct its_cmd_desc *desc)
934{
935 if (WARN_ON(!is_v4_1(its)))
936 return NULL;
937
938 its_encode_cmd(cmd, GITS_CMD_INVDB);
939 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id);
940
941 its_fixup_cmd(cmd);
942
943 return valid_vpe(its, desc->its_invdb_cmd.vpe);
944}
945
Marc Zyngiere252cf82020-03-04 20:33:16 +0000946static struct its_vpe *its_build_vsgi_cmd(struct its_node *its,
947 struct its_cmd_block *cmd,
948 struct its_cmd_desc *desc)
949{
950 if (WARN_ON(!is_v4_1(its)))
951 return NULL;
952
953 its_encode_cmd(cmd, GITS_CMD_VSGI);
954 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id);
955 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi);
956 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority);
957 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group);
958 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear);
959 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable);
960
961 its_fixup_cmd(cmd);
962
963 return valid_vpe(its, desc->its_vsgi_cmd.vpe);
964}
965
Marc Zyngiercc2d3212014-11-24 14:35:11 +0000966static u64 its_cmd_ptr_to_offset(struct its_node *its,
967 struct its_cmd_block *ptr)
968{
969 return (ptr - its->cmd_base) * sizeof(*ptr);
970}
971
972static int its_queue_full(struct its_node *its)
973{
974 int widx;
975 int ridx;
976
977 widx = its->cmd_write - its->cmd_base;
978 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
979
980 /* This is incredibly unlikely to happen, unless the ITS locks up. */
981 if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
982 return 1;
983
984 return 0;
985}
986
987static struct its_cmd_block *its_allocate_entry(struct its_node *its)
988{
989 struct its_cmd_block *cmd;
990 u32 count = 1000000; /* 1s! */
991
992 while (its_queue_full(its)) {
993 count--;
994 if (!count) {
995 pr_err_ratelimited("ITS queue not draining\n");
996 return NULL;
997 }
998 cpu_relax();
999 udelay(1);
1000 }
1001
1002 cmd = its->cmd_write++;
1003
1004 /* Handle queue wrapping */
1005 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
1006 its->cmd_write = its->cmd_base;
1007
Marc Zyngier34d677a2016-12-19 17:16:45 +00001008 /* Clear command */
1009 cmd->raw_cmd[0] = 0;
1010 cmd->raw_cmd[1] = 0;
1011 cmd->raw_cmd[2] = 0;
1012 cmd->raw_cmd[3] = 0;
1013
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001014 return cmd;
1015}
1016
1017static struct its_cmd_block *its_post_commands(struct its_node *its)
1018{
1019 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
1020
1021 writel_relaxed(wr, its->base + GITS_CWRITER);
1022
1023 return its->cmd_write;
1024}
1025
1026static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
1027{
1028 /*
1029 * Make sure the commands written to memory are observable by
1030 * the ITS.
1031 */
1032 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
Vladimir Murzin328191c2016-11-02 11:54:05 +00001033 gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001034 else
1035 dsb(ishst);
1036}
1037
Marc Zyngiera19b4622017-08-04 17:45:50 +01001038static int its_wait_for_range_completion(struct its_node *its,
Heyi Guoa050fa52019-05-13 19:42:06 +08001039 u64 prev_idx,
Marc Zyngiera19b4622017-08-04 17:45:50 +01001040 struct its_cmd_block *to)
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001041{
Heyi Guoa050fa52019-05-13 19:42:06 +08001042 u64 rd_idx, to_idx, linear_idx;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001043 u32 count = 1000000; /* 1s! */
1044
Heyi Guoa050fa52019-05-13 19:42:06 +08001045 /* Linearize to_idx if the command set has wrapped around */
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001046 to_idx = its_cmd_ptr_to_offset(its, to);
Heyi Guoa050fa52019-05-13 19:42:06 +08001047 if (to_idx < prev_idx)
1048 to_idx += ITS_CMD_QUEUE_SZ;
1049
1050 linear_idx = prev_idx;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001051
1052 while (1) {
Heyi Guoa050fa52019-05-13 19:42:06 +08001053 s64 delta;
1054
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001055 rd_idx = readl_relaxed(its->base + GITS_CREADR);
Marc Zyngier9bdd8b12017-08-19 10:16:02 +01001056
Heyi Guoa050fa52019-05-13 19:42:06 +08001057 /*
1058 * Compute the read pointer progress, taking the
1059 * potential wrap-around into account.
1060 */
1061 delta = rd_idx - prev_idx;
1062 if (rd_idx < prev_idx)
1063 delta += ITS_CMD_QUEUE_SZ;
Marc Zyngier9bdd8b12017-08-19 10:16:02 +01001064
Heyi Guoa050fa52019-05-13 19:42:06 +08001065 linear_idx += delta;
1066 if (linear_idx >= to_idx)
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001067 break;
1068
1069 count--;
1070 if (!count) {
Heyi Guoa050fa52019-05-13 19:42:06 +08001071 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
1072 to_idx, linear_idx);
Marc Zyngiera19b4622017-08-04 17:45:50 +01001073 return -1;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001074 }
Heyi Guoa050fa52019-05-13 19:42:06 +08001075 prev_idx = rd_idx;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001076 cpu_relax();
1077 udelay(1);
1078 }
Marc Zyngiera19b4622017-08-04 17:45:50 +01001079
1080 return 0;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001081}
1082
Marc Zyngiere4f90942016-12-19 17:56:32 +00001083/* Warning, macro hell follows */
1084#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn) \
1085void name(struct its_node *its, \
1086 buildtype builder, \
1087 struct its_cmd_desc *desc) \
1088{ \
1089 struct its_cmd_block *cmd, *sync_cmd, *next_cmd; \
1090 synctype *sync_obj; \
1091 unsigned long flags; \
Heyi Guoa050fa52019-05-13 19:42:06 +08001092 u64 rd_idx; \
Marc Zyngiere4f90942016-12-19 17:56:32 +00001093 \
1094 raw_spin_lock_irqsave(&its->lock, flags); \
1095 \
1096 cmd = its_allocate_entry(its); \
1097 if (!cmd) { /* We're soooooo screewed... */ \
1098 raw_spin_unlock_irqrestore(&its->lock, flags); \
1099 return; \
1100 } \
Marc Zyngier67047f902017-07-28 21:16:58 +01001101 sync_obj = builder(its, cmd, desc); \
Marc Zyngiere4f90942016-12-19 17:56:32 +00001102 its_flush_cmd(its, cmd); \
1103 \
1104 if (sync_obj) { \
1105 sync_cmd = its_allocate_entry(its); \
1106 if (!sync_cmd) \
1107 goto post; \
1108 \
Marc Zyngier67047f902017-07-28 21:16:58 +01001109 buildfn(its, sync_cmd, sync_obj); \
Marc Zyngiere4f90942016-12-19 17:56:32 +00001110 its_flush_cmd(its, sync_cmd); \
1111 } \
1112 \
1113post: \
Heyi Guoa050fa52019-05-13 19:42:06 +08001114 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
Marc Zyngiere4f90942016-12-19 17:56:32 +00001115 next_cmd = its_post_commands(its); \
1116 raw_spin_unlock_irqrestore(&its->lock, flags); \
1117 \
Heyi Guoa050fa52019-05-13 19:42:06 +08001118 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
Marc Zyngiera19b4622017-08-04 17:45:50 +01001119 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001120}
1121
Marc Zyngier67047f902017-07-28 21:16:58 +01001122static void its_build_sync_cmd(struct its_node *its,
1123 struct its_cmd_block *sync_cmd,
Marc Zyngiere4f90942016-12-19 17:56:32 +00001124 struct its_collection *sync_col)
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001125{
Marc Zyngiere4f90942016-12-19 17:56:32 +00001126 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
1127 its_encode_target(sync_cmd, sync_col->target_address);
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001128
Marc Zyngiere4f90942016-12-19 17:56:32 +00001129 its_fixup_cmd(sync_cmd);
1130}
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001131
Marc Zyngiere4f90942016-12-19 17:56:32 +00001132static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
1133 struct its_collection, its_build_sync_cmd)
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001134
Marc Zyngier67047f902017-07-28 21:16:58 +01001135static void its_build_vsync_cmd(struct its_node *its,
1136 struct its_cmd_block *sync_cmd,
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001137 struct its_vpe *sync_vpe)
1138{
1139 its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
1140 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001141
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001142 its_fixup_cmd(sync_cmd);
1143}
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001144
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001145static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
1146 struct its_vpe, its_build_vsync_cmd)
1147
Marc Zyngier8d85dce2016-12-19 18:02:13 +00001148static void its_send_int(struct its_device *dev, u32 event_id)
1149{
1150 struct its_cmd_desc desc;
1151
1152 desc.its_int_cmd.dev = dev;
1153 desc.its_int_cmd.event_id = event_id;
1154
1155 its_send_single_command(dev->its, its_build_int_cmd, &desc);
1156}
1157
1158static void its_send_clear(struct its_device *dev, u32 event_id)
1159{
1160 struct its_cmd_desc desc;
1161
1162 desc.its_clear_cmd.dev = dev;
1163 desc.its_clear_cmd.event_id = event_id;
1164
1165 its_send_single_command(dev->its, its_build_clear_cmd, &desc);
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001166}
1167
1168static void its_send_inv(struct its_device *dev, u32 event_id)
1169{
1170 struct its_cmd_desc desc;
1171
1172 desc.its_inv_cmd.dev = dev;
1173 desc.its_inv_cmd.event_id = event_id;
1174
1175 its_send_single_command(dev->its, its_build_inv_cmd, &desc);
1176}
1177
1178static void its_send_mapd(struct its_device *dev, int valid)
1179{
1180 struct its_cmd_desc desc;
1181
1182 desc.its_mapd_cmd.dev = dev;
1183 desc.its_mapd_cmd.valid = !!valid;
1184
1185 its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
1186}
1187
1188static void its_send_mapc(struct its_node *its, struct its_collection *col,
1189 int valid)
1190{
1191 struct its_cmd_desc desc;
1192
1193 desc.its_mapc_cmd.col = col;
1194 desc.its_mapc_cmd.valid = !!valid;
1195
1196 its_send_single_command(its, its_build_mapc_cmd, &desc);
1197}
1198
Marc Zyngier6a25ad32016-12-20 15:52:26 +00001199static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001200{
1201 struct its_cmd_desc desc;
1202
Marc Zyngier6a25ad32016-12-20 15:52:26 +00001203 desc.its_mapti_cmd.dev = dev;
1204 desc.its_mapti_cmd.phys_id = irq_id;
1205 desc.its_mapti_cmd.event_id = id;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001206
Marc Zyngier6a25ad32016-12-20 15:52:26 +00001207 its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001208}
1209
1210static void its_send_movi(struct its_device *dev,
1211 struct its_collection *col, u32 id)
1212{
1213 struct its_cmd_desc desc;
1214
1215 desc.its_movi_cmd.dev = dev;
1216 desc.its_movi_cmd.col = col;
Marc Zyngier591e5be2015-07-17 10:46:42 +01001217 desc.its_movi_cmd.event_id = id;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00001218
1219 its_send_single_command(dev->its, its_build_movi_cmd, &desc);
1220}
1221
1222static void its_send_discard(struct its_device *dev, u32 id)
1223{
1224 struct its_cmd_desc desc;
1225
1226 desc.its_discard_cmd.dev = dev;
1227 desc.its_discard_cmd.event_id = id;
1228
1229 its_send_single_command(dev->its, its_build_discard_cmd, &desc);
1230}
1231
1232static void its_send_invall(struct its_node *its, struct its_collection *col)
1233{
1234 struct its_cmd_desc desc;
1235
1236 desc.its_invall_cmd.col = col;
1237
1238 its_send_single_command(its, its_build_invall_cmd, &desc);
1239}
Marc Zyngierc48ed512014-11-24 14:35:12 +00001240
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001241static void its_send_vmapti(struct its_device *dev, u32 id)
1242{
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001243 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001244 struct its_cmd_desc desc;
1245
1246 desc.its_vmapti_cmd.vpe = map->vpe;
1247 desc.its_vmapti_cmd.dev = dev;
1248 desc.its_vmapti_cmd.virt_id = map->vintid;
1249 desc.its_vmapti_cmd.event_id = id;
1250 desc.its_vmapti_cmd.db_enabled = map->db_enabled;
1251
1252 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
1253}
1254
1255static void its_send_vmovi(struct its_device *dev, u32 id)
1256{
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001257 struct its_vlpi_map *map = dev_event_to_vlpi_map(dev, id);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001258 struct its_cmd_desc desc;
1259
1260 desc.its_vmovi_cmd.vpe = map->vpe;
1261 desc.its_vmovi_cmd.dev = dev;
1262 desc.its_vmovi_cmd.event_id = id;
1263 desc.its_vmovi_cmd.db_enabled = map->db_enabled;
1264
1265 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
1266}
1267
Marc Zyngier75fd9512017-10-08 18:46:39 +01001268static void its_send_vmapp(struct its_node *its,
1269 struct its_vpe *vpe, bool valid)
Marc Zyngiereb781922016-12-20 14:47:05 +00001270{
1271 struct its_cmd_desc desc;
Marc Zyngiereb781922016-12-20 14:47:05 +00001272
1273 desc.its_vmapp_cmd.vpe = vpe;
1274 desc.its_vmapp_cmd.valid = valid;
Marc Zyngier75fd9512017-10-08 18:46:39 +01001275 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
Marc Zyngiereb781922016-12-20 14:47:05 +00001276
Marc Zyngier75fd9512017-10-08 18:46:39 +01001277 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
Marc Zyngiereb781922016-12-20 14:47:05 +00001278}
1279
Marc Zyngier3171a472016-12-20 15:17:28 +00001280static void its_send_vmovp(struct its_vpe *vpe)
1281{
Zenghui Yu84243122019-10-23 03:46:26 +00001282 struct its_cmd_desc desc = {};
Marc Zyngier3171a472016-12-20 15:17:28 +00001283 struct its_node *its;
1284 unsigned long flags;
1285 int col_id = vpe->col_idx;
1286
1287 desc.its_vmovp_cmd.vpe = vpe;
Marc Zyngier3171a472016-12-20 15:17:28 +00001288
1289 if (!its_list_map) {
1290 its = list_first_entry(&its_nodes, struct its_node, entry);
Marc Zyngier3171a472016-12-20 15:17:28 +00001291 desc.its_vmovp_cmd.col = &its->collections[col_id];
1292 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1293 return;
1294 }
1295
1296 /*
1297 * Yet another marvel of the architecture. If using the
1298 * its_list "feature", we need to make sure that all ITSs
1299 * receive all VMOVP commands in the same order. The only way
1300 * to guarantee this is to make vmovp a serialization point.
1301 *
1302 * Wall <-- Head.
1303 */
1304 raw_spin_lock_irqsave(&vmovp_lock, flags);
1305
1306 desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;
Zenghui Yu84243122019-10-23 03:46:26 +00001307 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm);
Marc Zyngier3171a472016-12-20 15:17:28 +00001308
1309 /* Emit VMOVPs */
1310 list_for_each_entry(its, &its_nodes, entry) {
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00001311 if (!is_v4(its))
Marc Zyngier3171a472016-12-20 15:17:28 +00001312 continue;
1313
Marc Zyngier009384b2020-03-04 20:33:23 +00001314 if (!require_its_list_vmovp(vpe->its_vm, its))
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001315 continue;
1316
Marc Zyngier3171a472016-12-20 15:17:28 +00001317 desc.its_vmovp_cmd.col = &its->collections[col_id];
1318 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
1319 }
1320
1321 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1322}
1323
Marc Zyngier40619a22017-10-08 15:16:09 +01001324static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
Marc Zyngiereb781922016-12-20 14:47:05 +00001325{
1326 struct its_cmd_desc desc;
Marc Zyngiereb781922016-12-20 14:47:05 +00001327
1328 desc.its_vinvall_cmd.vpe = vpe;
Marc Zyngier40619a22017-10-08 15:16:09 +01001329 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
Marc Zyngiereb781922016-12-20 14:47:05 +00001330}
1331
Marc Zyngier28614692019-11-08 16:58:02 +00001332static void its_send_vinv(struct its_device *dev, u32 event_id)
1333{
1334 struct its_cmd_desc desc;
1335
1336 /*
1337 * There is no real VINV command. This is just a normal INV,
1338 * with a VSYNC instead of a SYNC.
1339 */
1340 desc.its_inv_cmd.dev = dev;
1341 desc.its_inv_cmd.event_id = event_id;
1342
1343 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc);
1344}
1345
Marc Zyngiered0e4aa2019-11-08 16:58:03 +00001346static void its_send_vint(struct its_device *dev, u32 event_id)
1347{
1348 struct its_cmd_desc desc;
1349
1350 /*
1351 * There is no real VINT command. This is just a normal INT,
1352 * with a VSYNC instead of a SYNC.
1353 */
1354 desc.its_int_cmd.dev = dev;
1355 desc.its_int_cmd.event_id = event_id;
1356
1357 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc);
1358}
1359
1360static void its_send_vclear(struct its_device *dev, u32 event_id)
1361{
1362 struct its_cmd_desc desc;
1363
1364 /*
1365 * There is no real VCLEAR command. This is just a normal CLEAR,
1366 * with a VSYNC instead of a SYNC.
1367 */
1368 desc.its_clear_cmd.dev = dev;
1369 desc.its_clear_cmd.event_id = event_id;
1370
1371 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc);
1372}
1373
Marc Zyngierd97c97b2019-12-24 11:10:33 +00001374static void its_send_invdb(struct its_node *its, struct its_vpe *vpe)
1375{
1376 struct its_cmd_desc desc;
1377
1378 desc.its_invdb_cmd.vpe = vpe;
1379 its_send_single_vcommand(its, its_build_invdb_cmd, &desc);
1380}
1381
Marc Zyngierc48ed512014-11-24 14:35:12 +00001382/*
1383 * irqchip functions - assumes MSI, mostly.
1384 */
Marc Zyngier015ec032016-12-20 09:54:57 +00001385static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
Marc Zyngierc48ed512014-11-24 14:35:12 +00001386{
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001387 struct its_vlpi_map *map = get_vlpi_map(d);
Marc Zyngier015ec032016-12-20 09:54:57 +00001388 irq_hw_number_t hwirq;
Marc Zyngiere1a2e202018-07-27 14:36:00 +01001389 void *va;
Marc Zyngieradcdb942016-12-19 19:18:13 +00001390 u8 *cfg;
Marc Zyngierc48ed512014-11-24 14:35:12 +00001391
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001392 if (map) {
1393 va = page_address(map->vm->vprop_page);
Marc Zyngierd4d7b4a2017-10-26 10:44:07 +01001394 hwirq = map->vintid;
1395
1396 /* Remember the updated property */
1397 map->properties &= ~clr;
1398 map->properties |= set | LPI_PROP_GROUP1;
Marc Zyngier015ec032016-12-20 09:54:57 +00001399 } else {
Marc Zyngiere1a2e202018-07-27 14:36:00 +01001400 va = gic_rdists->prop_table_va;
Marc Zyngier015ec032016-12-20 09:54:57 +00001401 hwirq = d->hwirq;
1402 }
Marc Zyngieradcdb942016-12-19 19:18:13 +00001403
Marc Zyngiere1a2e202018-07-27 14:36:00 +01001404 cfg = va + hwirq - 8192;
Marc Zyngieradcdb942016-12-19 19:18:13 +00001405 *cfg &= ~clr;
Marc Zyngier015ec032016-12-20 09:54:57 +00001406 *cfg |= set | LPI_PROP_GROUP1;
Marc Zyngierc48ed512014-11-24 14:35:12 +00001407
1408 /*
1409 * Make the above write visible to the redistributors.
1410 * And yes, we're flushing exactly: One. Single. Byte.
1411 * Humpf...
1412 */
1413 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
Vladimir Murzin328191c2016-11-02 11:54:05 +00001414 gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
Marc Zyngierc48ed512014-11-24 14:35:12 +00001415 else
1416 dsb(ishst);
Marc Zyngier015ec032016-12-20 09:54:57 +00001417}
1418
Marc Zyngier2f4f0642019-11-08 16:57:56 +00001419static void wait_for_syncr(void __iomem *rdbase)
1420{
Heyi Guo04d80db2020-02-25 17:00:23 +08001421 while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
Marc Zyngier2f4f0642019-11-08 16:57:56 +00001422 cpu_relax();
1423}
1424
Marc Zyngier425c09b2019-11-08 16:57:57 +00001425static void direct_lpi_inv(struct irq_data *d)
1426{
Marc Zyngierf4a81f52019-12-24 11:10:38 +00001427 struct its_vlpi_map *map = get_vlpi_map(d);
Marc Zyngier425c09b2019-11-08 16:57:57 +00001428 void __iomem *rdbase;
Marc Zyngierf3a059212020-03-04 20:33:10 +00001429 unsigned long flags;
Marc Zyngierf4a81f52019-12-24 11:10:38 +00001430 u64 val;
Marc Zyngierf3a059212020-03-04 20:33:10 +00001431 int cpu;
Marc Zyngierf4a81f52019-12-24 11:10:38 +00001432
1433 if (map) {
1434 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1435
1436 WARN_ON(!is_v4_1(its_dev->its));
1437
1438 val = GICR_INVLPIR_V;
1439 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id);
1440 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid);
1441 } else {
1442 val = d->hwirq;
1443 }
Marc Zyngier425c09b2019-11-08 16:57:57 +00001444
1445 /* Target the redistributor this LPI is currently routed to */
Marc Zyngierf3a059212020-03-04 20:33:10 +00001446 cpu = irq_to_cpuid_lock(d, &flags);
Marc Zyngier9058a4e2020-03-04 20:33:12 +00001447 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
Marc Zyngierf3a059212020-03-04 20:33:10 +00001448 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
Marc Zyngierf4a81f52019-12-24 11:10:38 +00001449 gic_write_lpir(val, rdbase + GICR_INVLPIR);
Marc Zyngier425c09b2019-11-08 16:57:57 +00001450
1451 wait_for_syncr(rdbase);
Marc Zyngier9058a4e2020-03-04 20:33:12 +00001452 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
Marc Zyngierf3a059212020-03-04 20:33:10 +00001453 irq_to_cpuid_unlock(d, flags);
Marc Zyngier425c09b2019-11-08 16:57:57 +00001454}
1455
Marc Zyngier015ec032016-12-20 09:54:57 +00001456static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
1457{
1458 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1459
1460 lpi_write_config(d, clr, set);
Marc Zyngierf4a81f52019-12-24 11:10:38 +00001461 if (gic_rdists->has_direct_lpi &&
1462 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d)))
Marc Zyngier425c09b2019-11-08 16:57:57 +00001463 direct_lpi_inv(d);
Marc Zyngier28614692019-11-08 16:58:02 +00001464 else if (!irqd_is_forwarded_to_vcpu(d))
Marc Zyngier425c09b2019-11-08 16:57:57 +00001465 its_send_inv(its_dev, its_get_event_id(d));
Marc Zyngier28614692019-11-08 16:58:02 +00001466 else
1467 its_send_vinv(its_dev, its_get_event_id(d));
Marc Zyngierc48ed512014-11-24 14:35:12 +00001468}
1469
Marc Zyngier015ec032016-12-20 09:54:57 +00001470static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
1471{
1472 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1473 u32 event = its_get_event_id(d);
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001474 struct its_vlpi_map *map;
Marc Zyngier015ec032016-12-20 09:54:57 +00001475
Marc Zyngier3858d4d2019-12-24 11:10:37 +00001476 /*
1477 * GICv4.1 does away with the per-LPI nonsense, nothing to do
1478 * here.
1479 */
1480 if (is_v4_1(its_dev->its))
1481 return;
1482
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001483 map = dev_event_to_vlpi_map(its_dev, event);
1484
1485 if (map->db_enabled == enable)
Marc Zyngier015ec032016-12-20 09:54:57 +00001486 return;
1487
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001488 map->db_enabled = enable;
Marc Zyngier015ec032016-12-20 09:54:57 +00001489
1490 /*
1491 * More fun with the architecture:
1492 *
1493 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
1494 * value or to 1023, depending on the enable bit. But that
1495 * would be issueing a mapping for an /existing/ DevID+EventID
1496 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
1497 * to the /same/ vPE, using this opportunity to adjust the
1498 * doorbell. Mouahahahaha. We loves it, Precious.
1499 */
1500 its_send_vmovi(its_dev, event);
Marc Zyngierc48ed512014-11-24 14:35:12 +00001501}
1502
1503static void its_mask_irq(struct irq_data *d)
1504{
Marc Zyngier015ec032016-12-20 09:54:57 +00001505 if (irqd_is_forwarded_to_vcpu(d))
1506 its_vlpi_set_doorbell(d, false);
1507
Marc Zyngieradcdb942016-12-19 19:18:13 +00001508 lpi_update_config(d, LPI_PROP_ENABLED, 0);
Marc Zyngierc48ed512014-11-24 14:35:12 +00001509}
1510
1511static void its_unmask_irq(struct irq_data *d)
1512{
Marc Zyngier015ec032016-12-20 09:54:57 +00001513 if (irqd_is_forwarded_to_vcpu(d))
1514 its_vlpi_set_doorbell(d, true);
1515
Marc Zyngieradcdb942016-12-19 19:18:13 +00001516 lpi_update_config(d, 0, LPI_PROP_ENABLED);
Marc Zyngierc48ed512014-11-24 14:35:12 +00001517}
1518
Marc Zyngier2f13ff12020-05-15 17:57:51 +01001519static __maybe_unused u32 its_read_lpi_count(struct irq_data *d, int cpu)
1520{
1521 if (irqd_affinity_is_managed(d))
1522 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1523
1524 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1525}
1526
1527static void its_inc_lpi_count(struct irq_data *d, int cpu)
1528{
1529 if (irqd_affinity_is_managed(d))
1530 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1531 else
1532 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1533}
1534
1535static void its_dec_lpi_count(struct irq_data *d, int cpu)
1536{
1537 if (irqd_affinity_is_managed(d))
1538 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed);
1539 else
1540 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged);
1541}
1542
Marc Zyngierc5d60822020-05-15 17:57:52 +01001543static unsigned int cpumask_pick_least_loaded(struct irq_data *d,
1544 const struct cpumask *cpu_mask)
1545{
1546 unsigned int cpu = nr_cpu_ids, tmp;
1547 int count = S32_MAX;
1548
1549 for_each_cpu(tmp, cpu_mask) {
1550 int this_count = its_read_lpi_count(d, tmp);
1551 if (this_count < count) {
1552 cpu = tmp;
1553 count = this_count;
1554 }
1555 }
1556
1557 return cpu;
1558}
1559
1560/*
1561 * As suggested by Thomas Gleixner in:
1562 * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
1563 */
1564static int its_select_cpu(struct irq_data *d,
1565 const struct cpumask *aff_mask)
1566{
1567 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1568 cpumask_var_t tmpmask;
1569 int cpu, node;
1570
1571 if (!alloc_cpumask_var(&tmpmask, GFP_ATOMIC))
1572 return -ENOMEM;
1573
1574 node = its_dev->its->numa_node;
1575
1576 if (!irqd_affinity_is_managed(d)) {
1577 /* First try the NUMA node */
1578 if (node != NUMA_NO_NODE) {
1579 /*
1580 * Try the intersection of the affinity mask and the
1581 * node mask (and the online mask, just to be safe).
1582 */
1583 cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
1584 cpumask_and(tmpmask, tmpmask, cpu_online_mask);
1585
1586 /*
1587 * Ideally, we would check if the mask is empty, and
1588 * try again on the full node here.
1589 *
1590 * But it turns out that the way ACPI describes the
1591 * affinity for ITSs only deals about memory, and
1592 * not target CPUs, so it cannot describe a single
1593 * ITS placed next to two NUMA nodes.
1594 *
1595 * Instead, just fallback on the online mask. This
1596 * diverges from Thomas' suggestion above.
1597 */
1598 cpu = cpumask_pick_least_loaded(d, tmpmask);
1599 if (cpu < nr_cpu_ids)
1600 goto out;
1601
1602 /* If we can't cross sockets, give up */
1603 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
1604 goto out;
1605
1606 /* If the above failed, expand the search */
1607 }
1608
1609 /* Try the intersection of the affinity and online masks */
1610 cpumask_and(tmpmask, aff_mask, cpu_online_mask);
1611
1612 /* If that doesn't fly, the online mask is the last resort */
1613 if (cpumask_empty(tmpmask))
1614 cpumask_copy(tmpmask, cpu_online_mask);
1615
1616 cpu = cpumask_pick_least_loaded(d, tmpmask);
1617 } else {
1618 cpumask_and(tmpmask, irq_data_get_affinity_mask(d), cpu_online_mask);
1619
1620 /* If we cannot cross sockets, limit the search to that node */
1621 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) &&
1622 node != NUMA_NO_NODE)
1623 cpumask_and(tmpmask, tmpmask, cpumask_of_node(node));
1624
1625 cpu = cpumask_pick_least_loaded(d, tmpmask);
1626 }
1627out:
1628 free_cpumask_var(tmpmask);
1629
1630 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
1631 return cpu;
1632}
1633
Marc Zyngierc48ed512014-11-24 14:35:12 +00001634static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
1635 bool force)
1636{
Marc Zyngierc48ed512014-11-24 14:35:12 +00001637 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1638 struct its_collection *target_col;
1639 u32 id = its_get_event_id(d);
Marc Zyngierc5d60822020-05-15 17:57:52 +01001640 int cpu, prev_cpu;
Marc Zyngierc48ed512014-11-24 14:35:12 +00001641
Marc Zyngier015ec032016-12-20 09:54:57 +00001642 /* A forwarded interrupt should use irq_set_vcpu_affinity */
1643 if (irqd_is_forwarded_to_vcpu(d))
1644 return -EINVAL;
1645
Marc Zyngier2f13ff12020-05-15 17:57:51 +01001646 prev_cpu = its_dev->event_map.col_map[id];
1647 its_dec_lpi_count(d, prev_cpu);
1648
Marc Zyngierc5d60822020-05-15 17:57:52 +01001649 if (!force)
1650 cpu = its_select_cpu(d, mask_val);
1651 else
1652 cpu = cpumask_pick_least_loaded(d, mask_val);
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +02001653
Marc Zyngierc5d60822020-05-15 17:57:52 +01001654 if (cpu < 0 || cpu >= nr_cpu_ids)
Marc Zyngier2f13ff12020-05-15 17:57:51 +01001655 goto err;
Marc Zyngierc48ed512014-11-24 14:35:12 +00001656
MaJun8b8d94a2017-05-18 16:19:13 +08001657 /* don't set the affinity when the target cpu is same as current one */
Marc Zyngier2f13ff12020-05-15 17:57:51 +01001658 if (cpu != prev_cpu) {
MaJun8b8d94a2017-05-18 16:19:13 +08001659 target_col = &its_dev->its->collections[cpu];
1660 its_send_movi(its_dev, target_col, id);
1661 its_dev->event_map.col_map[id] = cpu;
Marc Zyngier0d224d32017-08-18 09:39:18 +01001662 irq_data_update_effective_affinity(d, cpumask_of(cpu));
MaJun8b8d94a2017-05-18 16:19:13 +08001663 }
Marc Zyngierc48ed512014-11-24 14:35:12 +00001664
Marc Zyngier2f13ff12020-05-15 17:57:51 +01001665 its_inc_lpi_count(d, cpu);
1666
Marc Zyngierc48ed512014-11-24 14:35:12 +00001667 return IRQ_SET_MASK_OK_DONE;
Marc Zyngier2f13ff12020-05-15 17:57:51 +01001668
1669err:
1670 its_inc_lpi_count(d, prev_cpu);
1671 return -EINVAL;
Marc Zyngierc48ed512014-11-24 14:35:12 +00001672}
1673
Ard Biesheuvel558b0162017-10-17 17:55:56 +01001674static u64 its_irq_get_msi_base(struct its_device *its_dev)
1675{
1676 struct its_node *its = its_dev->its;
1677
1678 return its->phys_base + GITS_TRANSLATER;
1679}
1680
Marc Zyngierb48ac832014-11-24 14:35:16 +00001681static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
1682{
1683 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1684 struct its_node *its;
1685 u64 addr;
1686
1687 its = its_dev->its;
Ard Biesheuvel558b0162017-10-17 17:55:56 +01001688 addr = its->get_msi_base(its_dev);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001689
Vladimir Murzinb11283e2016-11-02 11:54:03 +00001690 msg->address_lo = lower_32_bits(addr);
1691 msg->address_hi = upper_32_bits(addr);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001692 msg->data = its_get_event_id(d);
Robin Murphy44bb7e22016-09-12 17:13:59 +01001693
Julien Grall35ae7df2019-05-01 14:58:21 +01001694 iommu_dma_compose_msi_msg(irq_data_get_msi_desc(d), msg);
Marc Zyngierb48ac832014-11-24 14:35:16 +00001695}
1696
Marc Zyngier8d85dce2016-12-19 18:02:13 +00001697static int its_irq_set_irqchip_state(struct irq_data *d,
1698 enum irqchip_irq_state which,
1699 bool state)
1700{
1701 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1702 u32 event = its_get_event_id(d);
1703
1704 if (which != IRQCHIP_STATE_PENDING)
1705 return -EINVAL;
1706
Marc Zyngiered0e4aa2019-11-08 16:58:03 +00001707 if (irqd_is_forwarded_to_vcpu(d)) {
1708 if (state)
1709 its_send_vint(its_dev, event);
1710 else
1711 its_send_vclear(its_dev, event);
1712 } else {
1713 if (state)
1714 its_send_int(its_dev, event);
1715 else
1716 its_send_clear(its_dev, event);
1717 }
Marc Zyngier8d85dce2016-12-19 18:02:13 +00001718
1719 return 0;
1720}
1721
Marc Zyngier5f774f52020-07-31 11:33:13 +01001722static int its_irq_retrigger(struct irq_data *d)
1723{
1724 return !its_irq_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
1725}
1726
Marc Zyngier009384b2020-03-04 20:33:23 +00001727/*
1728 * Two favourable cases:
1729 *
1730 * (a) Either we have a GICv4.1, and all vPEs have to be mapped at all times
1731 * for vSGI delivery
1732 *
1733 * (b) Or the ITSs do not use a list map, meaning that VMOVP is cheap enough
1734 * and we're better off mapping all VPEs always
1735 *
1736 * If neither (a) nor (b) is true, then we map vPEs on demand.
1737 *
1738 */
1739static bool gic_requires_eager_mapping(void)
1740{
1741 if (!its_list_map || gic_rdists->has_rvpeid)
1742 return true;
1743
1744 return false;
1745}
1746
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001747static void its_map_vm(struct its_node *its, struct its_vm *vm)
1748{
1749 unsigned long flags;
1750
Marc Zyngier009384b2020-03-04 20:33:23 +00001751 if (gic_requires_eager_mapping())
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001752 return;
1753
1754 raw_spin_lock_irqsave(&vmovp_lock, flags);
1755
1756 /*
1757 * If the VM wasn't mapped yet, iterate over the vpes and get
1758 * them mapped now.
1759 */
1760 vm->vlpi_count[its->list_nr]++;
1761
1762 if (vm->vlpi_count[its->list_nr] == 1) {
1763 int i;
1764
1765 for (i = 0; i < vm->nr_vpes; i++) {
1766 struct its_vpe *vpe = vm->vpes[i];
Marc Zyngier44c4c252017-10-19 10:11:34 +01001767 struct irq_data *d = irq_get_irq_data(vpe->irq);
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001768
1769 /* Map the VPE to the first possible CPU */
1770 vpe->col_idx = cpumask_first(cpu_online_mask);
1771 its_send_vmapp(its, vpe, true);
1772 its_send_vinvall(its, vpe);
Marc Zyngier44c4c252017-10-19 10:11:34 +01001773 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001774 }
1775 }
1776
1777 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1778}
1779
1780static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
1781{
1782 unsigned long flags;
1783
1784 /* Not using the ITS list? Everything is always mapped. */
Marc Zyngier009384b2020-03-04 20:33:23 +00001785 if (gic_requires_eager_mapping())
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001786 return;
1787
1788 raw_spin_lock_irqsave(&vmovp_lock, flags);
1789
1790 if (!--vm->vlpi_count[its->list_nr]) {
1791 int i;
1792
1793 for (i = 0; i < vm->nr_vpes; i++)
1794 its_send_vmapp(its, vm->vpes[i], false);
1795 }
1796
1797 raw_spin_unlock_irqrestore(&vmovp_lock, flags);
1798}
1799
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001800static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
1801{
1802 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1803 u32 event = its_get_event_id(d);
1804 int ret = 0;
1805
1806 if (!info->map)
1807 return -EINVAL;
1808
Marc Zyngier11635fa2019-11-08 16:58:05 +00001809 raw_spin_lock(&its_dev->event_map.vlpi_lock);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001810
1811 if (!its_dev->event_map.vm) {
1812 struct its_vlpi_map *maps;
1813
Kees Cook6396bb22018-06-12 14:03:40 -07001814 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
Marc Zyngier11635fa2019-11-08 16:58:05 +00001815 GFP_ATOMIC);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001816 if (!maps) {
1817 ret = -ENOMEM;
1818 goto out;
1819 }
1820
1821 its_dev->event_map.vm = info->map->vm;
1822 its_dev->event_map.vlpi_maps = maps;
1823 } else if (its_dev->event_map.vm != info->map->vm) {
1824 ret = -EINVAL;
1825 goto out;
1826 }
1827
1828 /* Get our private copy of the mapping information */
1829 its_dev->event_map.vlpi_maps[event] = *info->map;
1830
1831 if (irqd_is_forwarded_to_vcpu(d)) {
1832 /* Already mapped, move it around */
1833 its_send_vmovi(its_dev, event);
1834 } else {
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001835 /* Ensure all the VPEs are mapped on this ITS */
1836 its_map_vm(its_dev->its, info->map->vm);
1837
Marc Zyngierd4d7b4a2017-10-26 10:44:07 +01001838 /*
1839 * Flag the interrupt as forwarded so that we can
1840 * start poking the virtual property table.
1841 */
1842 irqd_set_forwarded_to_vcpu(d);
1843
1844 /* Write out the property to the prop table */
1845 lpi_write_config(d, 0xff, info->map->properties);
1846
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001847 /* Drop the physical mapping */
1848 its_send_discard(its_dev, event);
1849
1850 /* and install the virtual one */
1851 its_send_vmapti(its_dev, event);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001852
1853 /* Increment the number of VLPIs */
1854 its_dev->event_map.nr_vlpis++;
1855 }
1856
1857out:
Marc Zyngier11635fa2019-11-08 16:58:05 +00001858 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001859 return ret;
1860}
1861
1862static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
1863{
1864 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
Marc Zyngier046b5052019-11-08 16:58:04 +00001865 struct its_vlpi_map *map;
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001866 int ret = 0;
1867
Marc Zyngier11635fa2019-11-08 16:58:05 +00001868 raw_spin_lock(&its_dev->event_map.vlpi_lock);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001869
Marc Zyngier046b5052019-11-08 16:58:04 +00001870 map = get_vlpi_map(d);
1871
1872 if (!its_dev->event_map.vm || !map) {
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001873 ret = -EINVAL;
1874 goto out;
1875 }
1876
1877 /* Copy our mapping information to the incoming request */
Marc Zyngierc1d4d5c2019-11-08 16:58:01 +00001878 *info->map = *map;
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001879
1880out:
Marc Zyngier11635fa2019-11-08 16:58:05 +00001881 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001882 return ret;
1883}
1884
1885static int its_vlpi_unmap(struct irq_data *d)
1886{
1887 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1888 u32 event = its_get_event_id(d);
1889 int ret = 0;
1890
Marc Zyngier11635fa2019-11-08 16:58:05 +00001891 raw_spin_lock(&its_dev->event_map.vlpi_lock);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001892
1893 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
1894 ret = -EINVAL;
1895 goto out;
1896 }
1897
1898 /* Drop the virtual mapping */
1899 its_send_discard(its_dev, event);
1900
1901 /* and restore the physical one */
1902 irqd_clr_forwarded_to_vcpu(d);
1903 its_send_mapti(its_dev, d->hwirq, event);
1904 lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
1905 LPI_PROP_ENABLED |
1906 LPI_PROP_GROUP1));
1907
Marc Zyngier2247e1b2017-10-08 18:50:36 +01001908 /* Potentially unmap the VM from this ITS */
1909 its_unmap_vm(its_dev->its, its_dev->event_map.vm);
1910
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001911 /*
1912 * Drop the refcount and make the device available again if
1913 * this was the last VLPI.
1914 */
1915 if (!--its_dev->event_map.nr_vlpis) {
1916 its_dev->event_map.vm = NULL;
1917 kfree(its_dev->event_map.vlpi_maps);
1918 }
1919
1920out:
Marc Zyngier11635fa2019-11-08 16:58:05 +00001921 raw_spin_unlock(&its_dev->event_map.vlpi_lock);
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001922 return ret;
1923}
1924
Marc Zyngier015ec032016-12-20 09:54:57 +00001925static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
1926{
1927 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1928
1929 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
1930 return -EINVAL;
1931
1932 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
1933 lpi_update_config(d, 0xff, info->config);
1934 else
1935 lpi_write_config(d, 0xff, info->config);
1936 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));
1937
1938 return 0;
1939}
1940
Marc Zyngierc808eea2016-12-20 09:31:20 +00001941static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1942{
1943 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1944 struct its_cmd_info *info = vcpu_info;
1945
1946 /* Need a v4 ITS */
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00001947 if (!is_v4(its_dev->its))
Marc Zyngierc808eea2016-12-20 09:31:20 +00001948 return -EINVAL;
1949
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001950 /* Unmap request? */
1951 if (!info)
1952 return its_vlpi_unmap(d);
1953
Marc Zyngierc808eea2016-12-20 09:31:20 +00001954 switch (info->cmd_type) {
1955 case MAP_VLPI:
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001956 return its_vlpi_map(d, info);
Marc Zyngierc808eea2016-12-20 09:31:20 +00001957
1958 case GET_VLPI:
Marc Zyngierd011e4e2016-12-20 09:44:41 +00001959 return its_vlpi_get(d, info);
Marc Zyngierc808eea2016-12-20 09:31:20 +00001960
1961 case PROP_UPDATE_VLPI:
1962 case PROP_UPDATE_AND_INV_VLPI:
Marc Zyngier015ec032016-12-20 09:54:57 +00001963 return its_vlpi_prop_update(d, info);
Marc Zyngierc808eea2016-12-20 09:31:20 +00001964
1965 default:
1966 return -EINVAL;
1967 }
1968}
1969
Marc Zyngierc48ed512014-11-24 14:35:12 +00001970static struct irq_chip its_irq_chip = {
1971 .name = "ITS",
1972 .irq_mask = its_mask_irq,
1973 .irq_unmask = its_unmask_irq,
Ashok Kumar004fa082016-02-11 05:38:53 -08001974 .irq_eoi = irq_chip_eoi_parent,
Marc Zyngierc48ed512014-11-24 14:35:12 +00001975 .irq_set_affinity = its_set_affinity,
Marc Zyngierb48ac832014-11-24 14:35:16 +00001976 .irq_compose_msi_msg = its_irq_compose_msi_msg,
Marc Zyngier8d85dce2016-12-19 18:02:13 +00001977 .irq_set_irqchip_state = its_irq_set_irqchip_state,
Marc Zyngier5f774f52020-07-31 11:33:13 +01001978 .irq_retrigger = its_irq_retrigger,
Marc Zyngierc808eea2016-12-20 09:31:20 +00001979 .irq_set_vcpu_affinity = its_irq_set_vcpu_affinity,
Marc Zyngierb48ac832014-11-24 14:35:16 +00001980};
1981
Marc Zyngier880cb3c2018-05-27 16:14:15 +01001982
Marc Zyngierbf9529f2014-11-24 14:35:13 +00001983/*
1984 * How we allocate LPIs:
1985 *
Marc Zyngier880cb3c2018-05-27 16:14:15 +01001986 * lpi_range_list contains ranges of LPIs that are to available to
1987 * allocate from. To allocate LPIs, just pick the first range that
1988 * fits the required allocation, and reduce it by the required
1989 * amount. Once empty, remove the range from the list.
Marc Zyngierbf9529f2014-11-24 14:35:13 +00001990 *
Marc Zyngier880cb3c2018-05-27 16:14:15 +01001991 * To free a range of LPIs, add a free range to the list, sort it and
1992 * merge the result if the new range happens to be adjacent to an
1993 * already free block.
1994 *
1995 * The consequence of the above is that allocation is cost is low, but
1996 * freeing is expensive. We assumes that freeing rarely occurs.
1997 */
Jia He4cb205c2018-08-28 12:53:26 +08001998#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
Marc Zyngier880cb3c2018-05-27 16:14:15 +01001999
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002000static DEFINE_MUTEX(lpi_range_lock);
2001static LIST_HEAD(lpi_range_list);
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002002
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002003struct lpi_range {
2004 struct list_head entry;
2005 u32 base_id;
2006 u32 span;
2007};
2008
2009static struct lpi_range *mk_lpi_range(u32 base, u32 span)
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002010{
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002011 struct lpi_range *range;
2012
Rasmus Villemoes1c73fac2019-03-12 18:33:48 +01002013 range = kmalloc(sizeof(*range), GFP_KERNEL);
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002014 if (range) {
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002015 range->base_id = base;
2016 range->span = span;
2017 }
2018
2019 return range;
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002020}
2021
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002022static int alloc_lpi_range(u32 nr_lpis, u32 *base)
2023{
2024 struct lpi_range *range, *tmp;
2025 int err = -ENOSPC;
2026
2027 mutex_lock(&lpi_range_lock);
2028
2029 list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
2030 if (range->span >= nr_lpis) {
2031 *base = range->base_id;
2032 range->base_id += nr_lpis;
2033 range->span -= nr_lpis;
2034
2035 if (range->span == 0) {
2036 list_del(&range->entry);
2037 kfree(range);
2038 }
2039
2040 err = 0;
2041 break;
2042 }
2043 }
2044
2045 mutex_unlock(&lpi_range_lock);
2046
2047 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
2048 return err;
2049}
2050
Rasmus Villemoes12eade12019-03-12 18:33:49 +01002051static void merge_lpi_ranges(struct lpi_range *a, struct lpi_range *b)
2052{
2053 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list)
2054 return;
2055 if (a->base_id + a->span != b->base_id)
2056 return;
2057 b->base_id = a->base_id;
2058 b->span += a->span;
2059 list_del(&a->entry);
2060 kfree(a);
2061}
2062
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002063static int free_lpi_range(u32 base, u32 nr_lpis)
2064{
Rasmus Villemoes12eade12019-03-12 18:33:49 +01002065 struct lpi_range *new, *old;
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002066
2067 new = mk_lpi_range(base, nr_lpis);
Rasmus Villemoesb31a3832019-03-12 18:33:47 +01002068 if (!new)
2069 return -ENOMEM;
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002070
2071 mutex_lock(&lpi_range_lock);
2072
Rasmus Villemoes12eade12019-03-12 18:33:49 +01002073 list_for_each_entry_reverse(old, &lpi_range_list, entry) {
2074 if (old->base_id < base)
2075 break;
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002076 }
Rasmus Villemoes12eade12019-03-12 18:33:49 +01002077 /*
2078 * old is the last element with ->base_id smaller than base,
2079 * so new goes right after it. If there are no elements with
2080 * ->base_id smaller than base, &old->entry ends up pointing
2081 * at the head of the list, and inserting new it the start of
2082 * the list is the right thing to do in that case as well.
2083 */
2084 list_add(&new->entry, &old->entry);
2085 /*
2086 * Now check if we can merge with the preceding and/or
2087 * following ranges.
2088 */
2089 merge_lpi_ranges(old, new);
2090 merge_lpi_ranges(new, list_next_entry(new, entry));
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002091
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002092 mutex_unlock(&lpi_range_lock);
Rasmus Villemoesb31a3832019-03-12 18:33:47 +01002093 return 0;
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002094}
2095
Tomasz Nowicki04a0e4d2016-01-19 14:11:18 +01002096static int __init its_lpi_init(u32 id_bits)
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002097{
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002098 u32 lpis = (1UL << id_bits) - 8192;
Marc Zyngier12b29052018-05-31 09:01:59 +01002099 u32 numlpis;
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002100 int err;
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002101
Marc Zyngier12b29052018-05-31 09:01:59 +01002102 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);
2103
2104 if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
2105 lpis = numlpis;
2106 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
2107 lpis);
2108 }
2109
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002110 /*
2111 * Initializing the allocator is just the same as freeing the
2112 * full range of LPIs.
2113 */
2114 err = free_lpi_range(8192, lpis);
2115 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
2116 return err;
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002117}
2118
Marc Zyngier38dd7c42018-05-27 17:03:03 +01002119static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002120{
2121 unsigned long *bitmap = NULL;
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002122 int err = 0;
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002123
2124 do {
Marc Zyngier38dd7c42018-05-27 17:03:03 +01002125 err = alloc_lpi_range(nr_irqs, base);
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002126 if (!err)
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002127 break;
2128
Marc Zyngier38dd7c42018-05-27 17:03:03 +01002129 nr_irqs /= 2;
2130 } while (nr_irqs > 0);
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002131
Marc Zyngier45725e02019-01-29 15:19:23 +00002132 if (!nr_irqs)
2133 err = -ENOSPC;
2134
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002135 if (err)
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002136 goto out;
2137
Marc Zyngier38dd7c42018-05-27 17:03:03 +01002138 bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002139 if (!bitmap)
2140 goto out;
2141
Marc Zyngier38dd7c42018-05-27 17:03:03 +01002142 *nr_ids = nr_irqs;
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002143
2144out:
Marc Zyngierc8415b92015-10-02 16:44:05 +01002145 if (!bitmap)
2146 *base = *nr_ids = 0;
2147
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002148 return bitmap;
2149}
2150
Marc Zyngier38dd7c42018-05-27 17:03:03 +01002151static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002152{
Marc Zyngier880cb3c2018-05-27 16:14:15 +01002153 WARN_ON(free_lpi_range(base, nr_ids));
Marc Zyngiercf2be8b2016-12-19 18:49:59 +00002154 kfree(bitmap);
Marc Zyngierbf9529f2014-11-24 14:35:13 +00002155}
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002156
Marc Zyngier053be482018-07-27 15:02:27 +01002157static void gic_reset_prop_table(void *va)
2158{
2159 /* Priority 0xa0, Group-1, disabled */
2160 memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);
2161
2162 /* Make sure the GIC will observe the written configuration */
2163 gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
2164}
2165
Marc Zyngier0e5ccf92016-12-19 18:15:05 +00002166static struct page *its_allocate_prop_table(gfp_t gfp_flags)
2167{
2168 struct page *prop_page;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002169
Marc Zyngier0e5ccf92016-12-19 18:15:05 +00002170 prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
2171 if (!prop_page)
2172 return NULL;
2173
Marc Zyngier053be482018-07-27 15:02:27 +01002174 gic_reset_prop_table(page_address(prop_page));
Marc Zyngier0e5ccf92016-12-19 18:15:05 +00002175
2176 return prop_page;
2177}
2178
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00002179static void its_free_prop_table(struct page *prop_page)
2180{
2181 free_pages((unsigned long)page_address(prop_page),
2182 get_order(LPI_PROPBASE_SZ));
2183}
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002184
Marc Zyngier5e2c9f92018-07-27 16:23:18 +01002185static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
2186{
2187 phys_addr_t start, end, addr_end;
2188 u64 i;
2189
2190 /*
2191 * We don't bother checking for a kdump kernel as by
2192 * construction, the LPI tables are out of this kernel's
2193 * memory map.
2194 */
2195 if (is_kdump_kernel())
2196 return true;
2197
2198 addr_end = addr + size - 1;
2199
Mike Rapoport9f3d5ea2020-10-13 16:58:25 -07002200 for_each_reserved_mem_range(i, &start, &end) {
Marc Zyngier5e2c9f92018-07-27 16:23:18 +01002201 if (addr >= start && addr_end <= end)
2202 return true;
2203 }
2204
2205 /* Not found, not a good sign... */
2206 pr_warn("GICv3: Expected reserved range [%pa:%pa], not found\n",
2207 &addr, &addr_end);
2208 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
2209 return false;
2210}
2211
Marc Zyngier3fb68fa2018-07-27 16:21:18 +01002212static int gic_reserve_range(phys_addr_t addr, unsigned long size)
2213{
2214 if (efi_enabled(EFI_CONFIG_TABLES))
2215 return efi_mem_reserve_persistent(addr, size);
2216
2217 return 0;
2218}
2219
Marc Zyngier11e37d32018-07-27 13:38:54 +01002220static int __init its_setup_lpi_prop_table(void)
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002221{
Marc Zyngierc440a9d2018-07-27 15:40:13 +01002222 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
2223 u64 val;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002224
Marc Zyngierc440a9d2018-07-27 15:40:13 +01002225 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2226 lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
2227
2228 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
2229 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
2230 LPI_PROPBASE_SZ,
2231 MEMREMAP_WB);
2232 gic_reset_prop_table(gic_rdists->prop_table_va);
2233 } else {
2234 struct page *page;
2235
2236 lpi_id_bits = min_t(u32,
2237 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
2238 ITS_MAX_LPI_NRBITS);
2239 page = its_allocate_prop_table(GFP_NOWAIT);
2240 if (!page) {
2241 pr_err("Failed to allocate PROPBASE\n");
2242 return -ENOMEM;
2243 }
2244
2245 gic_rdists->prop_table_pa = page_to_phys(page);
2246 gic_rdists->prop_table_va = page_address(page);
Marc Zyngier3fb68fa2018-07-27 16:21:18 +01002247 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
2248 LPI_PROPBASE_SZ));
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002249 }
2250
Marc Zyngiere1a2e202018-07-27 14:36:00 +01002251 pr_info("GICv3: using LPI property table @%pa\n",
2252 &gic_rdists->prop_table_pa);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002253
Shanker Donthineni6c31e122017-06-22 18:19:14 -05002254 return its_lpi_init(lpi_id_bits);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002255}
2256
2257static const char *its_base_type_string[] = {
2258 [GITS_BASER_TYPE_DEVICE] = "Devices",
2259 [GITS_BASER_TYPE_VCPU] = "Virtual CPUs",
Marc Zyngier4f46de92016-12-20 15:50:14 +00002260 [GITS_BASER_TYPE_RESERVED3] = "Reserved (3)",
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002261 [GITS_BASER_TYPE_COLLECTION] = "Interrupt Collections",
2262 [GITS_BASER_TYPE_RESERVED5] = "Reserved (5)",
2263 [GITS_BASER_TYPE_RESERVED6] = "Reserved (6)",
2264 [GITS_BASER_TYPE_RESERVED7] = "Reserved (7)",
2265};
2266
Shanker Donthineni2d81d422016-06-06 18:17:28 -05002267static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
2268{
2269 u32 idx = baser - its->tables;
2270
Vladimir Murzin0968a612016-11-02 11:54:06 +00002271 return gits_read_baser(its->base + GITS_BASER + (idx << 3));
Shanker Donthineni2d81d422016-06-06 18:17:28 -05002272}
2273
2274static void its_write_baser(struct its_node *its, struct its_baser *baser,
2275 u64 val)
2276{
2277 u32 idx = baser - its->tables;
2278
Vladimir Murzin0968a612016-11-02 11:54:06 +00002279 gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
Shanker Donthineni2d81d422016-06-06 18:17:28 -05002280 baser->val = its_read_baser(its, baser);
2281}
2282
Shanker Donthineni93473592016-06-06 18:17:30 -05002283static int its_setup_baser(struct its_node *its, struct its_baser *baser,
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002284 u64 cache, u64 shr, u32 order, bool indirect)
Shanker Donthineni93473592016-06-06 18:17:30 -05002285{
2286 u64 val = its_read_baser(its, baser);
2287 u64 esz = GITS_BASER_ENTRY_SIZE(val);
2288 u64 type = GITS_BASER_TYPE(val);
Shanker Donthineni30ae9612017-10-09 11:46:55 -05002289 u64 baser_phys, tmp;
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002290 u32 alloc_pages, psz;
Shanker Donthineni539d3782019-01-14 09:50:19 +00002291 struct page *page;
Shanker Donthineni93473592016-06-06 18:17:30 -05002292 void *base;
Shanker Donthineni93473592016-06-06 18:17:30 -05002293
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002294 psz = baser->psz;
Shanker Donthineni93473592016-06-06 18:17:30 -05002295 alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
2296 if (alloc_pages > GITS_BASER_PAGES_MAX) {
2297 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
2298 &its->phys_base, its_base_type_string[type],
2299 alloc_pages, GITS_BASER_PAGES_MAX);
2300 alloc_pages = GITS_BASER_PAGES_MAX;
2301 order = get_order(GITS_BASER_PAGES_MAX * psz);
2302 }
2303
Shanker Donthineni539d3782019-01-14 09:50:19 +00002304 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
2305 if (!page)
Shanker Donthineni93473592016-06-06 18:17:30 -05002306 return -ENOMEM;
2307
Shanker Donthineni539d3782019-01-14 09:50:19 +00002308 base = (void *)page_address(page);
Shanker Donthineni30ae9612017-10-09 11:46:55 -05002309 baser_phys = virt_to_phys(base);
2310
2311 /* Check if the physical address of the memory is above 48bits */
2312 if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {
2313
2314 /* 52bit PA is supported only when PageSize=64K */
2315 if (psz != SZ_64K) {
2316 pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
2317 free_pages((unsigned long)base, order);
2318 return -ENXIO;
2319 }
2320
2321 /* Convert 52bit PA to 48bit field */
2322 baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
2323 }
2324
Shanker Donthineni93473592016-06-06 18:17:30 -05002325retry_baser:
Shanker Donthineni30ae9612017-10-09 11:46:55 -05002326 val = (baser_phys |
Shanker Donthineni93473592016-06-06 18:17:30 -05002327 (type << GITS_BASER_TYPE_SHIFT) |
2328 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
2329 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) |
2330 cache |
2331 shr |
2332 GITS_BASER_VALID);
2333
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002334 val |= indirect ? GITS_BASER_INDIRECT : 0x0;
2335
Shanker Donthineni93473592016-06-06 18:17:30 -05002336 switch (psz) {
2337 case SZ_4K:
2338 val |= GITS_BASER_PAGE_SIZE_4K;
2339 break;
2340 case SZ_16K:
2341 val |= GITS_BASER_PAGE_SIZE_16K;
2342 break;
2343 case SZ_64K:
2344 val |= GITS_BASER_PAGE_SIZE_64K;
2345 break;
2346 }
2347
2348 its_write_baser(its, baser, val);
2349 tmp = baser->val;
2350
2351 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
2352 /*
2353 * Shareability didn't stick. Just use
2354 * whatever the read reported, which is likely
2355 * to be the only thing this redistributor
2356 * supports. If that's zero, make it
2357 * non-cacheable as well.
2358 */
2359 shr = tmp & GITS_BASER_SHAREABILITY_MASK;
2360 if (!shr) {
2361 cache = GITS_BASER_nC;
Vladimir Murzin328191c2016-11-02 11:54:05 +00002362 gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
Shanker Donthineni93473592016-06-06 18:17:30 -05002363 }
2364 goto retry_baser;
2365 }
2366
Shanker Donthineni93473592016-06-06 18:17:30 -05002367 if (val != tmp) {
Vladimir Murzinb11283e2016-11-02 11:54:03 +00002368 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
Shanker Donthineni93473592016-06-06 18:17:30 -05002369 &its->phys_base, its_base_type_string[type],
Vladimir Murzinb11283e2016-11-02 11:54:03 +00002370 val, tmp);
Shanker Donthineni93473592016-06-06 18:17:30 -05002371 free_pages((unsigned long)base, order);
2372 return -ENXIO;
2373 }
2374
2375 baser->order = order;
2376 baser->base = base;
2377 baser->psz = psz;
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002378 tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
Shanker Donthineni93473592016-06-06 18:17:30 -05002379
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002380 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
Vladimir Murzind524eaa2016-11-02 11:54:04 +00002381 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
Shanker Donthineni93473592016-06-06 18:17:30 -05002382 its_base_type_string[type],
2383 (unsigned long)virt_to_phys(base),
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002384 indirect ? "indirect" : "flat", (int)esz,
Shanker Donthineni93473592016-06-06 18:17:30 -05002385 psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
2386
2387 return 0;
2388}
2389
Marc Zyngier4cacac52016-12-19 18:18:34 +00002390static bool its_parse_indirect_baser(struct its_node *its,
2391 struct its_baser *baser,
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002392 u32 *order, u32 ids)
Shanker Donthineni4b75c452016-06-06 18:17:29 -05002393{
Marc Zyngier4cacac52016-12-19 18:18:34 +00002394 u64 tmp = its_read_baser(its, baser);
2395 u64 type = GITS_BASER_TYPE(tmp);
2396 u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
Shanker Donthineni2fd632a2017-01-25 21:51:41 -06002397 u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
Shanker Donthineni4b75c452016-06-06 18:17:29 -05002398 u32 new_order = *order;
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002399 u32 psz = baser->psz;
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002400 bool indirect = false;
2401
2402 /* No need to enable Indirection if memory requirement < (psz*2)bytes */
2403 if ((esz << ids) > (psz * 2)) {
2404 /*
2405 * Find out whether hw supports a single or two-level table by
2406 * table by reading bit at offset '62' after writing '1' to it.
2407 */
2408 its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
2409 indirect = !!(baser->val & GITS_BASER_INDIRECT);
2410
2411 if (indirect) {
2412 /*
2413 * The size of the lvl2 table is equal to ITS page size
2414 * which is 'psz'. For computing lvl1 table size,
2415 * subtract ID bits that sparse lvl2 table from 'ids'
2416 * which is reported by ITS hardware times lvl1 table
2417 * entry size.
2418 */
Vladimir Murzind524eaa2016-11-02 11:54:04 +00002419 ids -= ilog2(psz / (int)esz);
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002420 esz = GITS_LVL1_ENTRY_SIZE;
2421 }
2422 }
Shanker Donthineni4b75c452016-06-06 18:17:29 -05002423
2424 /*
2425 * Allocate as many entries as required to fit the
2426 * range of device IDs that the ITS can grok... The ID
2427 * space being incredibly sparse, this results in a
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002428 * massive waste of memory if two-level device table
2429 * feature is not supported by hardware.
Shanker Donthineni4b75c452016-06-06 18:17:29 -05002430 */
2431 new_order = max_t(u32, get_order(esz << ids), new_order);
2432 if (new_order >= MAX_ORDER) {
2433 new_order = MAX_ORDER - 1;
Vladimir Murzind524eaa2016-11-02 11:54:04 +00002434 ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
Marc Zyngier576a8342019-11-08 16:58:00 +00002435 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n",
Marc Zyngier4cacac52016-12-19 18:18:34 +00002436 &its->phys_base, its_base_type_string[type],
Marc Zyngier576a8342019-11-08 16:58:00 +00002437 device_ids(its), ids);
Shanker Donthineni4b75c452016-06-06 18:17:29 -05002438 }
2439
2440 *order = new_order;
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002441
2442 return indirect;
Shanker Donthineni4b75c452016-06-06 18:17:29 -05002443}
2444
Marc Zyngier5e516842019-12-24 11:10:28 +00002445static u32 compute_common_aff(u64 val)
2446{
2447 u32 aff, clpiaff;
2448
2449 aff = FIELD_GET(GICR_TYPER_AFFINITY, val);
2450 clpiaff = FIELD_GET(GICR_TYPER_COMMON_LPI_AFF, val);
2451
2452 return aff & ~(GENMASK(31, 0) >> (clpiaff * 8));
2453}
2454
2455static u32 compute_its_aff(struct its_node *its)
2456{
2457 u64 val;
2458 u32 svpet;
2459
2460 /*
2461 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute
2462 * the resulting affinity. We then use that to see if this match
2463 * our own affinity.
2464 */
2465 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer);
2466 val = FIELD_PREP(GICR_TYPER_COMMON_LPI_AFF, svpet);
2467 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr);
2468 return compute_common_aff(val);
2469}
2470
2471static struct its_node *find_sibling_its(struct its_node *cur_its)
2472{
2473 struct its_node *its;
2474 u32 aff;
2475
2476 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer))
2477 return NULL;
2478
2479 aff = compute_its_aff(cur_its);
2480
2481 list_for_each_entry(its, &its_nodes, entry) {
2482 u64 baser;
2483
2484 if (!is_v4_1(its) || its == cur_its)
2485 continue;
2486
2487 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2488 continue;
2489
2490 if (aff != compute_its_aff(its))
2491 continue;
2492
2493 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2494 baser = its->tables[2].val;
2495 if (!(baser & GITS_BASER_VALID))
2496 continue;
2497
2498 return its;
2499 }
2500
2501 return NULL;
2502}
2503
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002504static void its_free_tables(struct its_node *its)
2505{
2506 int i;
2507
2508 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
Shanker Donthineni1a485f42016-02-01 20:19:44 -06002509 if (its->tables[i].base) {
2510 free_pages((unsigned long)its->tables[i].base,
2511 its->tables[i].order);
2512 its->tables[i].base = NULL;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002513 }
2514 }
2515}
2516
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002517static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser)
2518{
2519 u64 psz = SZ_64K;
2520
2521 while (psz) {
2522 u64 val, gpsz;
2523
2524 val = its_read_baser(its, baser);
2525 val &= ~GITS_BASER_PAGE_SIZE_MASK;
2526
2527 switch (psz) {
2528 case SZ_64K:
2529 gpsz = GITS_BASER_PAGE_SIZE_64K;
2530 break;
2531 case SZ_16K:
2532 gpsz = GITS_BASER_PAGE_SIZE_16K;
2533 break;
2534 case SZ_4K:
2535 default:
2536 gpsz = GITS_BASER_PAGE_SIZE_4K;
2537 break;
2538 }
2539
2540 gpsz >>= GITS_BASER_PAGE_SIZE_SHIFT;
2541
2542 val |= FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, gpsz);
2543 its_write_baser(its, baser, val);
2544
2545 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz)
2546 break;
2547
2548 switch (psz) {
2549 case SZ_64K:
2550 psz = SZ_16K;
2551 break;
2552 case SZ_16K:
2553 psz = SZ_4K;
2554 break;
2555 case SZ_4K:
2556 default:
2557 return -1;
2558 }
2559 }
2560
2561 baser->psz = psz;
2562 return 0;
2563}
2564
Shanker Donthineni0e0b0f62016-06-06 18:17:31 -05002565static int its_alloc_tables(struct its_node *its)
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002566{
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002567 u64 shr = GITS_BASER_InnerShareable;
Shanker Donthineni2fd632a2017-01-25 21:51:41 -06002568 u64 cache = GITS_BASER_RaWaWb;
Shanker Donthineni93473592016-06-06 18:17:30 -05002569 int err, i;
Robert Richter94100972015-09-21 22:58:38 +02002570
Ard Biesheuvelfa150012017-10-17 17:55:54 +01002571 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
2572 /* erratum 24313: ignore memory access type */
2573 cache = GITS_BASER_nCnB;
Shanker Donthineni466b7d12016-03-09 22:10:49 -06002574
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002575 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
Shanker Donthineni2d81d422016-06-06 18:17:28 -05002576 struct its_baser *baser = its->tables + i;
2577 u64 val = its_read_baser(its, baser);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002578 u64 type = GITS_BASER_TYPE(val);
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05002579 bool indirect = false;
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002580 u32 order;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002581
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002582 if (type == GITS_BASER_TYPE_NONE)
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002583 continue;
2584
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002585 if (its_probe_baser_psz(its, baser)) {
2586 its_free_tables(its);
2587 return -ENXIO;
2588 }
2589
2590 order = get_order(baser->psz);
2591
2592 switch (type) {
Marc Zyngier4cacac52016-12-19 18:18:34 +00002593 case GITS_BASER_TYPE_DEVICE:
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002594 indirect = its_parse_indirect_baser(its, baser, &order,
Marc Zyngier576a8342019-11-08 16:58:00 +00002595 device_ids(its));
Zenghui Yu8d565742019-02-10 05:24:10 +00002596 break;
2597
Marc Zyngier4cacac52016-12-19 18:18:34 +00002598 case GITS_BASER_TYPE_VCPU:
Marc Zyngier5e516842019-12-24 11:10:28 +00002599 if (is_v4_1(its)) {
2600 struct its_node *sibling;
2601
2602 WARN_ON(i != 2);
2603 if ((sibling = find_sibling_its(its))) {
2604 *baser = sibling->tables[2];
2605 its_write_baser(its, baser, baser->val);
2606 continue;
2607 }
2608 }
2609
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002610 indirect = its_parse_indirect_baser(its, baser, &order,
Shanker Donthineni32bd44d2017-10-07 15:43:48 -05002611 ITS_MAX_VPEID_BITS);
Marc Zyngier4cacac52016-12-19 18:18:34 +00002612 break;
2613 }
Marc Zyngierf54b97e2015-03-06 16:37:41 +00002614
Marc Zyngierd5df9dc2020-03-13 11:01:15 +00002615 err = its_setup_baser(its, baser, cache, shr, order, indirect);
Shanker Donthineni93473592016-06-06 18:17:30 -05002616 if (err < 0) {
2617 its_free_tables(its);
2618 return err;
Robert Richter30f21362015-09-21 22:58:34 +02002619 }
2620
Shanker Donthineni93473592016-06-06 18:17:30 -05002621 /* Update settings which will be used for next BASERn */
Shanker Donthineni93473592016-06-06 18:17:30 -05002622 cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
2623 shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002624 }
2625
2626 return 0;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002627}
2628
Marc Zyngier5e516842019-12-24 11:10:28 +00002629static u64 inherit_vpe_l1_table_from_its(void)
2630{
2631 struct its_node *its;
2632 u64 val;
2633 u32 aff;
2634
2635 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2636 aff = compute_common_aff(val);
2637
2638 list_for_each_entry(its, &its_nodes, entry) {
2639 u64 baser, addr;
2640
2641 if (!is_v4_1(its))
2642 continue;
2643
2644 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer))
2645 continue;
2646
2647 if (aff != compute_its_aff(its))
2648 continue;
2649
2650 /* GICv4.1 guarantees that the vPE table is GITS_BASER2 */
2651 baser = its->tables[2].val;
2652 if (!(baser & GITS_BASER_VALID))
2653 continue;
2654
2655 /* We have a winner! */
Zenghui Yu8b718d42020-02-06 15:57:07 +08002656 gic_data_rdist()->vpe_l1_base = its->tables[2].base;
2657
Marc Zyngier5e516842019-12-24 11:10:28 +00002658 val = GICR_VPROPBASER_4_1_VALID;
2659 if (baser & GITS_BASER_INDIRECT)
2660 val |= GICR_VPROPBASER_4_1_INDIRECT;
2661 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE,
2662 FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser));
2663 switch (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser)) {
2664 case GIC_PAGE_SIZE_64K:
2665 addr = GITS_BASER_ADDR_48_to_52(baser);
2666 break;
2667 default:
2668 addr = baser & GENMASK_ULL(47, 12);
2669 break;
2670 }
2671 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, addr >> 12);
2672 val |= FIELD_PREP(GICR_VPROPBASER_SHAREABILITY_MASK,
2673 FIELD_GET(GITS_BASER_SHAREABILITY_MASK, baser));
2674 val |= FIELD_PREP(GICR_VPROPBASER_INNER_CACHEABILITY_MASK,
2675 FIELD_GET(GITS_BASER_INNER_CACHEABILITY_MASK, baser));
2676 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1);
2677
2678 return val;
2679 }
2680
2681 return 0;
2682}
2683
2684static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
2685{
2686 u32 aff;
2687 u64 val;
2688 int cpu;
2689
2690 val = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
2691 aff = compute_common_aff(val);
2692
2693 for_each_possible_cpu(cpu) {
2694 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
Marc Zyngier5e516842019-12-24 11:10:28 +00002695
2696 if (!base || cpu == smp_processor_id())
2697 continue;
2698
2699 val = gic_read_typer(base + GICR_TYPER);
Zenghui Yu4bccf1d2020-02-06 15:57:09 +08002700 if (aff != compute_common_aff(val))
Marc Zyngier5e516842019-12-24 11:10:28 +00002701 continue;
2702
2703 /*
2704 * At this point, we have a victim. This particular CPU
2705 * has already booted, and has an affinity that matches
2706 * ours wrt CommonLPIAff. Let's use its own VPROPBASER.
2707 * Make sure we don't write the Z bit in that case.
2708 */
Zenghui Yu5186a6c2020-02-06 15:57:11 +08002709 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
Marc Zyngier5e516842019-12-24 11:10:28 +00002710 val &= ~GICR_VPROPBASER_4_1_Z;
2711
Zenghui Yu8b718d42020-02-06 15:57:07 +08002712 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base;
Marc Zyngier5e516842019-12-24 11:10:28 +00002713 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask;
2714
2715 return val;
2716 }
2717
2718 return 0;
2719}
2720
Zenghui Yu4e6437f2020-02-06 15:57:08 +08002721static bool allocate_vpe_l2_table(int cpu, u32 id)
2722{
2723 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
Marc Zyngier490d3322020-02-09 22:48:50 +00002724 unsigned int psz, esz, idx, npg, gpsz;
2725 u64 val;
Zenghui Yu4e6437f2020-02-06 15:57:08 +08002726 struct page *page;
2727 __le64 *table;
2728
2729 if (!gic_rdists->has_rvpeid)
2730 return true;
2731
Marc Zyngier28d160d2020-03-04 20:33:09 +00002732 /* Skip non-present CPUs */
2733 if (!base)
2734 return true;
2735
Zenghui Yu5186a6c2020-02-06 15:57:11 +08002736 val = gicr_read_vpropbaser(base + SZ_128K + GICR_VPROPBASER);
Zenghui Yu4e6437f2020-02-06 15:57:08 +08002737
2738 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val) + 1;
2739 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2740 npg = FIELD_GET(GICR_VPROPBASER_4_1_SIZE, val) + 1;
2741
2742 switch (gpsz) {
2743 default:
2744 WARN_ON(1);
Gustavo A. R. Silvadf561f662020-08-23 17:36:59 -05002745 fallthrough;
Zenghui Yu4e6437f2020-02-06 15:57:08 +08002746 case GIC_PAGE_SIZE_4K:
2747 psz = SZ_4K;
2748 break;
2749 case GIC_PAGE_SIZE_16K:
2750 psz = SZ_16K;
2751 break;
2752 case GIC_PAGE_SIZE_64K:
2753 psz = SZ_64K;
2754 break;
2755 }
2756
2757 /* Don't allow vpe_id that exceeds single, flat table limit */
2758 if (!(val & GICR_VPROPBASER_4_1_INDIRECT))
2759 return (id < (npg * psz / (esz * SZ_8)));
2760
2761 /* Compute 1st level table index & check if that exceeds table limit */
2762 idx = id >> ilog2(psz / (esz * SZ_8));
2763 if (idx >= (npg * psz / GITS_LVL1_ENTRY_SIZE))
2764 return false;
2765
2766 table = gic_data_rdist_cpu(cpu)->vpe_l1_base;
2767
2768 /* Allocate memory for 2nd level table */
2769 if (!table[idx]) {
2770 page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
2771 if (!page)
2772 return false;
2773
2774 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
2775 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2776 gic_flush_dcache_to_poc(page_address(page), psz);
2777
2778 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
2779
2780 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
2781 if (!(val & GICR_VPROPBASER_SHAREABILITY_MASK))
2782 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2783
2784 /* Ensure updated table contents are visible to RD hardware */
2785 dsb(sy);
2786 }
2787
2788 return true;
2789}
2790
Marc Zyngier5e516842019-12-24 11:10:28 +00002791static int allocate_vpe_l1_table(void)
2792{
2793 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2794 u64 val, gpsz, npg, pa;
2795 unsigned int psz = SZ_64K;
2796 unsigned int np, epp, esz;
2797 struct page *page;
2798
2799 if (!gic_rdists->has_rvpeid)
2800 return 0;
2801
2802 /*
2803 * if VPENDBASER.Valid is set, disable any previously programmed
2804 * VPE by setting PendingLast while clearing Valid. This has the
2805 * effect of making sure no doorbell will be generated and we can
2806 * then safely clear VPROPBASER.Valid.
2807 */
Zenghui Yu5186a6c2020-02-06 15:57:11 +08002808 if (gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER) & GICR_VPENDBASER_Valid)
2809 gicr_write_vpendbaser(GICR_VPENDBASER_PendingLast,
Marc Zyngier5e516842019-12-24 11:10:28 +00002810 vlpi_base + GICR_VPENDBASER);
2811
2812 /*
2813 * If we can inherit the configuration from another RD, let's do
2814 * so. Otherwise, we have to go through the allocation process. We
2815 * assume that all RDs have the exact same requirements, as
2816 * nothing will work otherwise.
2817 */
2818 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask);
2819 if (val & GICR_VPROPBASER_4_1_VALID)
2820 goto out;
2821
Zenghui Yud1bd7e02020-06-30 21:37:46 +08002822 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC);
Marc Zyngier5e516842019-12-24 11:10:28 +00002823 if (!gic_data_rdist()->vpe_table_mask)
2824 return -ENOMEM;
2825
2826 val = inherit_vpe_l1_table_from_its();
2827 if (val & GICR_VPROPBASER_4_1_VALID)
2828 goto out;
2829
2830 /* First probe the page size */
2831 val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K);
Zenghui Yu5186a6c2020-02-06 15:57:11 +08002832 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
2833 val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER);
Marc Zyngier5e516842019-12-24 11:10:28 +00002834 gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val);
2835 esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val);
2836
2837 switch (gpsz) {
2838 default:
2839 gpsz = GIC_PAGE_SIZE_4K;
Gustavo A. R. Silvadf561f662020-08-23 17:36:59 -05002840 fallthrough;
Marc Zyngier5e516842019-12-24 11:10:28 +00002841 case GIC_PAGE_SIZE_4K:
2842 psz = SZ_4K;
2843 break;
2844 case GIC_PAGE_SIZE_16K:
2845 psz = SZ_16K;
2846 break;
2847 case GIC_PAGE_SIZE_64K:
2848 psz = SZ_64K;
2849 break;
2850 }
2851
2852 /*
2853 * Start populating the register from scratch, including RO fields
2854 * (which we want to print in debug cases...)
2855 */
2856 val = 0;
2857 val |= FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, gpsz);
2858 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ENTRY_SIZE, esz);
2859
2860 /* How many entries per GIC page? */
2861 esz++;
2862 epp = psz / (esz * SZ_8);
2863
2864 /*
2865 * If we need more than just a single L1 page, flag the table
2866 * as indirect and compute the number of required L1 pages.
2867 */
2868 if (epp < ITS_MAX_VPEID) {
2869 int nl2;
2870
2871 val |= GICR_VPROPBASER_4_1_INDIRECT;
2872
2873 /* Number of L2 pages required to cover the VPEID space */
2874 nl2 = DIV_ROUND_UP(ITS_MAX_VPEID, epp);
2875
2876 /* Number of L1 pages to point to the L2 pages */
2877 npg = DIV_ROUND_UP(nl2 * SZ_8, psz);
2878 } else {
2879 npg = 1;
2880 }
2881
Zenghui Yue88bd312020-02-06 15:57:06 +08002882 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1);
Marc Zyngier5e516842019-12-24 11:10:28 +00002883
2884 /* Right, that's the number of CPU pages we need for L1 */
2885 np = DIV_ROUND_UP(npg * psz, PAGE_SIZE);
2886
2887 pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
2888 np, npg, psz, epp, esz);
Zenghui Yud1bd7e02020-06-30 21:37:46 +08002889 page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
Marc Zyngier5e516842019-12-24 11:10:28 +00002890 if (!page)
2891 return -ENOMEM;
2892
Zenghui Yu8b718d42020-02-06 15:57:07 +08002893 gic_data_rdist()->vpe_l1_base = page_address(page);
Marc Zyngier5e516842019-12-24 11:10:28 +00002894 pa = virt_to_phys(page_address(page));
2895 WARN_ON(!IS_ALIGNED(pa, psz));
2896
2897 val |= FIELD_PREP(GICR_VPROPBASER_4_1_ADDR, pa >> 12);
2898 val |= GICR_VPROPBASER_RaWb;
2899 val |= GICR_VPROPBASER_InnerShareable;
2900 val |= GICR_VPROPBASER_4_1_Z;
2901 val |= GICR_VPROPBASER_4_1_VALID;
2902
2903out:
Zenghui Yu5186a6c2020-02-06 15:57:11 +08002904 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
Marc Zyngier5e516842019-12-24 11:10:28 +00002905 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask);
2906
2907 pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n",
2908 smp_processor_id(), val,
2909 cpumask_pr_args(gic_data_rdist()->vpe_table_mask));
2910
2911 return 0;
2912}
2913
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002914static int its_alloc_collections(struct its_node *its)
2915{
Marc Zyngier83559b42018-06-22 10:52:52 +01002916 int i;
2917
Kees Cook6396bb22018-06-12 14:03:40 -07002918 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002919 GFP_KERNEL);
2920 if (!its->collections)
2921 return -ENOMEM;
2922
Marc Zyngier83559b42018-06-22 10:52:52 +01002923 for (i = 0; i < nr_cpu_ids; i++)
2924 its->collections[i].target_address = ~0ULL;
2925
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00002926 return 0;
2927}
2928
Marc Zyngier7c297a22016-12-19 18:34:38 +00002929static struct page *its_allocate_pending_table(gfp_t gfp_flags)
2930{
2931 struct page *pend_page;
Marc Zyngieradaab502018-07-17 18:06:39 +01002932
Marc Zyngier7c297a22016-12-19 18:34:38 +00002933 pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
Marc Zyngieradaab502018-07-17 18:06:39 +01002934 get_order(LPI_PENDBASE_SZ));
Marc Zyngier7c297a22016-12-19 18:34:38 +00002935 if (!pend_page)
2936 return NULL;
2937
2938 /* Make sure the GIC will observe the zero-ed page */
2939 gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
2940
2941 return pend_page;
2942}
2943
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00002944static void its_free_pending_table(struct page *pt)
2945{
Marc Zyngieradaab502018-07-17 18:06:39 +01002946 free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00002947}
2948
Marc Zyngierc6e2ccb2018-06-26 11:21:11 +01002949/*
Marc Zyngier5e2c9f92018-07-27 16:23:18 +01002950 * Booting with kdump and LPIs enabled is generally fine. Any other
2951 * case is wrong in the absence of firmware/EFI support.
Marc Zyngierc6e2ccb2018-06-26 11:21:11 +01002952 */
Marc Zyngierc440a9d2018-07-27 15:40:13 +01002953static bool enabled_lpis_allowed(void)
2954{
Marc Zyngier5e2c9f92018-07-27 16:23:18 +01002955 phys_addr_t addr;
2956 u64 val;
Marc Zyngierc6e2ccb2018-06-26 11:21:11 +01002957
Marc Zyngier5e2c9f92018-07-27 16:23:18 +01002958 /* Check whether the property table is in a reserved region */
2959 val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
2960 addr = val & GENMASK_ULL(51, 12);
2961
2962 return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
Marc Zyngierc440a9d2018-07-27 15:40:13 +01002963}
2964
Marc Zyngier11e37d32018-07-27 13:38:54 +01002965static int __init allocate_lpi_tables(void)
2966{
Marc Zyngierc440a9d2018-07-27 15:40:13 +01002967 u64 val;
Marc Zyngier11e37d32018-07-27 13:38:54 +01002968 int err, cpu;
2969
Marc Zyngierc440a9d2018-07-27 15:40:13 +01002970 /*
2971 * If LPIs are enabled while we run this from the boot CPU,
2972 * flag the RD tables as pre-allocated if the stars do align.
2973 */
2974 val = readl_relaxed(gic_data_rdist_rd_base() + GICR_CTLR);
2975 if ((val & GICR_CTLR_ENABLE_LPIS) && enabled_lpis_allowed()) {
2976 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED |
2977 RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING);
2978 pr_info("GICv3: Using preallocated redistributor tables\n");
2979 }
2980
Marc Zyngier11e37d32018-07-27 13:38:54 +01002981 err = its_setup_lpi_prop_table();
2982 if (err)
2983 return err;
2984
2985 /*
2986 * We allocate all the pending tables anyway, as we may have a
2987 * mix of RDs that have had LPIs enabled, and some that
2988 * don't. We'll free the unused ones as each CPU comes online.
2989 */
2990 for_each_possible_cpu(cpu) {
2991 struct page *pend_page;
2992
2993 pend_page = its_allocate_pending_table(GFP_NOWAIT);
2994 if (!pend_page) {
2995 pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
2996 return -ENOMEM;
2997 }
2998
2999 gic_data_rdist_cpu(cpu)->pend_page = pend_page;
3000 }
3001
3002 return 0;
3003}
3004
Marc Zyngiere64fab12019-12-24 11:10:35 +00003005static u64 its_clear_vpend_valid(void __iomem *vlpi_base, u64 clr, u64 set)
Heyi Guo64794502019-01-24 21:37:08 +08003006{
3007 u32 count = 1000000; /* 1s! */
3008 bool clean;
3009 u64 val;
3010
Zenghui Yu5186a6c2020-02-06 15:57:11 +08003011 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
Heyi Guo64794502019-01-24 21:37:08 +08003012 val &= ~GICR_VPENDBASER_Valid;
Marc Zyngiere64fab12019-12-24 11:10:35 +00003013 val &= ~clr;
3014 val |= set;
Zenghui Yu5186a6c2020-02-06 15:57:11 +08003015 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
Heyi Guo64794502019-01-24 21:37:08 +08003016
3017 do {
Zenghui Yu5186a6c2020-02-06 15:57:11 +08003018 val = gicr_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
Heyi Guo64794502019-01-24 21:37:08 +08003019 clean = !(val & GICR_VPENDBASER_Dirty);
3020 if (!clean) {
3021 count--;
3022 cpu_relax();
3023 udelay(1);
3024 }
3025 } while (!clean && count);
3026
Marc Zyngiere64fab12019-12-24 11:10:35 +00003027 if (unlikely(val & GICR_VPENDBASER_Dirty)) {
3028 pr_err_ratelimited("ITS virtual pending table not cleaning\n");
3029 val |= GICR_VPENDBASER_PendingLast;
3030 }
3031
Heyi Guo64794502019-01-24 21:37:08 +08003032 return val;
3033}
3034
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003035static void its_cpu_init_lpis(void)
3036{
3037 void __iomem *rbase = gic_data_rdist_rd_base();
3038 struct page *pend_page;
Marc Zyngier11e37d32018-07-27 13:38:54 +01003039 phys_addr_t paddr;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003040 u64 val, tmp;
3041
Marc Zyngier11e37d32018-07-27 13:38:54 +01003042 if (gic_data_rdist()->lpi_enabled)
3043 return;
3044
Marc Zyngierc440a9d2018-07-27 15:40:13 +01003045 val = readl_relaxed(rbase + GICR_CTLR);
3046 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) &&
3047 (val & GICR_CTLR_ENABLE_LPIS)) {
Marc Zyngierf842ca82018-07-27 16:03:31 +01003048 /*
3049 * Check that we get the same property table on all
3050 * RDs. If we don't, this is hopeless.
3051 */
3052 paddr = gicr_read_propbaser(rbase + GICR_PROPBASER);
3053 paddr &= GENMASK_ULL(51, 12);
3054 if (WARN_ON(gic_rdists->prop_table_pa != paddr))
3055 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
3056
Marc Zyngierc440a9d2018-07-27 15:40:13 +01003057 paddr = gicr_read_pendbaser(rbase + GICR_PENDBASER);
3058 paddr &= GENMASK_ULL(51, 16);
3059
Marc Zyngier5e2c9f92018-07-27 16:23:18 +01003060 WARN_ON(!gic_check_reserved_range(paddr, LPI_PENDBASE_SZ));
Marc Zyngierc440a9d2018-07-27 15:40:13 +01003061 its_free_pending_table(gic_data_rdist()->pend_page);
3062 gic_data_rdist()->pend_page = NULL;
3063
3064 goto out;
3065 }
3066
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003067 pend_page = gic_data_rdist()->pend_page;
Marc Zyngier11e37d32018-07-27 13:38:54 +01003068 paddr = page_to_phys(pend_page);
Marc Zyngier3fb68fa2018-07-27 16:21:18 +01003069 WARN_ON(gic_reserve_range(paddr, LPI_PENDBASE_SZ));
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003070
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003071 /* set PROPBASE */
Marc Zyngiere1a2e202018-07-27 14:36:00 +01003072 val = (gic_rdists->prop_table_pa |
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003073 GICR_PROPBASER_InnerShareable |
Shanker Donthineni2fd632a2017-01-25 21:51:41 -06003074 GICR_PROPBASER_RaWaWb |
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003075 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
3076
Vladimir Murzin0968a612016-11-02 11:54:06 +00003077 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
3078 tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003079
3080 if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
Marc Zyngier241a3862015-03-27 14:15:05 +00003081 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
3082 /*
3083 * The HW reports non-shareable, we must
3084 * remove the cacheability attributes as
3085 * well.
3086 */
3087 val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
3088 GICR_PROPBASER_CACHEABILITY_MASK);
3089 val |= GICR_PROPBASER_nC;
Vladimir Murzin0968a612016-11-02 11:54:06 +00003090 gicr_write_propbaser(val, rbase + GICR_PROPBASER);
Marc Zyngier241a3862015-03-27 14:15:05 +00003091 }
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003092 pr_info_once("GIC: using cache flushing for LPI property table\n");
3093 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
3094 }
3095
3096 /* set PENDBASE */
3097 val = (page_to_phys(pend_page) |
Marc Zyngier4ad3e362015-03-27 14:15:04 +00003098 GICR_PENDBASER_InnerShareable |
Shanker Donthineni2fd632a2017-01-25 21:51:41 -06003099 GICR_PENDBASER_RaWaWb);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003100
Vladimir Murzin0968a612016-11-02 11:54:06 +00003101 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
3102 tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
Marc Zyngier241a3862015-03-27 14:15:05 +00003103
3104 if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
3105 /*
3106 * The HW reports non-shareable, we must remove the
3107 * cacheability attributes as well.
3108 */
3109 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
3110 GICR_PENDBASER_CACHEABILITY_MASK);
3111 val |= GICR_PENDBASER_nC;
Vladimir Murzin0968a612016-11-02 11:54:06 +00003112 gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
Marc Zyngier241a3862015-03-27 14:15:05 +00003113 }
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003114
3115 /* Enable LPIs */
3116 val = readl_relaxed(rbase + GICR_CTLR);
3117 val |= GICR_CTLR_ENABLE_LPIS;
3118 writel_relaxed(val, rbase + GICR_CTLR);
3119
Marc Zyngier5e516842019-12-24 11:10:28 +00003120 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) {
Heyi Guo64794502019-01-24 21:37:08 +08003121 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3122
3123 /*
3124 * It's possible for CPU to receive VLPIs before it is
3125 * sheduled as a vPE, especially for the first CPU, and the
3126 * VLPI with INTID larger than 2^(IDbits+1) will be considered
3127 * as out of range and dropped by GIC.
3128 * So we initialize IDbits to known value to avoid VLPI drop.
3129 */
3130 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3131 pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
3132 smp_processor_id(), val);
Zenghui Yu5186a6c2020-02-06 15:57:11 +08003133 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
Heyi Guo64794502019-01-24 21:37:08 +08003134
3135 /*
3136 * Also clear Valid bit of GICR_VPENDBASER, in case some
3137 * ancient programming gets left in and has possibility of
3138 * corrupting memory.
3139 */
Marc Zyngiere64fab12019-12-24 11:10:35 +00003140 val = its_clear_vpend_valid(vlpi_base, 0, 0);
Heyi Guo64794502019-01-24 21:37:08 +08003141 }
3142
Marc Zyngier5e516842019-12-24 11:10:28 +00003143 if (allocate_vpe_l1_table()) {
3144 /*
3145 * If the allocation has failed, we're in massive trouble.
3146 * Disable direct injection, and pray that no VM was
3147 * already running...
3148 */
3149 gic_rdists->has_rvpeid = false;
3150 gic_rdists->has_vlpis = false;
3151 }
3152
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003153 /* Make sure the GIC has seen the above */
3154 dsb(sy);
Marc Zyngierc440a9d2018-07-27 15:40:13 +01003155out:
Marc Zyngier11e37d32018-07-27 13:38:54 +01003156 gic_data_rdist()->lpi_enabled = true;
Marc Zyngierc440a9d2018-07-27 15:40:13 +01003157 pr_info("GICv3: CPU%d: using %s LPI pending table @%pa\n",
Marc Zyngier11e37d32018-07-27 13:38:54 +01003158 smp_processor_id(),
Marc Zyngierc440a9d2018-07-27 15:40:13 +01003159 gic_data_rdist()->pend_page ? "allocated" : "reserved",
Marc Zyngier11e37d32018-07-27 13:38:54 +01003160 &paddr);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003161}
3162
Derek Basehore920181c2018-02-28 21:48:20 -08003163static void its_cpu_init_collection(struct its_node *its)
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003164{
Derek Basehore920181c2018-02-28 21:48:20 -08003165 int cpu = smp_processor_id();
3166 u64 target;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003167
Derek Basehore920181c2018-02-28 21:48:20 -08003168 /* avoid cross node collections and its mapping */
3169 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
3170 struct device_node *cpu_node;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003171
Derek Basehore920181c2018-02-28 21:48:20 -08003172 cpu_node = of_get_cpu_node(cpu, NULL);
3173 if (its->numa_node != NUMA_NO_NODE &&
3174 its->numa_node != of_node_to_nid(cpu_node))
3175 return;
3176 }
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003177
Derek Basehore920181c2018-02-28 21:48:20 -08003178 /*
3179 * We now have to bind each collection to its target
3180 * redistributor.
3181 */
3182 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003183 /*
Derek Basehore920181c2018-02-28 21:48:20 -08003184 * This ITS wants the physical address of the
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003185 * redistributor.
3186 */
Derek Basehore920181c2018-02-28 21:48:20 -08003187 target = gic_data_rdist()->phys_base;
3188 } else {
3189 /* This ITS wants a linear CPU number. */
3190 target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
3191 target = GICR_TYPER_CPU_NUMBER(target) << 16;
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003192 }
3193
Derek Basehore920181c2018-02-28 21:48:20 -08003194 /* Perform collection mapping */
3195 its->collections[cpu].target_address = target;
3196 its->collections[cpu].col_id = cpu;
3197
3198 its_send_mapc(its, &its->collections[cpu], 1);
3199 its_send_invall(its, &its->collections[cpu]);
3200}
3201
3202static void its_cpu_init_collections(void)
3203{
3204 struct its_node *its;
3205
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02003206 raw_spin_lock(&its_lock);
Derek Basehore920181c2018-02-28 21:48:20 -08003207
3208 list_for_each_entry(its, &its_nodes, entry)
3209 its_cpu_init_collection(its);
3210
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02003211 raw_spin_unlock(&its_lock);
Marc Zyngier1ac19ca2014-11-24 14:35:14 +00003212}
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003213
3214static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
3215{
3216 struct its_device *its_dev = NULL, *tmp;
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003217 unsigned long flags;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003218
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003219 raw_spin_lock_irqsave(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003220
3221 list_for_each_entry(tmp, &its->its_device_list, entry) {
3222 if (tmp->device_id == dev_id) {
3223 its_dev = tmp;
3224 break;
3225 }
3226 }
3227
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003228 raw_spin_unlock_irqrestore(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003229
3230 return its_dev;
3231}
3232
Shanker Donthineni466b7d12016-03-09 22:10:49 -06003233static struct its_baser *its_get_baser(struct its_node *its, u32 type)
3234{
3235 int i;
3236
3237 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
3238 if (GITS_BASER_TYPE(its->tables[i].val) == type)
3239 return &its->tables[i];
3240 }
3241
3242 return NULL;
3243}
3244
Shanker Donthineni539d3782019-01-14 09:50:19 +00003245static bool its_alloc_table_entry(struct its_node *its,
3246 struct its_baser *baser, u32 id)
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003247{
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003248 struct page *page;
3249 u32 esz, idx;
3250 __le64 *table;
3251
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003252 /* Don't allow device id that exceeds single, flat table limit */
3253 esz = GITS_BASER_ENTRY_SIZE(baser->val);
3254 if (!(baser->val & GITS_BASER_INDIRECT))
Marc Zyngier70cc81e2016-12-19 18:53:02 +00003255 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003256
3257 /* Compute 1st level table index & check if that exceeds table limit */
Marc Zyngier70cc81e2016-12-19 18:53:02 +00003258 idx = id >> ilog2(baser->psz / esz);
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003259 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
3260 return false;
3261
3262 table = baser->base;
3263
3264 /* Allocate memory for 2nd level table */
3265 if (!table[idx]) {
Shanker Donthineni539d3782019-01-14 09:50:19 +00003266 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
3267 get_order(baser->psz));
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003268 if (!page)
3269 return false;
3270
3271 /* Flush Lvl2 table to PoC if hw doesn't support coherency */
3272 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
Vladimir Murzin328191c2016-11-02 11:54:05 +00003273 gic_flush_dcache_to_poc(page_address(page), baser->psz);
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003274
3275 table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);
3276
3277 /* Flush Lvl1 entry to PoC if hw doesn't support coherency */
3278 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
Vladimir Murzin328191c2016-11-02 11:54:05 +00003279 gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003280
3281 /* Ensure updated table contents are visible to ITS hardware */
3282 dsb(sy);
3283 }
3284
3285 return true;
3286}
3287
Marc Zyngier70cc81e2016-12-19 18:53:02 +00003288static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
3289{
3290 struct its_baser *baser;
3291
3292 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);
3293
3294 /* Don't allow device id that exceeds ITS hardware limit */
3295 if (!baser)
Marc Zyngier576a8342019-11-08 16:58:00 +00003296 return (ilog2(dev_id) < device_ids(its));
Marc Zyngier70cc81e2016-12-19 18:53:02 +00003297
Shanker Donthineni539d3782019-01-14 09:50:19 +00003298 return its_alloc_table_entry(its, baser, dev_id);
Marc Zyngier70cc81e2016-12-19 18:53:02 +00003299}
3300
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00003301static bool its_alloc_vpe_table(u32 vpe_id)
3302{
3303 struct its_node *its;
Zenghui Yu4e6437f2020-02-06 15:57:08 +08003304 int cpu;
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00003305
3306 /*
3307 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
3308 * could try and only do it on ITSs corresponding to devices
3309 * that have interrupts targeted at this VPE, but the
3310 * complexity becomes crazy (and you have tons of memory
3311 * anyway, right?).
3312 */
3313 list_for_each_entry(its, &its_nodes, entry) {
3314 struct its_baser *baser;
3315
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00003316 if (!is_v4(its))
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00003317 continue;
3318
3319 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
3320 if (!baser)
3321 return false;
3322
Shanker Donthineni539d3782019-01-14 09:50:19 +00003323 if (!its_alloc_table_entry(its, baser, vpe_id))
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00003324 return false;
3325 }
3326
Zenghui Yu4e6437f2020-02-06 15:57:08 +08003327 /* Non v4.1? No need to iterate RDs and go back early. */
3328 if (!gic_rdists->has_rvpeid)
3329 return true;
3330
3331 /*
3332 * Make sure the L2 tables are allocated for all copies of
3333 * the L1 table on *all* v4.1 RDs.
3334 */
3335 for_each_possible_cpu(cpu) {
3336 if (!allocate_vpe_l2_table(cpu, vpe_id))
3337 return false;
3338 }
3339
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00003340 return true;
3341}
3342
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003343static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003344 int nvecs, bool alloc_lpis)
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003345{
3346 struct its_device *dev;
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003347 unsigned long *lpi_map = NULL;
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003348 unsigned long flags;
Marc Zyngier591e5be2015-07-17 10:46:42 +01003349 u16 *col_map = NULL;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003350 void *itt;
3351 int lpi_base;
3352 int nr_lpis;
Marc Zyngierc8481262014-12-12 10:51:24 +00003353 int nr_ites;
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003354 int sz;
3355
Shanker Donthineni3faf24e2016-06-06 18:17:32 -05003356 if (!its_alloc_device_table(its, dev_id))
Shanker Donthineni466b7d12016-03-09 22:10:49 -06003357 return NULL;
3358
Marc Zyngier147c8f32018-05-27 16:39:55 +01003359 if (WARN_ON(!is_power_of_2(nvecs)))
3360 nvecs = roundup_pow_of_two(nvecs);
3361
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003362 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
Marc Zyngierc8481262014-12-12 10:51:24 +00003363 /*
Marc Zyngier147c8f32018-05-27 16:39:55 +01003364 * Even if the device wants a single LPI, the ITT must be
3365 * sized as a power of two (and you need at least one bit...).
Marc Zyngierc8481262014-12-12 10:51:24 +00003366 */
Marc Zyngier147c8f32018-05-27 16:39:55 +01003367 nr_ites = max(2, nvecs);
Marc Zyngierffedbf02019-11-08 16:57:59 +00003368 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003369 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
Shanker Donthineni539d3782019-01-14 09:50:19 +00003370 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003371 if (alloc_lpis) {
Marc Zyngier38dd7c42018-05-27 17:03:03 +01003372 lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003373 if (lpi_map)
Kees Cook6396bb22018-06-12 14:03:40 -07003374 col_map = kcalloc(nr_lpis, sizeof(*col_map),
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003375 GFP_KERNEL);
3376 } else {
Kees Cook6396bb22018-06-12 14:03:40 -07003377 col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003378 nr_lpis = 0;
3379 lpi_base = 0;
3380 }
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003381
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003382 if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003383 kfree(dev);
3384 kfree(itt);
3385 kfree(lpi_map);
Marc Zyngier591e5be2015-07-17 10:46:42 +01003386 kfree(col_map);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003387 return NULL;
3388 }
3389
Vladimir Murzin328191c2016-11-02 11:54:05 +00003390 gic_flush_dcache_to_poc(itt, sz);
Marc Zyngier5a9a8912015-09-13 12:14:32 +01003391
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003392 dev->its = its;
3393 dev->itt = itt;
Marc Zyngierc8481262014-12-12 10:51:24 +00003394 dev->nr_ites = nr_ites;
Marc Zyngier591e5be2015-07-17 10:46:42 +01003395 dev->event_map.lpi_map = lpi_map;
3396 dev->event_map.col_map = col_map;
3397 dev->event_map.lpi_base = lpi_base;
3398 dev->event_map.nr_lpis = nr_lpis;
Marc Zyngier11635fa2019-11-08 16:58:05 +00003399 raw_spin_lock_init(&dev->event_map.vlpi_lock);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003400 dev->device_id = dev_id;
3401 INIT_LIST_HEAD(&dev->entry);
3402
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003403 raw_spin_lock_irqsave(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003404 list_add(&dev->entry, &its->its_device_list);
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003405 raw_spin_unlock_irqrestore(&its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003406
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003407 /* Map device to its ITT */
3408 its_send_mapd(dev, 1);
3409
3410 return dev;
3411}
3412
3413static void its_free_device(struct its_device *its_dev)
3414{
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003415 unsigned long flags;
3416
3417 raw_spin_lock_irqsave(&its_dev->its->lock, flags);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003418 list_del(&its_dev->entry);
Marc Zyngier3e39e8f52015-03-06 16:37:43 +00003419 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
Marc Zyngier898aa5c2019-11-08 16:57:55 +00003420 kfree(its_dev->event_map.col_map);
Marc Zyngier84a6a2e2014-11-24 14:35:15 +00003421 kfree(its_dev->itt);
3422 kfree(its_dev);
3423}
Marc Zyngierb48ac832014-11-24 14:35:16 +00003424
Marc Zyngier8208d172019-01-18 14:08:59 +00003425static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
Marc Zyngierb48ac832014-11-24 14:35:16 +00003426{
3427 int idx;
3428
Zenghui Yu342be102019-07-27 06:14:22 +00003429 /* Find a free LPI region in lpi_map and allocate them. */
Marc Zyngier8208d172019-01-18 14:08:59 +00003430 idx = bitmap_find_free_region(dev->event_map.lpi_map,
3431 dev->event_map.nr_lpis,
3432 get_count_order(nvecs));
3433 if (idx < 0)
Marc Zyngierb48ac832014-11-24 14:35:16 +00003434 return -ENOSPC;
3435
Marc Zyngier591e5be2015-07-17 10:46:42 +01003436 *hwirq = dev->event_map.lpi_base + idx;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003437
Marc Zyngierb48ac832014-11-24 14:35:16 +00003438 return 0;
3439}
3440
Marc Zyngier54456db2015-07-28 14:46:21 +01003441static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
3442 int nvec, msi_alloc_info_t *info)
Marc Zyngiere8137f42015-03-06 16:37:42 +00003443{
Marc Zyngierb48ac832014-11-24 14:35:16 +00003444 struct its_node *its;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003445 struct its_device *its_dev;
Marc Zyngier54456db2015-07-28 14:46:21 +01003446 struct msi_domain_info *msi_info;
3447 u32 dev_id;
Marc Zyngier9791ec72019-01-29 10:02:33 +00003448 int err = 0;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003449
Marc Zyngier54456db2015-07-28 14:46:21 +01003450 /*
Julien Gralla7c90f52019-04-18 16:58:14 +01003451 * We ignore "dev" entirely, and rely on the dev_id that has
Marc Zyngier54456db2015-07-28 14:46:21 +01003452 * been passed via the scratchpad. This limits this domain's
3453 * usefulness to upper layers that definitely know that they
3454 * are built on top of the ITS.
3455 */
3456 dev_id = info->scratchpad[0].ul;
3457
3458 msi_info = msi_get_domain_info(domain);
3459 its = msi_info->data;
3460
Marc Zyngier20b3d542016-12-20 15:23:22 +00003461 if (!gic_rdists->has_direct_lpi &&
3462 vpe_proxy.dev &&
3463 vpe_proxy.dev->its == its &&
3464 dev_id == vpe_proxy.dev->device_id) {
3465 /* Bad luck. Get yourself a better implementation */
3466 WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
3467 dev_id);
3468 return -EINVAL;
3469 }
3470
Marc Zyngier9791ec72019-01-29 10:02:33 +00003471 mutex_lock(&its->dev_alloc_lock);
Marc Zyngierf1304202015-07-28 14:46:18 +01003472 its_dev = its_find_device(its, dev_id);
Marc Zyngiere8137f42015-03-06 16:37:42 +00003473 if (its_dev) {
3474 /*
3475 * We already have seen this ID, probably through
3476 * another alias (PCI bridge of some sort). No need to
3477 * create the device.
3478 */
Marc Zyngier9791ec72019-01-29 10:02:33 +00003479 its_dev->shared = true;
Marc Zyngierf1304202015-07-28 14:46:18 +01003480 pr_debug("Reusing ITT for devID %x\n", dev_id);
Marc Zyngiere8137f42015-03-06 16:37:42 +00003481 goto out;
3482 }
Marc Zyngierb48ac832014-11-24 14:35:16 +00003483
Marc Zyngier93f94ea2017-08-04 18:37:09 +01003484 its_dev = its_create_device(its, dev_id, nvec, true);
Marc Zyngier9791ec72019-01-29 10:02:33 +00003485 if (!its_dev) {
3486 err = -ENOMEM;
3487 goto out;
3488 }
Marc Zyngierb48ac832014-11-24 14:35:16 +00003489
Marc Zyngierf1304202015-07-28 14:46:18 +01003490 pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
Marc Zyngiere8137f42015-03-06 16:37:42 +00003491out:
Marc Zyngier9791ec72019-01-29 10:02:33 +00003492 mutex_unlock(&its->dev_alloc_lock);
Marc Zyngierb48ac832014-11-24 14:35:16 +00003493 info->scratchpad[0].ptr = its_dev;
Marc Zyngier9791ec72019-01-29 10:02:33 +00003494 return err;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003495}
3496
Marc Zyngier54456db2015-07-28 14:46:21 +01003497static struct msi_domain_ops its_msi_domain_ops = {
3498 .msi_prepare = its_msi_prepare,
3499};
3500
Marc Zyngierb48ac832014-11-24 14:35:16 +00003501static int its_irq_gic_domain_alloc(struct irq_domain *domain,
3502 unsigned int virq,
3503 irq_hw_number_t hwirq)
3504{
Marc Zyngierf833f572015-10-13 12:51:33 +01003505 struct irq_fwspec fwspec;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003506
Marc Zyngierf833f572015-10-13 12:51:33 +01003507 if (irq_domain_get_of_node(domain->parent)) {
3508 fwspec.fwnode = domain->parent->fwnode;
3509 fwspec.param_count = 3;
3510 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
3511 fwspec.param[1] = hwirq;
3512 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02003513 } else if (is_fwnode_irqchip(domain->parent->fwnode)) {
3514 fwspec.fwnode = domain->parent->fwnode;
3515 fwspec.param_count = 2;
3516 fwspec.param[0] = hwirq;
3517 fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
Marc Zyngierf833f572015-10-13 12:51:33 +01003518 } else {
3519 return -EINVAL;
3520 }
Marc Zyngierb48ac832014-11-24 14:35:16 +00003521
Marc Zyngierf833f572015-10-13 12:51:33 +01003522 return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
Marc Zyngierb48ac832014-11-24 14:35:16 +00003523}
3524
3525static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
3526 unsigned int nr_irqs, void *args)
3527{
3528 msi_alloc_info_t *info = args;
3529 struct its_device *its_dev = info->scratchpad[0].ptr;
Julien Grall35ae7df2019-05-01 14:58:21 +01003530 struct its_node *its = its_dev->its;
Thomas Gleixnerf0c7bac2020-07-24 22:44:41 +02003531 struct irq_data *irqd;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003532 irq_hw_number_t hwirq;
3533 int err;
3534 int i;
3535
Marc Zyngier8208d172019-01-18 14:08:59 +00003536 err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
3537 if (err)
3538 return err;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003539
Julien Grall35ae7df2019-05-01 14:58:21 +01003540 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev));
3541 if (err)
3542 return err;
3543
Marc Zyngier8208d172019-01-18 14:08:59 +00003544 for (i = 0; i < nr_irqs; i++) {
3545 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
Marc Zyngierb48ac832014-11-24 14:35:16 +00003546 if (err)
3547 return err;
3548
3549 irq_domain_set_hwirq_and_chip(domain, virq + i,
Marc Zyngier8208d172019-01-18 14:08:59 +00003550 hwirq + i, &its_irq_chip, its_dev);
Thomas Gleixnerf0c7bac2020-07-24 22:44:41 +02003551 irqd = irq_get_irq_data(virq + i);
3552 irqd_set_single_target(irqd);
3553 irqd_set_affinity_on_activate(irqd);
Marc Zyngierf1304202015-07-28 14:46:18 +01003554 pr_debug("ID:%d pID:%d vID:%d\n",
Marc Zyngier8208d172019-01-18 14:08:59 +00003555 (int)(hwirq + i - its_dev->event_map.lpi_base),
3556 (int)(hwirq + i), virq + i);
Marc Zyngierb48ac832014-11-24 14:35:16 +00003557 }
3558
3559 return 0;
3560}
3561
Thomas Gleixner72491642017-09-13 23:29:10 +02003562static int its_irq_domain_activate(struct irq_domain *domain,
Thomas Gleixner702cb0a2017-12-29 16:59:06 +01003563 struct irq_data *d, bool reserve)
Marc Zyngieraca268d2014-12-12 10:51:23 +00003564{
3565 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3566 u32 event = its_get_event_id(d);
Marc Zyngier0d224d32017-08-18 09:39:18 +01003567 int cpu;
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +02003568
Marc Zyngierc5d60822020-05-15 17:57:52 +01003569 cpu = its_select_cpu(d, cpu_online_mask);
3570 if (cpu < 0 || cpu >= nr_cpu_ids)
3571 return -EINVAL;
Yang Yingliangc1797b12018-06-22 10:52:51 +01003572
Marc Zyngier2f13ff12020-05-15 17:57:51 +01003573 its_inc_lpi_count(d, cpu);
Marc Zyngier0d224d32017-08-18 09:39:18 +01003574 its_dev->event_map.col_map[event] = cpu;
3575 irq_data_update_effective_affinity(d, cpumask_of(cpu));
Marc Zyngier591e5be2015-07-17 10:46:42 +01003576
Marc Zyngieraca268d2014-12-12 10:51:23 +00003577 /* Map the GIC IRQ and event to the device */
Marc Zyngier6a25ad32016-12-20 15:52:26 +00003578 its_send_mapti(its_dev, d->hwirq, event);
Thomas Gleixner72491642017-09-13 23:29:10 +02003579 return 0;
Marc Zyngieraca268d2014-12-12 10:51:23 +00003580}
3581
3582static void its_irq_domain_deactivate(struct irq_domain *domain,
3583 struct irq_data *d)
3584{
3585 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
3586 u32 event = its_get_event_id(d);
3587
Marc Zyngier2f13ff12020-05-15 17:57:51 +01003588 its_dec_lpi_count(d, its_dev->event_map.col_map[event]);
Marc Zyngieraca268d2014-12-12 10:51:23 +00003589 /* Stop the delivery of interrupts */
3590 its_send_discard(its_dev, event);
3591}
3592
Marc Zyngierb48ac832014-11-24 14:35:16 +00003593static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
3594 unsigned int nr_irqs)
3595{
3596 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
3597 struct its_device *its_dev = irq_data_get_irq_chip_data(d);
Marc Zyngier9791ec72019-01-29 10:02:33 +00003598 struct its_node *its = its_dev->its;
Marc Zyngierb48ac832014-11-24 14:35:16 +00003599 int i;
3600
Marc Zyngierc9c96e32019-09-05 14:56:47 +01003601 bitmap_release_region(its_dev->event_map.lpi_map,
3602 its_get_event_id(irq_domain_get_irq_data(domain, virq)),
3603 get_count_order(nr_irqs));
3604
Marc Zyngierb48ac832014-11-24 14:35:16 +00003605 for (i = 0; i < nr_irqs; i++) {
3606 struct irq_data *data = irq_domain_get_irq_data(domain,
3607 virq + i);
Marc Zyngierb48ac832014-11-24 14:35:16 +00003608 /* Nuke the entry in the domain */
Marc Zyngier2da39942014-12-12 10:51:22 +00003609 irq_domain_reset_irq_data(data);
Marc Zyngierb48ac832014-11-24 14:35:16 +00003610 }
3611
Marc Zyngier9791ec72019-01-29 10:02:33 +00003612 mutex_lock(&its->dev_alloc_lock);
3613
3614 /*
3615 * If all interrupts have been freed, start mopping the
3616 * floor. This is conditionned on the device not being shared.
3617 */
3618 if (!its_dev->shared &&
3619 bitmap_empty(its_dev->event_map.lpi_map,
Marc Zyngier591e5be2015-07-17 10:46:42 +01003620 its_dev->event_map.nr_lpis)) {
Marc Zyngier38dd7c42018-05-27 17:03:03 +01003621 its_lpi_free(its_dev->event_map.lpi_map,
3622 its_dev->event_map.lpi_base,
3623 its_dev->event_map.nr_lpis);
Marc Zyngierb48ac832014-11-24 14:35:16 +00003624
3625 /* Unmap device/itt */
3626 its_send_mapd(its_dev, 0);
3627 its_free_device(its_dev);
3628 }
3629
Marc Zyngier9791ec72019-01-29 10:02:33 +00003630 mutex_unlock(&its->dev_alloc_lock);
3631
Marc Zyngierb48ac832014-11-24 14:35:16 +00003632 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
3633}
3634
3635static const struct irq_domain_ops its_domain_ops = {
3636 .alloc = its_irq_domain_alloc,
3637 .free = its_irq_domain_free,
Marc Zyngieraca268d2014-12-12 10:51:23 +00003638 .activate = its_irq_domain_activate,
3639 .deactivate = its_irq_domain_deactivate,
Marc Zyngierb48ac832014-11-24 14:35:16 +00003640};
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00003641
Marc Zyngier20b3d542016-12-20 15:23:22 +00003642/*
3643 * This is insane.
3644 *
Marc Zyngier0684c702019-12-24 11:10:30 +00003645 * If a GICv4.0 doesn't implement Direct LPIs (which is extremely
Marc Zyngier20b3d542016-12-20 15:23:22 +00003646 * likely), the only way to perform an invalidate is to use a fake
3647 * device to issue an INV command, implying that the LPI has first
3648 * been mapped to some event on that device. Since this is not exactly
3649 * cheap, we try to keep that mapping around as long as possible, and
3650 * only issue an UNMAP if we're short on available slots.
3651 *
3652 * Broken by design(tm).
Marc Zyngier0684c702019-12-24 11:10:30 +00003653 *
3654 * GICv4.1, on the other hand, mandates that we're able to invalidate
3655 * by writing to a MMIO register. It doesn't implement the whole of
3656 * DirectLPI, but that's good enough. And most of the time, we don't
3657 * even have to invalidate anything, as the redistributor can be told
3658 * whether to generate a doorbell or not (we thus leave it enabled,
3659 * always).
Marc Zyngier20b3d542016-12-20 15:23:22 +00003660 */
3661static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
3662{
Marc Zyngier0684c702019-12-24 11:10:30 +00003663 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3664 if (gic_rdists->has_rvpeid)
3665 return;
3666
Marc Zyngier20b3d542016-12-20 15:23:22 +00003667 /* Already unmapped? */
3668 if (vpe->vpe_proxy_event == -1)
3669 return;
3670
3671 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
3672 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;
3673
3674 /*
3675 * We don't track empty slots at all, so let's move the
3676 * next_victim pointer if we can quickly reuse that slot
3677 * instead of nuking an existing entry. Not clear that this is
3678 * always a win though, and this might just generate a ripple
3679 * effect... Let's just hope VPEs don't migrate too often.
3680 */
3681 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3682 vpe_proxy.next_victim = vpe->vpe_proxy_event;
3683
3684 vpe->vpe_proxy_event = -1;
3685}
3686
3687static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
3688{
Marc Zyngier0684c702019-12-24 11:10:30 +00003689 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3690 if (gic_rdists->has_rvpeid)
3691 return;
3692
Marc Zyngier20b3d542016-12-20 15:23:22 +00003693 if (!gic_rdists->has_direct_lpi) {
3694 unsigned long flags;
3695
3696 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3697 its_vpe_db_proxy_unmap_locked(vpe);
3698 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3699 }
3700}
3701
3702static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
3703{
Marc Zyngier0684c702019-12-24 11:10:30 +00003704 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3705 if (gic_rdists->has_rvpeid)
3706 return;
3707
Marc Zyngier20b3d542016-12-20 15:23:22 +00003708 /* Already mapped? */
3709 if (vpe->vpe_proxy_event != -1)
3710 return;
3711
3712 /* This slot was already allocated. Kick the other VPE out. */
3713 if (vpe_proxy.vpes[vpe_proxy.next_victim])
3714 its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);
3715
3716 /* Map the new VPE instead */
3717 vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
3718 vpe->vpe_proxy_event = vpe_proxy.next_victim;
3719 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;
3720
3721 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
3722 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
3723}
3724
Marc Zyngier958b90d2017-08-18 16:14:17 +01003725static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
3726{
3727 unsigned long flags;
3728 struct its_collection *target_col;
3729
Marc Zyngier0684c702019-12-24 11:10:30 +00003730 /* GICv4.1 doesn't use a proxy, so nothing to do here */
3731 if (gic_rdists->has_rvpeid)
3732 return;
3733
Marc Zyngier958b90d2017-08-18 16:14:17 +01003734 if (gic_rdists->has_direct_lpi) {
3735 void __iomem *rdbase;
3736
3737 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
3738 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
Marc Zyngier2f4f0642019-11-08 16:57:56 +00003739 wait_for_syncr(rdbase);
Marc Zyngier958b90d2017-08-18 16:14:17 +01003740
3741 return;
3742 }
3743
3744 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3745
3746 its_vpe_db_proxy_map_locked(vpe);
3747
3748 target_col = &vpe_proxy.dev->its->collections[to];
3749 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
3750 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;
3751
3752 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3753}
3754
Marc Zyngier3171a472016-12-20 15:17:28 +00003755static int its_vpe_set_affinity(struct irq_data *d,
3756 const struct cpumask *mask_val,
3757 bool force)
3758{
3759 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
Marc Zyngierdd3f0502019-12-24 11:10:31 +00003760 int from, cpu = cpumask_first(mask_val);
Marc Zyngierf3a059212020-03-04 20:33:10 +00003761 unsigned long flags;
Marc Zyngier3171a472016-12-20 15:17:28 +00003762
3763 /*
3764 * Changing affinity is mega expensive, so let's be as lazy as
Marc Zyngier20b3d542016-12-20 15:23:22 +00003765 * we can and only do it if we really have to. Also, if mapped
Marc Zyngier958b90d2017-08-18 16:14:17 +01003766 * into the proxy device, we need to move the doorbell
3767 * interrupt to its new location.
Marc Zyngierf3a059212020-03-04 20:33:10 +00003768 *
3769 * Another thing is that changing the affinity of a vPE affects
3770 * *other interrupts* such as all the vLPIs that are routed to
3771 * this vPE. This means that the irq_desc lock is not enough to
3772 * protect us, and that we must ensure nobody samples vpe->col_idx
3773 * during the update, hence the lock below which must also be
3774 * taken on any vLPI handling path that evaluates vpe->col_idx.
Marc Zyngier3171a472016-12-20 15:17:28 +00003775 */
Marc Zyngierf3a059212020-03-04 20:33:10 +00003776 from = vpe_to_cpuid_lock(vpe, &flags);
3777 if (from == cpu)
Marc Zyngierdd3f0502019-12-24 11:10:31 +00003778 goto out;
Marc Zyngier958b90d2017-08-18 16:14:17 +01003779
Marc Zyngierdd3f0502019-12-24 11:10:31 +00003780 vpe->col_idx = cpu;
Marc Zyngier3171a472016-12-20 15:17:28 +00003781
Marc Zyngierdd3f0502019-12-24 11:10:31 +00003782 /*
3783 * GICv4.1 allows us to skip VMOVP if moving to a cpu whose RD
3784 * is sharing its VPE table with the current one.
3785 */
3786 if (gic_data_rdist_cpu(cpu)->vpe_table_mask &&
3787 cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask))
3788 goto out;
3789
3790 its_send_vmovp(vpe);
3791 its_vpe_db_proxy_move(vpe, from, cpu);
3792
3793out:
Marc Zyngier44c4c252017-10-19 10:11:34 +01003794 irq_data_update_effective_affinity(d, cpumask_of(cpu));
Marc Zyngierf3a059212020-03-04 20:33:10 +00003795 vpe_to_cpuid_unlock(vpe, flags);
Marc Zyngier44c4c252017-10-19 10:11:34 +01003796
Marc Zyngier3171a472016-12-20 15:17:28 +00003797 return IRQ_SET_MASK_OK_DONE;
3798}
3799
Marc Zyngier96806222020-04-10 11:13:26 +01003800static void its_wait_vpt_parse_complete(void)
3801{
3802 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
3803 u64 val;
3804
3805 if (!gic_rdists->has_vpend_valid_dirty)
3806 return;
3807
Zenghui Yu31dbb6b2020-06-05 13:23:45 +08003808 WARN_ON_ONCE(readq_relaxed_poll_timeout_atomic(vlpi_base + GICR_VPENDBASER,
3809 val,
3810 !(val & GICR_VPENDBASER_Dirty),
3811 10, 500));
Marc Zyngier96806222020-04-10 11:13:26 +01003812}
3813
Marc Zyngiere643d802016-12-20 15:09:31 +00003814static void its_vpe_schedule(struct its_vpe *vpe)
3815{
Robin Murphy50c33092018-02-16 16:57:56 +00003816 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
Marc Zyngiere643d802016-12-20 15:09:31 +00003817 u64 val;
3818
3819 /* Schedule the VPE */
3820 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
3821 GENMASK_ULL(51, 12);
3822 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
3823 val |= GICR_VPROPBASER_RaWb;
3824 val |= GICR_VPROPBASER_InnerShareable;
Zenghui Yu5186a6c2020-02-06 15:57:11 +08003825 gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);
Marc Zyngiere643d802016-12-20 15:09:31 +00003826
3827 val = virt_to_phys(page_address(vpe->vpt_page)) &
3828 GENMASK_ULL(51, 16);
3829 val |= GICR_VPENDBASER_RaWaWb;
Heyi Guob2cb11f2019-11-30 15:38:49 +08003830 val |= GICR_VPENDBASER_InnerShareable;
Marc Zyngiere643d802016-12-20 15:09:31 +00003831 /*
3832 * There is no good way of finding out if the pending table is
3833 * empty as we can race against the doorbell interrupt very
3834 * easily. So in the end, vpe->pending_last is only an
3835 * indication that the vcpu has something pending, not one
3836 * that the pending table is empty. A good implementation
3837 * would be able to read its coarse map pretty quickly anyway,
3838 * making this a tolerable issue.
3839 */
3840 val |= GICR_VPENDBASER_PendingLast;
3841 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
3842 val |= GICR_VPENDBASER_Valid;
Zenghui Yu5186a6c2020-02-06 15:57:11 +08003843 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
Marc Zyngier96806222020-04-10 11:13:26 +01003844
3845 its_wait_vpt_parse_complete();
Marc Zyngiere643d802016-12-20 15:09:31 +00003846}
3847
3848static void its_vpe_deschedule(struct its_vpe *vpe)
3849{
Robin Murphy50c33092018-02-16 16:57:56 +00003850 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
Marc Zyngiere643d802016-12-20 15:09:31 +00003851 u64 val;
3852
Marc Zyngiere64fab12019-12-24 11:10:35 +00003853 val = its_clear_vpend_valid(vlpi_base, 0, 0);
Marc Zyngiere643d802016-12-20 15:09:31 +00003854
Marc Zyngiere64fab12019-12-24 11:10:35 +00003855 vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
3856 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
Marc Zyngiere643d802016-12-20 15:09:31 +00003857}
3858
Marc Zyngier40619a22017-10-08 15:16:09 +01003859static void its_vpe_invall(struct its_vpe *vpe)
3860{
3861 struct its_node *its;
3862
3863 list_for_each_entry(its, &its_nodes, entry) {
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00003864 if (!is_v4(its))
Marc Zyngier40619a22017-10-08 15:16:09 +01003865 continue;
3866
Marc Zyngier2247e1b2017-10-08 18:50:36 +01003867 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
3868 continue;
3869
Marc Zyngier3c1ccee2017-10-09 13:17:43 +01003870 /*
3871 * Sending a VINVALL to a single ITS is enough, as all
3872 * we need is to reach the redistributors.
3873 */
Marc Zyngier40619a22017-10-08 15:16:09 +01003874 its_send_vinvall(its, vpe);
Marc Zyngier3c1ccee2017-10-09 13:17:43 +01003875 return;
Marc Zyngier40619a22017-10-08 15:16:09 +01003876 }
3877}
3878
Marc Zyngiere643d802016-12-20 15:09:31 +00003879static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
3880{
3881 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3882 struct its_cmd_info *info = vcpu_info;
3883
3884 switch (info->cmd_type) {
3885 case SCHEDULE_VPE:
3886 its_vpe_schedule(vpe);
3887 return 0;
3888
3889 case DESCHEDULE_VPE:
3890 its_vpe_deschedule(vpe);
3891 return 0;
3892
Marc Zyngier5e2f7642016-12-20 15:10:50 +00003893 case INVALL_VPE:
Marc Zyngier40619a22017-10-08 15:16:09 +01003894 its_vpe_invall(vpe);
Marc Zyngier5e2f7642016-12-20 15:10:50 +00003895 return 0;
3896
Marc Zyngiere643d802016-12-20 15:09:31 +00003897 default:
3898 return -EINVAL;
3899 }
3900}
3901
Marc Zyngier20b3d542016-12-20 15:23:22 +00003902static void its_vpe_send_cmd(struct its_vpe *vpe,
3903 void (*cmd)(struct its_device *, u32))
3904{
3905 unsigned long flags;
3906
3907 raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
3908
3909 its_vpe_db_proxy_map_locked(vpe);
3910 cmd(vpe_proxy.dev, vpe->vpe_proxy_event);
3911
3912 raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
3913}
3914
Marc Zyngierf6a91da2016-12-20 15:20:38 +00003915static void its_vpe_send_inv(struct irq_data *d)
3916{
3917 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
Marc Zyngierf6a91da2016-12-20 15:20:38 +00003918
Marc Zyngier20b3d542016-12-20 15:23:22 +00003919 if (gic_rdists->has_direct_lpi) {
3920 void __iomem *rdbase;
3921
Marc Zyngier425c09b2019-11-08 16:57:57 +00003922 /* Target the redistributor this VPE is currently known on */
Marc Zyngier9058a4e2020-03-04 20:33:12 +00003923 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
Marc Zyngier20b3d542016-12-20 15:23:22 +00003924 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
Marc Zyngier425c09b2019-11-08 16:57:57 +00003925 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR);
Marc Zyngier2f4f0642019-11-08 16:57:56 +00003926 wait_for_syncr(rdbase);
Marc Zyngier9058a4e2020-03-04 20:33:12 +00003927 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock);
Marc Zyngier20b3d542016-12-20 15:23:22 +00003928 } else {
3929 its_vpe_send_cmd(vpe, its_send_inv);
3930 }
Marc Zyngierf6a91da2016-12-20 15:20:38 +00003931}
3932
3933static void its_vpe_mask_irq(struct irq_data *d)
3934{
3935 /*
3936 * We need to unmask the LPI, which is described by the parent
3937 * irq_data. Instead of calling into the parent (which won't
3938 * exactly do the right thing, let's simply use the
3939 * parent_data pointer. Yes, I'm naughty.
3940 */
3941 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
3942 its_vpe_send_inv(d);
3943}
3944
3945static void its_vpe_unmask_irq(struct irq_data *d)
3946{
3947 /* Same hack as above... */
3948 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
3949 its_vpe_send_inv(d);
3950}
3951
Marc Zyngiere57a3e282017-07-31 14:47:24 +01003952static int its_vpe_set_irqchip_state(struct irq_data *d,
3953 enum irqchip_irq_state which,
3954 bool state)
3955{
3956 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3957
3958 if (which != IRQCHIP_STATE_PENDING)
3959 return -EINVAL;
3960
3961 if (gic_rdists->has_direct_lpi) {
3962 void __iomem *rdbase;
3963
3964 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
3965 if (state) {
3966 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
3967 } else {
3968 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
Marc Zyngier2f4f0642019-11-08 16:57:56 +00003969 wait_for_syncr(rdbase);
Marc Zyngiere57a3e282017-07-31 14:47:24 +01003970 }
3971 } else {
3972 if (state)
3973 its_vpe_send_cmd(vpe, its_send_int);
3974 else
3975 its_vpe_send_cmd(vpe, its_send_clear);
3976 }
3977
3978 return 0;
3979}
3980
Marc Zyngier7809f702020-03-10 18:49:21 +00003981static int its_vpe_retrigger(struct irq_data *d)
3982{
3983 return !its_vpe_set_irqchip_state(d, IRQCHIP_STATE_PENDING, true);
3984}
3985
Marc Zyngier8fff27a2016-12-20 13:41:55 +00003986static struct irq_chip its_vpe_irq_chip = {
3987 .name = "GICv4-vpe",
Marc Zyngierf6a91da2016-12-20 15:20:38 +00003988 .irq_mask = its_vpe_mask_irq,
3989 .irq_unmask = its_vpe_unmask_irq,
3990 .irq_eoi = irq_chip_eoi_parent,
Marc Zyngier3171a472016-12-20 15:17:28 +00003991 .irq_set_affinity = its_vpe_set_affinity,
Marc Zyngier7809f702020-03-10 18:49:21 +00003992 .irq_retrigger = its_vpe_retrigger,
Marc Zyngiere57a3e282017-07-31 14:47:24 +01003993 .irq_set_irqchip_state = its_vpe_set_irqchip_state,
Marc Zyngiere643d802016-12-20 15:09:31 +00003994 .irq_set_vcpu_affinity = its_vpe_set_vcpu_affinity,
Marc Zyngier8fff27a2016-12-20 13:41:55 +00003995};
3996
Marc Zyngierd97c97b2019-12-24 11:10:33 +00003997static struct its_node *find_4_1_its(void)
3998{
3999 static struct its_node *its = NULL;
4000
4001 if (!its) {
4002 list_for_each_entry(its, &its_nodes, entry) {
4003 if (is_v4_1(its))
4004 return its;
4005 }
4006
4007 /* Oops? */
4008 its = NULL;
4009 }
4010
4011 return its;
4012}
4013
4014static void its_vpe_4_1_send_inv(struct irq_data *d)
4015{
4016 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4017 struct its_node *its;
4018
4019 /*
4020 * GICv4.1 wants doorbells to be invalidated using the
4021 * INVDB command in order to be broadcast to all RDs. Send
4022 * it to the first valid ITS, and let the HW do its magic.
4023 */
4024 its = find_4_1_its();
4025 if (its)
4026 its_send_invdb(its, vpe);
4027}
4028
4029static void its_vpe_4_1_mask_irq(struct irq_data *d)
4030{
4031 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
4032 its_vpe_4_1_send_inv(d);
4033}
4034
4035static void its_vpe_4_1_unmask_irq(struct irq_data *d)
4036{
4037 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
4038 its_vpe_4_1_send_inv(d);
4039}
4040
Marc Zyngier91bf6392019-12-24 11:10:34 +00004041static void its_vpe_4_1_schedule(struct its_vpe *vpe,
4042 struct its_cmd_info *info)
4043{
4044 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4045 u64 val = 0;
4046
4047 /* Schedule the VPE */
4048 val |= GICR_VPENDBASER_Valid;
4049 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0;
4050 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0;
4051 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
4052
Zenghui Yu5186a6c2020-02-06 15:57:11 +08004053 gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
Marc Zyngier96806222020-04-10 11:13:26 +01004054
4055 its_wait_vpt_parse_complete();
Marc Zyngier91bf6392019-12-24 11:10:34 +00004056}
4057
Marc Zyngiere64fab12019-12-24 11:10:35 +00004058static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
4059 struct its_cmd_info *info)
4060{
4061 void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
4062 u64 val;
4063
4064 if (info->req_db) {
Marc Zyngiera3f574c2020-06-23 10:44:08 +01004065 unsigned long flags;
4066
Marc Zyngiere64fab12019-12-24 11:10:35 +00004067 /*
4068 * vPE is going to block: make the vPE non-resident with
4069 * PendingLast clear and DB set. The GIC guarantees that if
4070 * we read-back PendingLast clear, then a doorbell will be
4071 * delivered when an interrupt comes.
Marc Zyngiera3f574c2020-06-23 10:44:08 +01004072 *
4073 * Note the locking to deal with the concurrent update of
4074 * pending_last from the doorbell interrupt handler that can
4075 * run concurrently.
Marc Zyngiere64fab12019-12-24 11:10:35 +00004076 */
Marc Zyngiera3f574c2020-06-23 10:44:08 +01004077 raw_spin_lock_irqsave(&vpe->vpe_lock, flags);
Marc Zyngiere64fab12019-12-24 11:10:35 +00004078 val = its_clear_vpend_valid(vlpi_base,
4079 GICR_VPENDBASER_PendingLast,
4080 GICR_VPENDBASER_4_1_DB);
4081 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
Marc Zyngiera3f574c2020-06-23 10:44:08 +01004082 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags);
Marc Zyngiere64fab12019-12-24 11:10:35 +00004083 } else {
4084 /*
4085 * We're not blocking, so just make the vPE non-resident
4086 * with PendingLast set, indicating that we'll be back.
4087 */
4088 val = its_clear_vpend_valid(vlpi_base,
4089 0,
4090 GICR_VPENDBASER_PendingLast);
4091 vpe->pending_last = true;
4092 }
4093}
4094
Marc Zyngierb4a4bd02019-12-24 11:10:36 +00004095static void its_vpe_4_1_invall(struct its_vpe *vpe)
4096{
4097 void __iomem *rdbase;
Zenghui Yu3af95712020-07-20 17:23:28 +08004098 unsigned long flags;
Marc Zyngierb4a4bd02019-12-24 11:10:36 +00004099 u64 val;
Zenghui Yu3af95712020-07-20 17:23:28 +08004100 int cpu;
Marc Zyngierb4a4bd02019-12-24 11:10:36 +00004101
4102 val = GICR_INVALLR_V;
4103 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);
4104
4105 /* Target the redistributor this vPE is currently known on */
Zenghui Yu3af95712020-07-20 17:23:28 +08004106 cpu = vpe_to_cpuid_lock(vpe, &flags);
4107 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4108 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base;
Marc Zyngierb4a4bd02019-12-24 11:10:36 +00004109 gic_write_lpir(val, rdbase + GICR_INVALLR);
Zenghui Yub978c252020-03-04 20:33:11 +00004110
4111 wait_for_syncr(rdbase);
Zenghui Yu3af95712020-07-20 17:23:28 +08004112 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4113 vpe_to_cpuid_unlock(vpe, flags);
Marc Zyngierb4a4bd02019-12-24 11:10:36 +00004114}
4115
Marc Zyngier29c647f2019-12-24 11:10:32 +00004116static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4117{
Marc Zyngier91bf6392019-12-24 11:10:34 +00004118 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
Marc Zyngier29c647f2019-12-24 11:10:32 +00004119 struct its_cmd_info *info = vcpu_info;
4120
4121 switch (info->cmd_type) {
4122 case SCHEDULE_VPE:
Marc Zyngier91bf6392019-12-24 11:10:34 +00004123 its_vpe_4_1_schedule(vpe, info);
Marc Zyngier29c647f2019-12-24 11:10:32 +00004124 return 0;
4125
4126 case DESCHEDULE_VPE:
Marc Zyngiere64fab12019-12-24 11:10:35 +00004127 its_vpe_4_1_deschedule(vpe, info);
Marc Zyngier29c647f2019-12-24 11:10:32 +00004128 return 0;
4129
4130 case INVALL_VPE:
Marc Zyngierb4a4bd02019-12-24 11:10:36 +00004131 its_vpe_4_1_invall(vpe);
Marc Zyngier29c647f2019-12-24 11:10:32 +00004132 return 0;
4133
4134 default:
4135 return -EINVAL;
4136 }
4137}
4138
4139static struct irq_chip its_vpe_4_1_irq_chip = {
4140 .name = "GICv4.1-vpe",
Marc Zyngierd97c97b2019-12-24 11:10:33 +00004141 .irq_mask = its_vpe_4_1_mask_irq,
4142 .irq_unmask = its_vpe_4_1_unmask_irq,
Marc Zyngier29c647f2019-12-24 11:10:32 +00004143 .irq_eoi = irq_chip_eoi_parent,
4144 .irq_set_affinity = its_vpe_set_affinity,
4145 .irq_set_vcpu_affinity = its_vpe_4_1_set_vcpu_affinity,
4146};
4147
Marc Zyngiere252cf82020-03-04 20:33:16 +00004148static void its_configure_sgi(struct irq_data *d, bool clear)
4149{
4150 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4151 struct its_cmd_desc desc;
4152
4153 desc.its_vsgi_cmd.vpe = vpe;
4154 desc.its_vsgi_cmd.sgi = d->hwirq;
4155 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority;
4156 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled;
4157 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group;
4158 desc.its_vsgi_cmd.clear = clear;
4159
4160 /*
4161 * GICv4.1 allows us to send VSGI commands to any ITS as long as the
4162 * destination VPE is mapped there. Since we map them eagerly at
4163 * activation time, we're pretty sure the first GICv4.1 ITS will do.
4164 */
4165 its_send_single_vcommand(find_4_1_its(), its_build_vsgi_cmd, &desc);
4166}
4167
Marc Zyngierb4e8d642020-03-04 20:33:17 +00004168static void its_sgi_mask_irq(struct irq_data *d)
4169{
4170 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4171
4172 vpe->sgi_config[d->hwirq].enabled = false;
4173 its_configure_sgi(d, false);
4174}
4175
4176static void its_sgi_unmask_irq(struct irq_data *d)
4177{
4178 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4179
4180 vpe->sgi_config[d->hwirq].enabled = true;
4181 its_configure_sgi(d, false);
4182}
4183
Marc Zyngier166cba72020-03-04 20:33:15 +00004184static int its_sgi_set_affinity(struct irq_data *d,
4185 const struct cpumask *mask_val,
4186 bool force)
4187{
4188 /*
4189 * There is no notion of affinity for virtual SGIs, at least
4190 * not on the host (since they can only be targetting a vPE).
4191 * Tell the kernel we've done whatever it asked for.
4192 */
Marc Zyngier4b2dfe12020-04-10 12:11:39 +01004193 irq_data_update_effective_affinity(d, mask_val);
Marc Zyngier166cba72020-03-04 20:33:15 +00004194 return IRQ_SET_MASK_OK;
4195}
4196
Marc Zyngier7017ff02020-03-04 20:33:18 +00004197static int its_sgi_set_irqchip_state(struct irq_data *d,
4198 enum irqchip_irq_state which,
4199 bool state)
4200{
4201 if (which != IRQCHIP_STATE_PENDING)
4202 return -EINVAL;
4203
4204 if (state) {
4205 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4206 struct its_node *its = find_4_1_its();
4207 u64 val;
4208
4209 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id);
4210 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq);
4211 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K);
4212 } else {
4213 its_configure_sgi(d, true);
4214 }
4215
4216 return 0;
4217}
4218
4219static int its_sgi_get_irqchip_state(struct irq_data *d,
4220 enum irqchip_irq_state which, bool *val)
4221{
4222 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4223 void __iomem *base;
4224 unsigned long flags;
4225 u32 count = 1000000; /* 1s! */
4226 u32 status;
4227 int cpu;
4228
4229 if (which != IRQCHIP_STATE_PENDING)
4230 return -EINVAL;
4231
4232 /*
4233 * Locking galore! We can race against two different events:
4234 *
4235 * - Concurent vPE affinity change: we must make sure it cannot
4236 * happen, or we'll talk to the wrong redistributor. This is
4237 * identical to what happens with vLPIs.
4238 *
4239 * - Concurrent VSGIPENDR access: As it involves accessing two
4240 * MMIO registers, this must be made atomic one way or another.
4241 */
4242 cpu = vpe_to_cpuid_lock(vpe, &flags);
4243 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock);
4244 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K;
4245 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR);
4246 do {
4247 status = readl_relaxed(base + GICR_VSGIPENDR);
4248 if (!(status & GICR_VSGIPENDR_BUSY))
4249 goto out;
4250
4251 count--;
4252 if (!count) {
4253 pr_err_ratelimited("Unable to get SGI status\n");
4254 goto out;
4255 }
4256 cpu_relax();
4257 udelay(1);
4258 } while (count);
4259
4260out:
4261 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock);
4262 vpe_to_cpuid_unlock(vpe, flags);
4263
4264 if (!count)
4265 return -ENXIO;
4266
4267 *val = !!(status & (1 << d->hwirq));
4268
4269 return 0;
4270}
4271
Marc Zyngier05d32df2020-03-04 20:33:19 +00004272static int its_sgi_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
4273{
4274 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4275 struct its_cmd_info *info = vcpu_info;
4276
4277 switch (info->cmd_type) {
4278 case PROP_UPDATE_VSGI:
4279 vpe->sgi_config[d->hwirq].priority = info->priority;
4280 vpe->sgi_config[d->hwirq].group = info->group;
4281 its_configure_sgi(d, false);
4282 return 0;
4283
4284 default:
4285 return -EINVAL;
4286 }
4287}
4288
Marc Zyngier166cba72020-03-04 20:33:15 +00004289static struct irq_chip its_sgi_irq_chip = {
4290 .name = "GICv4.1-sgi",
Marc Zyngierb4e8d642020-03-04 20:33:17 +00004291 .irq_mask = its_sgi_mask_irq,
4292 .irq_unmask = its_sgi_unmask_irq,
Marc Zyngier166cba72020-03-04 20:33:15 +00004293 .irq_set_affinity = its_sgi_set_affinity,
Marc Zyngier7017ff02020-03-04 20:33:18 +00004294 .irq_set_irqchip_state = its_sgi_set_irqchip_state,
4295 .irq_get_irqchip_state = its_sgi_get_irqchip_state,
Marc Zyngier05d32df2020-03-04 20:33:19 +00004296 .irq_set_vcpu_affinity = its_sgi_set_vcpu_affinity,
Marc Zyngier166cba72020-03-04 20:33:15 +00004297};
4298
4299static int its_sgi_irq_domain_alloc(struct irq_domain *domain,
4300 unsigned int virq, unsigned int nr_irqs,
4301 void *args)
4302{
4303 struct its_vpe *vpe = args;
4304 int i;
4305
4306 /* Yes, we do want 16 SGIs */
4307 WARN_ON(nr_irqs != 16);
4308
4309 for (i = 0; i < 16; i++) {
4310 vpe->sgi_config[i].priority = 0;
4311 vpe->sgi_config[i].enabled = false;
4312 vpe->sgi_config[i].group = false;
4313
4314 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
4315 &its_sgi_irq_chip, vpe);
4316 irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY);
4317 }
4318
4319 return 0;
4320}
4321
4322static void its_sgi_irq_domain_free(struct irq_domain *domain,
4323 unsigned int virq,
4324 unsigned int nr_irqs)
4325{
4326 /* Nothing to do */
4327}
4328
4329static int its_sgi_irq_domain_activate(struct irq_domain *domain,
4330 struct irq_data *d, bool reserve)
4331{
Marc Zyngiere252cf82020-03-04 20:33:16 +00004332 /* Write out the initial SGI configuration */
4333 its_configure_sgi(d, false);
Marc Zyngier166cba72020-03-04 20:33:15 +00004334 return 0;
4335}
4336
4337static void its_sgi_irq_domain_deactivate(struct irq_domain *domain,
4338 struct irq_data *d)
4339{
Marc Zyngiere252cf82020-03-04 20:33:16 +00004340 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
4341
4342 /*
4343 * The VSGI command is awkward:
4344 *
4345 * - To change the configuration, CLEAR must be set to false,
4346 * leaving the pending bit unchanged.
4347 * - To clear the pending bit, CLEAR must be set to true, leaving
4348 * the configuration unchanged.
4349 *
4350 * You just can't do both at once, hence the two commands below.
4351 */
4352 vpe->sgi_config[d->hwirq].enabled = false;
4353 its_configure_sgi(d, false);
4354 its_configure_sgi(d, true);
Marc Zyngier166cba72020-03-04 20:33:15 +00004355}
4356
4357static const struct irq_domain_ops its_sgi_domain_ops = {
4358 .alloc = its_sgi_irq_domain_alloc,
4359 .free = its_sgi_irq_domain_free,
4360 .activate = its_sgi_irq_domain_activate,
4361 .deactivate = its_sgi_irq_domain_deactivate,
4362};
4363
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004364static int its_vpe_id_alloc(void)
4365{
Shanker Donthineni32bd44d2017-10-07 15:43:48 -05004366 return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004367}
4368
4369static void its_vpe_id_free(u16 id)
4370{
4371 ida_simple_remove(&its_vpeid_ida, id);
4372}
4373
4374static int its_vpe_init(struct its_vpe *vpe)
4375{
4376 struct page *vpt_page;
4377 int vpe_id;
4378
4379 /* Allocate vpe_id */
4380 vpe_id = its_vpe_id_alloc();
4381 if (vpe_id < 0)
4382 return vpe_id;
4383
4384 /* Allocate VPT */
4385 vpt_page = its_allocate_pending_table(GFP_KERNEL);
4386 if (!vpt_page) {
4387 its_vpe_id_free(vpe_id);
4388 return -ENOMEM;
4389 }
4390
4391 if (!its_alloc_vpe_table(vpe_id)) {
4392 its_vpe_id_free(vpe_id);
Nianyao Tang34f8eb92019-07-26 17:32:57 +08004393 its_free_pending_table(vpt_page);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004394 return -ENOMEM;
4395 }
4396
Marc Zyngierf3a059212020-03-04 20:33:10 +00004397 raw_spin_lock_init(&vpe->vpe_lock);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004398 vpe->vpe_id = vpe_id;
4399 vpe->vpt_page = vpt_page;
Marc Zyngier64edfaa2019-12-24 11:10:29 +00004400 if (gic_rdists->has_rvpeid)
4401 atomic_set(&vpe->vmapp_count, 0);
4402 else
4403 vpe->vpe_proxy_event = -1;
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004404
4405 return 0;
4406}
4407
4408static void its_vpe_teardown(struct its_vpe *vpe)
4409{
Marc Zyngier20b3d542016-12-20 15:23:22 +00004410 its_vpe_db_proxy_unmap(vpe);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004411 its_vpe_id_free(vpe->vpe_id);
4412 its_free_pending_table(vpe->vpt_page);
4413}
4414
4415static void its_vpe_irq_domain_free(struct irq_domain *domain,
4416 unsigned int virq,
4417 unsigned int nr_irqs)
4418{
4419 struct its_vm *vm = domain->host_data;
4420 int i;
4421
4422 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
4423
4424 for (i = 0; i < nr_irqs; i++) {
4425 struct irq_data *data = irq_domain_get_irq_data(domain,
4426 virq + i);
4427 struct its_vpe *vpe = irq_data_get_irq_chip_data(data);
4428
4429 BUG_ON(vm != vpe->its_vm);
4430
4431 clear_bit(data->hwirq, vm->db_bitmap);
4432 its_vpe_teardown(vpe);
4433 irq_domain_reset_irq_data(data);
4434 }
4435
4436 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
Marc Zyngier38dd7c42018-05-27 17:03:03 +01004437 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004438 its_free_prop_table(vm->vprop_page);
4439 }
4440}
4441
4442static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
4443 unsigned int nr_irqs, void *args)
4444{
Marc Zyngier29c647f2019-12-24 11:10:32 +00004445 struct irq_chip *irqchip = &its_vpe_irq_chip;
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004446 struct its_vm *vm = args;
4447 unsigned long *bitmap;
4448 struct page *vprop_page;
4449 int base, nr_ids, i, err = 0;
4450
4451 BUG_ON(!vm);
4452
Marc Zyngier38dd7c42018-05-27 17:03:03 +01004453 bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004454 if (!bitmap)
4455 return -ENOMEM;
4456
4457 if (nr_ids < nr_irqs) {
Marc Zyngier38dd7c42018-05-27 17:03:03 +01004458 its_lpi_free(bitmap, base, nr_ids);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004459 return -ENOMEM;
4460 }
4461
4462 vprop_page = its_allocate_prop_table(GFP_KERNEL);
4463 if (!vprop_page) {
Marc Zyngier38dd7c42018-05-27 17:03:03 +01004464 its_lpi_free(bitmap, base, nr_ids);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004465 return -ENOMEM;
4466 }
4467
4468 vm->db_bitmap = bitmap;
4469 vm->db_lpi_base = base;
4470 vm->nr_db_lpis = nr_ids;
4471 vm->vprop_page = vprop_page;
4472
Marc Zyngier29c647f2019-12-24 11:10:32 +00004473 if (gic_rdists->has_rvpeid)
4474 irqchip = &its_vpe_4_1_irq_chip;
4475
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004476 for (i = 0; i < nr_irqs; i++) {
4477 vm->vpes[i]->vpe_db_lpi = base + i;
4478 err = its_vpe_init(vm->vpes[i]);
4479 if (err)
4480 break;
4481 err = its_irq_gic_domain_alloc(domain, virq + i,
4482 vm->vpes[i]->vpe_db_lpi);
4483 if (err)
4484 break;
4485 irq_domain_set_hwirq_and_chip(domain, virq + i, i,
Marc Zyngier29c647f2019-12-24 11:10:32 +00004486 irqchip, vm->vpes[i]);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004487 set_bit(i, bitmap);
4488 }
4489
4490 if (err) {
4491 if (i > 0)
4492 its_vpe_irq_domain_free(domain, virq, i - 1);
4493
Marc Zyngier38dd7c42018-05-27 17:03:03 +01004494 its_lpi_free(bitmap, base, nr_ids);
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004495 its_free_prop_table(vprop_page);
4496 }
4497
4498 return err;
4499}
4500
Thomas Gleixner72491642017-09-13 23:29:10 +02004501static int its_vpe_irq_domain_activate(struct irq_domain *domain,
Thomas Gleixner702cb0a2017-12-29 16:59:06 +01004502 struct irq_data *d, bool reserve)
Marc Zyngiereb781922016-12-20 14:47:05 +00004503{
4504 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
Marc Zyngier40619a22017-10-08 15:16:09 +01004505 struct its_node *its;
Marc Zyngiereb781922016-12-20 14:47:05 +00004506
Marc Zyngier009384b2020-03-04 20:33:23 +00004507 /*
4508 * If we use the list map, we issue VMAPP on demand... Unless
4509 * we're on a GICv4.1 and we eagerly map the VPE on all ITSs
4510 * so that VSGIs can work.
4511 */
4512 if (!gic_requires_eager_mapping())
Marc Zyngier6ef930f2017-11-07 10:04:38 +00004513 return 0;
Marc Zyngiereb781922016-12-20 14:47:05 +00004514
4515 /* Map the VPE to the first possible CPU */
4516 vpe->col_idx = cpumask_first(cpu_online_mask);
Marc Zyngier40619a22017-10-08 15:16:09 +01004517
4518 list_for_each_entry(its, &its_nodes, entry) {
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00004519 if (!is_v4(its))
Marc Zyngier40619a22017-10-08 15:16:09 +01004520 continue;
4521
Marc Zyngier75fd9512017-10-08 18:46:39 +01004522 its_send_vmapp(its, vpe, true);
Marc Zyngier40619a22017-10-08 15:16:09 +01004523 its_send_vinvall(its, vpe);
4524 }
4525
Marc Zyngier44c4c252017-10-19 10:11:34 +01004526 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
4527
Thomas Gleixner72491642017-09-13 23:29:10 +02004528 return 0;
Marc Zyngiereb781922016-12-20 14:47:05 +00004529}
4530
4531static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
4532 struct irq_data *d)
4533{
4534 struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
Marc Zyngier75fd9512017-10-08 18:46:39 +01004535 struct its_node *its;
Marc Zyngiereb781922016-12-20 14:47:05 +00004536
Marc Zyngier2247e1b2017-10-08 18:50:36 +01004537 /*
Marc Zyngier009384b2020-03-04 20:33:23 +00004538 * If we use the list map on GICv4.0, we unmap the VPE once no
4539 * VLPIs are associated with the VM.
Marc Zyngier2247e1b2017-10-08 18:50:36 +01004540 */
Marc Zyngier009384b2020-03-04 20:33:23 +00004541 if (!gic_requires_eager_mapping())
Marc Zyngier2247e1b2017-10-08 18:50:36 +01004542 return;
4543
Marc Zyngier75fd9512017-10-08 18:46:39 +01004544 list_for_each_entry(its, &its_nodes, entry) {
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00004545 if (!is_v4(its))
Marc Zyngier75fd9512017-10-08 18:46:39 +01004546 continue;
4547
4548 its_send_vmapp(its, vpe, false);
4549 }
Marc Zyngiereb781922016-12-20 14:47:05 +00004550}
4551
Marc Zyngier8fff27a2016-12-20 13:41:55 +00004552static const struct irq_domain_ops its_vpe_domain_ops = {
Marc Zyngier7d75bbb2016-12-20 13:55:54 +00004553 .alloc = its_vpe_irq_domain_alloc,
4554 .free = its_vpe_irq_domain_free,
Marc Zyngiereb781922016-12-20 14:47:05 +00004555 .activate = its_vpe_irq_domain_activate,
4556 .deactivate = its_vpe_irq_domain_deactivate,
Marc Zyngier8fff27a2016-12-20 13:41:55 +00004557};
4558
Yun Wu4559fbb2015-03-06 16:37:50 +00004559static int its_force_quiescent(void __iomem *base)
4560{
4561 u32 count = 1000000; /* 1s */
4562 u32 val;
4563
4564 val = readl_relaxed(base + GITS_CTLR);
David Daney7611da82016-08-18 15:41:58 -07004565 /*
4566 * GIC architecture specification requires the ITS to be both
4567 * disabled and quiescent for writes to GITS_BASER<n> or
4568 * GITS_CBASER to not have UNPREDICTABLE results.
4569 */
4570 if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
Yun Wu4559fbb2015-03-06 16:37:50 +00004571 return 0;
4572
4573 /* Disable the generation of all interrupts to this ITS */
Marc Zyngierd51c4b42017-06-27 21:24:25 +01004574 val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
Yun Wu4559fbb2015-03-06 16:37:50 +00004575 writel_relaxed(val, base + GITS_CTLR);
4576
4577 /* Poll GITS_CTLR and wait until ITS becomes quiescent */
4578 while (1) {
4579 val = readl_relaxed(base + GITS_CTLR);
4580 if (val & GITS_CTLR_QUIESCENT)
4581 return 0;
4582
4583 count--;
4584 if (!count)
4585 return -EBUSY;
4586
4587 cpu_relax();
4588 udelay(1);
4589 }
4590}
4591
Ard Biesheuvel9d111d42017-10-17 17:55:55 +01004592static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
Robert Richter94100972015-09-21 22:58:38 +02004593{
4594 struct its_node *its = data;
4595
Marc Zyngier576a8342019-11-08 16:58:00 +00004596 /* erratum 22375: only alloc 8MB table size (20 bits) */
4597 its->typer &= ~GITS_TYPER_DEVBITS;
4598 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1);
Robert Richter94100972015-09-21 22:58:38 +02004599 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
Ard Biesheuvel9d111d42017-10-17 17:55:55 +01004600
4601 return true;
Robert Richter94100972015-09-21 22:58:38 +02004602}
4603
Ard Biesheuvel9d111d42017-10-17 17:55:55 +01004604static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +02004605{
4606 struct its_node *its = data;
4607
4608 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
Ard Biesheuvel9d111d42017-10-17 17:55:55 +01004609
4610 return true;
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +02004611}
4612
Ard Biesheuvel9d111d42017-10-17 17:55:55 +01004613static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
Shanker Donthineni90922a22017-03-07 08:20:38 -06004614{
4615 struct its_node *its = data;
4616
4617 /* On QDF2400, the size of the ITE is 16Bytes */
Marc Zyngierffedbf02019-11-08 16:57:59 +00004618 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE;
4619 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1);
Ard Biesheuvel9d111d42017-10-17 17:55:55 +01004620
4621 return true;
Shanker Donthineni90922a22017-03-07 08:20:38 -06004622}
4623
Ard Biesheuvel558b0162017-10-17 17:55:56 +01004624static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
4625{
4626 struct its_node *its = its_dev->its;
4627
4628 /*
4629 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
4630 * which maps 32-bit writes targeted at a separate window of
4631 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
4632 * with device ID taken from bits [device_id_bits + 1:2] of
4633 * the window offset.
4634 */
4635 return its->pre_its_base + (its_dev->device_id << 2);
4636}
4637
4638static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
4639{
4640 struct its_node *its = data;
4641 u32 pre_its_window[2];
4642 u32 ids;
4643
4644 if (!fwnode_property_read_u32_array(its->fwnode_handle,
4645 "socionext,synquacer-pre-its",
4646 pre_its_window,
4647 ARRAY_SIZE(pre_its_window))) {
4648
4649 its->pre_its_base = pre_its_window[0];
4650 its->get_msi_base = its_irq_get_msi_base_pre_its;
4651
4652 ids = ilog2(pre_its_window[1]) - 2;
Marc Zyngier576a8342019-11-08 16:58:00 +00004653 if (device_ids(its) > ids) {
4654 its->typer &= ~GITS_TYPER_DEVBITS;
4655 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1);
4656 }
Ard Biesheuvel558b0162017-10-17 17:55:56 +01004657
4658 /* the pre-ITS breaks isolation, so disable MSI remapping */
4659 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
4660 return true;
4661 }
4662 return false;
4663}
4664
Marc Zyngier5c9a8822017-07-28 21:20:37 +01004665static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
4666{
4667 struct its_node *its = data;
4668
4669 /*
4670 * Hip07 insists on using the wrong address for the VLPI
4671 * page. Trick it into doing the right thing...
4672 */
4673 its->vlpi_redist_offset = SZ_128K;
4674 return true;
Marc Zyngiercc2d3212014-11-24 14:35:11 +00004675}
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004676
Robert Richter67510cc2015-09-21 22:58:37 +02004677static const struct gic_quirk its_quirks[] = {
Robert Richter94100972015-09-21 22:58:38 +02004678#ifdef CONFIG_CAVIUM_ERRATUM_22375
4679 {
4680 .desc = "ITS: Cavium errata 22375, 24313",
4681 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4682 .mask = 0xffff0fff,
4683 .init = its_enable_quirk_cavium_22375,
4684 },
4685#endif
Ganapatrao Kulkarnifbf8f402016-05-25 15:29:20 +02004686#ifdef CONFIG_CAVIUM_ERRATUM_23144
4687 {
4688 .desc = "ITS: Cavium erratum 23144",
4689 .iidr = 0xa100034c, /* ThunderX pass 1.x */
4690 .mask = 0xffff0fff,
4691 .init = its_enable_quirk_cavium_23144,
4692 },
4693#endif
Shanker Donthineni90922a22017-03-07 08:20:38 -06004694#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
4695 {
4696 .desc = "ITS: QDF2400 erratum 0065",
4697 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4698 .mask = 0xffffffff,
4699 .init = its_enable_quirk_qdf2400_e0065,
4700 },
4701#endif
Ard Biesheuvel558b0162017-10-17 17:55:56 +01004702#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
4703 {
4704 /*
4705 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4706 * implementation, but with a 'pre-ITS' added that requires
4707 * special handling in software.
4708 */
4709 .desc = "ITS: Socionext Synquacer pre-ITS",
4710 .iidr = 0x0001143b,
4711 .mask = 0xffffffff,
4712 .init = its_enable_quirk_socionext_synquacer,
4713 },
4714#endif
Marc Zyngier5c9a8822017-07-28 21:20:37 +01004715#ifdef CONFIG_HISILICON_ERRATUM_161600802
4716 {
4717 .desc = "ITS: Hip07 erratum 161600802",
4718 .iidr = 0x00000004,
4719 .mask = 0xffffffff,
4720 .init = its_enable_quirk_hip07_161600802,
4721 },
4722#endif
Robert Richter67510cc2015-09-21 22:58:37 +02004723 {
4724 }
4725};
4726
4727static void its_enable_quirks(struct its_node *its)
4728{
4729 u32 iidr = readl_relaxed(its->base + GITS_IIDR);
4730
4731 gic_enable_quirks(iidr, its_quirks, its);
4732}
4733
Derek Basehoredba0bc72018-02-28 21:48:18 -08004734static int its_save_disable(void)
4735{
4736 struct its_node *its;
4737 int err = 0;
4738
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02004739 raw_spin_lock(&its_lock);
Derek Basehoredba0bc72018-02-28 21:48:18 -08004740 list_for_each_entry(its, &its_nodes, entry) {
4741 void __iomem *base;
4742
Derek Basehoredba0bc72018-02-28 21:48:18 -08004743 base = its->base;
4744 its->ctlr_save = readl_relaxed(base + GITS_CTLR);
4745 err = its_force_quiescent(base);
4746 if (err) {
4747 pr_err("ITS@%pa: failed to quiesce: %d\n",
4748 &its->phys_base, err);
4749 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4750 goto err;
4751 }
4752
4753 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
4754 }
4755
4756err:
4757 if (err) {
4758 list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
4759 void __iomem *base;
4760
Derek Basehoredba0bc72018-02-28 21:48:18 -08004761 base = its->base;
4762 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
4763 }
4764 }
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02004765 raw_spin_unlock(&its_lock);
Derek Basehoredba0bc72018-02-28 21:48:18 -08004766
4767 return err;
4768}
4769
4770static void its_restore_enable(void)
4771{
4772 struct its_node *its;
4773 int ret;
4774
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02004775 raw_spin_lock(&its_lock);
Derek Basehoredba0bc72018-02-28 21:48:18 -08004776 list_for_each_entry(its, &its_nodes, entry) {
4777 void __iomem *base;
4778 int i;
4779
Derek Basehoredba0bc72018-02-28 21:48:18 -08004780 base = its->base;
4781
4782 /*
4783 * Make sure that the ITS is disabled. If it fails to quiesce,
4784 * don't restore it since writing to CBASER or BASER<n>
4785 * registers is undefined according to the GIC v3 ITS
4786 * Specification.
Xu Qiang74cde1a2020-11-07 10:42:26 +00004787 *
4788 * Firmware resuming with the ITS enabled is terminally broken.
Derek Basehoredba0bc72018-02-28 21:48:18 -08004789 */
Xu Qiang74cde1a2020-11-07 10:42:26 +00004790 WARN_ON(readl_relaxed(base + GITS_CTLR) & GITS_CTLR_ENABLE);
Derek Basehoredba0bc72018-02-28 21:48:18 -08004791 ret = its_force_quiescent(base);
4792 if (ret) {
4793 pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
4794 &its->phys_base, ret);
4795 continue;
4796 }
4797
4798 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);
4799
4800 /*
4801 * Writing CBASER resets CREADR to 0, so make CWRITER and
4802 * cmd_write line up with it.
4803 */
4804 its->cmd_write = its->cmd_base;
4805 gits_write_cwriter(0, base + GITS_CWRITER);
4806
4807 /* Restore GITS_BASER from the value cache. */
4808 for (i = 0; i < GITS_BASER_NR_REGS; i++) {
4809 struct its_baser *baser = &its->tables[i];
4810
4811 if (!(baser->val & GITS_BASER_VALID))
4812 continue;
4813
4814 its_write_baser(its, baser, baser->val);
4815 }
4816 writel_relaxed(its->ctlr_save, base + GITS_CTLR);
Derek Basehore920181c2018-02-28 21:48:20 -08004817
4818 /*
4819 * Reinit the collection if it's stored in the ITS. This is
4820 * indicated by the col_id being less than the HCC field.
4821 * CID < HCC as specified in the GIC v3 Documentation.
4822 */
4823 if (its->collections[smp_processor_id()].col_id <
4824 GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
4825 its_cpu_init_collection(its);
Derek Basehoredba0bc72018-02-28 21:48:18 -08004826 }
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02004827 raw_spin_unlock(&its_lock);
Derek Basehoredba0bc72018-02-28 21:48:18 -08004828}
4829
4830static struct syscore_ops its_syscore_ops = {
4831 .suspend = its_save_disable,
4832 .resume = its_restore_enable,
4833};
4834
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004835static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
Tomasz Nowickid14ae5e2016-09-12 20:32:23 +02004836{
4837 struct irq_domain *inner_domain;
4838 struct msi_domain_info *info;
4839
4840 info = kzalloc(sizeof(*info), GFP_KERNEL);
4841 if (!info)
4842 return -ENOMEM;
4843
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004844 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
Tomasz Nowickid14ae5e2016-09-12 20:32:23 +02004845 if (!inner_domain) {
4846 kfree(info);
4847 return -ENOMEM;
4848 }
4849
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004850 inner_domain->parent = its_parent;
Marc Zyngier96f0d932017-06-22 11:42:50 +01004851 irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
Ard Biesheuvel558b0162017-10-17 17:55:56 +01004852 inner_domain->flags |= its->msi_domain_flags;
Tomasz Nowickid14ae5e2016-09-12 20:32:23 +02004853 info->ops = &its_msi_domain_ops;
4854 info->data = its;
4855 inner_domain->host_data = info;
4856
4857 return 0;
4858}
4859
Marc Zyngier8fff27a2016-12-20 13:41:55 +00004860static int its_init_vpe_domain(void)
4861{
Marc Zyngier20b3d542016-12-20 15:23:22 +00004862 struct its_node *its;
4863 u32 devid;
4864 int entries;
4865
4866 if (gic_rdists->has_direct_lpi) {
4867 pr_info("ITS: Using DirectLPI for VPE invalidation\n");
4868 return 0;
4869 }
4870
4871 /* Any ITS will do, even if not v4 */
4872 its = list_first_entry(&its_nodes, struct its_node, entry);
4873
4874 entries = roundup_pow_of_two(nr_cpu_ids);
Kees Cook6396bb22018-06-12 14:03:40 -07004875 vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
Marc Zyngier20b3d542016-12-20 15:23:22 +00004876 GFP_KERNEL);
4877 if (!vpe_proxy.vpes) {
4878 pr_err("ITS: Can't allocate GICv4 proxy device array\n");
4879 return -ENOMEM;
4880 }
4881
4882 /* Use the last possible DevID */
Marc Zyngier576a8342019-11-08 16:58:00 +00004883 devid = GENMASK(device_ids(its) - 1, 0);
Marc Zyngier20b3d542016-12-20 15:23:22 +00004884 vpe_proxy.dev = its_create_device(its, devid, entries, false);
4885 if (!vpe_proxy.dev) {
4886 kfree(vpe_proxy.vpes);
4887 pr_err("ITS: Can't allocate GICv4 proxy device\n");
4888 return -ENOMEM;
4889 }
4890
Shanker Donthinenic427a472017-09-23 13:50:19 -05004891 BUG_ON(entries > vpe_proxy.dev->nr_ites);
Marc Zyngier20b3d542016-12-20 15:23:22 +00004892
4893 raw_spin_lock_init(&vpe_proxy.lock);
4894 vpe_proxy.next_victim = 0;
4895 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
4896 devid, vpe_proxy.dev->nr_ites);
4897
Marc Zyngier8fff27a2016-12-20 13:41:55 +00004898 return 0;
4899}
4900
Marc Zyngier3dfa5762016-12-19 17:25:54 +00004901static int __init its_compute_its_list_map(struct resource *res,
4902 void __iomem *its_base)
4903{
4904 int its_number;
4905 u32 ctlr;
4906
4907 /*
4908 * This is assumed to be done early enough that we're
4909 * guaranteed to be single-threaded, hence no
4910 * locking. Should this change, we should address
4911 * this.
4912 */
Marc Zyngierab604912017-10-08 18:48:06 +01004913 its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
4914 if (its_number >= GICv4_ITS_LIST_MAX) {
Marc Zyngier3dfa5762016-12-19 17:25:54 +00004915 pr_err("ITS@%pa: No ITSList entry available!\n",
4916 &res->start);
4917 return -EINVAL;
4918 }
4919
4920 ctlr = readl_relaxed(its_base + GITS_CTLR);
4921 ctlr &= ~GITS_CTLR_ITS_NUMBER;
4922 ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
4923 writel_relaxed(ctlr, its_base + GITS_CTLR);
4924 ctlr = readl_relaxed(its_base + GITS_CTLR);
4925 if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
4926 its_number = ctlr & GITS_CTLR_ITS_NUMBER;
4927 its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
4928 }
4929
4930 if (test_and_set_bit(its_number, &its_list_map)) {
4931 pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
4932 &res->start, its_number);
4933 return -EINVAL;
4934 }
4935
4936 return its_number;
4937}
4938
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004939static int __init its_probe_one(struct resource *res,
4940 struct fwnode_handle *handle, int numa_node)
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004941{
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004942 struct its_node *its;
4943 void __iomem *its_base;
Marc Zyngier3dfa5762016-12-19 17:25:54 +00004944 u32 val, ctlr;
4945 u64 baser, tmp, typer;
Shanker Donthineni539d3782019-01-14 09:50:19 +00004946 struct page *page;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004947 int err;
4948
Marc Zyngier5e46a482020-03-04 20:33:14 +00004949 its_base = ioremap(res->start, SZ_64K);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004950 if (!its_base) {
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004951 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004952 return -ENOMEM;
4953 }
4954
4955 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
4956 if (val != 0x30 && val != 0x40) {
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004957 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004958 err = -ENODEV;
4959 goto out_unmap;
4960 }
4961
Yun Wu4559fbb2015-03-06 16:37:50 +00004962 err = its_force_quiescent(its_base);
4963 if (err) {
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004964 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
Yun Wu4559fbb2015-03-06 16:37:50 +00004965 goto out_unmap;
4966 }
4967
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004968 pr_info("ITS %pR\n", res);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004969
4970 its = kzalloc(sizeof(*its), GFP_KERNEL);
4971 if (!its) {
4972 err = -ENOMEM;
4973 goto out_unmap;
4974 }
4975
4976 raw_spin_lock_init(&its->lock);
Marc Zyngier9791ec72019-01-29 10:02:33 +00004977 mutex_init(&its->dev_alloc_lock);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004978 INIT_LIST_HEAD(&its->entry);
4979 INIT_LIST_HEAD(&its->its_device_list);
Marc Zyngier3dfa5762016-12-19 17:25:54 +00004980 typer = gic_read_typer(its_base + GITS_TYPER);
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00004981 its->typer = typer;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00004982 its->base = its_base;
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02004983 its->phys_base = res->start;
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00004984 if (is_v4(its)) {
Marc Zyngier3dfa5762016-12-19 17:25:54 +00004985 if (!(typer & GITS_TYPER_VMOVP)) {
4986 err = its_compute_its_list_map(res, its_base);
4987 if (err < 0)
4988 goto out_free_its;
4989
Marc Zyngierdebf6d02017-10-08 18:44:42 +01004990 its->list_nr = err;
4991
Marc Zyngier3dfa5762016-12-19 17:25:54 +00004992 pr_info("ITS@%pa: Using ITS number %d\n",
4993 &res->start, err);
4994 } else {
4995 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
4996 }
Marc Zyngier5e516842019-12-24 11:10:28 +00004997
4998 if (is_v4_1(its)) {
4999 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, typer);
Marc Zyngier5e46a482020-03-04 20:33:14 +00005000
5001 its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K);
5002 if (!its->sgir_base) {
5003 err = -ENOMEM;
5004 goto out_free_its;
5005 }
5006
Marc Zyngier5e516842019-12-24 11:10:28 +00005007 its->mpidr = readl_relaxed(its_base + GITS_MPIDR);
5008
5009 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n",
5010 &res->start, its->mpidr, svpet);
5011 }
Marc Zyngier3dfa5762016-12-19 17:25:54 +00005012 }
5013
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005014 its->numa_node = numa_node;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005015
Shanker Donthineni539d3782019-01-14 09:50:19 +00005016 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
5017 get_order(ITS_CMD_QUEUE_SZ));
5018 if (!page) {
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005019 err = -ENOMEM;
Marc Zyngier5e46a482020-03-04 20:33:14 +00005020 goto out_unmap_sgir;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005021 }
Shanker Donthineni539d3782019-01-14 09:50:19 +00005022 its->cmd_base = (void *)page_address(page);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005023 its->cmd_write = its->cmd_base;
Ard Biesheuvel558b0162017-10-17 17:55:56 +01005024 its->fwnode_handle = handle;
5025 its->get_msi_base = its_irq_get_msi_base;
5026 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005027
Robert Richter67510cc2015-09-21 22:58:37 +02005028 its_enable_quirks(its);
5029
Shanker Donthineni0e0b0f62016-06-06 18:17:31 -05005030 err = its_alloc_tables(its);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005031 if (err)
5032 goto out_free_cmd;
5033
5034 err = its_alloc_collections(its);
5035 if (err)
5036 goto out_free_tables;
5037
5038 baser = (virt_to_phys(its->cmd_base) |
Shanker Donthineni2fd632a2017-01-25 21:51:41 -06005039 GITS_CBASER_RaWaWb |
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005040 GITS_CBASER_InnerShareable |
5041 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
5042 GITS_CBASER_VALID);
5043
Vladimir Murzin0968a612016-11-02 11:54:06 +00005044 gits_write_cbaser(baser, its->base + GITS_CBASER);
5045 tmp = gits_read_cbaser(its->base + GITS_CBASER);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005046
Marc Zyngier4ad3e362015-03-27 14:15:04 +00005047 if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
Marc Zyngier241a3862015-03-27 14:15:05 +00005048 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
5049 /*
5050 * The HW reports non-shareable, we must
5051 * remove the cacheability attributes as
5052 * well.
5053 */
5054 baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
5055 GITS_CBASER_CACHEABILITY_MASK);
5056 baser |= GITS_CBASER_nC;
Vladimir Murzin0968a612016-11-02 11:54:06 +00005057 gits_write_cbaser(baser, its->base + GITS_CBASER);
Marc Zyngier241a3862015-03-27 14:15:05 +00005058 }
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005059 pr_info("ITS: using cache flushing for cmd queue\n");
5060 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
5061 }
5062
Vladimir Murzin0968a612016-11-02 11:54:06 +00005063 gits_write_cwriter(0, its->base + GITS_CWRITER);
Marc Zyngier3dfa5762016-12-19 17:25:54 +00005064 ctlr = readl_relaxed(its->base + GITS_CTLR);
Marc Zyngierd51c4b42017-06-27 21:24:25 +01005065 ctlr |= GITS_CTLR_ENABLE;
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00005066 if (is_v4(its))
Marc Zyngierd51c4b42017-06-27 21:24:25 +01005067 ctlr |= GITS_CTLR_ImDe;
5068 writel_relaxed(ctlr, its->base + GITS_CTLR);
Marc Zyngier241a3862015-03-27 14:15:05 +00005069
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005070 err = its_init_domain(handle, its);
Tomasz Nowickid14ae5e2016-09-12 20:32:23 +02005071 if (err)
5072 goto out_free_tables;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005073
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02005074 raw_spin_lock(&its_lock);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005075 list_add(&its->entry, &its_nodes);
Sebastian Andrzej Siewiora8db7452018-07-18 17:42:04 +02005076 raw_spin_unlock(&its_lock);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005077
5078 return 0;
5079
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005080out_free_tables:
5081 its_free_tables(its);
5082out_free_cmd:
Robert Richter5bc13c22017-02-01 18:38:25 +01005083 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
Marc Zyngier5e46a482020-03-04 20:33:14 +00005084out_unmap_sgir:
5085 if (its->sgir_base)
5086 iounmap(its->sgir_base);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005087out_free_its:
5088 kfree(its);
5089out_unmap:
5090 iounmap(its_base);
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005091 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005092 return err;
5093}
5094
5095static bool gic_rdists_supports_plpis(void)
5096{
Marc Zyngier589ce5f2016-10-14 15:13:07 +01005097 return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005098}
5099
Shanker Donthineni6eb486b2018-03-21 20:58:49 -05005100static int redist_disable_lpis(void)
5101{
5102 void __iomem *rbase = gic_data_rdist_rd_base();
5103 u64 timeout = USEC_PER_SEC;
5104 u64 val;
5105
5106 if (!gic_rdists_supports_plpis()) {
5107 pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
5108 return -ENXIO;
5109 }
5110
5111 val = readl_relaxed(rbase + GICR_CTLR);
5112 if (!(val & GICR_CTLR_ENABLE_LPIS))
5113 return 0;
5114
Marc Zyngier11e37d32018-07-27 13:38:54 +01005115 /*
5116 * If coming via a CPU hotplug event, we don't need to disable
5117 * LPIs before trying to re-enable them. They are already
5118 * configured and all is well in the world.
Marc Zyngierc440a9d2018-07-27 15:40:13 +01005119 *
5120 * If running with preallocated tables, there is nothing to do.
Marc Zyngier11e37d32018-07-27 13:38:54 +01005121 */
Marc Zyngierc440a9d2018-07-27 15:40:13 +01005122 if (gic_data_rdist()->lpi_enabled ||
5123 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED))
Marc Zyngier11e37d32018-07-27 13:38:54 +01005124 return 0;
5125
5126 /*
5127 * From that point on, we only try to do some damage control.
5128 */
5129 pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
Shanker Donthineni6eb486b2018-03-21 20:58:49 -05005130 smp_processor_id());
5131 add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
5132
5133 /* Disable LPIs */
5134 val &= ~GICR_CTLR_ENABLE_LPIS;
5135 writel_relaxed(val, rbase + GICR_CTLR);
5136
5137 /* Make sure any change to GICR_CTLR is observable by the GIC */
5138 dsb(sy);
5139
5140 /*
5141 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
5142 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
5143 * Error out if we time out waiting for RWP to clear.
5144 */
5145 while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
5146 if (!timeout) {
5147 pr_err("CPU%d: Timeout while disabling LPIs\n",
5148 smp_processor_id());
5149 return -ETIMEDOUT;
5150 }
5151 udelay(1);
5152 timeout--;
5153 }
5154
5155 /*
5156 * After it has been written to 1, it is IMPLEMENTATION
5157 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
5158 * cleared to 0. Error out if clearing the bit failed.
5159 */
5160 if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
5161 pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
5162 return -EBUSY;
5163 }
5164
5165 return 0;
5166}
5167
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005168int its_cpu_init(void)
5169{
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005170 if (!list_empty(&its_nodes)) {
Shanker Donthineni6eb486b2018-03-21 20:58:49 -05005171 int ret;
5172
5173 ret = redist_disable_lpis();
5174 if (ret)
5175 return ret;
5176
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005177 its_cpu_init_lpis();
Derek Basehore920181c2018-02-28 21:48:20 -08005178 its_cpu_init_collections();
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005179 }
5180
5181 return 0;
5182}
5183
Arvind Yadav935bba72017-06-22 16:05:30 +05305184static const struct of_device_id its_device_id[] = {
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005185 { .compatible = "arm,gic-v3-its", },
5186 {},
5187};
5188
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005189static int __init its_of_probe(struct device_node *node)
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005190{
5191 struct device_node *np;
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005192 struct resource res;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005193
5194 for (np = of_find_matching_node(node, its_device_id); np;
5195 np = of_find_matching_node(np, its_device_id)) {
Stephen Boyd95a25622018-02-01 09:03:29 -08005196 if (!of_device_is_available(np))
5197 continue;
Tomasz Nowickid14ae5e2016-09-12 20:32:23 +02005198 if (!of_property_read_bool(np, "msi-controller")) {
Rob Herringe81f54c2017-07-18 16:43:10 -05005199 pr_warn("%pOF: no msi-controller property, ITS ignored\n",
5200 np);
Tomasz Nowickid14ae5e2016-09-12 20:32:23 +02005201 continue;
5202 }
5203
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005204 if (of_address_to_resource(np, 0, &res)) {
Rob Herringe81f54c2017-07-18 16:43:10 -05005205 pr_warn("%pOF: no regs?\n", np);
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005206 continue;
5207 }
5208
5209 its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005210 }
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005211 return 0;
5212}
5213
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005214#ifdef CONFIG_ACPI
5215
5216#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)
5217
Robert Richterd1ce2632017-07-12 15:25:09 +02005218#ifdef CONFIG_ACPI_NUMA
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305219struct its_srat_map {
5220 /* numa node id */
5221 u32 numa_node;
5222 /* GIC ITS ID */
5223 u32 its_id;
5224};
5225
Hanjun Guofdf6e7a2017-07-26 18:15:49 +08005226static struct its_srat_map *its_srat_maps __initdata;
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305227static int its_in_srat __initdata;
5228
5229static int __init acpi_get_its_numa_node(u32 its_id)
5230{
5231 int i;
5232
5233 for (i = 0; i < its_in_srat; i++) {
5234 if (its_id == its_srat_maps[i].its_id)
5235 return its_srat_maps[i].numa_node;
5236 }
5237 return NUMA_NO_NODE;
5238}
5239
Keith Busch60574d12019-03-11 14:55:57 -06005240static int __init gic_acpi_match_srat_its(union acpi_subtable_headers *header,
Hanjun Guofdf6e7a2017-07-26 18:15:49 +08005241 const unsigned long end)
5242{
5243 return 0;
5244}
5245
Keith Busch60574d12019-03-11 14:55:57 -06005246static int __init gic_acpi_parse_srat_its(union acpi_subtable_headers *header,
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305247 const unsigned long end)
5248{
5249 int node;
5250 struct acpi_srat_gic_its_affinity *its_affinity;
5251
5252 its_affinity = (struct acpi_srat_gic_its_affinity *)header;
5253 if (!its_affinity)
5254 return -EINVAL;
5255
5256 if (its_affinity->header.length < sizeof(*its_affinity)) {
5257 pr_err("SRAT: Invalid header length %d in ITS affinity\n",
5258 its_affinity->header.length);
5259 return -EINVAL;
5260 }
5261
Jonathan Cameron95ac5bf2020-08-18 22:24:30 +08005262 /*
5263 * Note that in theory a new proximity node could be created by this
5264 * entry as it is an SRAT resource allocation structure.
5265 * We do not currently support doing so.
5266 */
5267 node = pxm_to_node(its_affinity->proximity_domain);
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305268
5269 if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
5270 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
5271 return 0;
5272 }
5273
5274 its_srat_maps[its_in_srat].numa_node = node;
5275 its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
5276 its_in_srat++;
5277 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
5278 its_affinity->proximity_domain, its_affinity->its_id, node);
5279
5280 return 0;
5281}
5282
5283static void __init acpi_table_parse_srat_its(void)
5284{
Hanjun Guofdf6e7a2017-07-26 18:15:49 +08005285 int count;
5286
5287 count = acpi_table_parse_entries(ACPI_SIG_SRAT,
5288 sizeof(struct acpi_table_srat),
5289 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5290 gic_acpi_match_srat_its, 0);
5291 if (count <= 0)
5292 return;
5293
Kees Cook6da2ec52018-06-12 13:55:00 -07005294 its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
5295 GFP_KERNEL);
Hanjun Guofdf6e7a2017-07-26 18:15:49 +08005296 if (!its_srat_maps) {
5297 pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
5298 return;
5299 }
5300
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305301 acpi_table_parse_entries(ACPI_SIG_SRAT,
5302 sizeof(struct acpi_table_srat),
5303 ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
5304 gic_acpi_parse_srat_its, 0);
5305}
Hanjun Guofdf6e7a2017-07-26 18:15:49 +08005306
5307/* free the its_srat_maps after ITS probing */
5308static void __init acpi_its_srat_maps_free(void)
5309{
5310 kfree(its_srat_maps);
5311}
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305312#else
5313static void __init acpi_table_parse_srat_its(void) { }
5314static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
Hanjun Guofdf6e7a2017-07-26 18:15:49 +08005315static void __init acpi_its_srat_maps_free(void) { }
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305316#endif
5317
Keith Busch60574d12019-03-11 14:55:57 -06005318static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header,
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005319 const unsigned long end)
5320{
5321 struct acpi_madt_generic_translator *its_entry;
5322 struct fwnode_handle *dom_handle;
5323 struct resource res;
5324 int err;
5325
5326 its_entry = (struct acpi_madt_generic_translator *)header;
5327 memset(&res, 0, sizeof(res));
5328 res.start = its_entry->base_address;
5329 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
5330 res.flags = IORESOURCE_MEM;
5331
Marc Zyngier5778cc72019-07-31 16:13:42 +01005332 dom_handle = irq_domain_alloc_fwnode(&res.start);
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005333 if (!dom_handle) {
5334 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
5335 &res.start);
5336 return -ENOMEM;
5337 }
5338
Shameer Kolothum8b4282e2018-02-13 15:20:50 +00005339 err = iort_register_domain_token(its_entry->translation_id, res.start,
5340 dom_handle);
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005341 if (err) {
5342 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
5343 &res.start, its_entry->translation_id);
5344 goto dom_err;
5345 }
5346
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305347 err = its_probe_one(&res, dom_handle,
5348 acpi_get_its_numa_node(its_entry->translation_id));
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005349 if (!err)
5350 return 0;
5351
5352 iort_deregister_domain_token(its_entry->translation_id);
5353dom_err:
5354 irq_domain_free_fwnode(dom_handle);
5355 return err;
5356}
5357
5358static void __init its_acpi_probe(void)
5359{
Ganapatrao Kulkarnidbd2b822017-06-22 11:40:12 +05305360 acpi_table_parse_srat_its();
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005361 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
5362 gic_acpi_parse_madt_its, 0);
Hanjun Guofdf6e7a2017-07-26 18:15:49 +08005363 acpi_its_srat_maps_free();
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005364}
5365#else
5366static void __init its_acpi_probe(void) { }
5367#endif
5368
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005369int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
5370 struct irq_domain *parent_domain)
5371{
5372 struct device_node *of_node;
Marc Zyngier8fff27a2016-12-20 13:41:55 +00005373 struct its_node *its;
5374 bool has_v4 = false;
Marc Zyngier3c407062020-03-04 20:33:13 +00005375 bool has_v4_1 = false;
Marc Zyngier8fff27a2016-12-20 13:41:55 +00005376 int err;
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005377
Marc Zyngier5e516842019-12-24 11:10:28 +00005378 gic_rdists = rdists;
5379
Tomasz Nowickidb40f0a2016-09-12 20:32:24 +02005380 its_parent = parent_domain;
5381 of_node = to_of_node(handle);
5382 if (of_node)
5383 its_of_probe(of_node);
5384 else
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +02005385 its_acpi_probe();
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005386
5387 if (list_empty(&its_nodes)) {
5388 pr_warn("ITS: No ITS available, not enabling LPIs\n");
5389 return -ENXIO;
5390 }
5391
Marc Zyngier11e37d32018-07-27 13:38:54 +01005392 err = allocate_lpi_tables();
Marc Zyngier8fff27a2016-12-20 13:41:55 +00005393 if (err)
5394 return err;
5395
Marc Zyngier3c407062020-03-04 20:33:13 +00005396 list_for_each_entry(its, &its_nodes, entry) {
Marc Zyngier0dd57fe2019-11-08 16:57:58 +00005397 has_v4 |= is_v4(its);
Marc Zyngier3c407062020-03-04 20:33:13 +00005398 has_v4_1 |= is_v4_1(its);
5399 }
5400
5401 /* Don't bother with inconsistent systems */
5402 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid))
5403 rdists->has_rvpeid = false;
Marc Zyngier8fff27a2016-12-20 13:41:55 +00005404
5405 if (has_v4 & rdists->has_vlpis) {
Marc Zyngier166cba72020-03-04 20:33:15 +00005406 const struct irq_domain_ops *sgi_ops;
5407
5408 if (has_v4_1)
5409 sgi_ops = &its_sgi_domain_ops;
5410 else
5411 sgi_ops = NULL;
5412
Marc Zyngier3d63cb52016-12-20 15:31:54 +00005413 if (its_init_vpe_domain() ||
Marc Zyngier166cba72020-03-04 20:33:15 +00005414 its_init_v4(parent_domain, &its_vpe_domain_ops, sgi_ops)) {
Marc Zyngier8fff27a2016-12-20 13:41:55 +00005415 rdists->has_vlpis = false;
5416 pr_err("ITS: Disabling GICv4 support\n");
5417 }
5418 }
5419
Derek Basehoredba0bc72018-02-28 21:48:18 -08005420 register_syscore_ops(&its_syscore_ops);
5421
Marc Zyngier8fff27a2016-12-20 13:41:55 +00005422 return 0;
Marc Zyngier4c21f3c2014-11-24 14:35:17 +00005423}