Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/drivers/video/omap2/dss/dsi.c |
| 3 | * |
| 4 | * Copyright (C) 2009 Nokia Corporation |
| 5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License version 2 as published by |
| 9 | * the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #define DSS_SUBSYS_NAME "DSI" |
| 21 | |
| 22 | #include <linux/kernel.h> |
| 23 | #include <linux/io.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <linux/mutex.h> |
Paul Gortmaker | 355b200 | 2011-07-03 16:17:28 -0400 | [diff] [blame] | 30 | #include <linux/module.h> |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 31 | #include <linux/semaphore.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 32 | #include <linux/seq_file.h> |
| 33 | #include <linux/platform_device.h> |
| 34 | #include <linux/regulator/consumer.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 35 | #include <linux/wait.h> |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 36 | #include <linux/workqueue.h> |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 37 | #include <linux/sched.h> |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 38 | #include <linux/slab.h> |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 39 | #include <linux/debugfs.h> |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 40 | #include <linux/pm_runtime.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 41 | |
Tomi Valkeinen | a0b38cc | 2011-05-11 14:05:07 +0300 | [diff] [blame] | 42 | #include <video/omapdss.h> |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 43 | #include <video/mipi_display.h> |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 44 | #include <plat/clock.h> |
| 45 | |
| 46 | #include "dss.h" |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 47 | #include "dss_features.h" |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 48 | |
| 49 | /*#define VERBOSE_IRQ*/ |
| 50 | #define DSI_CATCH_MISSING_TE |
| 51 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 52 | struct dsi_reg { u16 idx; }; |
| 53 | |
| 54 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) |
| 55 | |
| 56 | #define DSI_SZ_REGS SZ_1K |
| 57 | /* DSI Protocol Engine */ |
| 58 | |
| 59 | #define DSI_REVISION DSI_REG(0x0000) |
| 60 | #define DSI_SYSCONFIG DSI_REG(0x0010) |
| 61 | #define DSI_SYSSTATUS DSI_REG(0x0014) |
| 62 | #define DSI_IRQSTATUS DSI_REG(0x0018) |
| 63 | #define DSI_IRQENABLE DSI_REG(0x001C) |
| 64 | #define DSI_CTRL DSI_REG(0x0040) |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 65 | #define DSI_GNQ DSI_REG(0x0044) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 66 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
| 67 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) |
| 68 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) |
| 69 | #define DSI_CLK_CTRL DSI_REG(0x0054) |
| 70 | #define DSI_TIMING1 DSI_REG(0x0058) |
| 71 | #define DSI_TIMING2 DSI_REG(0x005C) |
| 72 | #define DSI_VM_TIMING1 DSI_REG(0x0060) |
| 73 | #define DSI_VM_TIMING2 DSI_REG(0x0064) |
| 74 | #define DSI_VM_TIMING3 DSI_REG(0x0068) |
| 75 | #define DSI_CLK_TIMING DSI_REG(0x006C) |
| 76 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) |
| 77 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) |
| 78 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) |
| 79 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) |
| 80 | #define DSI_VM_TIMING4 DSI_REG(0x0080) |
| 81 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) |
| 82 | #define DSI_VM_TIMING5 DSI_REG(0x0088) |
| 83 | #define DSI_VM_TIMING6 DSI_REG(0x008C) |
| 84 | #define DSI_VM_TIMING7 DSI_REG(0x0090) |
| 85 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) |
| 86 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) |
| 87 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) |
| 88 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) |
| 89 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) |
| 90 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) |
| 91 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) |
| 92 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) |
| 93 | |
| 94 | /* DSIPHY_SCP */ |
| 95 | |
| 96 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) |
| 97 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) |
| 98 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) |
| 99 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 100 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 101 | |
| 102 | /* DSI_PLL_CTRL_SCP */ |
| 103 | |
| 104 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) |
| 105 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) |
| 106 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) |
| 107 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) |
| 108 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) |
| 109 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 110 | #define REG_GET(dsidev, idx, start, end) \ |
| 111 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 112 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 113 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ |
| 114 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 115 | |
| 116 | /* Global interrupts */ |
| 117 | #define DSI_IRQ_VC0 (1 << 0) |
| 118 | #define DSI_IRQ_VC1 (1 << 1) |
| 119 | #define DSI_IRQ_VC2 (1 << 2) |
| 120 | #define DSI_IRQ_VC3 (1 << 3) |
| 121 | #define DSI_IRQ_WAKEUP (1 << 4) |
| 122 | #define DSI_IRQ_RESYNC (1 << 5) |
| 123 | #define DSI_IRQ_PLL_LOCK (1 << 7) |
| 124 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) |
| 125 | #define DSI_IRQ_PLL_RECALL (1 << 9) |
| 126 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) |
| 127 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) |
| 128 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) |
| 129 | #define DSI_IRQ_TE_TRIGGER (1 << 16) |
| 130 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) |
| 131 | #define DSI_IRQ_SYNC_LOST (1 << 18) |
| 132 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) |
| 133 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) |
| 134 | #define DSI_IRQ_ERROR_MASK \ |
| 135 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 136 | DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 137 | #define DSI_IRQ_CHANNEL_MASK 0xf |
| 138 | |
| 139 | /* Virtual channel interrupts */ |
| 140 | #define DSI_VC_IRQ_CS (1 << 0) |
| 141 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) |
| 142 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) |
| 143 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) |
| 144 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) |
| 145 | #define DSI_VC_IRQ_BTA (1 << 5) |
| 146 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) |
| 147 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) |
| 148 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) |
| 149 | #define DSI_VC_IRQ_ERROR_MASK \ |
| 150 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ |
| 151 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ |
| 152 | DSI_VC_IRQ_FIFO_TX_UDF) |
| 153 | |
| 154 | /* ComplexIO interrupts */ |
| 155 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) |
| 156 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) |
| 157 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 158 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
| 159 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 160 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
| 161 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) |
| 162 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 163 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
| 164 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 165 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
| 166 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) |
| 167 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 168 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
| 169 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 170 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
| 171 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) |
| 172 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 173 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
| 174 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 175 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
| 176 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) |
| 177 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) |
| 178 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) |
| 179 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) |
| 180 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 181 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
| 182 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) |
| 183 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) |
| 184 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 185 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
| 186 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 187 | #define DSI_CIO_IRQ_ERROR_MASK \ |
| 188 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 189 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
| 190 | DSI_CIO_IRQ_ERRSYNCESC5 | \ |
| 191 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ |
| 192 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ |
| 193 | DSI_CIO_IRQ_ERRESC5 | \ |
| 194 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ |
| 195 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ |
| 196 | DSI_CIO_IRQ_ERRCONTROL5 | \ |
Tomi Valkeinen | bbecb50 | 2010-05-10 14:35:33 +0300 | [diff] [blame] | 197 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
| 198 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ |
Tomi Valkeinen | 6705615 | 2011-03-24 16:30:17 +0200 | [diff] [blame] | 199 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
| 200 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ |
| 201 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 202 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 203 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
| 204 | |
| 205 | #define DSI_MAX_NR_ISRS 2 |
Tomi Valkeinen | 739a7f4 | 2011-10-13 11:22:06 +0300 | [diff] [blame] | 206 | #define DSI_MAX_NR_LANES 5 |
| 207 | |
| 208 | enum dsi_lane_function { |
| 209 | DSI_LANE_UNUSED = 0, |
| 210 | DSI_LANE_CLK, |
| 211 | DSI_LANE_DATA1, |
| 212 | DSI_LANE_DATA2, |
| 213 | DSI_LANE_DATA3, |
| 214 | DSI_LANE_DATA4, |
| 215 | }; |
| 216 | |
| 217 | struct dsi_lane_config { |
| 218 | enum dsi_lane_function function; |
| 219 | u8 polarity; |
| 220 | }; |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 221 | |
| 222 | struct dsi_isr_data { |
| 223 | omap_dsi_isr_t isr; |
| 224 | void *arg; |
| 225 | u32 mask; |
| 226 | }; |
| 227 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 228 | enum fifo_size { |
| 229 | DSI_FIFO_SIZE_0 = 0, |
| 230 | DSI_FIFO_SIZE_32 = 1, |
| 231 | DSI_FIFO_SIZE_64 = 2, |
| 232 | DSI_FIFO_SIZE_96 = 3, |
| 233 | DSI_FIFO_SIZE_128 = 4, |
| 234 | }; |
| 235 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 236 | enum dsi_vc_source { |
| 237 | DSI_VC_SOURCE_L4 = 0, |
| 238 | DSI_VC_SOURCE_VP, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 239 | }; |
| 240 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 241 | struct dsi_irq_stats { |
| 242 | unsigned long last_reset; |
| 243 | unsigned irq_count; |
| 244 | unsigned dsi_irqs[32]; |
| 245 | unsigned vc_irqs[4][32]; |
| 246 | unsigned cio_irqs[32]; |
| 247 | }; |
| 248 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 249 | struct dsi_isr_tables { |
| 250 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; |
| 251 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; |
| 252 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; |
| 253 | }; |
| 254 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 255 | struct dsi_data { |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 256 | struct platform_device *pdev; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 257 | void __iomem *base; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 258 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 259 | int irq; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 260 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 261 | struct clk *dss_clk; |
| 262 | struct clk *sys_clk; |
| 263 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 264 | struct dsi_clock_info current_cinfo; |
| 265 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 266 | bool vdds_dsi_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 267 | struct regulator *vdds_dsi_reg; |
| 268 | |
| 269 | struct { |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 270 | enum dsi_vc_source source; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 271 | struct omap_dss_device *dssdev; |
| 272 | enum fifo_size fifo_size; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 273 | int vc_id; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 274 | } vc[4]; |
| 275 | |
| 276 | struct mutex lock; |
Tomi Valkeinen | b9eb5d7 | 2010-01-11 16:33:56 +0200 | [diff] [blame] | 277 | struct semaphore bus_lock; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 278 | |
| 279 | unsigned pll_locked; |
| 280 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 281 | spinlock_t irq_lock; |
| 282 | struct dsi_isr_tables isr_tables; |
| 283 | /* space for a copy used by the interrupt handler */ |
| 284 | struct dsi_isr_tables isr_tables_copy; |
| 285 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 286 | int update_channel; |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 287 | #ifdef DEBUG |
| 288 | unsigned update_bytes; |
| 289 | #endif |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 290 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 291 | bool te_enabled; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 292 | bool ulps_enabled; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 293 | |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 294 | void (*framedone_callback)(int, void *); |
| 295 | void *framedone_data; |
| 296 | |
| 297 | struct delayed_work framedone_timeout_work; |
| 298 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 299 | #ifdef DSI_CATCH_MISSING_TE |
| 300 | struct timer_list te_timer; |
| 301 | #endif |
| 302 | |
| 303 | unsigned long cache_req_pck; |
| 304 | unsigned long cache_clk_freq; |
| 305 | struct dsi_clock_info cache_cinfo; |
| 306 | |
| 307 | u32 errors; |
| 308 | spinlock_t errors_lock; |
| 309 | #ifdef DEBUG |
| 310 | ktime_t perf_setup_time; |
| 311 | ktime_t perf_start_time; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 312 | #endif |
| 313 | int debug_read; |
| 314 | int debug_write; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 315 | |
| 316 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 317 | spinlock_t irq_stats_lock; |
| 318 | struct dsi_irq_stats irq_stats; |
| 319 | #endif |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 320 | /* DSI PLL Parameter Ranges */ |
| 321 | unsigned long regm_max, regn_max; |
| 322 | unsigned long regm_dispc_max, regm_dsi_max; |
| 323 | unsigned long fint_min, fint_max; |
| 324 | unsigned long lpdiv_max; |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 325 | |
Tomi Valkeinen | d982085 | 2011-10-12 15:05:59 +0300 | [diff] [blame] | 326 | unsigned num_lanes_supported; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 327 | |
Tomi Valkeinen | 739a7f4 | 2011-10-13 11:22:06 +0300 | [diff] [blame] | 328 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; |
| 329 | unsigned num_lanes_used; |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 330 | |
| 331 | unsigned scp_clk_refcount; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 332 | }; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 333 | |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 334 | struct dsi_packet_sent_handler_data { |
| 335 | struct platform_device *dsidev; |
| 336 | struct completion *completion; |
| 337 | }; |
| 338 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 339 | static struct platform_device *dsi_pdev_map[MAX_NUM_DSI]; |
| 340 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 341 | #ifdef DEBUG |
Rusty Russell | 90ab5ee | 2012-01-13 09:32:20 +1030 | [diff] [blame] | 342 | static bool dsi_perf; |
| 343 | module_param(dsi_perf, bool, 0644); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 344 | #endif |
| 345 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 346 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) |
| 347 | { |
| 348 | return dev_get_drvdata(&dsidev->dev); |
| 349 | } |
| 350 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 351 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) |
| 352 | { |
| 353 | return dsi_pdev_map[dssdev->phy.dsi.module]; |
| 354 | } |
| 355 | |
| 356 | struct platform_device *dsi_get_dsidev_from_id(int module) |
| 357 | { |
| 358 | return dsi_pdev_map[module]; |
| 359 | } |
| 360 | |
Tomi Valkeinen | 7c68dd9 | 2011-08-03 14:00:57 +0300 | [diff] [blame] | 361 | static inline int dsi_get_dsidev_id(struct platform_device *dsidev) |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 362 | { |
Tomi Valkeinen | 7c68dd9 | 2011-08-03 14:00:57 +0300 | [diff] [blame] | 363 | return dsidev->id; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 364 | } |
| 365 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 366 | static inline void dsi_write_reg(struct platform_device *dsidev, |
| 367 | const struct dsi_reg idx, u32 val) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 368 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 369 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 370 | |
| 371 | __raw_writel(val, dsi->base + idx.idx); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 372 | } |
| 373 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 374 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
| 375 | const struct dsi_reg idx) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 376 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 377 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 378 | |
| 379 | return __raw_readl(dsi->base + idx.idx); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 380 | } |
| 381 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 382 | void dsi_bus_lock(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 383 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 384 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 385 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 386 | |
| 387 | down(&dsi->bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 388 | } |
| 389 | EXPORT_SYMBOL(dsi_bus_lock); |
| 390 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 391 | void dsi_bus_unlock(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 392 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 393 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 394 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 395 | |
| 396 | up(&dsi->bus_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 397 | } |
| 398 | EXPORT_SYMBOL(dsi_bus_unlock); |
| 399 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 400 | static bool dsi_bus_is_locked(struct platform_device *dsidev) |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 401 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 402 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 403 | |
| 404 | return dsi->bus_lock.count == 0; |
Tomi Valkeinen | 4f76502 | 2010-01-18 16:27:52 +0200 | [diff] [blame] | 405 | } |
| 406 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 407 | static void dsi_completion_handler(void *data, u32 mask) |
| 408 | { |
| 409 | complete((struct completion *)data); |
| 410 | } |
| 411 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 412 | static inline int wait_for_bit_change(struct platform_device *dsidev, |
| 413 | const struct dsi_reg idx, int bitnum, int value) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 414 | { |
Tomi Valkeinen | 3b98409 | 2011-10-13 19:06:49 +0300 | [diff] [blame] | 415 | unsigned long timeout; |
| 416 | ktime_t wait; |
| 417 | int t; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 418 | |
Tomi Valkeinen | 3b98409 | 2011-10-13 19:06:49 +0300 | [diff] [blame] | 419 | /* first busyloop to see if the bit changes right away */ |
| 420 | t = 100; |
| 421 | while (t-- > 0) { |
| 422 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) |
| 423 | return value; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 424 | } |
| 425 | |
Tomi Valkeinen | 3b98409 | 2011-10-13 19:06:49 +0300 | [diff] [blame] | 426 | /* then loop for 500ms, sleeping for 1ms in between */ |
| 427 | timeout = jiffies + msecs_to_jiffies(500); |
| 428 | while (time_before(jiffies, timeout)) { |
| 429 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) |
| 430 | return value; |
| 431 | |
| 432 | wait = ns_to_ktime(1000 * 1000); |
| 433 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 434 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); |
| 435 | } |
| 436 | |
| 437 | return !value; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 438 | } |
| 439 | |
Archit Taneja | a3b3cc2 | 2011-09-08 18:42:16 +0530 | [diff] [blame] | 440 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
| 441 | { |
| 442 | switch (fmt) { |
| 443 | case OMAP_DSS_DSI_FMT_RGB888: |
| 444 | case OMAP_DSS_DSI_FMT_RGB666: |
| 445 | return 24; |
| 446 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: |
| 447 | return 18; |
| 448 | case OMAP_DSS_DSI_FMT_RGB565: |
| 449 | return 16; |
| 450 | default: |
| 451 | BUG(); |
| 452 | } |
| 453 | } |
| 454 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 455 | #ifdef DEBUG |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 456 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 457 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 458 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 459 | dsi->perf_setup_time = ktime_get(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 460 | } |
| 461 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 462 | static void dsi_perf_mark_start(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 463 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 464 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 465 | dsi->perf_start_time = ktime_get(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 466 | } |
| 467 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 468 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 469 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 470 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 471 | ktime_t t, setup_time, trans_time; |
| 472 | u32 total_bytes; |
| 473 | u32 setup_us, trans_us, total_us; |
| 474 | |
| 475 | if (!dsi_perf) |
| 476 | return; |
| 477 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 478 | t = ktime_get(); |
| 479 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 480 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 481 | setup_us = (u32)ktime_to_us(setup_time); |
| 482 | if (setup_us == 0) |
| 483 | setup_us = 1; |
| 484 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 485 | trans_time = ktime_sub(t, dsi->perf_start_time); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 486 | trans_us = (u32)ktime_to_us(trans_time); |
| 487 | if (trans_us == 0) |
| 488 | trans_us = 1; |
| 489 | |
| 490 | total_us = setup_us + trans_us; |
| 491 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 492 | total_bytes = dsi->update_bytes; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 493 | |
Tomi Valkeinen | 1bbb275 | 2010-01-11 16:41:10 +0200 | [diff] [blame] | 494 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
| 495 | "%u bytes, %u kbytes/sec\n", |
| 496 | name, |
| 497 | setup_us, |
| 498 | trans_us, |
| 499 | total_us, |
| 500 | 1000*1000 / total_us, |
| 501 | total_bytes, |
| 502 | total_bytes * 1000 / total_us); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 503 | } |
| 504 | #else |
Tomi Valkeinen | 4a9a5e3 | 2011-05-23 16:36:09 +0300 | [diff] [blame] | 505 | static inline void dsi_perf_mark_setup(struct platform_device *dsidev) |
| 506 | { |
| 507 | } |
| 508 | |
| 509 | static inline void dsi_perf_mark_start(struct platform_device *dsidev) |
| 510 | { |
| 511 | } |
| 512 | |
| 513 | static inline void dsi_perf_show(struct platform_device *dsidev, |
| 514 | const char *name) |
| 515 | { |
| 516 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 517 | #endif |
| 518 | |
| 519 | static void print_irq_status(u32 status) |
| 520 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 521 | if (status == 0) |
| 522 | return; |
| 523 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 524 | #ifndef VERBOSE_IRQ |
| 525 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) |
| 526 | return; |
| 527 | #endif |
| 528 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); |
| 529 | |
| 530 | #define PIS(x) \ |
| 531 | if (status & DSI_IRQ_##x) \ |
| 532 | printk(#x " "); |
| 533 | #ifdef VERBOSE_IRQ |
| 534 | PIS(VC0); |
| 535 | PIS(VC1); |
| 536 | PIS(VC2); |
| 537 | PIS(VC3); |
| 538 | #endif |
| 539 | PIS(WAKEUP); |
| 540 | PIS(RESYNC); |
| 541 | PIS(PLL_LOCK); |
| 542 | PIS(PLL_UNLOCK); |
| 543 | PIS(PLL_RECALL); |
| 544 | PIS(COMPLEXIO_ERR); |
| 545 | PIS(HS_TX_TIMEOUT); |
| 546 | PIS(LP_RX_TIMEOUT); |
| 547 | PIS(TE_TRIGGER); |
| 548 | PIS(ACK_TRIGGER); |
| 549 | PIS(SYNC_LOST); |
| 550 | PIS(LDO_POWER_GOOD); |
| 551 | PIS(TA_TIMEOUT); |
| 552 | #undef PIS |
| 553 | |
| 554 | printk("\n"); |
| 555 | } |
| 556 | |
| 557 | static void print_irq_status_vc(int channel, u32 status) |
| 558 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 559 | if (status == 0) |
| 560 | return; |
| 561 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 562 | #ifndef VERBOSE_IRQ |
| 563 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) |
| 564 | return; |
| 565 | #endif |
| 566 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); |
| 567 | |
| 568 | #define PIS(x) \ |
| 569 | if (status & DSI_VC_IRQ_##x) \ |
| 570 | printk(#x " "); |
| 571 | PIS(CS); |
| 572 | PIS(ECC_CORR); |
| 573 | #ifdef VERBOSE_IRQ |
| 574 | PIS(PACKET_SENT); |
| 575 | #endif |
| 576 | PIS(FIFO_TX_OVF); |
| 577 | PIS(FIFO_RX_OVF); |
| 578 | PIS(BTA); |
| 579 | PIS(ECC_NO_CORR); |
| 580 | PIS(FIFO_TX_UDF); |
| 581 | PIS(PP_BUSY_CHANGE); |
| 582 | #undef PIS |
| 583 | printk("\n"); |
| 584 | } |
| 585 | |
| 586 | static void print_irq_status_cio(u32 status) |
| 587 | { |
Tomi Valkeinen | d80d499 | 2011-03-02 15:53:07 +0200 | [diff] [blame] | 588 | if (status == 0) |
| 589 | return; |
| 590 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 591 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
| 592 | |
| 593 | #define PIS(x) \ |
| 594 | if (status & DSI_CIO_IRQ_##x) \ |
| 595 | printk(#x " "); |
| 596 | PIS(ERRSYNCESC1); |
| 597 | PIS(ERRSYNCESC2); |
| 598 | PIS(ERRSYNCESC3); |
| 599 | PIS(ERRESC1); |
| 600 | PIS(ERRESC2); |
| 601 | PIS(ERRESC3); |
| 602 | PIS(ERRCONTROL1); |
| 603 | PIS(ERRCONTROL2); |
| 604 | PIS(ERRCONTROL3); |
| 605 | PIS(STATEULPS1); |
| 606 | PIS(STATEULPS2); |
| 607 | PIS(STATEULPS3); |
| 608 | PIS(ERRCONTENTIONLP0_1); |
| 609 | PIS(ERRCONTENTIONLP1_1); |
| 610 | PIS(ERRCONTENTIONLP0_2); |
| 611 | PIS(ERRCONTENTIONLP1_2); |
| 612 | PIS(ERRCONTENTIONLP0_3); |
| 613 | PIS(ERRCONTENTIONLP1_3); |
| 614 | PIS(ULPSACTIVENOT_ALL0); |
| 615 | PIS(ULPSACTIVENOT_ALL1); |
| 616 | #undef PIS |
| 617 | |
| 618 | printk("\n"); |
| 619 | } |
| 620 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 621 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 622 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
| 623 | u32 *vcstatus, u32 ciostatus) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 624 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 625 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 626 | int i; |
| 627 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 628 | spin_lock(&dsi->irq_stats_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 629 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 630 | dsi->irq_stats.irq_count++; |
| 631 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 632 | |
| 633 | for (i = 0; i < 4; ++i) |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 634 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 635 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 636 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 637 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 638 | spin_unlock(&dsi->irq_stats_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 639 | } |
| 640 | #else |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 641 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 642 | #endif |
| 643 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 644 | static int debug_irq; |
| 645 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 646 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, |
| 647 | u32 *vcstatus, u32 ciostatus) |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 648 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 649 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 650 | int i; |
| 651 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 652 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
| 653 | DSSERR("DSI error, irqstatus %x\n", irqstatus); |
| 654 | print_irq_status(irqstatus); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 655 | spin_lock(&dsi->errors_lock); |
| 656 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; |
| 657 | spin_unlock(&dsi->errors_lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 658 | } else if (debug_irq) { |
| 659 | print_irq_status(irqstatus); |
| 660 | } |
| 661 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 662 | for (i = 0; i < 4; ++i) { |
| 663 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
| 664 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", |
| 665 | i, vcstatus[i]); |
| 666 | print_irq_status_vc(i, vcstatus[i]); |
| 667 | } else if (debug_irq) { |
| 668 | print_irq_status_vc(i, vcstatus[i]); |
| 669 | } |
| 670 | } |
| 671 | |
| 672 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
| 673 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); |
| 674 | print_irq_status_cio(ciostatus); |
| 675 | } else if (debug_irq) { |
| 676 | print_irq_status_cio(ciostatus); |
| 677 | } |
| 678 | } |
| 679 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 680 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
| 681 | unsigned isr_array_size, u32 irqstatus) |
| 682 | { |
| 683 | struct dsi_isr_data *isr_data; |
| 684 | int i; |
| 685 | |
| 686 | for (i = 0; i < isr_array_size; i++) { |
| 687 | isr_data = &isr_array[i]; |
| 688 | if (isr_data->isr && isr_data->mask & irqstatus) |
| 689 | isr_data->isr(isr_data->arg, irqstatus); |
| 690 | } |
| 691 | } |
| 692 | |
| 693 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, |
| 694 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) |
| 695 | { |
| 696 | int i; |
| 697 | |
| 698 | dsi_call_isrs(isr_tables->isr_table, |
| 699 | ARRAY_SIZE(isr_tables->isr_table), |
| 700 | irqstatus); |
| 701 | |
| 702 | for (i = 0; i < 4; ++i) { |
| 703 | if (vcstatus[i] == 0) |
| 704 | continue; |
| 705 | dsi_call_isrs(isr_tables->isr_table_vc[i], |
| 706 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), |
| 707 | vcstatus[i]); |
| 708 | } |
| 709 | |
| 710 | if (ciostatus != 0) |
| 711 | dsi_call_isrs(isr_tables->isr_table_cio, |
| 712 | ARRAY_SIZE(isr_tables->isr_table_cio), |
| 713 | ciostatus); |
| 714 | } |
| 715 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 716 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
| 717 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 718 | struct platform_device *dsidev; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 719 | struct dsi_data *dsi; |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 720 | u32 irqstatus, vcstatus[4], ciostatus; |
| 721 | int i; |
| 722 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 723 | dsidev = (struct platform_device *) arg; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 724 | dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 725 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 726 | spin_lock(&dsi->irq_lock); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 727 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 728 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 729 | |
| 730 | /* IRQ is not for us */ |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 731 | if (!irqstatus) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 732 | spin_unlock(&dsi->irq_lock); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 733 | return IRQ_NONE; |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 734 | } |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 735 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 736 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 737 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 738 | dsi_read_reg(dsidev, DSI_IRQSTATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 739 | |
| 740 | for (i = 0; i < 4; ++i) { |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 741 | if ((irqstatus & (1 << i)) == 0) { |
| 742 | vcstatus[i] = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 743 | continue; |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 744 | } |
| 745 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 746 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 747 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 748 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 749 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 750 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 751 | } |
| 752 | |
| 753 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 754 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 755 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 756 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 757 | /* flush posted write */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 758 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 759 | } else { |
| 760 | ciostatus = 0; |
| 761 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 762 | |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 763 | #ifdef DSI_CATCH_MISSING_TE |
| 764 | if (irqstatus & DSI_IRQ_TE_TRIGGER) |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 765 | del_timer(&dsi->te_timer); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 766 | #endif |
| 767 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 768 | /* make a copy and unlock, so that isrs can unregister |
| 769 | * themselves */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 770 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
| 771 | sizeof(dsi->isr_tables)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 772 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 773 | spin_unlock(&dsi->irq_lock); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 774 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 775 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 776 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 777 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 778 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 779 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); |
Tomi Valkeinen | 69b281a | 2011-03-02 14:44:27 +0200 | [diff] [blame] | 780 | |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 781 | return IRQ_HANDLED; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 782 | } |
| 783 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 784 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 785 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, |
| 786 | struct dsi_isr_data *isr_array, |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 787 | unsigned isr_array_size, u32 default_mask, |
| 788 | const struct dsi_reg enable_reg, |
| 789 | const struct dsi_reg status_reg) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 790 | { |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 791 | struct dsi_isr_data *isr_data; |
| 792 | u32 mask; |
| 793 | u32 old_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 794 | int i; |
| 795 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 796 | mask = default_mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 797 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 798 | for (i = 0; i < isr_array_size; i++) { |
| 799 | isr_data = &isr_array[i]; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 800 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 801 | if (isr_data->isr == NULL) |
| 802 | continue; |
| 803 | |
| 804 | mask |= isr_data->mask; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 805 | } |
| 806 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 807 | old_mask = dsi_read_reg(dsidev, enable_reg); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 808 | /* clear the irqstatus for newly enabled irqs */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 809 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); |
| 810 | dsi_write_reg(dsidev, enable_reg, mask); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 811 | |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 812 | /* flush posted writes */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 813 | dsi_read_reg(dsidev, enable_reg); |
| 814 | dsi_read_reg(dsidev, status_reg); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 815 | } |
| 816 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 817 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 818 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 819 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 820 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 821 | u32 mask = DSI_IRQ_ERROR_MASK; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 822 | #ifdef DSI_CATCH_MISSING_TE |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 823 | mask |= DSI_IRQ_TE_TRIGGER; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 824 | #endif |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 825 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, |
| 826 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 827 | DSI_IRQENABLE, DSI_IRQSTATUS); |
| 828 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 829 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 830 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 831 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 832 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 833 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 834 | |
| 835 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], |
| 836 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 837 | DSI_VC_IRQ_ERROR_MASK, |
| 838 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); |
| 839 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 840 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 841 | /* dsi->irq_lock has to be locked by the caller */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 842 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 843 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 844 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 845 | |
| 846 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, |
| 847 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 848 | DSI_CIO_IRQ_ERROR_MASK, |
| 849 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); |
| 850 | } |
| 851 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 852 | static void _dsi_initialize_irq(struct platform_device *dsidev) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 853 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 854 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 855 | unsigned long flags; |
| 856 | int vc; |
| 857 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 858 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 859 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 860 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 861 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 862 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 863 | for (vc = 0; vc < 4; ++vc) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 864 | _omap_dsi_set_irqs_vc(dsidev, vc); |
| 865 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 866 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 867 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 868 | } |
| 869 | |
| 870 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 871 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 872 | { |
| 873 | struct dsi_isr_data *isr_data; |
| 874 | int free_idx; |
| 875 | int i; |
| 876 | |
| 877 | BUG_ON(isr == NULL); |
| 878 | |
| 879 | /* check for duplicate entry and find a free slot */ |
| 880 | free_idx = -1; |
| 881 | for (i = 0; i < isr_array_size; i++) { |
| 882 | isr_data = &isr_array[i]; |
| 883 | |
| 884 | if (isr_data->isr == isr && isr_data->arg == arg && |
| 885 | isr_data->mask == mask) { |
| 886 | return -EINVAL; |
| 887 | } |
| 888 | |
| 889 | if (isr_data->isr == NULL && free_idx == -1) |
| 890 | free_idx = i; |
| 891 | } |
| 892 | |
| 893 | if (free_idx == -1) |
| 894 | return -EBUSY; |
| 895 | |
| 896 | isr_data = &isr_array[free_idx]; |
| 897 | isr_data->isr = isr; |
| 898 | isr_data->arg = arg; |
| 899 | isr_data->mask = mask; |
| 900 | |
| 901 | return 0; |
| 902 | } |
| 903 | |
| 904 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
| 905 | struct dsi_isr_data *isr_array, unsigned isr_array_size) |
| 906 | { |
| 907 | struct dsi_isr_data *isr_data; |
| 908 | int i; |
| 909 | |
| 910 | for (i = 0; i < isr_array_size; i++) { |
| 911 | isr_data = &isr_array[i]; |
| 912 | if (isr_data->isr != isr || isr_data->arg != arg || |
| 913 | isr_data->mask != mask) |
| 914 | continue; |
| 915 | |
| 916 | isr_data->isr = NULL; |
| 917 | isr_data->arg = NULL; |
| 918 | isr_data->mask = 0; |
| 919 | |
| 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | return -EINVAL; |
| 924 | } |
| 925 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 926 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, |
| 927 | void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 928 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 929 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 930 | unsigned long flags; |
| 931 | int r; |
| 932 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 933 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 934 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 935 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
| 936 | ARRAY_SIZE(dsi->isr_tables.isr_table)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 937 | |
| 938 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 939 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 940 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 941 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 942 | |
| 943 | return r; |
| 944 | } |
| 945 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 946 | static int dsi_unregister_isr(struct platform_device *dsidev, |
| 947 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 948 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 949 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 950 | unsigned long flags; |
| 951 | int r; |
| 952 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 953 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 954 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 955 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
| 956 | ARRAY_SIZE(dsi->isr_tables.isr_table)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 957 | |
| 958 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 959 | _omap_dsi_set_irqs(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 960 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 961 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 962 | |
| 963 | return r; |
| 964 | } |
| 965 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 966 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, |
| 967 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 968 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 969 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 970 | unsigned long flags; |
| 971 | int r; |
| 972 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 973 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 974 | |
| 975 | r = _dsi_register_isr(isr, arg, mask, |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 976 | dsi->isr_tables.isr_table_vc[channel], |
| 977 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 978 | |
| 979 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 980 | _omap_dsi_set_irqs_vc(dsidev, channel); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 981 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 982 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 983 | |
| 984 | return r; |
| 985 | } |
| 986 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 987 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, |
| 988 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 989 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 990 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 991 | unsigned long flags; |
| 992 | int r; |
| 993 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 994 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 995 | |
| 996 | r = _dsi_unregister_isr(isr, arg, mask, |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 997 | dsi->isr_tables.isr_table_vc[channel], |
| 998 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 999 | |
| 1000 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1001 | _omap_dsi_set_irqs_vc(dsidev, channel); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1002 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1003 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1004 | |
| 1005 | return r; |
| 1006 | } |
| 1007 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1008 | static int dsi_register_isr_cio(struct platform_device *dsidev, |
| 1009 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1010 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1011 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1012 | unsigned long flags; |
| 1013 | int r; |
| 1014 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1015 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1016 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1017 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
| 1018 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1019 | |
| 1020 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1021 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1022 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1023 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1024 | |
| 1025 | return r; |
| 1026 | } |
| 1027 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1028 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, |
| 1029 | omap_dsi_isr_t isr, void *arg, u32 mask) |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1030 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1031 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1032 | unsigned long flags; |
| 1033 | int r; |
| 1034 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1035 | spin_lock_irqsave(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1036 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1037 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
| 1038 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1039 | |
| 1040 | if (r == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1041 | _omap_dsi_set_irqs_cio(dsidev); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1042 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1043 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
Tomi Valkeinen | 4ae2ddd | 2011-03-02 14:47:04 +0200 | [diff] [blame] | 1044 | |
| 1045 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1046 | } |
| 1047 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1048 | static u32 dsi_get_errors(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1049 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1050 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1051 | unsigned long flags; |
| 1052 | u32 e; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1053 | spin_lock_irqsave(&dsi->errors_lock, flags); |
| 1054 | e = dsi->errors; |
| 1055 | dsi->errors = 0; |
| 1056 | spin_unlock_irqrestore(&dsi->errors_lock, flags); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1057 | return e; |
| 1058 | } |
| 1059 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1060 | int dsi_runtime_get(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1061 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1062 | int r; |
| 1063 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1064 | |
| 1065 | DSSDBG("dsi_runtime_get\n"); |
| 1066 | |
| 1067 | r = pm_runtime_get_sync(&dsi->pdev->dev); |
| 1068 | WARN_ON(r < 0); |
| 1069 | return r < 0 ? r : 0; |
| 1070 | } |
| 1071 | |
| 1072 | void dsi_runtime_put(struct platform_device *dsidev) |
| 1073 | { |
| 1074 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1075 | int r; |
| 1076 | |
| 1077 | DSSDBG("dsi_runtime_put\n"); |
| 1078 | |
Tomi Valkeinen | 0eaf9f5 | 2012-01-23 13:23:08 +0200 | [diff] [blame] | 1079 | r = pm_runtime_put_sync(&dsi->pdev->dev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1080 | WARN_ON(r < 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1081 | } |
| 1082 | |
| 1083 | /* source clock for DSI PLL. this could also be PCLKFREE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1084 | static inline void dsi_enable_pll_clock(struct platform_device *dsidev, |
| 1085 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1086 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1087 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1088 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1089 | if (enable) |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1090 | clk_enable(dsi->sys_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1091 | else |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1092 | clk_disable(dsi->sys_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1093 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1094 | if (enable && dsi->pll_locked) { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1095 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1096 | DSSERR("cannot lock PLL when enabling clocks\n"); |
| 1097 | } |
| 1098 | } |
| 1099 | |
| 1100 | #ifdef DEBUG |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1101 | static void _dsi_print_reset_status(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1102 | { |
| 1103 | u32 l; |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1104 | int b0, b1, b2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1105 | |
| 1106 | if (!dss_debug) |
| 1107 | return; |
| 1108 | |
| 1109 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 1110 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 1111 | * I/O. */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1112 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1113 | |
| 1114 | printk(KERN_DEBUG "DSI resets: "); |
| 1115 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1116 | l = dsi_read_reg(dsidev, DSI_PLL_STATUS); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1117 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
| 1118 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1119 | l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1120 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
| 1121 | |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1122 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
| 1123 | b0 = 28; |
| 1124 | b1 = 27; |
| 1125 | b2 = 26; |
| 1126 | } else { |
| 1127 | b0 = 24; |
| 1128 | b1 = 25; |
| 1129 | b2 = 26; |
| 1130 | } |
| 1131 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1132 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | c335cbf | 2010-10-07 13:27:42 +0300 | [diff] [blame] | 1133 | printk("PHY (%x%x%x, %d, %d, %d)\n", |
| 1134 | FLD_GET(l, b0, b0), |
| 1135 | FLD_GET(l, b1, b1), |
| 1136 | FLD_GET(l, b2, b2), |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1137 | FLD_GET(l, 29, 29), |
| 1138 | FLD_GET(l, 30, 30), |
| 1139 | FLD_GET(l, 31, 31)); |
| 1140 | } |
| 1141 | #else |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1142 | #define _dsi_print_reset_status(x) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1143 | #endif |
| 1144 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1145 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1146 | { |
| 1147 | DSSDBG("dsi_if_enable(%d)\n", enable); |
| 1148 | |
| 1149 | enable = enable ? 1 : 0; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1150 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1151 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1152 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1153 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
| 1154 | return -EIO; |
| 1155 | } |
| 1156 | |
| 1157 | return 0; |
| 1158 | } |
| 1159 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1160 | unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1161 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1162 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1163 | |
| 1164 | return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1165 | } |
| 1166 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1167 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1168 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1169 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1170 | |
| 1171 | return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1172 | } |
| 1173 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1174 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1175 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1176 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1177 | |
| 1178 | return dsi->current_cinfo.clkin4ddr / 16; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1179 | } |
| 1180 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1181 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1182 | { |
| 1183 | unsigned long r; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1184 | int dsi_module = dsi_get_dsidev_id(dsidev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1185 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1186 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1187 | if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1188 | /* DSI FCLK source is DSS_CLK_FCK */ |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1189 | r = clk_get_rate(dsi->dss_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1190 | } else { |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1191 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1192 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1193 | } |
| 1194 | |
| 1195 | return r; |
| 1196 | } |
| 1197 | |
| 1198 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) |
| 1199 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1200 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1201 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1202 | unsigned long dsi_fclk; |
| 1203 | unsigned lp_clk_div; |
| 1204 | unsigned long lp_clk; |
| 1205 | |
Tomi Valkeinen | c6940a3 | 2011-02-22 13:36:10 +0200 | [diff] [blame] | 1206 | lp_clk_div = dssdev->clocks.dsi.lp_clk_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1207 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1208 | if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1209 | return -EINVAL; |
| 1210 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1211 | dsi_fclk = dsi_fclk_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1212 | |
| 1213 | lp_clk = dsi_fclk / 2 / lp_clk_div; |
| 1214 | |
| 1215 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1216 | dsi->current_cinfo.lp_clk = lp_clk; |
| 1217 | dsi->current_cinfo.lp_clk_div = lp_clk_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1218 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1219 | /* LP_CLK_DIVISOR */ |
| 1220 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1221 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1222 | /* LP_RX_SYNCHRO_ENABLE */ |
| 1223 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1224 | |
| 1225 | return 0; |
| 1226 | } |
| 1227 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1228 | static void dsi_enable_scp_clk(struct platform_device *dsidev) |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1229 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1230 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1231 | |
| 1232 | if (dsi->scp_clk_refcount++ == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1233 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1234 | } |
| 1235 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1236 | static void dsi_disable_scp_clk(struct platform_device *dsidev) |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1237 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1238 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1239 | |
| 1240 | WARN_ON(dsi->scp_clk_refcount == 0); |
| 1241 | if (--dsi->scp_clk_refcount == 0) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1242 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1243 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1244 | |
| 1245 | enum dsi_pll_power_state { |
| 1246 | DSI_PLL_POWER_OFF = 0x0, |
| 1247 | DSI_PLL_POWER_ON_HSCLK = 0x1, |
| 1248 | DSI_PLL_POWER_ON_ALL = 0x2, |
| 1249 | DSI_PLL_POWER_ON_DIV = 0x3, |
| 1250 | }; |
| 1251 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1252 | static int dsi_pll_power(struct platform_device *dsidev, |
| 1253 | enum dsi_pll_power_state state) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1254 | { |
| 1255 | int t = 0; |
| 1256 | |
Tomi Valkeinen | c94dfe05 | 2011-04-15 10:42:59 +0300 | [diff] [blame] | 1257 | /* DSI-PLL power command 0x3 is not working */ |
| 1258 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && |
| 1259 | state == DSI_PLL_POWER_ON_DIV) |
| 1260 | state = DSI_PLL_POWER_ON_ALL; |
| 1261 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1262 | /* PLL_PWR_CMD */ |
| 1263 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1264 | |
| 1265 | /* PLL_PWR_STATUS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1266 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1267 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1268 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
| 1269 | state); |
| 1270 | return -ENODEV; |
| 1271 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1272 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1273 | } |
| 1274 | |
| 1275 | return 0; |
| 1276 | } |
| 1277 | |
| 1278 | /* calculate clock rates using dividers in cinfo */ |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1279 | static int dsi_calc_clock_rates(struct platform_device *dsidev, |
Sumit Semwal | ff1b2cd | 2010-12-02 11:27:11 +0000 | [diff] [blame] | 1280 | struct dsi_clock_info *cinfo) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1281 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1282 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1283 | |
| 1284 | if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1285 | return -EINVAL; |
| 1286 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1287 | if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1288 | return -EINVAL; |
| 1289 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1290 | if (cinfo->regm_dispc > dsi->regm_dispc_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1291 | return -EINVAL; |
| 1292 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1293 | if (cinfo->regm_dsi > dsi->regm_dsi_max) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1294 | return -EINVAL; |
| 1295 | |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1296 | cinfo->clkin = clk_get_rate(dsi->sys_clk); |
| 1297 | cinfo->fint = cinfo->clkin / cinfo->regn; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1298 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1299 | if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1300 | return -EINVAL; |
| 1301 | |
| 1302 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; |
| 1303 | |
| 1304 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) |
| 1305 | return -EINVAL; |
| 1306 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1307 | if (cinfo->regm_dispc > 0) |
| 1308 | cinfo->dsi_pll_hsdiv_dispc_clk = |
| 1309 | cinfo->clkin4ddr / cinfo->regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1310 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1311 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1312 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1313 | if (cinfo->regm_dsi > 0) |
| 1314 | cinfo->dsi_pll_hsdiv_dsi_clk = |
| 1315 | cinfo->clkin4ddr / cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1316 | else |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1317 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1318 | |
| 1319 | return 0; |
| 1320 | } |
| 1321 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1322 | int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, |
| 1323 | unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1324 | struct dispc_clock_info *dispc_cinfo) |
| 1325 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1326 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1327 | struct dsi_clock_info cur, best; |
| 1328 | struct dispc_clock_info best_dispc; |
| 1329 | int min_fck_per_pck; |
| 1330 | int match = 0; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1331 | unsigned long dss_sys_clk, max_dss_fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1332 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1333 | dss_sys_clk = clk_get_rate(dsi->sys_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1334 | |
Taneja, Archit | 31ef823 | 2011-03-14 23:28:22 -0500 | [diff] [blame] | 1335 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 1336 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1337 | if (req_pck == dsi->cache_req_pck && |
| 1338 | dsi->cache_cinfo.clkin == dss_sys_clk) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1339 | DSSDBG("DSI clock info found from cache\n"); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1340 | *dsi_cinfo = dsi->cache_cinfo; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1341 | dispc_find_clk_divs(is_tft, req_pck, |
| 1342 | dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1343 | return 0; |
| 1344 | } |
| 1345 | |
| 1346 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; |
| 1347 | |
| 1348 | if (min_fck_per_pck && |
Archit Taneja | 819d807 | 2011-03-01 11:54:00 +0530 | [diff] [blame] | 1349 | req_pck * min_fck_per_pck > max_dss_fck) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1350 | DSSERR("Requested pixel clock not possible with the current " |
| 1351 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " |
| 1352 | "the constraint off.\n"); |
| 1353 | min_fck_per_pck = 0; |
| 1354 | } |
| 1355 | |
| 1356 | DSSDBG("dsi_pll_calc\n"); |
| 1357 | |
| 1358 | retry: |
| 1359 | memset(&best, 0, sizeof(best)); |
| 1360 | memset(&best_dispc, 0, sizeof(best_dispc)); |
| 1361 | |
| 1362 | memset(&cur, 0, sizeof(cur)); |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1363 | cur.clkin = dss_sys_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1364 | |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1365 | /* 0.75MHz < Fint = clkin / regn < 2.1MHz */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1366 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1367 | for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) { |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1368 | cur.fint = cur.clkin / cur.regn; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1369 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1370 | if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1371 | continue; |
| 1372 | |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1373 | /* DSIPHY(MHz) = (2 * regm / regn) * clkin */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1374 | for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1375 | unsigned long a, b; |
| 1376 | |
| 1377 | a = 2 * cur.regm * (cur.clkin/1000); |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1378 | b = cur.regn; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1379 | cur.clkin4ddr = a / b * 1000; |
| 1380 | |
| 1381 | if (cur.clkin4ddr > 1800 * 1000 * 1000) |
| 1382 | break; |
| 1383 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1384 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
| 1385 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1386 | for (cur.regm_dispc = 1; cur.regm_dispc < |
| 1387 | dsi->regm_dispc_max; ++cur.regm_dispc) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1388 | struct dispc_clock_info cur_dispc; |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1389 | cur.dsi_pll_hsdiv_dispc_clk = |
| 1390 | cur.clkin4ddr / cur.regm_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1391 | |
| 1392 | /* this will narrow down the search a bit, |
| 1393 | * but still give pixclocks below what was |
| 1394 | * requested */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1395 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1396 | break; |
| 1397 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1398 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1399 | continue; |
| 1400 | |
| 1401 | if (min_fck_per_pck && |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1402 | cur.dsi_pll_hsdiv_dispc_clk < |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1403 | req_pck * min_fck_per_pck) |
| 1404 | continue; |
| 1405 | |
| 1406 | match = 1; |
| 1407 | |
| 1408 | dispc_find_clk_divs(is_tft, req_pck, |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1409 | cur.dsi_pll_hsdiv_dispc_clk, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1410 | &cur_dispc); |
| 1411 | |
| 1412 | if (abs(cur_dispc.pck - req_pck) < |
| 1413 | abs(best_dispc.pck - req_pck)) { |
| 1414 | best = cur; |
| 1415 | best_dispc = cur_dispc; |
| 1416 | |
| 1417 | if (cur_dispc.pck == req_pck) |
| 1418 | goto found; |
| 1419 | } |
| 1420 | } |
| 1421 | } |
| 1422 | } |
| 1423 | found: |
| 1424 | if (!match) { |
| 1425 | if (min_fck_per_pck) { |
| 1426 | DSSERR("Could not find suitable clock settings.\n" |
| 1427 | "Turning FCK/PCK constraint off and" |
| 1428 | "trying again.\n"); |
| 1429 | min_fck_per_pck = 0; |
| 1430 | goto retry; |
| 1431 | } |
| 1432 | |
| 1433 | DSSERR("Could not find suitable clock settings.\n"); |
| 1434 | |
| 1435 | return -EINVAL; |
| 1436 | } |
| 1437 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1438 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
| 1439 | best.regm_dsi = 0; |
| 1440 | best.dsi_pll_hsdiv_dsi_clk = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1441 | |
| 1442 | if (dsi_cinfo) |
| 1443 | *dsi_cinfo = best; |
| 1444 | if (dispc_cinfo) |
| 1445 | *dispc_cinfo = best_dispc; |
| 1446 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1447 | dsi->cache_req_pck = req_pck; |
| 1448 | dsi->cache_clk_freq = 0; |
| 1449 | dsi->cache_cinfo = best; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1450 | |
| 1451 | return 0; |
| 1452 | } |
| 1453 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1454 | int dsi_pll_set_clock_div(struct platform_device *dsidev, |
| 1455 | struct dsi_clock_info *cinfo) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1456 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1457 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1458 | int r = 0; |
| 1459 | u32 l; |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1460 | int f = 0; |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1461 | u8 regn_start, regn_end, regm_start, regm_end; |
| 1462 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1463 | |
| 1464 | DSSDBGF(); |
| 1465 | |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1466 | dsi->current_cinfo.clkin = cinfo->clkin; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1467 | dsi->current_cinfo.fint = cinfo->fint; |
| 1468 | dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; |
| 1469 | dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1470 | cinfo->dsi_pll_hsdiv_dispc_clk; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1471 | dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk = |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1472 | cinfo->dsi_pll_hsdiv_dsi_clk; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1473 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1474 | dsi->current_cinfo.regn = cinfo->regn; |
| 1475 | dsi->current_cinfo.regm = cinfo->regm; |
| 1476 | dsi->current_cinfo.regm_dispc = cinfo->regm_dispc; |
| 1477 | dsi->current_cinfo.regm_dsi = cinfo->regm_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1478 | |
| 1479 | DSSDBG("DSI Fint %ld\n", cinfo->fint); |
| 1480 | |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1481 | DSSDBG("clkin rate %ld\n", cinfo->clkin); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1482 | |
| 1483 | /* DSIPHY == CLKIN4DDR */ |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1484 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1485 | cinfo->regm, |
| 1486 | cinfo->regn, |
| 1487 | cinfo->clkin, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1488 | cinfo->clkin4ddr); |
| 1489 | |
| 1490 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", |
| 1491 | cinfo->clkin4ddr / 1000 / 1000 / 2); |
| 1492 | |
| 1493 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); |
| 1494 | |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1495 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1496 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 1497 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1498 | cinfo->dsi_pll_hsdiv_dispc_clk); |
| 1499 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1500 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 1501 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1502 | cinfo->dsi_pll_hsdiv_dsi_clk); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1503 | |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1504 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
| 1505 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); |
| 1506 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, |
| 1507 | ®m_dispc_end); |
| 1508 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, |
| 1509 | ®m_dsi_end); |
| 1510 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1511 | /* DSI_PLL_AUTOMODE = manual */ |
| 1512 | REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1513 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1514 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1515 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1516 | /* DSI_PLL_REGN */ |
| 1517 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); |
| 1518 | /* DSI_PLL_REGM */ |
| 1519 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); |
| 1520 | /* DSI_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1521 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1522 | regm_dispc_start, regm_dispc_end); |
| 1523 | /* DSIPROTO_CLOCK_DIV */ |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1524 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 1525 | regm_dsi_start, regm_dsi_end); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1526 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1527 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1528 | BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1529 | |
| 1530 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { |
| 1531 | f = cinfo->fint < 1000000 ? 0x3 : |
| 1532 | cinfo->fint < 1250000 ? 0x4 : |
| 1533 | cinfo->fint < 1500000 ? 0x5 : |
| 1534 | cinfo->fint < 1750000 ? 0x6 : |
| 1535 | 0x7; |
| 1536 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1537 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1538 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 1539 | |
| 1540 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) |
| 1541 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1542 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1543 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ |
| 1544 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1545 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1546 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1547 | REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1548 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1549 | if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1550 | DSSERR("dsi pll go bit not going down.\n"); |
| 1551 | r = -EIO; |
| 1552 | goto err; |
| 1553 | } |
| 1554 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1555 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1556 | DSSERR("cannot lock PLL\n"); |
| 1557 | r = -EIO; |
| 1558 | goto err; |
| 1559 | } |
| 1560 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1561 | dsi->pll_locked = 1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1562 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1563 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1564 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
| 1565 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ |
| 1566 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ |
| 1567 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ |
| 1568 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ |
| 1569 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ |
| 1570 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
| 1571 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ |
| 1572 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ |
| 1573 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ |
| 1574 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ |
| 1575 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ |
| 1576 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ |
| 1577 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1578 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1579 | |
| 1580 | DSSDBG("PLL config done\n"); |
| 1581 | err: |
| 1582 | return r; |
| 1583 | } |
| 1584 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1585 | int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, |
| 1586 | bool enable_hsdiv) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1587 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1588 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1589 | int r = 0; |
| 1590 | enum dsi_pll_power_state pwstate; |
| 1591 | |
| 1592 | DSSDBG("PLL init\n"); |
| 1593 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1594 | if (dsi->vdds_dsi_reg == NULL) { |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1595 | struct regulator *vdds_dsi; |
| 1596 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1597 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1598 | |
| 1599 | if (IS_ERR(vdds_dsi)) { |
| 1600 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 1601 | return PTR_ERR(vdds_dsi); |
| 1602 | } |
| 1603 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1604 | dsi->vdds_dsi_reg = vdds_dsi; |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1605 | } |
Tomi Valkeinen | f2988ab | 2011-03-02 10:06:48 +0200 | [diff] [blame] | 1606 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1607 | dsi_enable_pll_clock(dsidev, 1); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1608 | /* |
| 1609 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. |
| 1610 | */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1611 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1612 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1613 | if (!dsi->vdds_dsi_enabled) { |
| 1614 | r = regulator_enable(dsi->vdds_dsi_reg); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1615 | if (r) |
| 1616 | goto err0; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1617 | dsi->vdds_dsi_enabled = true; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1618 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1619 | |
| 1620 | /* XXX PLL does not come out of reset without this... */ |
| 1621 | dispc_pck_free_enable(1); |
| 1622 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1623 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1624 | DSSERR("PLL not coming out of reset.\n"); |
| 1625 | r = -ENODEV; |
Ville Syrjälä | 481dfa0 | 2010-04-22 22:50:04 +0200 | [diff] [blame] | 1626 | dispc_pck_free_enable(0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1627 | goto err1; |
| 1628 | } |
| 1629 | |
| 1630 | /* XXX ... but if left on, we get problems when planes do not |
| 1631 | * fill the whole display. No idea about this */ |
| 1632 | dispc_pck_free_enable(0); |
| 1633 | |
| 1634 | if (enable_hsclk && enable_hsdiv) |
| 1635 | pwstate = DSI_PLL_POWER_ON_ALL; |
| 1636 | else if (enable_hsclk) |
| 1637 | pwstate = DSI_PLL_POWER_ON_HSCLK; |
| 1638 | else if (enable_hsdiv) |
| 1639 | pwstate = DSI_PLL_POWER_ON_DIV; |
| 1640 | else |
| 1641 | pwstate = DSI_PLL_POWER_OFF; |
| 1642 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1643 | r = dsi_pll_power(dsidev, pwstate); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1644 | |
| 1645 | if (r) |
| 1646 | goto err1; |
| 1647 | |
| 1648 | DSSDBG("PLL init done\n"); |
| 1649 | |
| 1650 | return 0; |
| 1651 | err1: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1652 | if (dsi->vdds_dsi_enabled) { |
| 1653 | regulator_disable(dsi->vdds_dsi_reg); |
| 1654 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1655 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1656 | err0: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1657 | dsi_disable_scp_clk(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1658 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1659 | return r; |
| 1660 | } |
| 1661 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1662 | void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1663 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1664 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1665 | |
| 1666 | dsi->pll_locked = 0; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1667 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1668 | if (disconnect_lanes) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1669 | WARN_ON(!dsi->vdds_dsi_enabled); |
| 1670 | regulator_disable(dsi->vdds_dsi_reg); |
| 1671 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 1672 | } |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1673 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1674 | dsi_disable_scp_clk(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1675 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 24c1ae4 | 2011-04-13 17:12:52 +0300 | [diff] [blame] | 1676 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1677 | DSSDBG("PLL uninit done\n"); |
| 1678 | } |
| 1679 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1680 | static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, |
| 1681 | struct seq_file *s) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1682 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1683 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 1684 | struct dsi_clock_info *cinfo = &dsi->current_cinfo; |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1685 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1686 | int dsi_module = dsi_get_dsidev_id(dsidev); |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1687 | |
| 1688 | dispc_clk_src = dss_get_dispc_clk_source(); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1689 | dsi_clk_src = dss_get_dsi_clk_source(dsi_module); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1690 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1691 | if (dsi_runtime_get(dsidev)) |
| 1692 | return; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1693 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1694 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1695 | |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 1696 | seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1697 | |
| 1698 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); |
| 1699 | |
| 1700 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", |
| 1701 | cinfo->clkin4ddr, cinfo->regm); |
| 1702 | |
Archit Taneja | 84309f1 | 2011-12-12 11:47:41 +0530 | [diff] [blame] | 1703 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n", |
| 1704 | dss_feat_get_clk_source_name(dsi_module == 0 ? |
| 1705 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : |
| 1706 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1707 | cinfo->dsi_pll_hsdiv_dispc_clk, |
| 1708 | cinfo->regm_dispc, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1709 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1710 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1711 | |
Archit Taneja | 84309f1 | 2011-12-12 11:47:41 +0530 | [diff] [blame] | 1712 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n", |
| 1713 | dss_feat_get_clk_source_name(dsi_module == 0 ? |
| 1714 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : |
| 1715 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), |
Archit Taneja | 1bb4783 | 2011-02-24 14:17:30 +0530 | [diff] [blame] | 1716 | cinfo->dsi_pll_hsdiv_dsi_clk, |
| 1717 | cinfo->regm_dsi, |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 1718 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
Tomi Valkeinen | 63cf28a | 2010-02-23 17:40:00 +0200 | [diff] [blame] | 1719 | "off" : "on"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1720 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1721 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1722 | |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 1723 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
| 1724 | dss_get_generic_clk_source_name(dsi_clk_src), |
| 1725 | dss_feat_get_clk_source_name(dsi_clk_src)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1726 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1727 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1728 | |
| 1729 | seq_printf(s, "DDR_CLK\t\t%lu\n", |
| 1730 | cinfo->clkin4ddr / 4); |
| 1731 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1732 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1733 | |
| 1734 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); |
| 1735 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1736 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1737 | } |
| 1738 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1739 | void dsi_dump_clocks(struct seq_file *s) |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1740 | { |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1741 | struct platform_device *dsidev; |
| 1742 | int i; |
| 1743 | |
| 1744 | for (i = 0; i < MAX_NUM_DSI; i++) { |
| 1745 | dsidev = dsi_get_dsidev_from_id(i); |
| 1746 | if (dsidev) |
| 1747 | dsi_dump_dsidev_clocks(dsidev, s); |
| 1748 | } |
| 1749 | } |
| 1750 | |
| 1751 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 1752 | static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, |
| 1753 | struct seq_file *s) |
| 1754 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1755 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1756 | unsigned long flags; |
| 1757 | struct dsi_irq_stats stats; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1758 | int dsi_module = dsi_get_dsidev_id(dsidev); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1759 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1760 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1761 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1762 | stats = dsi->irq_stats; |
| 1763 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); |
| 1764 | dsi->irq_stats.last_reset = jiffies; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1765 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 1766 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1767 | |
| 1768 | seq_printf(s, "period %u ms\n", |
| 1769 | jiffies_to_msecs(jiffies - stats.last_reset)); |
| 1770 | |
| 1771 | seq_printf(s, "irqs %d\n", stats.irq_count); |
| 1772 | #define PIS(x) \ |
| 1773 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); |
| 1774 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1775 | seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1); |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1776 | PIS(VC0); |
| 1777 | PIS(VC1); |
| 1778 | PIS(VC2); |
| 1779 | PIS(VC3); |
| 1780 | PIS(WAKEUP); |
| 1781 | PIS(RESYNC); |
| 1782 | PIS(PLL_LOCK); |
| 1783 | PIS(PLL_UNLOCK); |
| 1784 | PIS(PLL_RECALL); |
| 1785 | PIS(COMPLEXIO_ERR); |
| 1786 | PIS(HS_TX_TIMEOUT); |
| 1787 | PIS(LP_RX_TIMEOUT); |
| 1788 | PIS(TE_TRIGGER); |
| 1789 | PIS(ACK_TRIGGER); |
| 1790 | PIS(SYNC_LOST); |
| 1791 | PIS(LDO_POWER_GOOD); |
| 1792 | PIS(TA_TIMEOUT); |
| 1793 | #undef PIS |
| 1794 | |
| 1795 | #define PIS(x) \ |
| 1796 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ |
| 1797 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1798 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1799 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ |
| 1800 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); |
| 1801 | |
| 1802 | seq_printf(s, "-- VC interrupts --\n"); |
| 1803 | PIS(CS); |
| 1804 | PIS(ECC_CORR); |
| 1805 | PIS(PACKET_SENT); |
| 1806 | PIS(FIFO_TX_OVF); |
| 1807 | PIS(FIFO_RX_OVF); |
| 1808 | PIS(BTA); |
| 1809 | PIS(ECC_NO_CORR); |
| 1810 | PIS(FIFO_TX_UDF); |
| 1811 | PIS(PP_BUSY_CHANGE); |
| 1812 | #undef PIS |
| 1813 | |
| 1814 | #define PIS(x) \ |
| 1815 | seq_printf(s, "%-20s %10d\n", #x, \ |
| 1816 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); |
| 1817 | |
| 1818 | seq_printf(s, "-- CIO interrupts --\n"); |
| 1819 | PIS(ERRSYNCESC1); |
| 1820 | PIS(ERRSYNCESC2); |
| 1821 | PIS(ERRSYNCESC3); |
| 1822 | PIS(ERRESC1); |
| 1823 | PIS(ERRESC2); |
| 1824 | PIS(ERRESC3); |
| 1825 | PIS(ERRCONTROL1); |
| 1826 | PIS(ERRCONTROL2); |
| 1827 | PIS(ERRCONTROL3); |
| 1828 | PIS(STATEULPS1); |
| 1829 | PIS(STATEULPS2); |
| 1830 | PIS(STATEULPS3); |
| 1831 | PIS(ERRCONTENTIONLP0_1); |
| 1832 | PIS(ERRCONTENTIONLP1_1); |
| 1833 | PIS(ERRCONTENTIONLP0_2); |
| 1834 | PIS(ERRCONTENTIONLP1_2); |
| 1835 | PIS(ERRCONTENTIONLP0_3); |
| 1836 | PIS(ERRCONTENTIONLP1_3); |
| 1837 | PIS(ULPSACTIVENOT_ALL0); |
| 1838 | PIS(ULPSACTIVENOT_ALL1); |
| 1839 | #undef PIS |
| 1840 | } |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 1841 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1842 | static void dsi1_dump_irqs(struct seq_file *s) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1843 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1844 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
| 1845 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1846 | dsi_dump_dsidev_irqs(dsidev, s); |
| 1847 | } |
| 1848 | |
| 1849 | static void dsi2_dump_irqs(struct seq_file *s) |
| 1850 | { |
| 1851 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); |
| 1852 | |
| 1853 | dsi_dump_dsidev_irqs(dsidev, s); |
| 1854 | } |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1855 | #endif |
| 1856 | |
| 1857 | static void dsi_dump_dsidev_regs(struct platform_device *dsidev, |
| 1858 | struct seq_file *s) |
| 1859 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1860 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1861 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1862 | if (dsi_runtime_get(dsidev)) |
| 1863 | return; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1864 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1865 | |
| 1866 | DUMPREG(DSI_REVISION); |
| 1867 | DUMPREG(DSI_SYSCONFIG); |
| 1868 | DUMPREG(DSI_SYSSTATUS); |
| 1869 | DUMPREG(DSI_IRQSTATUS); |
| 1870 | DUMPREG(DSI_IRQENABLE); |
| 1871 | DUMPREG(DSI_CTRL); |
| 1872 | DUMPREG(DSI_COMPLEXIO_CFG1); |
| 1873 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); |
| 1874 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); |
| 1875 | DUMPREG(DSI_CLK_CTRL); |
| 1876 | DUMPREG(DSI_TIMING1); |
| 1877 | DUMPREG(DSI_TIMING2); |
| 1878 | DUMPREG(DSI_VM_TIMING1); |
| 1879 | DUMPREG(DSI_VM_TIMING2); |
| 1880 | DUMPREG(DSI_VM_TIMING3); |
| 1881 | DUMPREG(DSI_CLK_TIMING); |
| 1882 | DUMPREG(DSI_TX_FIFO_VC_SIZE); |
| 1883 | DUMPREG(DSI_RX_FIFO_VC_SIZE); |
| 1884 | DUMPREG(DSI_COMPLEXIO_CFG2); |
| 1885 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); |
| 1886 | DUMPREG(DSI_VM_TIMING4); |
| 1887 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); |
| 1888 | DUMPREG(DSI_VM_TIMING5); |
| 1889 | DUMPREG(DSI_VM_TIMING6); |
| 1890 | DUMPREG(DSI_VM_TIMING7); |
| 1891 | DUMPREG(DSI_STOPCLK_TIMING); |
| 1892 | |
| 1893 | DUMPREG(DSI_VC_CTRL(0)); |
| 1894 | DUMPREG(DSI_VC_TE(0)); |
| 1895 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); |
| 1896 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); |
| 1897 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); |
| 1898 | DUMPREG(DSI_VC_IRQSTATUS(0)); |
| 1899 | DUMPREG(DSI_VC_IRQENABLE(0)); |
| 1900 | |
| 1901 | DUMPREG(DSI_VC_CTRL(1)); |
| 1902 | DUMPREG(DSI_VC_TE(1)); |
| 1903 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); |
| 1904 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); |
| 1905 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); |
| 1906 | DUMPREG(DSI_VC_IRQSTATUS(1)); |
| 1907 | DUMPREG(DSI_VC_IRQENABLE(1)); |
| 1908 | |
| 1909 | DUMPREG(DSI_VC_CTRL(2)); |
| 1910 | DUMPREG(DSI_VC_TE(2)); |
| 1911 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); |
| 1912 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); |
| 1913 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); |
| 1914 | DUMPREG(DSI_VC_IRQSTATUS(2)); |
| 1915 | DUMPREG(DSI_VC_IRQENABLE(2)); |
| 1916 | |
| 1917 | DUMPREG(DSI_VC_CTRL(3)); |
| 1918 | DUMPREG(DSI_VC_TE(3)); |
| 1919 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); |
| 1920 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); |
| 1921 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); |
| 1922 | DUMPREG(DSI_VC_IRQSTATUS(3)); |
| 1923 | DUMPREG(DSI_VC_IRQENABLE(3)); |
| 1924 | |
| 1925 | DUMPREG(DSI_DSIPHY_CFG0); |
| 1926 | DUMPREG(DSI_DSIPHY_CFG1); |
| 1927 | DUMPREG(DSI_DSIPHY_CFG2); |
| 1928 | DUMPREG(DSI_DSIPHY_CFG5); |
| 1929 | |
| 1930 | DUMPREG(DSI_PLL_CONTROL); |
| 1931 | DUMPREG(DSI_PLL_STATUS); |
| 1932 | DUMPREG(DSI_PLL_GO); |
| 1933 | DUMPREG(DSI_PLL_CONFIGURATION1); |
| 1934 | DUMPREG(DSI_PLL_CONFIGURATION2); |
| 1935 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1936 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 1937 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1938 | #undef DUMPREG |
| 1939 | } |
| 1940 | |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 1941 | static void dsi1_dump_regs(struct seq_file *s) |
| 1942 | { |
| 1943 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
| 1944 | |
| 1945 | dsi_dump_dsidev_regs(dsidev, s); |
| 1946 | } |
| 1947 | |
| 1948 | static void dsi2_dump_regs(struct seq_file *s) |
| 1949 | { |
| 1950 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); |
| 1951 | |
| 1952 | dsi_dump_dsidev_regs(dsidev, s); |
| 1953 | } |
| 1954 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 1955 | enum dsi_cio_power_state { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1956 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
| 1957 | DSI_COMPLEXIO_POWER_ON = 0x1, |
| 1958 | DSI_COMPLEXIO_POWER_ULPS = 0x2, |
| 1959 | }; |
| 1960 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1961 | static int dsi_cio_power(struct platform_device *dsidev, |
| 1962 | enum dsi_cio_power_state state) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1963 | { |
| 1964 | int t = 0; |
| 1965 | |
| 1966 | /* PWR_CMD */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1967 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1968 | |
| 1969 | /* PWR_STATUS */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 1970 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), |
| 1971 | 26, 25) != state) { |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1972 | if (++t > 1000) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1973 | DSSERR("failed to set complexio power state to " |
| 1974 | "%d\n", state); |
| 1975 | return -ENODEV; |
| 1976 | } |
Tomi Valkeinen | 24be78b | 2010-01-07 14:19:48 +0200 | [diff] [blame] | 1977 | udelay(1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 1978 | } |
| 1979 | |
| 1980 | return 0; |
| 1981 | } |
| 1982 | |
Archit Taneja | 0c65622b | 2011-05-16 15:17:09 +0530 | [diff] [blame] | 1983 | static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) |
| 1984 | { |
| 1985 | int val; |
| 1986 | |
| 1987 | /* line buffer on OMAP3 is 1024 x 24bits */ |
| 1988 | /* XXX: for some reason using full buffer size causes |
| 1989 | * considerable TX slowdown with update sizes that fill the |
| 1990 | * whole buffer */ |
| 1991 | if (!dss_has_feature(FEAT_DSI_GNQ)) |
| 1992 | return 1023 * 3; |
| 1993 | |
| 1994 | val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ |
| 1995 | |
| 1996 | switch (val) { |
| 1997 | case 1: |
| 1998 | return 512 * 3; /* 512x24 bits */ |
| 1999 | case 2: |
| 2000 | return 682 * 3; /* 682x24 bits */ |
| 2001 | case 3: |
| 2002 | return 853 * 3; /* 853x24 bits */ |
| 2003 | case 4: |
| 2004 | return 1024 * 3; /* 1024x24 bits */ |
| 2005 | case 5: |
| 2006 | return 1194 * 3; /* 1194x24 bits */ |
| 2007 | case 6: |
| 2008 | return 1365 * 3; /* 1365x24 bits */ |
| 2009 | default: |
| 2010 | BUG(); |
| 2011 | } |
| 2012 | } |
| 2013 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2014 | static int dsi_set_lane_config(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2015 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2016 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2017 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2018 | static const u8 offsets[] = { 0, 4, 8, 12, 16 }; |
| 2019 | static const enum dsi_lane_function functions[] = { |
| 2020 | DSI_LANE_CLK, |
| 2021 | DSI_LANE_DATA1, |
| 2022 | DSI_LANE_DATA2, |
| 2023 | DSI_LANE_DATA3, |
| 2024 | DSI_LANE_DATA4, |
| 2025 | }; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2026 | u32 r; |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2027 | int i; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2028 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2029 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2030 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2031 | for (i = 0; i < dsi->num_lanes_used; ++i) { |
| 2032 | unsigned offset = offsets[i]; |
| 2033 | unsigned polarity, lane_number; |
| 2034 | unsigned t; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2035 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2036 | for (t = 0; t < dsi->num_lanes_supported; ++t) |
| 2037 | if (dsi->lanes[t].function == functions[i]) |
| 2038 | break; |
| 2039 | |
| 2040 | if (t == dsi->num_lanes_supported) |
| 2041 | return -EINVAL; |
| 2042 | |
| 2043 | lane_number = t; |
| 2044 | polarity = dsi->lanes[t].polarity; |
| 2045 | |
| 2046 | r = FLD_MOD(r, lane_number + 1, offset + 2, offset); |
| 2047 | r = FLD_MOD(r, polarity, offset + 3, offset + 3); |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2048 | } |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2049 | |
| 2050 | /* clear the unused lanes */ |
| 2051 | for (; i < dsi->num_lanes_supported; ++i) { |
| 2052 | unsigned offset = offsets[i]; |
| 2053 | |
| 2054 | r = FLD_MOD(r, 0, offset + 2, offset); |
| 2055 | r = FLD_MOD(r, 0, offset + 3, offset + 3); |
| 2056 | } |
| 2057 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2058 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2059 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2060 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2061 | } |
| 2062 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2063 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2064 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2065 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2066 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2067 | /* convert time in ns to ddr ticks, rounding up */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2068 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2069 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
| 2070 | } |
| 2071 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2072 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2073 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2074 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2075 | |
| 2076 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2077 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
| 2078 | } |
| 2079 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2080 | static void dsi_cio_timings(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2081 | { |
| 2082 | u32 r; |
| 2083 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; |
| 2084 | u32 tlpx_half, tclk_trail, tclk_zero; |
| 2085 | u32 tclk_prepare; |
| 2086 | |
| 2087 | /* calculate timings */ |
| 2088 | |
| 2089 | /* 1 * DDR_CLK = 2 * UI */ |
| 2090 | |
| 2091 | /* min 40ns + 4*UI max 85ns + 6*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2092 | ths_prepare = ns2ddr(dsidev, 70) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2093 | |
| 2094 | /* min 145ns + 10*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2095 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2096 | |
| 2097 | /* min max(8*UI, 60ns+4*UI) */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2098 | ths_trail = ns2ddr(dsidev, 60) + 5; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2099 | |
| 2100 | /* min 100ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2101 | ths_exit = ns2ddr(dsidev, 145); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2102 | |
| 2103 | /* tlpx min 50n */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2104 | tlpx_half = ns2ddr(dsidev, 25); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2105 | |
| 2106 | /* min 60ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2107 | tclk_trail = ns2ddr(dsidev, 60) + 2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2108 | |
| 2109 | /* min 38ns, max 95ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2110 | tclk_prepare = ns2ddr(dsidev, 65); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2111 | |
| 2112 | /* min tclk-prepare + tclk-zero = 300ns */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2113 | tclk_zero = ns2ddr(dsidev, 260); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2114 | |
| 2115 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2116 | ths_prepare, ddr2ns(dsidev, ths_prepare), |
| 2117 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2118 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2119 | ths_trail, ddr2ns(dsidev, ths_trail), |
| 2120 | ths_exit, ddr2ns(dsidev, ths_exit)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2121 | |
| 2122 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " |
| 2123 | "tclk_zero %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2124 | tlpx_half, ddr2ns(dsidev, tlpx_half), |
| 2125 | tclk_trail, ddr2ns(dsidev, tclk_trail), |
| 2126 | tclk_zero, ddr2ns(dsidev, tclk_zero)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2127 | DSSDBG("tclk_prepare %u (%uns)\n", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2128 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2129 | |
| 2130 | /* program timings */ |
| 2131 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2132 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2133 | r = FLD_MOD(r, ths_prepare, 31, 24); |
| 2134 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); |
| 2135 | r = FLD_MOD(r, ths_trail, 15, 8); |
| 2136 | r = FLD_MOD(r, ths_exit, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2137 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2138 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2139 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2140 | r = FLD_MOD(r, tlpx_half, 22, 16); |
| 2141 | r = FLD_MOD(r, tclk_trail, 15, 8); |
| 2142 | r = FLD_MOD(r, tclk_zero, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2143 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2144 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2145 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2146 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2147 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2148 | } |
| 2149 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2150 | /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2151 | static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2152 | unsigned mask_p, unsigned mask_n) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2153 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2154 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2155 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2156 | int i; |
| 2157 | u32 l; |
Tomi Valkeinen | d982085 | 2011-10-12 15:05:59 +0300 | [diff] [blame] | 2158 | u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2159 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2160 | l = 0; |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2161 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2162 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2163 | unsigned p = dsi->lanes[i].polarity; |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2164 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2165 | if (mask_p & (1 << i)) |
| 2166 | l |= 1 << (i * 2 + (p ? 0 : 1)); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2167 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2168 | if (mask_n & (1 << i)) |
| 2169 | l |= 1 << (i * 2 + (p ? 1 : 0)); |
| 2170 | } |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2171 | |
| 2172 | /* |
| 2173 | * Bits in REGLPTXSCPDAT4TO0DXDY: |
| 2174 | * 17: DY0 18: DX0 |
| 2175 | * 19: DY1 20: DX1 |
| 2176 | * 21: DY2 22: DX2 |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2177 | * 23: DY3 24: DX3 |
| 2178 | * 25: DY4 26: DX4 |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2179 | */ |
| 2180 | |
| 2181 | /* Set the lane override configuration */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2182 | |
| 2183 | /* REGLPTXSCPDAT4TO0DXDY */ |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2184 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2185 | |
| 2186 | /* Enable lane override */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2187 | |
| 2188 | /* ENLPTXSCPDAT */ |
| 2189 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2190 | } |
| 2191 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2192 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2193 | { |
| 2194 | /* Disable lane override */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2195 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2196 | /* Reset the lane override configuration */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2197 | /* REGLPTXSCPDAT4TO0DXDY */ |
| 2198 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); |
Tomi Valkeinen | 0a0ee46 | 2010-07-27 11:11:48 +0300 | [diff] [blame] | 2199 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2200 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2201 | static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev) |
| 2202 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2203 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2204 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2205 | int t, i; |
| 2206 | bool in_use[DSI_MAX_NR_LANES]; |
| 2207 | static const u8 offsets_old[] = { 28, 27, 26 }; |
| 2208 | static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; |
| 2209 | const u8 *offsets; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2210 | |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2211 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) |
| 2212 | offsets = offsets_old; |
| 2213 | else |
| 2214 | offsets = offsets_new; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2215 | |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2216 | for (i = 0; i < dsi->num_lanes_supported; ++i) |
| 2217 | in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2218 | |
| 2219 | t = 100000; |
| 2220 | while (true) { |
| 2221 | u32 l; |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2222 | int ok; |
| 2223 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2224 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2225 | |
| 2226 | ok = 0; |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2227 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2228 | if (!in_use[i] || (l & (1 << offsets[i]))) |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2229 | ok++; |
| 2230 | } |
| 2231 | |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2232 | if (ok == dsi->num_lanes_supported) |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2233 | break; |
| 2234 | |
| 2235 | if (--t == 0) { |
Tomi Valkeinen | 8dc0766 | 2011-10-13 15:26:50 +0300 | [diff] [blame] | 2236 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2237 | if (!in_use[i] || (l & (1 << offsets[i]))) |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2238 | continue; |
| 2239 | |
| 2240 | DSSERR("CIO TXCLKESC%d domain not coming " \ |
| 2241 | "out of reset\n", i); |
| 2242 | } |
| 2243 | return -EIO; |
| 2244 | } |
| 2245 | } |
| 2246 | |
| 2247 | return 0; |
| 2248 | } |
| 2249 | |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2250 | /* return bitmask of enabled lanes, lane0 being the lsb */ |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2251 | static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev) |
| 2252 | { |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2253 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 2254 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2255 | unsigned mask = 0; |
| 2256 | int i; |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2257 | |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2258 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2259 | if (dsi->lanes[i].function != DSI_LANE_UNUSED) |
| 2260 | mask |= 1 << i; |
| 2261 | } |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2262 | |
Tomi Valkeinen | 85f17e8 | 2011-10-13 15:12:23 +0300 | [diff] [blame] | 2263 | return mask; |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2264 | } |
| 2265 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2266 | static int dsi_cio_init(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2267 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2268 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2269 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2270 | int r; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2271 | u32 l; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2272 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 2273 | DSSDBGF(); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2274 | |
Tomi Valkeinen | 00928ea | 2012-02-20 11:50:06 +0200 | [diff] [blame] | 2275 | r = dss_dsi_enable_pads(dsi_get_dsidev_id(dsidev), dsi_get_lane_mask(dssdev)); |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2276 | if (r) |
| 2277 | return r; |
Tomi Valkeinen | d1f5857 | 2010-07-30 11:57:57 +0300 | [diff] [blame] | 2278 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2279 | dsi_enable_scp_clk(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2280 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2281 | /* A dummy read using the SCP interface to any DSIPHY register is |
| 2282 | * required after DSIPHY reset to complete the reset of the DSI complex |
| 2283 | * I/O. */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2284 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2285 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2286 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2287 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
| 2288 | r = -EIO; |
| 2289 | goto err_scp_clk_dom; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2290 | } |
| 2291 | |
Tomi Valkeinen | 4836839 | 2011-10-13 11:22:39 +0300 | [diff] [blame] | 2292 | r = dsi_set_lane_config(dssdev); |
| 2293 | if (r) |
| 2294 | goto err_scp_clk_dom; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2295 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2296 | /* set TX STOP MODE timer to maximum for this operation */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2297 | l = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2298 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
| 2299 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ |
| 2300 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ |
| 2301 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2302 | dsi_write_reg(dsidev, DSI_TIMING1, l); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2303 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2304 | if (dsi->ulps_enabled) { |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2305 | unsigned mask_p; |
| 2306 | int i; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2307 | |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2308 | DSSDBG("manual ulps exit\n"); |
| 2309 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2310 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
| 2311 | * stop state. DSS HW cannot do this via the normal |
| 2312 | * ULPS exit sequence, as after reset the DSS HW thinks |
| 2313 | * that we are not in ULPS mode, and refuses to send the |
| 2314 | * sequence. So we need to send the ULPS exit sequence |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2315 | * manually by setting positive lines high and negative lines |
| 2316 | * low for 1ms. |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2317 | */ |
| 2318 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2319 | mask_p = 0; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2320 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2321 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 2322 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) |
| 2323 | continue; |
| 2324 | mask_p |= 1 << i; |
| 2325 | } |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 2326 | |
Tomi Valkeinen | 9b4362f | 2011-10-13 16:06:43 +0300 | [diff] [blame] | 2327 | dsi_cio_enable_lane_override(dssdev, mask_p, 0); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2328 | } |
| 2329 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2330 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2331 | if (r) |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2332 | goto err_cio_pwr; |
| 2333 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2334 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2335 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
| 2336 | r = -ENODEV; |
| 2337 | goto err_cio_pwr_dom; |
| 2338 | } |
| 2339 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2340 | dsi_if_enable(dsidev, true); |
| 2341 | dsi_if_enable(dsidev, false); |
| 2342 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2343 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2344 | r = dsi_cio_wait_tx_clk_esc_reset(dssdev); |
| 2345 | if (r) |
| 2346 | goto err_tx_clk_esc_rst; |
| 2347 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2348 | if (dsi->ulps_enabled) { |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2349 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
| 2350 | ktime_t wait = ns_to_ktime(1000 * 1000); |
| 2351 | set_current_state(TASK_UNINTERRUPTIBLE); |
| 2352 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); |
| 2353 | |
| 2354 | /* Disable the override. The lanes should be set to Mark-11 |
| 2355 | * state by the HW */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2356 | dsi_cio_disable_lane_override(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2357 | } |
| 2358 | |
| 2359 | /* FORCE_TX_STOP_MODE_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2360 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 2361 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2362 | dsi_cio_timings(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2363 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2364 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 2365 | /* DDR_CLK_ALWAYS_ON */ |
| 2366 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, |
| 2367 | dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13); |
| 2368 | } |
| 2369 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2370 | dsi->ulps_enabled = false; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2371 | |
| 2372 | DSSDBG("CIO init done\n"); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2373 | |
| 2374 | return 0; |
| 2375 | |
Tomi Valkeinen | 03329ac | 2010-10-07 13:59:22 +0300 | [diff] [blame] | 2376 | err_tx_clk_esc_rst: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2377 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2378 | err_cio_pwr_dom: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2379 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2380 | err_cio_pwr: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2381 | if (dsi->ulps_enabled) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2382 | dsi_cio_disable_lane_override(dsidev); |
Tomi Valkeinen | 65c62bb | 2011-04-15 11:58:41 +0300 | [diff] [blame] | 2383 | err_scp_clk_dom: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2384 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | 00928ea | 2012-02-20 11:50:06 +0200 | [diff] [blame] | 2385 | dss_dsi_disable_pads(dsi_get_dsidev_id(dsidev), dsi_get_lane_mask(dssdev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2386 | return r; |
| 2387 | } |
| 2388 | |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2389 | static void dsi_cio_uninit(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2390 | { |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 2391 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2392 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2393 | /* DDR_CLK_ALWAYS_ON */ |
| 2394 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); |
| 2395 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2396 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
| 2397 | dsi_disable_scp_clk(dsidev); |
Tomi Valkeinen | 00928ea | 2012-02-20 11:50:06 +0200 | [diff] [blame] | 2398 | dss_dsi_disable_pads(dsi_get_dsidev_id(dsidev), dsi_get_lane_mask(dssdev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2399 | } |
| 2400 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2401 | static void dsi_config_tx_fifo(struct platform_device *dsidev, |
| 2402 | enum fifo_size size1, enum fifo_size size2, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2403 | enum fifo_size size3, enum fifo_size size4) |
| 2404 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2405 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2406 | u32 r = 0; |
| 2407 | int add = 0; |
| 2408 | int i; |
| 2409 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2410 | dsi->vc[0].fifo_size = size1; |
| 2411 | dsi->vc[1].fifo_size = size2; |
| 2412 | dsi->vc[2].fifo_size = size3; |
| 2413 | dsi->vc[3].fifo_size = size4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2414 | |
| 2415 | for (i = 0; i < 4; i++) { |
| 2416 | u8 v; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2417 | int size = dsi->vc[i].fifo_size; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2418 | |
| 2419 | if (add + size > 4) { |
| 2420 | DSSERR("Illegal FIFO configuration\n"); |
| 2421 | BUG(); |
| 2422 | } |
| 2423 | |
| 2424 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2425 | r |= v << (8 * i); |
| 2426 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2427 | add += size; |
| 2428 | } |
| 2429 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2430 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2431 | } |
| 2432 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2433 | static void dsi_config_rx_fifo(struct platform_device *dsidev, |
| 2434 | enum fifo_size size1, enum fifo_size size2, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2435 | enum fifo_size size3, enum fifo_size size4) |
| 2436 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2437 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2438 | u32 r = 0; |
| 2439 | int add = 0; |
| 2440 | int i; |
| 2441 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2442 | dsi->vc[0].fifo_size = size1; |
| 2443 | dsi->vc[1].fifo_size = size2; |
| 2444 | dsi->vc[2].fifo_size = size3; |
| 2445 | dsi->vc[3].fifo_size = size4; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2446 | |
| 2447 | for (i = 0; i < 4; i++) { |
| 2448 | u8 v; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2449 | int size = dsi->vc[i].fifo_size; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2450 | |
| 2451 | if (add + size > 4) { |
| 2452 | DSSERR("Illegal FIFO configuration\n"); |
| 2453 | BUG(); |
| 2454 | } |
| 2455 | |
| 2456 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); |
| 2457 | r |= v << (8 * i); |
| 2458 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ |
| 2459 | add += size; |
| 2460 | } |
| 2461 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2462 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2463 | } |
| 2464 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2465 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2466 | { |
| 2467 | u32 r; |
| 2468 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2469 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2470 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2471 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2472 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2473 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2474 | DSSERR("TX_STOP bit not going down\n"); |
| 2475 | return -EIO; |
| 2476 | } |
| 2477 | |
| 2478 | return 0; |
| 2479 | } |
| 2480 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2481 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2482 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2483 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2484 | } |
| 2485 | |
| 2486 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) |
| 2487 | { |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2488 | struct dsi_packet_sent_handler_data *vp_data = |
| 2489 | (struct dsi_packet_sent_handler_data *) data; |
| 2490 | struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2491 | const int channel = dsi->update_channel; |
| 2492 | u8 bit = dsi->te_enabled ? 30 : 31; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2493 | |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2494 | if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) |
| 2495 | complete(vp_data->completion); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2496 | } |
| 2497 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2498 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2499 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2500 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2501 | DECLARE_COMPLETION_ONSTACK(completion); |
| 2502 | struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion }; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2503 | int r = 0; |
| 2504 | u8 bit; |
| 2505 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2506 | bit = dsi->te_enabled ? 30 : 31; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2507 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2508 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2509 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2510 | if (r) |
| 2511 | goto err0; |
| 2512 | |
| 2513 | /* Wait for completion only if TE_EN/TE_START is still set */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2514 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2515 | if (wait_for_completion_timeout(&completion, |
| 2516 | msecs_to_jiffies(10)) == 0) { |
| 2517 | DSSERR("Failed to complete previous frame transfer\n"); |
| 2518 | r = -EIO; |
| 2519 | goto err1; |
| 2520 | } |
| 2521 | } |
| 2522 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2523 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2524 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2525 | |
| 2526 | return 0; |
| 2527 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2528 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2529 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2530 | err0: |
| 2531 | return r; |
| 2532 | } |
| 2533 | |
| 2534 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) |
| 2535 | { |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2536 | struct dsi_packet_sent_handler_data *l4_data = |
| 2537 | (struct dsi_packet_sent_handler_data *) data; |
| 2538 | struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2539 | const int channel = dsi->update_channel; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2540 | |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2541 | if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) |
| 2542 | complete(l4_data->completion); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2543 | } |
| 2544 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2545 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2546 | { |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2547 | DECLARE_COMPLETION_ONSTACK(completion); |
| 2548 | struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion }; |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2549 | int r = 0; |
| 2550 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2551 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2552 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2553 | if (r) |
| 2554 | goto err0; |
| 2555 | |
| 2556 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2557 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2558 | if (wait_for_completion_timeout(&completion, |
| 2559 | msecs_to_jiffies(10)) == 0) { |
| 2560 | DSSERR("Failed to complete previous l4 transfer\n"); |
| 2561 | r = -EIO; |
| 2562 | goto err1; |
| 2563 | } |
| 2564 | } |
| 2565 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2566 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2567 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2568 | |
| 2569 | return 0; |
| 2570 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2571 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
Archit Taneja | 2e868db | 2011-05-12 17:26:28 +0530 | [diff] [blame] | 2572 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2573 | err0: |
| 2574 | return r; |
| 2575 | } |
| 2576 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2577 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2578 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2579 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2580 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2581 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2582 | |
| 2583 | WARN_ON(in_interrupt()); |
| 2584 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2585 | if (!dsi_vc_is_enabled(dsidev, channel)) |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2586 | return 0; |
| 2587 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2588 | switch (dsi->vc[channel].source) { |
| 2589 | case DSI_VC_SOURCE_VP: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2590 | return dsi_sync_vc_vp(dsidev, channel); |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2591 | case DSI_VC_SOURCE_L4: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2592 | return dsi_sync_vc_l4(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2593 | default: |
| 2594 | BUG(); |
| 2595 | } |
| 2596 | } |
| 2597 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2598 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, |
| 2599 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2600 | { |
Tomi Valkeinen | 446f7bf | 2010-01-11 16:12:31 +0200 | [diff] [blame] | 2601 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
| 2602 | channel, enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2603 | |
| 2604 | enable = enable ? 1 : 0; |
| 2605 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2606 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2607 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2608 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), |
| 2609 | 0, enable) != enable) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2610 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
| 2611 | return -EIO; |
| 2612 | } |
| 2613 | |
| 2614 | return 0; |
| 2615 | } |
| 2616 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2617 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2618 | { |
| 2619 | u32 r; |
| 2620 | |
| 2621 | DSSDBGF("%d", channel); |
| 2622 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2623 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2624 | |
| 2625 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ |
| 2626 | DSSERR("VC(%d) busy when trying to configure it!\n", |
| 2627 | channel); |
| 2628 | |
| 2629 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ |
| 2630 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ |
| 2631 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ |
| 2632 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ |
| 2633 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ |
| 2634 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ |
| 2635 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2636 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
| 2637 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2638 | |
| 2639 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ |
| 2640 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ |
| 2641 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2642 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2643 | } |
| 2644 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2645 | static int dsi_vc_config_source(struct platform_device *dsidev, int channel, |
| 2646 | enum dsi_vc_source source) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2647 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2648 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2649 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2650 | if (dsi->vc[channel].source == source) |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2651 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2652 | |
| 2653 | DSSDBGF("%d", channel); |
| 2654 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2655 | dsi_sync_vc(dsidev, channel); |
Archit Taneja | cf398fb | 2011-03-23 09:59:34 +0000 | [diff] [blame] | 2656 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2657 | dsi_vc_enable(dsidev, channel, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2658 | |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2659 | /* VC_BUSY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2660 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2661 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2662 | return -EIO; |
| 2663 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2664 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2665 | /* SOURCE, 0 = L4, 1 = video port */ |
| 2666 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2667 | |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2668 | /* DCS_CMD_ENABLE */ |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2669 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
| 2670 | bool enable = source == DSI_VC_SOURCE_VP; |
| 2671 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); |
| 2672 | } |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 2673 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2674 | dsi_vc_enable(dsidev, channel, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2675 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2676 | dsi->vc[channel].source = source; |
Tomi Valkeinen | 9ecd968 | 2010-04-30 11:24:33 +0300 | [diff] [blame] | 2677 | |
| 2678 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2679 | } |
| 2680 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2681 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
| 2682 | bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2683 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2684 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 2685 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2686 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
| 2687 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2688 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2689 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2690 | dsi_vc_enable(dsidev, channel, 0); |
| 2691 | dsi_if_enable(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2692 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2693 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2694 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2695 | dsi_vc_enable(dsidev, channel, 1); |
| 2696 | dsi_if_enable(dsidev, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2697 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2698 | dsi_force_tx_stop_mode_io(dsidev); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 2699 | |
| 2700 | /* start the DDR clock by sending a NULL packet */ |
| 2701 | if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable) |
| 2702 | dsi_vc_send_null(dssdev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2703 | } |
Tomi Valkeinen | 61140c9 | 2010-01-12 16:00:30 +0200 | [diff] [blame] | 2704 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2705 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2706 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2707 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2708 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2709 | u32 val; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2710 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2711 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
| 2712 | (val >> 0) & 0xff, |
| 2713 | (val >> 8) & 0xff, |
| 2714 | (val >> 16) & 0xff, |
| 2715 | (val >> 24) & 0xff); |
| 2716 | } |
| 2717 | } |
| 2718 | |
| 2719 | static void dsi_show_rx_ack_with_err(u16 err) |
| 2720 | { |
| 2721 | DSSERR("\tACK with ERROR (%#x):\n", err); |
| 2722 | if (err & (1 << 0)) |
| 2723 | DSSERR("\t\tSoT Error\n"); |
| 2724 | if (err & (1 << 1)) |
| 2725 | DSSERR("\t\tSoT Sync Error\n"); |
| 2726 | if (err & (1 << 2)) |
| 2727 | DSSERR("\t\tEoT Sync Error\n"); |
| 2728 | if (err & (1 << 3)) |
| 2729 | DSSERR("\t\tEscape Mode Entry Command Error\n"); |
| 2730 | if (err & (1 << 4)) |
| 2731 | DSSERR("\t\tLP Transmit Sync Error\n"); |
| 2732 | if (err & (1 << 5)) |
| 2733 | DSSERR("\t\tHS Receive Timeout Error\n"); |
| 2734 | if (err & (1 << 6)) |
| 2735 | DSSERR("\t\tFalse Control Error\n"); |
| 2736 | if (err & (1 << 7)) |
| 2737 | DSSERR("\t\t(reserved7)\n"); |
| 2738 | if (err & (1 << 8)) |
| 2739 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); |
| 2740 | if (err & (1 << 9)) |
| 2741 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); |
| 2742 | if (err & (1 << 10)) |
| 2743 | DSSERR("\t\tChecksum Error\n"); |
| 2744 | if (err & (1 << 11)) |
| 2745 | DSSERR("\t\tData type not recognized\n"); |
| 2746 | if (err & (1 << 12)) |
| 2747 | DSSERR("\t\tInvalid VC ID\n"); |
| 2748 | if (err & (1 << 13)) |
| 2749 | DSSERR("\t\tInvalid Transmission Length\n"); |
| 2750 | if (err & (1 << 14)) |
| 2751 | DSSERR("\t\t(reserved14)\n"); |
| 2752 | if (err & (1 << 15)) |
| 2753 | DSSERR("\t\tDSI Protocol Violation\n"); |
| 2754 | } |
| 2755 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2756 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, |
| 2757 | int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2758 | { |
| 2759 | /* RX_FIFO_NOT_EMPTY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2760 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2761 | u32 val; |
| 2762 | u8 dt; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2763 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2764 | DSSERR("\trawval %#08x\n", val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2765 | dt = FLD_GET(val, 5, 0); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2766 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2767 | u16 err = FLD_GET(val, 23, 8); |
| 2768 | dsi_show_rx_ack_with_err(err); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2769 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2770 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2771 | FLD_GET(val, 23, 8)); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2772 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2773 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2774 | FLD_GET(val, 23, 8)); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2775 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { |
Tomi Valkeinen | 86a7867 | 2010-03-16 16:19:06 +0200 | [diff] [blame] | 2776 | DSSERR("\tDCS long response, len %d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2777 | FLD_GET(val, 23, 8)); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2778 | dsi_vc_flush_long_data(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2779 | } else { |
| 2780 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
| 2781 | } |
| 2782 | } |
| 2783 | return 0; |
| 2784 | } |
| 2785 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2786 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2787 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2788 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 2789 | |
| 2790 | if (dsi->debug_write || dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2791 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
| 2792 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2793 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2794 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2795 | /* RX_FIFO_NOT_EMPTY */ |
| 2796 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2797 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2798 | dsi_vc_flush_receive_data(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2799 | } |
| 2800 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2801 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2802 | |
Tomi Valkeinen | 968f8e9 | 2011-10-12 10:13:14 +0300 | [diff] [blame] | 2803 | /* flush posted write */ |
| 2804 | dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
| 2805 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2806 | return 0; |
| 2807 | } |
| 2808 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2809 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2810 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2811 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2812 | DECLARE_COMPLETION_ONSTACK(completion); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2813 | int r = 0; |
| 2814 | u32 err; |
| 2815 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2816 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2817 | &completion, DSI_VC_IRQ_BTA); |
| 2818 | if (r) |
| 2819 | goto err0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2820 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2821 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2822 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2823 | if (r) |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2824 | goto err1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2825 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2826 | r = dsi_vc_send_bta(dsidev, channel); |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2827 | if (r) |
| 2828 | goto err2; |
| 2829 | |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2830 | if (wait_for_completion_timeout(&completion, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2831 | msecs_to_jiffies(500)) == 0) { |
| 2832 | DSSERR("Failed to receive BTA\n"); |
| 2833 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2834 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2835 | } |
| 2836 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2837 | err = dsi_get_errors(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2838 | if (err) { |
| 2839 | DSSERR("Error while sending BTA: %x\n", err); |
| 2840 | r = -EIO; |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2841 | goto err2; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2842 | } |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2843 | err2: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2844 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 773b30b | 2010-10-08 16:15:25 +0300 | [diff] [blame] | 2845 | DSI_IRQ_ERROR_MASK); |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2846 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2847 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, |
Tomi Valkeinen | f36a06e | 2011-03-02 14:48:41 +0200 | [diff] [blame] | 2848 | &completion, DSI_VC_IRQ_BTA); |
| 2849 | err0: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2850 | return r; |
| 2851 | } |
| 2852 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); |
| 2853 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2854 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, |
| 2855 | int channel, u8 data_type, u16 len, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2856 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2857 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2858 | u32 val; |
| 2859 | u8 data_id; |
| 2860 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2861 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2862 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2863 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2864 | |
| 2865 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | |
| 2866 | FLD_VAL(ecc, 31, 24); |
| 2867 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2868 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2869 | } |
| 2870 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2871 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, |
| 2872 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2873 | { |
| 2874 | u32 val; |
| 2875 | |
| 2876 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; |
| 2877 | |
| 2878 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", |
| 2879 | b1, b2, b3, b4, val); */ |
| 2880 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2881 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2882 | } |
| 2883 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2884 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, |
| 2885 | u8 data_type, u8 *data, u16 len, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2886 | { |
| 2887 | /*u32 val; */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2888 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2889 | int i; |
| 2890 | u8 *p; |
| 2891 | int r = 0; |
| 2892 | u8 b1, b2, b3, b4; |
| 2893 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2894 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2895 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
| 2896 | |
| 2897 | /* len + header */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2898 | if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2899 | DSSERR("unable to send long packet: packet too long.\n"); |
| 2900 | return -EINVAL; |
| 2901 | } |
| 2902 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2903 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2904 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2905 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2906 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2907 | p = data; |
| 2908 | for (i = 0; i < len >> 2; i++) { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2909 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2910 | DSSDBG("\tsending full packet %d\n", i); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2911 | |
| 2912 | b1 = *p++; |
| 2913 | b2 = *p++; |
| 2914 | b3 = *p++; |
| 2915 | b4 = *p++; |
| 2916 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2917 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2918 | } |
| 2919 | |
| 2920 | i = len % 4; |
| 2921 | if (i) { |
| 2922 | b1 = 0; b2 = 0; b3 = 0; |
| 2923 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2924 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2925 | DSSDBG("\tsending remainder bytes %d\n", i); |
| 2926 | |
| 2927 | switch (i) { |
| 2928 | case 3: |
| 2929 | b1 = *p++; |
| 2930 | b2 = *p++; |
| 2931 | b3 = *p++; |
| 2932 | break; |
| 2933 | case 2: |
| 2934 | b1 = *p++; |
| 2935 | b2 = *p++; |
| 2936 | break; |
| 2937 | case 1: |
| 2938 | b1 = *p++; |
| 2939 | break; |
| 2940 | } |
| 2941 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2942 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2943 | } |
| 2944 | |
| 2945 | return r; |
| 2946 | } |
| 2947 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2948 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, |
| 2949 | u8 data_type, u16 data, u8 ecc) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2950 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2951 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2952 | u32 r; |
| 2953 | u8 data_id; |
| 2954 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2955 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2956 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2957 | if (dsi->debug_write) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2958 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
| 2959 | channel, |
| 2960 | data_type, data & 0xff, (data >> 8) & 0xff); |
| 2961 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 2962 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2963 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2964 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2965 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
| 2966 | return -EINVAL; |
| 2967 | } |
| 2968 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 2969 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2970 | |
| 2971 | r = (data_id << 0) | (data << 8) | (ecc << 24); |
| 2972 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2973 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2974 | |
| 2975 | return 0; |
| 2976 | } |
| 2977 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 2978 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2979 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2980 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2981 | |
Archit Taneja | 18b7d09 | 2011-09-05 17:01:08 +0530 | [diff] [blame] | 2982 | return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, |
| 2983 | 0, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2984 | } |
| 2985 | EXPORT_SYMBOL(dsi_vc_send_null); |
| 2986 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2987 | static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev, |
| 2988 | int channel, u8 *data, int len, enum dss_dsi_content_type type) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2989 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 2990 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 2991 | int r; |
| 2992 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2993 | if (len == 0) { |
| 2994 | BUG_ON(type == DSS_DSI_CONTENT_DCS); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 2995 | r = dsi_vc_send_short(dsidev, channel, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 2996 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); |
| 2997 | } else if (len == 1) { |
| 2998 | r = dsi_vc_send_short(dsidev, channel, |
| 2999 | type == DSS_DSI_CONTENT_GENERIC ? |
| 3000 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 3001 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3002 | } else if (len == 2) { |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 3003 | r = dsi_vc_send_short(dsidev, channel, |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3004 | type == DSS_DSI_CONTENT_GENERIC ? |
| 3005 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 3006 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3007 | data[0] | (data[1] << 8), 0); |
| 3008 | } else { |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3009 | r = dsi_vc_send_long(dsidev, channel, |
| 3010 | type == DSS_DSI_CONTENT_GENERIC ? |
| 3011 | MIPI_DSI_GENERIC_LONG_WRITE : |
| 3012 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3013 | } |
| 3014 | |
| 3015 | return r; |
| 3016 | } |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3017 | |
| 3018 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, |
| 3019 | u8 *data, int len) |
| 3020 | { |
| 3021 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, |
| 3022 | DSS_DSI_CONTENT_DCS); |
| 3023 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3024 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
| 3025 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3026 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
| 3027 | u8 *data, int len) |
| 3028 | { |
| 3029 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, |
| 3030 | DSS_DSI_CONTENT_GENERIC); |
| 3031 | } |
| 3032 | EXPORT_SYMBOL(dsi_vc_generic_write_nosync); |
| 3033 | |
| 3034 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, |
| 3035 | u8 *data, int len, enum dss_dsi_content_type type) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3036 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3037 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3038 | int r; |
| 3039 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3040 | r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3041 | if (r) |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3042 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3043 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3044 | r = dsi_vc_send_bta_sync(dssdev, channel); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3045 | if (r) |
| 3046 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3047 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3048 | /* RX_FIFO_NOT_EMPTY */ |
| 3049 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 3050 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3051 | dsi_vc_flush_receive_data(dsidev, channel); |
Tomi Valkeinen | b63ac1e | 2010-04-09 13:20:57 +0300 | [diff] [blame] | 3052 | r = -EIO; |
| 3053 | goto err; |
| 3054 | } |
| 3055 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3056 | return 0; |
| 3057 | err: |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3058 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3059 | channel, data[0], len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3060 | return r; |
| 3061 | } |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3062 | |
| 3063 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
| 3064 | int len) |
| 3065 | { |
| 3066 | return dsi_vc_write_common(dssdev, channel, data, len, |
| 3067 | DSS_DSI_CONTENT_DCS); |
| 3068 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3069 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
| 3070 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3071 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
| 3072 | int len) |
| 3073 | { |
| 3074 | return dsi_vc_write_common(dssdev, channel, data, len, |
| 3075 | DSS_DSI_CONTENT_GENERIC); |
| 3076 | } |
| 3077 | EXPORT_SYMBOL(dsi_vc_generic_write); |
| 3078 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3079 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd) |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 3080 | { |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3081 | return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1); |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 3082 | } |
| 3083 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); |
| 3084 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3085 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel) |
| 3086 | { |
| 3087 | return dsi_vc_generic_write(dssdev, channel, NULL, 0); |
| 3088 | } |
| 3089 | EXPORT_SYMBOL(dsi_vc_generic_write_0); |
| 3090 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3091 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
| 3092 | u8 param) |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 3093 | { |
| 3094 | u8 buf[2]; |
| 3095 | buf[0] = dcs_cmd; |
| 3096 | buf[1] = param; |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3097 | return dsi_vc_dcs_write(dssdev, channel, buf, 2); |
Tomi Valkeinen | 828c48f | 2009-12-16 14:53:15 +0200 | [diff] [blame] | 3098 | } |
| 3099 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); |
| 3100 | |
Archit Taneja | 6ff8aa3 | 2011-08-25 18:35:58 +0530 | [diff] [blame] | 3101 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, |
| 3102 | u8 param) |
| 3103 | { |
| 3104 | return dsi_vc_generic_write(dssdev, channel, ¶m, 1); |
| 3105 | } |
| 3106 | EXPORT_SYMBOL(dsi_vc_generic_write_1); |
| 3107 | |
| 3108 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, |
| 3109 | u8 param1, u8 param2) |
| 3110 | { |
| 3111 | u8 buf[2]; |
| 3112 | buf[0] = param1; |
| 3113 | buf[1] = param2; |
| 3114 | return dsi_vc_generic_write(dssdev, channel, buf, 2); |
| 3115 | } |
| 3116 | EXPORT_SYMBOL(dsi_vc_generic_write_2); |
| 3117 | |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3118 | static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev, |
| 3119 | int channel, u8 dcs_cmd) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3120 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3121 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3122 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3123 | int r; |
| 3124 | |
| 3125 | if (dsi->debug_read) |
| 3126 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", |
| 3127 | channel, dcs_cmd); |
| 3128 | |
| 3129 | r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); |
| 3130 | if (r) { |
| 3131 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" |
| 3132 | " failed\n", channel, dcs_cmd); |
| 3133 | return r; |
| 3134 | } |
| 3135 | |
| 3136 | return 0; |
| 3137 | } |
| 3138 | |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3139 | static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev, |
| 3140 | int channel, u8 *reqdata, int reqlen) |
| 3141 | { |
| 3142 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3143 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 3144 | u16 data; |
| 3145 | u8 data_type; |
| 3146 | int r; |
| 3147 | |
| 3148 | if (dsi->debug_read) |
| 3149 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", |
| 3150 | channel, reqlen); |
| 3151 | |
| 3152 | if (reqlen == 0) { |
| 3153 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; |
| 3154 | data = 0; |
| 3155 | } else if (reqlen == 1) { |
| 3156 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; |
| 3157 | data = reqdata[0]; |
| 3158 | } else if (reqlen == 2) { |
| 3159 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; |
| 3160 | data = reqdata[0] | (reqdata[1] << 8); |
| 3161 | } else { |
| 3162 | BUG(); |
| 3163 | } |
| 3164 | |
| 3165 | r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); |
| 3166 | if (r) { |
| 3167 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" |
| 3168 | " failed\n", channel, reqlen); |
| 3169 | return r; |
| 3170 | } |
| 3171 | |
| 3172 | return 0; |
| 3173 | } |
| 3174 | |
| 3175 | static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, |
| 3176 | u8 *buf, int buflen, enum dss_dsi_content_type type) |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3177 | { |
| 3178 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3179 | u32 val; |
| 3180 | u8 dt; |
| 3181 | int r; |
| 3182 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3183 | /* RX_FIFO_NOT_EMPTY */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3184 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3185 | DSSERR("RX fifo empty when trying to read.\n"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3186 | r = -EIO; |
| 3187 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3188 | } |
| 3189 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3190 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3191 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3192 | DSSDBG("\theader: %08x\n", val); |
| 3193 | dt = FLD_GET(val, 5, 0); |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 3194 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3195 | u16 err = FLD_GET(val, 23, 8); |
| 3196 | dsi_show_rx_ack_with_err(err); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3197 | r = -EIO; |
| 3198 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3199 | |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3200 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
| 3201 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : |
| 3202 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3203 | u8 data = FLD_GET(val, 15, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3204 | if (dsi->debug_read) |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3205 | DSSDBG("\t%s short response, 1 byte: %02x\n", |
| 3206 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : |
| 3207 | "DCS", data); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3208 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3209 | if (buflen < 1) { |
| 3210 | r = -EIO; |
| 3211 | goto err; |
| 3212 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3213 | |
| 3214 | buf[0] = data; |
| 3215 | |
| 3216 | return 1; |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3217 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
| 3218 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : |
| 3219 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3220 | u16 data = FLD_GET(val, 23, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3221 | if (dsi->debug_read) |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3222 | DSSDBG("\t%s short response, 2 byte: %04x\n", |
| 3223 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : |
| 3224 | "DCS", data); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3225 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3226 | if (buflen < 2) { |
| 3227 | r = -EIO; |
| 3228 | goto err; |
| 3229 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3230 | |
| 3231 | buf[0] = data & 0xff; |
| 3232 | buf[1] = (data >> 8) & 0xff; |
| 3233 | |
| 3234 | return 2; |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3235 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
| 3236 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : |
| 3237 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3238 | int w; |
| 3239 | int len = FLD_GET(val, 23, 8); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3240 | if (dsi->debug_read) |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3241 | DSSDBG("\t%s long response, len %d\n", |
| 3242 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : |
| 3243 | "DCS", len); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3244 | |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3245 | if (len > buflen) { |
| 3246 | r = -EIO; |
| 3247 | goto err; |
| 3248 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3249 | |
| 3250 | /* two byte checksum ends the packet, not included in len */ |
| 3251 | for (w = 0; w < len + 2;) { |
| 3252 | int b; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3253 | val = dsi_read_reg(dsidev, |
| 3254 | DSI_VC_SHORT_PACKET_HEADER(channel)); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3255 | if (dsi->debug_read) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3256 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
| 3257 | (val >> 0) & 0xff, |
| 3258 | (val >> 8) & 0xff, |
| 3259 | (val >> 16) & 0xff, |
| 3260 | (val >> 24) & 0xff); |
| 3261 | |
| 3262 | for (b = 0; b < 4; ++b) { |
| 3263 | if (w < len) |
| 3264 | buf[w] = (val >> (b * 8)) & 0xff; |
| 3265 | /* we discard the 2 byte checksum */ |
| 3266 | ++w; |
| 3267 | } |
| 3268 | } |
| 3269 | |
| 3270 | return len; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3271 | } else { |
| 3272 | DSSERR("\tunknown datatype 0x%02x\n", dt); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3273 | r = -EIO; |
| 3274 | goto err; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3275 | } |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3276 | |
| 3277 | BUG(); |
| 3278 | err: |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3279 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, |
| 3280 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); |
Tomi Valkeinen | 5d68e03 | 2010-02-26 11:32:56 +0200 | [diff] [blame] | 3281 | |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3282 | return r; |
| 3283 | } |
| 3284 | |
| 3285 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
| 3286 | u8 *buf, int buflen) |
| 3287 | { |
| 3288 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3289 | int r; |
| 3290 | |
| 3291 | r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd); |
| 3292 | if (r) |
| 3293 | goto err; |
| 3294 | |
| 3295 | r = dsi_vc_send_bta_sync(dssdev, channel); |
| 3296 | if (r) |
| 3297 | goto err; |
| 3298 | |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3299 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
| 3300 | DSS_DSI_CONTENT_DCS); |
Archit Taneja | b850975 | 2011-08-30 15:48:23 +0530 | [diff] [blame] | 3301 | if (r < 0) |
| 3302 | goto err; |
| 3303 | |
| 3304 | if (r != buflen) { |
| 3305 | r = -EIO; |
| 3306 | goto err; |
| 3307 | } |
| 3308 | |
| 3309 | return 0; |
| 3310 | err: |
| 3311 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); |
| 3312 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3313 | } |
| 3314 | EXPORT_SYMBOL(dsi_vc_dcs_read); |
| 3315 | |
Archit Taneja | b3b89c0 | 2011-08-30 16:07:39 +0530 | [diff] [blame] | 3316 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, |
| 3317 | u8 *reqdata, int reqlen, u8 *buf, int buflen) |
| 3318 | { |
| 3319 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3320 | int r; |
| 3321 | |
| 3322 | r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen); |
| 3323 | if (r) |
| 3324 | return r; |
| 3325 | |
| 3326 | r = dsi_vc_send_bta_sync(dssdev, channel); |
| 3327 | if (r) |
| 3328 | return r; |
| 3329 | |
| 3330 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
| 3331 | DSS_DSI_CONTENT_GENERIC); |
| 3332 | if (r < 0) |
| 3333 | return r; |
| 3334 | |
| 3335 | if (r != buflen) { |
| 3336 | r = -EIO; |
| 3337 | return r; |
| 3338 | } |
| 3339 | |
| 3340 | return 0; |
| 3341 | } |
| 3342 | |
| 3343 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, |
| 3344 | int buflen) |
| 3345 | { |
| 3346 | int r; |
| 3347 | |
| 3348 | r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen); |
| 3349 | if (r) { |
| 3350 | DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel); |
| 3351 | return r; |
| 3352 | } |
| 3353 | |
| 3354 | return 0; |
| 3355 | } |
| 3356 | EXPORT_SYMBOL(dsi_vc_generic_read_0); |
| 3357 | |
| 3358 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, |
| 3359 | u8 *buf, int buflen) |
| 3360 | { |
| 3361 | int r; |
| 3362 | |
| 3363 | r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen); |
| 3364 | if (r) { |
| 3365 | DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel); |
| 3366 | return r; |
| 3367 | } |
| 3368 | |
| 3369 | return 0; |
| 3370 | } |
| 3371 | EXPORT_SYMBOL(dsi_vc_generic_read_1); |
| 3372 | |
| 3373 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, |
| 3374 | u8 param1, u8 param2, u8 *buf, int buflen) |
| 3375 | { |
| 3376 | int r; |
| 3377 | u8 reqdata[2]; |
| 3378 | |
| 3379 | reqdata[0] = param1; |
| 3380 | reqdata[1] = param2; |
| 3381 | |
| 3382 | r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen); |
| 3383 | if (r) { |
| 3384 | DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel); |
| 3385 | return r; |
| 3386 | } |
| 3387 | |
| 3388 | return 0; |
| 3389 | } |
| 3390 | EXPORT_SYMBOL(dsi_vc_generic_read_2); |
| 3391 | |
Archit Taneja | 1ffefe7 | 2011-05-12 17:26:24 +0530 | [diff] [blame] | 3392 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
| 3393 | u16 len) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3394 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3395 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3396 | |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 3397 | return dsi_vc_send_short(dsidev, channel, |
| 3398 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3399 | } |
| 3400 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); |
| 3401 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3402 | static int dsi_enter_ulps(struct platform_device *dsidev) |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3403 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3404 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3405 | DECLARE_COMPLETION_ONSTACK(completion); |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3406 | int r, i; |
| 3407 | unsigned mask; |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3408 | |
| 3409 | DSSDBGF(); |
| 3410 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3411 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3412 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3413 | WARN_ON(dsi->ulps_enabled); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3414 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3415 | if (dsi->ulps_enabled) |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3416 | return 0; |
| 3417 | |
Tomi Valkeinen | 6cc78aa | 2011-10-13 19:22:43 +0300 | [diff] [blame] | 3418 | /* DDR_CLK_ALWAYS_ON */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3419 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { |
Tomi Valkeinen | 6cc78aa | 2011-10-13 19:22:43 +0300 | [diff] [blame] | 3420 | dsi_if_enable(dsidev, 0); |
| 3421 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); |
| 3422 | dsi_if_enable(dsidev, 1); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3423 | } |
| 3424 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3425 | dsi_sync_vc(dsidev, 0); |
| 3426 | dsi_sync_vc(dsidev, 1); |
| 3427 | dsi_sync_vc(dsidev, 2); |
| 3428 | dsi_sync_vc(dsidev, 3); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3429 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3430 | dsi_force_tx_stop_mode_io(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3431 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3432 | dsi_vc_enable(dsidev, 0, false); |
| 3433 | dsi_vc_enable(dsidev, 1, false); |
| 3434 | dsi_vc_enable(dsidev, 2, false); |
| 3435 | dsi_vc_enable(dsidev, 3, false); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3436 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3437 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3438 | DSSERR("HS busy when enabling ULPS\n"); |
| 3439 | return -EIO; |
| 3440 | } |
| 3441 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3442 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3443 | DSSERR("LP busy when enabling ULPS\n"); |
| 3444 | return -EIO; |
| 3445 | } |
| 3446 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3447 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3448 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3449 | if (r) |
| 3450 | return r; |
| 3451 | |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3452 | mask = 0; |
| 3453 | |
| 3454 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
| 3455 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) |
| 3456 | continue; |
| 3457 | mask |= 1 << i; |
| 3458 | } |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3459 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ |
| 3460 | /* LANEx_ULPS_SIG2 */ |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3461 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3462 | |
Tomi Valkeinen | a702c85 | 2011-10-12 10:10:21 +0300 | [diff] [blame] | 3463 | /* flush posted write and wait for SCP interface to finish the write */ |
| 3464 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3465 | |
| 3466 | if (wait_for_completion_timeout(&completion, |
| 3467 | msecs_to_jiffies(1000)) == 0) { |
| 3468 | DSSERR("ULPS enable timeout\n"); |
| 3469 | r = -EIO; |
| 3470 | goto err; |
| 3471 | } |
| 3472 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3473 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3474 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3475 | |
Tomi Valkeinen | 8ef0e61 | 2011-05-31 16:55:47 +0300 | [diff] [blame] | 3476 | /* Reset LANEx_ULPS_SIG2 */ |
Tomi Valkeinen | 522a0c2 | 2011-10-13 16:18:52 +0300 | [diff] [blame] | 3477 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); |
Tomi Valkeinen | 8ef0e61 | 2011-05-31 16:55:47 +0300 | [diff] [blame] | 3478 | |
Tomi Valkeinen | a702c85 | 2011-10-12 10:10:21 +0300 | [diff] [blame] | 3479 | /* flush posted write and wait for SCP interface to finish the write */ |
| 3480 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3481 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3482 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3483 | |
| 3484 | dsi_if_enable(dsidev, false); |
| 3485 | |
| 3486 | dsi->ulps_enabled = true; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3487 | |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 3488 | return 0; |
| 3489 | |
| 3490 | err: |
| 3491 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3492 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
| 3493 | return r; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3494 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3495 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3496 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, |
| 3497 | unsigned ticks, bool x4, bool x16) |
| 3498 | { |
| 3499 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3500 | unsigned long total_ticks; |
| 3501 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3502 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3503 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3504 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3505 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3506 | fck = dsi_fclk_rate(dsidev); |
| 3507 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3508 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3509 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3510 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3511 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ |
| 3512 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
| 3513 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
| 3514 | |
| 3515 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3516 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3517 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3518 | total_ticks, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3519 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3520 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3521 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3522 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3523 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, |
| 3524 | bool x8, bool x16) |
| 3525 | { |
| 3526 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3527 | unsigned long total_ticks; |
| 3528 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3529 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3530 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3531 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3532 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3533 | fck = dsi_fclk_rate(dsidev); |
| 3534 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3535 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3536 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3537 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3538 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ |
| 3539 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
| 3540 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
| 3541 | |
| 3542 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
| 3543 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3544 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3545 | total_ticks, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3546 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", |
| 3547 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3548 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3549 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3550 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, |
| 3551 | unsigned ticks, bool x4, bool x16) |
| 3552 | { |
| 3553 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3554 | unsigned long total_ticks; |
| 3555 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3556 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3557 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3558 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3559 | /* ticks in DSI_FCK */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3560 | fck = dsi_fclk_rate(dsidev); |
| 3561 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3562 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3563 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3564 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3565 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ |
| 3566 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
| 3567 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
| 3568 | |
| 3569 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3570 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3571 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", |
| 3572 | total_ticks, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3573 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
| 3574 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3575 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3576 | |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3577 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, |
| 3578 | unsigned ticks, bool x4, bool x16) |
| 3579 | { |
| 3580 | unsigned long fck; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3581 | unsigned long total_ticks; |
| 3582 | u32 r; |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3583 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3584 | BUG_ON(ticks > 0x1fff); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3585 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3586 | /* ticks in TxByteClkHS */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3587 | fck = dsi_get_txbyteclkhs(dsidev); |
| 3588 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3589 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3590 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3591 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
Tomi Valkeinen | 4ffa357 | 2010-04-12 10:40:12 +0300 | [diff] [blame] | 3592 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ |
| 3593 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
| 3594 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
| 3595 | |
| 3596 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
| 3597 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3598 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", |
| 3599 | total_ticks, |
| 3600 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3601 | (total_ticks * 1000) / (fck / 1000 / 1000)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3602 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3603 | |
| 3604 | static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev) |
| 3605 | { |
| 3606 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3607 | int num_line_buffers; |
| 3608 | |
| 3609 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 3610 | int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt); |
| 3611 | unsigned line_buf_size = dsi_get_line_buf_size(dsidev); |
| 3612 | struct omap_video_timings *timings = &dssdev->panel.timings; |
| 3613 | /* |
| 3614 | * Don't use line buffers if width is greater than the video |
| 3615 | * port's line buffer size |
| 3616 | */ |
| 3617 | if (line_buf_size <= timings->x_res * bpp / 8) |
| 3618 | num_line_buffers = 0; |
| 3619 | else |
| 3620 | num_line_buffers = 2; |
| 3621 | } else { |
| 3622 | /* Use maximum number of line buffers in command mode */ |
| 3623 | num_line_buffers = 2; |
| 3624 | } |
| 3625 | |
| 3626 | /* LINE_BUFFER */ |
| 3627 | REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); |
| 3628 | } |
| 3629 | |
| 3630 | static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev) |
| 3631 | { |
| 3632 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3633 | int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol; |
| 3634 | int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol; |
| 3635 | int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol; |
| 3636 | bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end; |
| 3637 | bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; |
| 3638 | u32 r; |
| 3639 | |
| 3640 | r = dsi_read_reg(dsidev, DSI_CTRL); |
| 3641 | r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */ |
| 3642 | r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */ |
| 3643 | r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */ |
| 3644 | r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ |
| 3645 | r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */ |
| 3646 | r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ |
| 3647 | r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */ |
| 3648 | dsi_write_reg(dsidev, DSI_CTRL, r); |
| 3649 | } |
| 3650 | |
| 3651 | static void dsi_config_blanking_modes(struct omap_dss_device *dssdev) |
| 3652 | { |
| 3653 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3654 | int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode; |
| 3655 | int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode; |
| 3656 | int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode; |
| 3657 | int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode; |
| 3658 | u32 r; |
| 3659 | |
| 3660 | /* |
| 3661 | * 0 = TX FIFO packets sent or LPS in corresponding blanking periods |
| 3662 | * 1 = Long blanking packets are sent in corresponding blanking periods |
| 3663 | */ |
| 3664 | r = dsi_read_reg(dsidev, DSI_CTRL); |
| 3665 | r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ |
| 3666 | r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ |
| 3667 | r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ |
| 3668 | r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ |
| 3669 | dsi_write_reg(dsidev, DSI_CTRL, r); |
| 3670 | } |
| 3671 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3672 | static int dsi_proto_config(struct omap_dss_device *dssdev) |
| 3673 | { |
| 3674 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3675 | u32 r; |
| 3676 | int buswidth = 0; |
| 3677 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3678 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3679 | DSI_FIFO_SIZE_32, |
| 3680 | DSI_FIFO_SIZE_32, |
| 3681 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3682 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3683 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, |
Tomi Valkeinen | dd8079d | 2009-12-16 16:49:03 +0200 | [diff] [blame] | 3684 | DSI_FIFO_SIZE_32, |
| 3685 | DSI_FIFO_SIZE_32, |
| 3686 | DSI_FIFO_SIZE_32); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3687 | |
| 3688 | /* XXX what values for the timeouts? */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3689 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); |
| 3690 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); |
| 3691 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); |
| 3692 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3693 | |
Archit Taneja | a3b3cc2 | 2011-09-08 18:42:16 +0530 | [diff] [blame] | 3694 | switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3695 | case 16: |
| 3696 | buswidth = 0; |
| 3697 | break; |
| 3698 | case 18: |
| 3699 | buswidth = 1; |
| 3700 | break; |
| 3701 | case 24: |
| 3702 | buswidth = 2; |
| 3703 | break; |
| 3704 | default: |
| 3705 | BUG(); |
| 3706 | } |
| 3707 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3708 | r = dsi_read_reg(dsidev, DSI_CTRL); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3709 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
| 3710 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ |
| 3711 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ |
| 3712 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ |
| 3713 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ |
| 3714 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3715 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
| 3716 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 3717 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
| 3718 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ |
| 3719 | /* DCS_CMD_CODE, 1=start, 0=continue */ |
| 3720 | r = FLD_MOD(r, 0, 25, 25); |
| 3721 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3722 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3723 | dsi_write_reg(dsidev, DSI_CTRL, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3724 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3725 | dsi_config_vp_num_line_buffers(dssdev); |
| 3726 | |
| 3727 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 3728 | dsi_config_vp_sync_events(dssdev); |
| 3729 | dsi_config_blanking_modes(dssdev); |
| 3730 | } |
| 3731 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3732 | dsi_vc_initial_config(dsidev, 0); |
| 3733 | dsi_vc_initial_config(dsidev, 1); |
| 3734 | dsi_vc_initial_config(dsidev, 2); |
| 3735 | dsi_vc_initial_config(dsidev, 3); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3736 | |
| 3737 | return 0; |
| 3738 | } |
| 3739 | |
| 3740 | static void dsi_proto_timings(struct omap_dss_device *dssdev) |
| 3741 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3742 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | db18644 | 2011-10-13 16:12:29 +0300 | [diff] [blame] | 3743 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3744 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
| 3745 | unsigned tclk_pre, tclk_post; |
| 3746 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; |
| 3747 | unsigned ths_trail, ths_exit; |
| 3748 | unsigned ddr_clk_pre, ddr_clk_post; |
| 3749 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; |
| 3750 | unsigned ths_eot; |
Tomi Valkeinen | db18644 | 2011-10-13 16:12:29 +0300 | [diff] [blame] | 3751 | int ndl = dsi->num_lanes_used - 1; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3752 | u32 r; |
| 3753 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3754 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3755 | ths_prepare = FLD_GET(r, 31, 24); |
| 3756 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); |
| 3757 | ths_zero = ths_prepare_ths_zero - ths_prepare; |
| 3758 | ths_trail = FLD_GET(r, 15, 8); |
| 3759 | ths_exit = FLD_GET(r, 7, 0); |
| 3760 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3761 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3762 | tlpx = FLD_GET(r, 22, 16) * 2; |
| 3763 | tclk_trail = FLD_GET(r, 15, 8); |
| 3764 | tclk_zero = FLD_GET(r, 7, 0); |
| 3765 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3766 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3767 | tclk_prepare = FLD_GET(r, 7, 0); |
| 3768 | |
| 3769 | /* min 8*UI */ |
| 3770 | tclk_pre = 20; |
| 3771 | /* min 60ns + 52*UI */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3772 | tclk_post = ns2ddr(dsidev, 60) + 26; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3773 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3774 | ths_eot = DIV_ROUND_UP(4, ndl); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3775 | |
| 3776 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, |
| 3777 | 4); |
| 3778 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; |
| 3779 | |
| 3780 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); |
| 3781 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); |
| 3782 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3783 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3784 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
| 3785 | r = FLD_MOD(r, ddr_clk_post, 7, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3786 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3787 | |
| 3788 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", |
| 3789 | ddr_clk_pre, |
| 3790 | ddr_clk_post); |
| 3791 | |
| 3792 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + |
| 3793 | DIV_ROUND_UP(ths_prepare, 4) + |
| 3794 | DIV_ROUND_UP(ths_zero + 3, 4); |
| 3795 | |
| 3796 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; |
| 3797 | |
| 3798 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | |
| 3799 | FLD_VAL(exit_hs_mode_lat, 15, 0); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3800 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3801 | |
| 3802 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", |
| 3803 | enter_hs_mode_lat, exit_hs_mode_lat); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3804 | |
| 3805 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 3806 | /* TODO: Implement a video mode check_timings function */ |
| 3807 | int hsa = dssdev->panel.dsi_vm_data.hsa; |
| 3808 | int hfp = dssdev->panel.dsi_vm_data.hfp; |
| 3809 | int hbp = dssdev->panel.dsi_vm_data.hbp; |
| 3810 | int vsa = dssdev->panel.dsi_vm_data.vsa; |
| 3811 | int vfp = dssdev->panel.dsi_vm_data.vfp; |
| 3812 | int vbp = dssdev->panel.dsi_vm_data.vbp; |
| 3813 | int window_sync = dssdev->panel.dsi_vm_data.window_sync; |
| 3814 | bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; |
| 3815 | struct omap_video_timings *timings = &dssdev->panel.timings; |
| 3816 | int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt); |
| 3817 | int tl, t_he, width_bytes; |
| 3818 | |
| 3819 | t_he = hsync_end ? |
| 3820 | ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; |
| 3821 | |
| 3822 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); |
| 3823 | |
| 3824 | /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ |
| 3825 | tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + |
| 3826 | DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; |
| 3827 | |
| 3828 | DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, |
| 3829 | hfp, hsync_end ? hsa : 0, tl); |
| 3830 | DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, |
| 3831 | vsa, timings->y_res); |
| 3832 | |
| 3833 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); |
| 3834 | r = FLD_MOD(r, hbp, 11, 0); /* HBP */ |
| 3835 | r = FLD_MOD(r, hfp, 23, 12); /* HFP */ |
| 3836 | r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ |
| 3837 | dsi_write_reg(dsidev, DSI_VM_TIMING1, r); |
| 3838 | |
| 3839 | r = dsi_read_reg(dsidev, DSI_VM_TIMING2); |
| 3840 | r = FLD_MOD(r, vbp, 7, 0); /* VBP */ |
| 3841 | r = FLD_MOD(r, vfp, 15, 8); /* VFP */ |
| 3842 | r = FLD_MOD(r, vsa, 23, 16); /* VSA */ |
| 3843 | r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ |
| 3844 | dsi_write_reg(dsidev, DSI_VM_TIMING2, r); |
| 3845 | |
| 3846 | r = dsi_read_reg(dsidev, DSI_VM_TIMING3); |
| 3847 | r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ |
| 3848 | r = FLD_MOD(r, tl, 31, 16); /* TL */ |
| 3849 | dsi_write_reg(dsidev, DSI_VM_TIMING3, r); |
| 3850 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3851 | } |
| 3852 | |
Tomi Valkeinen | e4a9e94 | 2012-03-28 15:58:56 +0300 | [diff] [blame] | 3853 | int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, |
| 3854 | const struct omap_dsi_pin_config *pin_cfg) |
| 3855 | { |
| 3856 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3857 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 3858 | int num_pins; |
| 3859 | const int *pins; |
| 3860 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; |
| 3861 | int num_lanes; |
| 3862 | int i; |
| 3863 | |
| 3864 | static const enum dsi_lane_function functions[] = { |
| 3865 | DSI_LANE_CLK, |
| 3866 | DSI_LANE_DATA1, |
| 3867 | DSI_LANE_DATA2, |
| 3868 | DSI_LANE_DATA3, |
| 3869 | DSI_LANE_DATA4, |
| 3870 | }; |
| 3871 | |
| 3872 | num_pins = pin_cfg->num_pins; |
| 3873 | pins = pin_cfg->pins; |
| 3874 | |
| 3875 | if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 |
| 3876 | || num_pins % 2 != 0) |
| 3877 | return -EINVAL; |
| 3878 | |
| 3879 | for (i = 0; i < DSI_MAX_NR_LANES; ++i) |
| 3880 | lanes[i].function = DSI_LANE_UNUSED; |
| 3881 | |
| 3882 | num_lanes = 0; |
| 3883 | |
| 3884 | for (i = 0; i < num_pins; i += 2) { |
| 3885 | u8 lane, pol; |
| 3886 | int dx, dy; |
| 3887 | |
| 3888 | dx = pins[i]; |
| 3889 | dy = pins[i + 1]; |
| 3890 | |
| 3891 | if (dx < 0 || dx >= dsi->num_lanes_supported * 2) |
| 3892 | return -EINVAL; |
| 3893 | |
| 3894 | if (dy < 0 || dy >= dsi->num_lanes_supported * 2) |
| 3895 | return -EINVAL; |
| 3896 | |
| 3897 | if (dx & 1) { |
| 3898 | if (dy != dx - 1) |
| 3899 | return -EINVAL; |
| 3900 | pol = 1; |
| 3901 | } else { |
| 3902 | if (dy != dx + 1) |
| 3903 | return -EINVAL; |
| 3904 | pol = 0; |
| 3905 | } |
| 3906 | |
| 3907 | lane = dx / 2; |
| 3908 | |
| 3909 | lanes[lane].function = functions[i / 2]; |
| 3910 | lanes[lane].polarity = pol; |
| 3911 | num_lanes++; |
| 3912 | } |
| 3913 | |
| 3914 | memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); |
| 3915 | dsi->num_lanes_used = num_lanes; |
| 3916 | |
| 3917 | return 0; |
| 3918 | } |
| 3919 | EXPORT_SYMBOL(omapdss_dsi_configure_pins); |
| 3920 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3921 | int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3922 | { |
| 3923 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3924 | int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt); |
| 3925 | u8 data_type; |
| 3926 | u16 word_count; |
Tomi Valkeinen | 33ca237 | 2011-11-21 13:42:58 +0200 | [diff] [blame] | 3927 | int r; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3928 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3929 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 3930 | switch (dssdev->panel.dsi_pix_fmt) { |
| 3931 | case OMAP_DSS_DSI_FMT_RGB888: |
| 3932 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; |
| 3933 | break; |
| 3934 | case OMAP_DSS_DSI_FMT_RGB666: |
| 3935 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; |
| 3936 | break; |
| 3937 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: |
| 3938 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; |
| 3939 | break; |
| 3940 | case OMAP_DSS_DSI_FMT_RGB565: |
| 3941 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; |
| 3942 | break; |
| 3943 | default: |
| 3944 | BUG(); |
| 3945 | }; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3946 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3947 | dsi_if_enable(dsidev, false); |
| 3948 | dsi_vc_enable(dsidev, channel, false); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3949 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3950 | /* MODE, 1 = video mode */ |
| 3951 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3952 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3953 | word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3954 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3955 | dsi_vc_write_long_header(dsidev, channel, data_type, |
| 3956 | word_count, 0); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3957 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3958 | dsi_vc_enable(dsidev, channel, true); |
| 3959 | dsi_if_enable(dsidev, true); |
| 3960 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3961 | |
Tomi Valkeinen | 33ca237 | 2011-11-21 13:42:58 +0200 | [diff] [blame] | 3962 | r = dss_mgr_enable(dssdev->manager); |
| 3963 | if (r) { |
| 3964 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 3965 | dsi_if_enable(dsidev, false); |
| 3966 | dsi_vc_enable(dsidev, channel, false); |
| 3967 | } |
| 3968 | |
| 3969 | return r; |
| 3970 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3971 | |
| 3972 | return 0; |
| 3973 | } |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3974 | EXPORT_SYMBOL(dsi_enable_video_output); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3975 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3976 | void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3977 | { |
| 3978 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 3979 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3980 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
| 3981 | dsi_if_enable(dsidev, false); |
| 3982 | dsi_vc_enable(dsidev, channel, false); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3983 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3984 | /* MODE, 0 = command mode */ |
| 3985 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3986 | |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3987 | dsi_vc_enable(dsidev, channel, true); |
| 3988 | dsi_if_enable(dsidev, true); |
| 3989 | } |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3990 | |
Tomi Valkeinen | 7797c6d | 2011-11-04 10:22:46 +0200 | [diff] [blame] | 3991 | dss_mgr_disable(dssdev->manager); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3992 | } |
Tomi Valkeinen | 9a147a6 | 2011-11-09 15:30:11 +0200 | [diff] [blame] | 3993 | EXPORT_SYMBOL(dsi_disable_video_output); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 3994 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3995 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 3996 | u16 w, u16 h) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 3997 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 3998 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 3999 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4000 | unsigned bytespp; |
| 4001 | unsigned bytespl; |
| 4002 | unsigned bytespf; |
| 4003 | unsigned total_len; |
| 4004 | unsigned packet_payload; |
| 4005 | unsigned packet_len; |
| 4006 | u32 l; |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4007 | int r; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4008 | const unsigned channel = dsi->update_channel; |
Archit Taneja | 0c65622b | 2011-05-16 15:17:09 +0530 | [diff] [blame] | 4009 | const unsigned line_buf_size = dsi_get_line_buf_size(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4010 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4011 | DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4012 | |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 4013 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4014 | |
Archit Taneja | a3b3cc2 | 2011-09-08 18:42:16 +0530 | [diff] [blame] | 4015 | bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4016 | bytespl = w * bytespp; |
| 4017 | bytespf = bytespl * h; |
| 4018 | |
| 4019 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is |
| 4020 | * number of lines in a packet. See errata about VP_CLK_RATIO */ |
| 4021 | |
| 4022 | if (bytespf < line_buf_size) |
| 4023 | packet_payload = bytespf; |
| 4024 | else |
| 4025 | packet_payload = (line_buf_size) / bytespl * bytespl; |
| 4026 | |
| 4027 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ |
| 4028 | total_len = (bytespf / packet_payload) * packet_len; |
| 4029 | |
| 4030 | if (bytespf % packet_payload) |
| 4031 | total_len += (bytespf % packet_payload) + 1; |
| 4032 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4033 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4034 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4035 | |
Archit Taneja | 7a7c48f | 2011-08-25 18:25:03 +0530 | [diff] [blame] | 4036 | dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4037 | packet_len, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4038 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4039 | if (dsi->te_enabled) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4040 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
| 4041 | else |
| 4042 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4043 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4044 | |
| 4045 | /* We put SIDLEMODE to no-idle for the duration of the transfer, |
| 4046 | * because DSS interrupts are not capable of waking up the CPU and the |
| 4047 | * framedone interrupt could be delayed for quite a long time. I think |
| 4048 | * the same goes for any DSS interrupts, but for some reason I have not |
| 4049 | * seen the problem anywhere else than here. |
| 4050 | */ |
| 4051 | dispc_disable_sidle(); |
| 4052 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4053 | dsi_perf_mark_start(dsidev); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4054 | |
Archit Taneja | 49dbf58 | 2011-05-16 15:17:07 +0530 | [diff] [blame] | 4055 | r = schedule_delayed_work(&dsi->framedone_timeout_work, |
| 4056 | msecs_to_jiffies(250)); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4057 | BUG_ON(r == 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4058 | |
Tomi Valkeinen | 1cb0017 | 2011-11-18 11:14:01 +0200 | [diff] [blame] | 4059 | dss_mgr_start_update(dssdev->manager); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4060 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4061 | if (dsi->te_enabled) { |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4062 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
| 4063 | * for TE is longer than the timer allows */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4064 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4065 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4066 | dsi_vc_send_bta(dsidev, channel); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4067 | |
| 4068 | #ifdef DSI_CATCH_MISSING_TE |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4069 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4070 | #endif |
| 4071 | } |
| 4072 | } |
| 4073 | |
| 4074 | #ifdef DSI_CATCH_MISSING_TE |
| 4075 | static void dsi_te_timeout(unsigned long arg) |
| 4076 | { |
| 4077 | DSSERR("TE not received for 250ms!\n"); |
| 4078 | } |
| 4079 | #endif |
| 4080 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4081 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4082 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4083 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4084 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4085 | /* SIDLEMODE back to smart-idle */ |
| 4086 | dispc_enable_sidle(); |
| 4087 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4088 | if (dsi->te_enabled) { |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4089 | /* enable LP_RX_TO again after the TE */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4090 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4091 | } |
| 4092 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4093 | dsi->framedone_callback(error, dsi->framedone_data); |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4094 | |
| 4095 | if (!error) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4096 | dsi_perf_show(dsidev, "DISPC"); |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4097 | } |
| 4098 | |
| 4099 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
| 4100 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4101 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
| 4102 | framedone_timeout_work.work); |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4103 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
| 4104 | * 250ms which would conflict with this timeout work. What should be |
| 4105 | * done is first cancel the transfer on the HW, and then cancel the |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4106 | * possibly scheduled framedone work. However, cancelling the transfer |
| 4107 | * on the HW is buggy, and would probably require resetting the whole |
| 4108 | * DSI */ |
Tomi Valkeinen | 0f16aa0 | 2010-04-12 09:57:19 +0300 | [diff] [blame] | 4109 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4110 | DSSERR("Framedone not received for 250ms!\n"); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4111 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4112 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4113 | } |
| 4114 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4115 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4116 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4117 | struct omap_dss_device *dssdev = (struct omap_dss_device *) data; |
| 4118 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4119 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4120 | |
Tomi Valkeinen | ab83b14 | 2010-06-09 15:31:01 +0300 | [diff] [blame] | 4121 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
| 4122 | * turns itself off. However, DSI still has the pixels in its buffers, |
| 4123 | * and is sending the data. |
| 4124 | */ |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4125 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4126 | __cancel_delayed_work(&dsi->framedone_timeout_work); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4127 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4128 | dsi_handle_framedone(dsidev, 0); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4129 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4130 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4131 | int omap_dsi_update(struct omap_dss_device *dssdev, int channel, |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4132 | void (*callback)(int, void *), void *data) |
| 4133 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4134 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4135 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4136 | u16 dw, dh; |
| 4137 | |
| 4138 | dsi_perf_mark_setup(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4139 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4140 | dsi->update_channel = channel; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4141 | |
Tomi Valkeinen | 4a9e78a | 2011-08-15 11:22:21 +0300 | [diff] [blame] | 4142 | dsi->framedone_callback = callback; |
| 4143 | dsi->framedone_data = data; |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4144 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4145 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4146 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4147 | #ifdef DEBUG |
| 4148 | dsi->update_bytes = dw * dh * |
| 4149 | dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8; |
| 4150 | #endif |
| 4151 | dsi_update_screen_dispc(dssdev, dw, dh); |
Tomi Valkeinen | 18946f6 | 2010-01-12 14:16:41 +0200 | [diff] [blame] | 4152 | |
| 4153 | return 0; |
| 4154 | } |
| 4155 | EXPORT_SYMBOL(omap_dsi_update); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4156 | |
| 4157 | /* Display funcs */ |
| 4158 | |
| 4159 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) |
| 4160 | { |
| 4161 | int r; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4162 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4163 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4164 | u16 dw, dh; |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4165 | u32 irq; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4166 | struct omap_video_timings timings = { |
| 4167 | .hsw = 1, |
| 4168 | .hfp = 1, |
| 4169 | .hbp = 1, |
| 4170 | .vsw = 1, |
| 4171 | .vfp = 0, |
| 4172 | .vbp = 0, |
| 4173 | }; |
| 4174 | |
Tomi Valkeinen | 5476e74 | 2011-11-03 16:34:20 +0200 | [diff] [blame] | 4175 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
| 4176 | timings.x_res = dw; |
| 4177 | timings.y_res = dh; |
| 4178 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4179 | irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? |
| 4180 | DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2; |
| 4181 | |
| 4182 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, |
| 4183 | (void *) dssdev, irq); |
| 4184 | if (r) { |
| 4185 | DSSERR("can't get FRAMEDONE irq\n"); |
| 4186 | return r; |
| 4187 | } |
| 4188 | |
| 4189 | dispc_mgr_enable_stallmode(dssdev->manager->id, true); |
| 4190 | dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1); |
| 4191 | |
Archit Taneja | 4172116 | 2012-04-26 20:10:46 +0530 | [diff] [blame] | 4192 | dss_mgr_set_timings(dssdev->manager, &timings); |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4193 | } else { |
| 4194 | dispc_mgr_enable_stallmode(dssdev->manager->id, false); |
| 4195 | dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0); |
| 4196 | |
Archit Taneja | 4172116 | 2012-04-26 20:10:46 +0530 | [diff] [blame] | 4197 | dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4198 | } |
| 4199 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4200 | dispc_mgr_set_lcd_display_type(dssdev->manager->id, |
| 4201 | OMAP_DSS_LCD_DISPLAY_TFT); |
| 4202 | dispc_mgr_set_tft_data_lines(dssdev->manager->id, |
| 4203 | dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4204 | return 0; |
| 4205 | } |
| 4206 | |
| 4207 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) |
| 4208 | { |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4209 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
| 4210 | u32 irq; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4211 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4212 | irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? |
| 4213 | DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2; |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4214 | |
Archit Taneja | 8af6ff0 | 2011-09-05 16:48:27 +0530 | [diff] [blame] | 4215 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, |
| 4216 | (void *) dssdev, irq); |
| 4217 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4218 | } |
| 4219 | |
| 4220 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) |
| 4221 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4222 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4223 | struct dsi_clock_info cinfo; |
| 4224 | int r; |
| 4225 | |
Tomi Valkeinen | c6940a3 | 2011-02-22 13:36:10 +0200 | [diff] [blame] | 4226 | cinfo.regn = dssdev->clocks.dsi.regn; |
| 4227 | cinfo.regm = dssdev->clocks.dsi.regm; |
| 4228 | cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; |
| 4229 | cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; |
Tomi Valkeinen | b6e695a | 2012-03-15 15:22:58 +0200 | [diff] [blame] | 4230 | r = dsi_calc_clock_rates(dsidev, &cinfo); |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 4231 | if (r) { |
| 4232 | DSSERR("Failed to calc dsi clocks\n"); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4233 | return r; |
Ville Syrjälä | ebf0a3f | 2010-04-22 22:50:05 +0200 | [diff] [blame] | 4234 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4235 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4236 | r = dsi_pll_set_clock_div(dsidev, &cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4237 | if (r) { |
| 4238 | DSSERR("Failed to set dsi clocks\n"); |
| 4239 | return r; |
| 4240 | } |
| 4241 | |
| 4242 | return 0; |
| 4243 | } |
| 4244 | |
| 4245 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) |
| 4246 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4247 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4248 | struct dispc_clock_info dispc_cinfo; |
| 4249 | int r; |
| 4250 | unsigned long long fck; |
| 4251 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4252 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4253 | |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 4254 | dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div; |
| 4255 | dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4256 | |
| 4257 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); |
| 4258 | if (r) { |
| 4259 | DSSERR("Failed to calc dispc clocks\n"); |
| 4260 | return r; |
| 4261 | } |
| 4262 | |
Tomi Valkeinen | 26d9dd0 | 2011-08-16 13:45:15 +0300 | [diff] [blame] | 4263 | r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4264 | if (r) { |
| 4265 | DSSERR("Failed to set dispc clocks\n"); |
| 4266 | return r; |
| 4267 | } |
| 4268 | |
| 4269 | return 0; |
| 4270 | } |
| 4271 | |
| 4272 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) |
| 4273 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4274 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4275 | int dsi_module = dsi_get_dsidev_id(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4276 | int r; |
| 4277 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4278 | r = dsi_pll_init(dsidev, true, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4279 | if (r) |
| 4280 | goto err0; |
| 4281 | |
| 4282 | r = dsi_configure_dsi_clocks(dssdev); |
| 4283 | if (r) |
| 4284 | goto err1; |
| 4285 | |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 4286 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4287 | dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src); |
Archit Taneja | 9613c02 | 2011-03-22 06:33:36 -0500 | [diff] [blame] | 4288 | dss_select_lcd_clk_source(dssdev->manager->id, |
Archit Taneja | e888166 | 2011-04-12 13:52:24 +0530 | [diff] [blame] | 4289 | dssdev->clocks.dispc.channel.lcd_clk_src); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4290 | |
| 4291 | DSSDBG("PLL OK\n"); |
| 4292 | |
| 4293 | r = dsi_configure_dispc_clocks(dssdev); |
| 4294 | if (r) |
| 4295 | goto err2; |
| 4296 | |
Tomi Valkeinen | cc5c185 | 2010-10-06 15:18:13 +0300 | [diff] [blame] | 4297 | r = dsi_cio_init(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4298 | if (r) |
| 4299 | goto err2; |
| 4300 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4301 | _dsi_print_reset_status(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4302 | |
| 4303 | dsi_proto_timings(dssdev); |
| 4304 | dsi_set_lp_clk_divisor(dssdev); |
| 4305 | |
| 4306 | if (1) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4307 | _dsi_print_reset_status(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4308 | |
| 4309 | r = dsi_proto_config(dssdev); |
| 4310 | if (r) |
| 4311 | goto err3; |
| 4312 | |
| 4313 | /* enable interface */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4314 | dsi_vc_enable(dsidev, 0, 1); |
| 4315 | dsi_vc_enable(dsidev, 1, 1); |
| 4316 | dsi_vc_enable(dsidev, 2, 1); |
| 4317 | dsi_vc_enable(dsidev, 3, 1); |
| 4318 | dsi_if_enable(dsidev, 1); |
| 4319 | dsi_force_tx_stop_mode_io(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4320 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4321 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4322 | err3: |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 4323 | dsi_cio_uninit(dssdev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4324 | err2: |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 4325 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4326 | dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 5e78509 | 2011-08-10 11:25:36 +0300 | [diff] [blame] | 4327 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
| 4328 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4329 | err1: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4330 | dsi_pll_uninit(dsidev, true); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4331 | err0: |
| 4332 | return r; |
| 4333 | } |
| 4334 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 4335 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 4336 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4337 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4338 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4339 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4340 | int dsi_module = dsi_get_dsidev_id(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4341 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4342 | if (enter_ulps && !dsi->ulps_enabled) |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4343 | dsi_enter_ulps(dsidev); |
Tomi Valkeinen | 40885ab | 2010-07-28 15:53:38 +0300 | [diff] [blame] | 4344 | |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 4345 | /* disable interface */ |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4346 | dsi_if_enable(dsidev, 0); |
| 4347 | dsi_vc_enable(dsidev, 0, 0); |
| 4348 | dsi_vc_enable(dsidev, 1, 0); |
| 4349 | dsi_vc_enable(dsidev, 2, 0); |
| 4350 | dsi_vc_enable(dsidev, 3, 0); |
Ville Syrjälä | d737010 | 2010-04-22 22:50:09 +0200 | [diff] [blame] | 4351 | |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 4352 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
Archit Taneja | 5a8b572 | 2011-05-12 17:26:29 +0530 | [diff] [blame] | 4353 | dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 5e78509 | 2011-08-10 11:25:36 +0300 | [diff] [blame] | 4354 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
Tomi Valkeinen | 5bc416c | 2011-06-15 15:21:12 +0300 | [diff] [blame] | 4355 | dsi_cio_uninit(dssdev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4356 | dsi_pll_uninit(dsidev, disconnect_lanes); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4357 | } |
| 4358 | |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4359 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4360 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4361 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4362 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4363 | int r = 0; |
| 4364 | |
| 4365 | DSSDBG("dsi_display_enable\n"); |
| 4366 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4367 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4368 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4369 | mutex_lock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4370 | |
Tomi Valkeinen | 05e1d60 | 2011-06-23 16:38:21 +0300 | [diff] [blame] | 4371 | if (dssdev->manager == NULL) { |
| 4372 | DSSERR("failed to enable display: no manager\n"); |
| 4373 | r = -ENODEV; |
| 4374 | goto err_start_dev; |
| 4375 | } |
| 4376 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4377 | r = omap_dss_start_device(dssdev); |
| 4378 | if (r) { |
| 4379 | DSSERR("failed to start device\n"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4380 | goto err_start_dev; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4381 | } |
| 4382 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4383 | r = dsi_runtime_get(dsidev); |
| 4384 | if (r) |
| 4385 | goto err_get_dsi; |
| 4386 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4387 | dsi_enable_pll_clock(dsidev, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4388 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4389 | _dsi_initialize_irq(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4390 | |
| 4391 | r = dsi_display_init_dispc(dssdev); |
| 4392 | if (r) |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4393 | goto err_init_dispc; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4394 | |
| 4395 | r = dsi_display_init_dsi(dssdev); |
| 4396 | if (r) |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4397 | goto err_init_dsi; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4398 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4399 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4400 | |
| 4401 | return 0; |
| 4402 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4403 | err_init_dsi: |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4404 | dsi_display_uninit_dispc(dssdev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4405 | err_init_dispc: |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4406 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4407 | dsi_runtime_put(dsidev); |
| 4408 | err_get_dsi: |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4409 | omap_dss_stop_device(dssdev); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4410 | err_start_dev: |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4411 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4412 | DSSDBG("dsi_display_enable FAILED\n"); |
| 4413 | return r; |
| 4414 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4415 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4416 | |
Tomi Valkeinen | 2a89dc1 | 2010-07-30 12:39:34 +0300 | [diff] [blame] | 4417 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 4418 | bool disconnect_lanes, bool enter_ulps) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4419 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4420 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4421 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4422 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4423 | DSSDBG("dsi_display_disable\n"); |
| 4424 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4425 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4426 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4427 | mutex_lock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4428 | |
Tomi Valkeinen | 15ffa1d | 2011-06-16 14:34:06 +0300 | [diff] [blame] | 4429 | dsi_sync_vc(dsidev, 0); |
| 4430 | dsi_sync_vc(dsidev, 1); |
| 4431 | dsi_sync_vc(dsidev, 2); |
| 4432 | dsi_sync_vc(dsidev, 3); |
| 4433 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4434 | dsi_display_uninit_dispc(dssdev); |
| 4435 | |
Tomi Valkeinen | 22d6d67 | 2010-10-11 11:33:30 +0300 | [diff] [blame] | 4436 | dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4437 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4438 | dsi_runtime_put(dsidev); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4439 | dsi_enable_pll_clock(dsidev, 0); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4440 | |
| 4441 | omap_dss_stop_device(dssdev); |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4442 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4443 | mutex_unlock(&dsi->lock); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4444 | } |
Tomi Valkeinen | 37ac60e | 2010-01-12 15:12:07 +0200 | [diff] [blame] | 4445 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4446 | |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 4447 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4448 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4449 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4450 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4451 | |
| 4452 | dsi->te_enabled = enable; |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 4453 | return 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4454 | } |
Tomi Valkeinen | 225b650 | 2010-01-11 15:11:01 +0200 | [diff] [blame] | 4455 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4456 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4457 | int dsi_init_display(struct omap_dss_device *dssdev) |
| 4458 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4459 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4460 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4461 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4462 | DSSDBG("DSI init\n"); |
| 4463 | |
Archit Taneja | 7e951ee | 2011-07-22 12:45:04 +0530 | [diff] [blame] | 4464 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
| 4465 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | |
| 4466 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; |
| 4467 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4468 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4469 | if (dsi->vdds_dsi_reg == NULL) { |
Tomi Valkeinen | 5f42f2ce | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 4470 | struct regulator *vdds_dsi; |
| 4471 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4472 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
Tomi Valkeinen | 5f42f2ce | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 4473 | |
| 4474 | if (IS_ERR(vdds_dsi)) { |
| 4475 | DSSERR("can't get VDDS_DSI regulator\n"); |
| 4476 | return PTR_ERR(vdds_dsi); |
| 4477 | } |
| 4478 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4479 | dsi->vdds_dsi_reg = vdds_dsi; |
Tomi Valkeinen | 5f42f2ce | 2011-02-22 15:53:46 +0200 | [diff] [blame] | 4480 | } |
| 4481 | |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4482 | return 0; |
| 4483 | } |
| 4484 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4485 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
| 4486 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4487 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4488 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4489 | int i; |
| 4490 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4491 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
| 4492 | if (!dsi->vc[i].dssdev) { |
| 4493 | dsi->vc[i].dssdev = dssdev; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4494 | *channel = i; |
| 4495 | return 0; |
| 4496 | } |
| 4497 | } |
| 4498 | |
| 4499 | DSSERR("cannot get VC for display %s", dssdev->name); |
| 4500 | return -ENOSPC; |
| 4501 | } |
| 4502 | EXPORT_SYMBOL(omap_dsi_request_vc); |
| 4503 | |
| 4504 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) |
| 4505 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4506 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4507 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4508 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4509 | if (vc_id < 0 || vc_id > 3) { |
| 4510 | DSSERR("VC ID out of range\n"); |
| 4511 | return -EINVAL; |
| 4512 | } |
| 4513 | |
| 4514 | if (channel < 0 || channel > 3) { |
| 4515 | DSSERR("Virtual Channel out of range\n"); |
| 4516 | return -EINVAL; |
| 4517 | } |
| 4518 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4519 | if (dsi->vc[channel].dssdev != dssdev) { |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4520 | DSSERR("Virtual Channel not allocated to display %s\n", |
| 4521 | dssdev->name); |
| 4522 | return -EINVAL; |
| 4523 | } |
| 4524 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4525 | dsi->vc[channel].vc_id = vc_id; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4526 | |
| 4527 | return 0; |
| 4528 | } |
| 4529 | EXPORT_SYMBOL(omap_dsi_set_vc_id); |
| 4530 | |
| 4531 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) |
| 4532 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4533 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
| 4534 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4535 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4536 | if ((channel >= 0 && channel <= 3) && |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4537 | dsi->vc[channel].dssdev == dssdev) { |
| 4538 | dsi->vc[channel].dssdev = NULL; |
| 4539 | dsi->vc[channel].vc_id = 0; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4540 | } |
| 4541 | } |
| 4542 | EXPORT_SYMBOL(omap_dsi_release_vc); |
| 4543 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4544 | void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4545 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4546 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 4547 | DSSERR("%s (%s) not active\n", |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 4548 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
| 4549 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4550 | } |
| 4551 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4552 | void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev) |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4553 | { |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4554 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1) |
Archit Taneja | 067a57e | 2011-03-02 11:57:25 +0530 | [diff] [blame] | 4555 | DSSERR("%s (%s) not active\n", |
Archit Taneja | 89a35e5 | 2011-04-12 13:52:23 +0530 | [diff] [blame] | 4556 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
| 4557 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); |
Tomi Valkeinen | e406f90 | 2010-06-09 15:28:12 +0300 | [diff] [blame] | 4558 | } |
| 4559 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4560 | static void dsi_calc_clock_param_ranges(struct platform_device *dsidev) |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 4561 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4562 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4563 | |
| 4564 | dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); |
| 4565 | dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); |
| 4566 | dsi->regm_dispc_max = |
| 4567 | dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); |
| 4568 | dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); |
| 4569 | dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); |
| 4570 | dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); |
| 4571 | dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 4572 | } |
| 4573 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4574 | static int dsi_get_clocks(struct platform_device *dsidev) |
| 4575 | { |
| 4576 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4577 | struct clk *clk; |
| 4578 | |
| 4579 | clk = clk_get(&dsidev->dev, "fck"); |
| 4580 | if (IS_ERR(clk)) { |
| 4581 | DSSERR("can't get fck\n"); |
| 4582 | return PTR_ERR(clk); |
| 4583 | } |
| 4584 | |
| 4585 | dsi->dss_clk = clk; |
| 4586 | |
Tomi Valkeinen | bfe4f8d | 2011-08-04 11:22:54 +0300 | [diff] [blame] | 4587 | clk = clk_get(&dsidev->dev, "sys_clk"); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4588 | if (IS_ERR(clk)) { |
| 4589 | DSSERR("can't get sys_clk\n"); |
| 4590 | clk_put(dsi->dss_clk); |
| 4591 | dsi->dss_clk = NULL; |
| 4592 | return PTR_ERR(clk); |
| 4593 | } |
| 4594 | |
| 4595 | dsi->sys_clk = clk; |
| 4596 | |
| 4597 | return 0; |
| 4598 | } |
| 4599 | |
| 4600 | static void dsi_put_clocks(struct platform_device *dsidev) |
| 4601 | { |
| 4602 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4603 | |
| 4604 | if (dsi->dss_clk) |
| 4605 | clk_put(dsi->dss_clk); |
| 4606 | if (dsi->sys_clk) |
| 4607 | clk_put(dsi->sys_clk); |
| 4608 | } |
| 4609 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 4610 | /* DSI1 HW IP initialisation */ |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 4611 | static int __init omap_dsihw_probe(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4612 | { |
| 4613 | u32 rev; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4614 | int r, i, dsi_module = dsi_get_dsidev_id(dsidev); |
Senthilvadivu Guruswamy | ea9da36 | 2011-01-24 06:22:04 +0000 | [diff] [blame] | 4615 | struct resource *dsi_mem; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4616 | struct dsi_data *dsi; |
Tomi Valkeinen | 35deca3 | 2012-03-01 15:45:53 +0200 | [diff] [blame^] | 4617 | struct omap_dss_board_info *pdata = dsidev->dev.platform_data; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4618 | |
Julia Lawall | 6e2a14d | 2012-01-24 14:00:45 +0100 | [diff] [blame] | 4619 | dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4620 | if (!dsi) |
| 4621 | return -ENOMEM; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4622 | |
| 4623 | dsi->pdev = dsidev; |
| 4624 | dsi_pdev_map[dsi_module] = dsidev; |
| 4625 | dev_set_drvdata(&dsidev->dev, dsi); |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4626 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4627 | spin_lock_init(&dsi->irq_lock); |
| 4628 | spin_lock_init(&dsi->errors_lock); |
| 4629 | dsi->errors = 0; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4630 | |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 4631 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4632 | spin_lock_init(&dsi->irq_stats_lock); |
| 4633 | dsi->irq_stats.last_reset = jiffies; |
Tomi Valkeinen | dfc0fd8 | 2009-12-17 14:35:21 +0200 | [diff] [blame] | 4634 | #endif |
| 4635 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4636 | mutex_init(&dsi->lock); |
| 4637 | sema_init(&dsi->bus_lock, 1); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4638 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4639 | INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work, |
| 4640 | dsi_framedone_timeout_work_callback); |
| 4641 | |
| 4642 | #ifdef DSI_CATCH_MISSING_TE |
| 4643 | init_timer(&dsi->te_timer); |
| 4644 | dsi->te_timer.function = dsi_te_timeout; |
| 4645 | dsi->te_timer.data = 0; |
| 4646 | #endif |
| 4647 | dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0); |
| 4648 | if (!dsi_mem) { |
| 4649 | DSSERR("can't get IORESOURCE_MEM DSI\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4650 | return -EINVAL; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4651 | } |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4652 | |
Julia Lawall | 6e2a14d | 2012-01-24 14:00:45 +0100 | [diff] [blame] | 4653 | dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start, |
| 4654 | resource_size(dsi_mem)); |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4655 | if (!dsi->base) { |
| 4656 | DSSERR("can't ioremap DSI\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4657 | return -ENOMEM; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4658 | } |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4659 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4660 | dsi->irq = platform_get_irq(dsi->pdev, 0); |
| 4661 | if (dsi->irq < 0) { |
| 4662 | DSSERR("platform_get_irq failed\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4663 | return -ENODEV; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4664 | } |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4665 | |
Julia Lawall | 6e2a14d | 2012-01-24 14:00:45 +0100 | [diff] [blame] | 4666 | r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, |
| 4667 | IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4668 | if (r < 0) { |
| 4669 | DSSERR("request_irq failed\n"); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4670 | return r; |
archit taneja | affe360 | 2011-02-23 08:41:03 +0000 | [diff] [blame] | 4671 | } |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4672 | |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4673 | /* DSI VCs initialization */ |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4674 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
Archit Taneja | d604914 | 2011-08-22 11:58:08 +0530 | [diff] [blame] | 4675 | dsi->vc[i].source = DSI_VC_SOURCE_L4; |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4676 | dsi->vc[i].dssdev = NULL; |
| 4677 | dsi->vc[i].vc_id = 0; |
Archit Taneja | 5ee3c14 | 2011-03-02 12:35:53 +0530 | [diff] [blame] | 4678 | } |
| 4679 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4680 | dsi_calc_clock_param_ranges(dsidev); |
Taneja, Archit | 4964111 | 2011-03-14 23:28:23 -0500 | [diff] [blame] | 4681 | |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4682 | r = dsi_get_clocks(dsidev); |
| 4683 | if (r) |
| 4684 | return r; |
| 4685 | |
| 4686 | pm_runtime_enable(&dsidev->dev); |
| 4687 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4688 | r = dsi_runtime_get(dsidev); |
| 4689 | if (r) |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4690 | goto err_runtime_get; |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4691 | |
Archit Taneja | a72b64b | 2011-05-12 17:26:26 +0530 | [diff] [blame] | 4692 | rev = dsi_read_reg(dsidev, DSI_REVISION); |
| 4693 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4694 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
| 4695 | |
Tomi Valkeinen | d982085 | 2011-10-12 15:05:59 +0300 | [diff] [blame] | 4696 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number |
| 4697 | * of data to 3 by default */ |
| 4698 | if (dss_has_feature(FEAT_DSI_GNQ)) |
| 4699 | /* NB_DATA_LANES */ |
| 4700 | dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); |
| 4701 | else |
| 4702 | dsi->num_lanes_supported = 3; |
Archit Taneja | 75d7247 | 2011-05-16 15:17:08 +0530 | [diff] [blame] | 4703 | |
Tomi Valkeinen | 35deca3 | 2012-03-01 15:45:53 +0200 | [diff] [blame^] | 4704 | for (i = 0; i < pdata->num_devices; ++i) { |
| 4705 | struct omap_dss_device *dssdev = pdata->devices[i]; |
| 4706 | |
| 4707 | if (dssdev->type != OMAP_DISPLAY_TYPE_DSI) |
| 4708 | continue; |
| 4709 | |
| 4710 | if (dssdev->phy.dsi.module != dsi_module) |
| 4711 | continue; |
| 4712 | |
| 4713 | r = omap_dss_register_device(dssdev, &dsidev->dev, i); |
| 4714 | if (r) |
| 4715 | DSSERR("device %s register failed: %d\n", |
| 4716 | dssdev->name, r); |
| 4717 | } |
| 4718 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4719 | dsi_runtime_put(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4720 | |
Tomi Valkeinen | e40402c | 2012-03-02 18:01:07 +0200 | [diff] [blame] | 4721 | if (dsi_module == 0) |
| 4722 | dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); |
| 4723 | else if (dsi_module == 1) |
| 4724 | dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); |
| 4725 | |
| 4726 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
| 4727 | if (dsi_module == 0) |
| 4728 | dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); |
| 4729 | else if (dsi_module == 1) |
| 4730 | dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); |
| 4731 | #endif |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4732 | return 0; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4733 | |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4734 | err_runtime_get: |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4735 | pm_runtime_disable(&dsidev->dev); |
Tomi Valkeinen | cd3b344 | 2012-01-25 13:31:04 +0200 | [diff] [blame] | 4736 | dsi_put_clocks(dsidev); |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4737 | return r; |
| 4738 | } |
| 4739 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 4740 | static int __exit omap_dsihw_remove(struct platform_device *dsidev) |
Tomi Valkeinen | 3de7a1d | 2009-10-28 11:59:56 +0200 | [diff] [blame] | 4741 | { |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4742 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
| 4743 | |
Tomi Valkeinen | b98482e | 2011-05-16 13:52:51 +0300 | [diff] [blame] | 4744 | WARN_ON(dsi->scp_clk_refcount > 0); |
| 4745 | |
Tomi Valkeinen | 35deca3 | 2012-03-01 15:45:53 +0200 | [diff] [blame^] | 4746 | omap_dss_unregister_child_devices(&dsidev->dev); |
| 4747 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4748 | pm_runtime_disable(&dsidev->dev); |
| 4749 | |
| 4750 | dsi_put_clocks(dsidev); |
| 4751 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4752 | if (dsi->vdds_dsi_reg != NULL) { |
| 4753 | if (dsi->vdds_dsi_enabled) { |
| 4754 | regulator_disable(dsi->vdds_dsi_reg); |
| 4755 | dsi->vdds_dsi_enabled = false; |
Tomi Valkeinen | 88257b2 | 2010-12-20 16:26:22 +0200 | [diff] [blame] | 4756 | } |
| 4757 | |
Archit Taneja | f1da39d | 2011-05-12 17:26:27 +0530 | [diff] [blame] | 4758 | regulator_put(dsi->vdds_dsi_reg); |
| 4759 | dsi->vdds_dsi_reg = NULL; |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4760 | } |
| 4761 | |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4762 | return 0; |
| 4763 | } |
| 4764 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4765 | static int dsi_runtime_suspend(struct device *dev) |
| 4766 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4767 | dispc_runtime_put(); |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4768 | |
| 4769 | return 0; |
| 4770 | } |
| 4771 | |
| 4772 | static int dsi_runtime_resume(struct device *dev) |
| 4773 | { |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4774 | int r; |
| 4775 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4776 | r = dispc_runtime_get(); |
| 4777 | if (r) |
Tomi Valkeinen | 852f083 | 2012-02-17 17:58:04 +0200 | [diff] [blame] | 4778 | return r; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4779 | |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4780 | return 0; |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4781 | } |
| 4782 | |
| 4783 | static const struct dev_pm_ops dsi_pm_ops = { |
| 4784 | .runtime_suspend = dsi_runtime_suspend, |
| 4785 | .runtime_resume = dsi_runtime_resume, |
| 4786 | }; |
| 4787 | |
Tomi Valkeinen | 7c68dd9 | 2011-08-03 14:00:57 +0300 | [diff] [blame] | 4788 | static struct platform_driver omap_dsihw_driver = { |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 4789 | .remove = __exit_p(omap_dsihw_remove), |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4790 | .driver = { |
Tomi Valkeinen | 7c68dd9 | 2011-08-03 14:00:57 +0300 | [diff] [blame] | 4791 | .name = "omapdss_dsi", |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4792 | .owner = THIS_MODULE, |
Tomi Valkeinen | 4fbafaf | 2011-05-27 10:52:19 +0300 | [diff] [blame] | 4793 | .pm = &dsi_pm_ops, |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4794 | }, |
| 4795 | }; |
| 4796 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 4797 | int __init dsi_init_platform_driver(void) |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4798 | { |
Tomi Valkeinen | 61055d4 | 2012-03-07 12:53:38 +0200 | [diff] [blame] | 4799 | return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe); |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4800 | } |
| 4801 | |
Tomi Valkeinen | 6e7e8f0 | 2012-02-17 17:41:13 +0200 | [diff] [blame] | 4802 | void __exit dsi_uninit_platform_driver(void) |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4803 | { |
Tomi Valkeinen | 04c742c | 2012-02-23 15:32:37 +0200 | [diff] [blame] | 4804 | platform_driver_unregister(&omap_dsihw_driver); |
Senthilvadivu Guruswamy | c8aac01 | 2011-01-24 06:22:02 +0000 | [diff] [blame] | 4805 | } |