blob: 8d91131aa5ab9c693a4f2b7146e5a62fa0d614bd [file] [log] [blame]
Ben Hutchings8ceee662008-04-27 12:55:59 +01001/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2006-2008 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9/*
10 * Useful functions for working with MDIO clause 45 PHYs
11 */
12#include <linux/types.h>
13#include <linux/ethtool.h>
14#include <linux/delay.h>
15#include "net_driver.h"
16#include "mdio_10g.h"
17#include "boards.h"
18
19int mdio_clause45_reset_mmd(struct efx_nic *port, int mmd,
20 int spins, int spintime)
21{
22 u32 ctrl;
23 int phy_id = port->mii.phy_id;
24
25 /* Catch callers passing values in the wrong units (or just silly) */
26 EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
27
28 mdio_clause45_write(port, phy_id, mmd, MDIO_MMDREG_CTRL1,
29 (1 << MDIO_MMDREG_CTRL1_RESET_LBN));
30 /* Wait for the reset bit to clear. */
31 do {
32 msleep(spintime);
33 ctrl = mdio_clause45_read(port, phy_id, mmd, MDIO_MMDREG_CTRL1);
34 spins--;
35
36 } while (spins && (ctrl & (1 << MDIO_MMDREG_CTRL1_RESET_LBN)));
37
38 return spins ? spins : -ETIMEDOUT;
39}
40
41static int mdio_clause45_check_mmd(struct efx_nic *efx, int mmd,
42 int fault_fatal)
43{
44 int status;
45 int phy_id = efx->mii.phy_id;
46
Ben Hutchings3273c2e2008-05-07 13:36:19 +010047 if (LOOPBACK_INTERNAL(efx))
48 return 0;
49
Ben Hutchings8ceee662008-04-27 12:55:59 +010050 /* Read MMD STATUS2 to check it is responding. */
51 status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT2);
52 if (((status >> MDIO_MMDREG_STAT2_PRESENT_LBN) &
53 ((1 << MDIO_MMDREG_STAT2_PRESENT_WIDTH) - 1)) !=
54 MDIO_MMDREG_STAT2_PRESENT_VAL) {
55 EFX_ERR(efx, "PHY MMD %d not responding.\n", mmd);
56 return -EIO;
57 }
58
59 /* Read MMD STATUS 1 to check for fault. */
60 status = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_STAT1);
61 if ((status & (1 << MDIO_MMDREG_STAT1_FAULT_LBN)) != 0) {
62 if (fault_fatal) {
63 EFX_ERR(efx, "PHY MMD %d reporting fatal"
64 " fault: status %x\n", mmd, status);
65 return -EIO;
66 } else {
67 EFX_LOG(efx, "PHY MMD %d reporting status"
68 " %x (expected)\n", mmd, status);
69 }
70 }
71 return 0;
72}
73
74/* This ought to be ridiculous overkill. We expect it to fail rarely */
75#define MDIO45_RESET_TIME 1000 /* ms */
76#define MDIO45_RESET_ITERS 100
77
78int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
79 unsigned int mmd_mask)
80{
81 const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
82 int tries = MDIO45_RESET_ITERS;
83 int rc = 0;
84 int in_reset;
85
86 while (tries) {
87 int mask = mmd_mask;
88 int mmd = 0;
89 int stat;
90 in_reset = 0;
91 while (mask) {
92 if (mask & 1) {
93 stat = mdio_clause45_read(efx,
94 efx->mii.phy_id,
95 mmd,
96 MDIO_MMDREG_CTRL1);
97 if (stat < 0) {
98 EFX_ERR(efx, "failed to read status of"
99 " MMD %d\n", mmd);
100 return -EIO;
101 }
102 if (stat & (1 << MDIO_MMDREG_CTRL1_RESET_LBN))
103 in_reset |= (1 << mmd);
104 }
105 mask = mask >> 1;
106 mmd++;
107 }
108 if (!in_reset)
109 break;
110 tries--;
111 msleep(spintime);
112 }
113 if (in_reset != 0) {
114 EFX_ERR(efx, "not all MMDs came out of reset in time."
115 " MMDs still in reset: %x\n", in_reset);
116 rc = -ETIMEDOUT;
117 }
118 return rc;
119}
120
121int mdio_clause45_check_mmds(struct efx_nic *efx,
122 unsigned int mmd_mask, unsigned int fatal_mask)
123{
Ben Hutchings27dd2ca2008-12-12 21:44:14 -0800124 u32 devices;
125 int mmd = 0, probe_mmd;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100126
127 /* Historically we have probed the PHYXS to find out what devices are
128 * present,but that doesn't work so well if the PHYXS isn't expected
129 * to exist, if so just find the first item in the list supplied. */
Ben Hutchings27dd2ca2008-12-12 21:44:14 -0800130 probe_mmd = (mmd_mask & MDIO_MMDREG_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
Ben Hutchings8ceee662008-04-27 12:55:59 +0100131 __ffs(mmd_mask);
Ben Hutchings27dd2ca2008-12-12 21:44:14 -0800132 devices = (mdio_clause45_read(efx, efx->mii.phy_id,
133 probe_mmd, MDIO_MMDREG_DEVS0) |
134 mdio_clause45_read(efx, efx->mii.phy_id,
135 probe_mmd, MDIO_MMDREG_DEVS1) << 16);
Ben Hutchings8ceee662008-04-27 12:55:59 +0100136
137 /* Check all the expected MMDs are present */
138 if (devices < 0) {
139 EFX_ERR(efx, "failed to read devices present\n");
140 return -EIO;
141 }
142 if ((devices & mmd_mask) != mmd_mask) {
143 EFX_ERR(efx, "required MMDs not present: got %x, "
144 "wanted %x\n", devices, mmd_mask);
145 return -ENODEV;
146 }
147 EFX_TRACE(efx, "Devices present: %x\n", devices);
148
149 /* Check all required MMDs are responding and happy. */
150 while (mmd_mask) {
151 if (mmd_mask & 1) {
152 int fault_fatal = fatal_mask & 1;
153 if (mdio_clause45_check_mmd(efx, mmd, fault_fatal))
154 return -EIO;
155 }
156 mmd_mask = mmd_mask >> 1;
157 fatal_mask = fatal_mask >> 1;
158 mmd++;
159 }
160
161 return 0;
162}
163
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100164bool mdio_clause45_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
Ben Hutchings8ceee662008-04-27 12:55:59 +0100165{
166 int phy_id = efx->mii.phy_id;
167 int status;
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100168 bool ok = true;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100169 int mmd = 0;
Ben Hutchings8ceee662008-04-27 12:55:59 +0100170
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100171 /* If the port is in loopback, then we should only consider a subset
172 * of mmd's */
173 if (LOOPBACK_INTERNAL(efx))
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100174 return true;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100175 else if (efx->loopback_mode == LOOPBACK_NETWORK)
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100176 return false;
Ben Hutchingsf8b87c12008-09-01 12:48:17 +0100177 else if (efx_phy_mode_disabled(efx->phy_mode))
178 return false;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100179 else if (efx->loopback_mode == LOOPBACK_PHYXS)
Ben Hutchings27dd2ca2008-12-12 21:44:14 -0800180 mmd_mask &= ~(MDIO_MMDREG_DEVS_PHYXS |
181 MDIO_MMDREG_DEVS_PCS |
182 MDIO_MMDREG_DEVS_PMAPMD);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100183 else if (efx->loopback_mode == LOOPBACK_PCS)
Ben Hutchings27dd2ca2008-12-12 21:44:14 -0800184 mmd_mask &= ~(MDIO_MMDREG_DEVS_PCS |
185 MDIO_MMDREG_DEVS_PMAPMD);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100186 else if (efx->loopback_mode == LOOPBACK_PMAPMD)
Ben Hutchings27dd2ca2008-12-12 21:44:14 -0800187 mmd_mask &= ~MDIO_MMDREG_DEVS_PMAPMD;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100188
Ben Hutchings8ceee662008-04-27 12:55:59 +0100189 while (mmd_mask) {
190 if (mmd_mask & 1) {
191 /* Double reads because link state is latched, and a
192 * read moves the current state into the register */
193 status = mdio_clause45_read(efx, phy_id,
194 mmd, MDIO_MMDREG_STAT1);
195 status = mdio_clause45_read(efx, phy_id,
196 mmd, MDIO_MMDREG_STAT1);
197
Ben Hutchingsdc8cfa52008-09-01 12:46:50 +0100198 ok = ok && (status & (1 << MDIO_MMDREG_STAT1_LINK_LBN));
Ben Hutchings8ceee662008-04-27 12:55:59 +0100199 }
200 mmd_mask = (mmd_mask >> 1);
201 mmd++;
202 }
203 return ok;
204}
205
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100206void mdio_clause45_transmit_disable(struct efx_nic *efx)
207{
Ben Hutchings356eebb2008-12-12 21:48:57 -0800208 mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
209 MDIO_MMDREG_TXDIS, MDIO_MMDREG_TXDIS_GLOBAL_LBN,
210 efx->phy_mode & PHY_MODE_TX_DISABLED);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100211}
212
213void mdio_clause45_phy_reconfigure(struct efx_nic *efx)
214{
215 int phy_id = efx->mii.phy_id;
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100216
Ben Hutchings356eebb2008-12-12 21:48:57 -0800217 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD,
218 MDIO_MMDREG_CTRL1, MDIO_PMAPMD_CTRL1_LBACK_LBN,
219 efx->loopback_mode == LOOPBACK_PMAPMD);
220 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PCS,
221 MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
222 efx->loopback_mode == LOOPBACK_PCS);
223 mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS,
224 MDIO_MMDREG_CTRL1, MDIO_MMDREG_CTRL1_LBACK_LBN,
225 efx->loopback_mode == LOOPBACK_NETWORK);
Ben Hutchings3273c2e2008-05-07 13:36:19 +0100226}
227
Ben Hutchings3e133c42008-11-04 20:34:56 +0000228static void mdio_clause45_set_mmd_lpower(struct efx_nic *efx,
229 int lpower, int mmd)
230{
231 int phy = efx->mii.phy_id;
232 int stat = mdio_clause45_read(efx, phy, mmd, MDIO_MMDREG_STAT1);
Ben Hutchings3e133c42008-11-04 20:34:56 +0000233
234 EFX_TRACE(efx, "Setting low power mode for MMD %d to %d\n",
235 mmd, lpower);
236
237 if (stat & (1 << MDIO_MMDREG_STAT1_LPABLE_LBN)) {
Ben Hutchings356eebb2008-12-12 21:48:57 -0800238 mdio_clause45_set_flag(efx, phy, mmd, MDIO_MMDREG_CTRL1,
239 MDIO_MMDREG_CTRL1_LPOWER_LBN, lpower);
Ben Hutchings3e133c42008-11-04 20:34:56 +0000240 }
241}
242
243void mdio_clause45_set_mmds_lpower(struct efx_nic *efx,
244 int low_power, unsigned int mmd_mask)
245{
246 int mmd = 0;
247 while (mmd_mask) {
248 if (mmd_mask & 1)
249 mdio_clause45_set_mmd_lpower(efx, low_power, mmd);
250 mmd_mask = (mmd_mask >> 1);
251 mmd++;
252 }
253}
254
Ben Hutchings8ceee662008-04-27 12:55:59 +0100255/**
256 * mdio_clause45_get_settings - Read (some of) the PHY settings over MDIO.
257 * @efx: Efx NIC
258 * @ecmd: Buffer for settings
259 *
260 * On return the 'port', 'speed', 'supported' and 'advertising' fields of
261 * ecmd have been filled out based on the PMA type.
262 */
263void mdio_clause45_get_settings(struct efx_nic *efx,
264 struct ethtool_cmd *ecmd)
265{
266 int pma_type;
267
268 /* If no PMA is present we are presumably talking something XAUI-ish
269 * like CX4. Which we report as FIBRE (see below) */
270 if ((efx->phy_op->mmds & DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)) == 0) {
271 ecmd->speed = SPEED_10000;
272 ecmd->port = PORT_FIBRE;
273 ecmd->supported = SUPPORTED_FIBRE;
274 ecmd->advertising = ADVERTISED_FIBRE;
275 return;
276 }
277
278 pma_type = mdio_clause45_read(efx, efx->mii.phy_id,
279 MDIO_MMD_PMAPMD, MDIO_MMDREG_CTRL2);
280 pma_type &= MDIO_PMAPMD_CTRL2_TYPE_MASK;
281
282 switch (pma_type) {
283 /* We represent CX4 as fibre in the absence of anything
284 better. */
285 case MDIO_PMAPMD_CTRL2_10G_CX4:
286 ecmd->speed = SPEED_10000;
287 ecmd->port = PORT_FIBRE;
288 ecmd->supported = SUPPORTED_FIBRE;
289 ecmd->advertising = ADVERTISED_FIBRE;
290 break;
291 /* 10G Base-T */
292 case MDIO_PMAPMD_CTRL2_10G_BT:
293 ecmd->speed = SPEED_10000;
294 ecmd->port = PORT_TP;
295 ecmd->supported = SUPPORTED_TP | SUPPORTED_10000baseT_Full;
296 ecmd->advertising = (ADVERTISED_FIBRE
297 | ADVERTISED_10000baseT_Full);
298 break;
299 case MDIO_PMAPMD_CTRL2_1G_BT:
300 ecmd->speed = SPEED_1000;
301 ecmd->port = PORT_TP;
302 ecmd->supported = SUPPORTED_TP | SUPPORTED_1000baseT_Full;
303 ecmd->advertising = (ADVERTISED_FIBRE
304 | ADVERTISED_1000baseT_Full);
305 break;
306 case MDIO_PMAPMD_CTRL2_100_BT:
307 ecmd->speed = SPEED_100;
308 ecmd->port = PORT_TP;
309 ecmd->supported = SUPPORTED_TP | SUPPORTED_100baseT_Full;
310 ecmd->advertising = (ADVERTISED_FIBRE
311 | ADVERTISED_100baseT_Full);
312 break;
313 case MDIO_PMAPMD_CTRL2_10_BT:
314 ecmd->speed = SPEED_10;
315 ecmd->port = PORT_TP;
316 ecmd->supported = SUPPORTED_TP | SUPPORTED_10baseT_Full;
317 ecmd->advertising = ADVERTISED_FIBRE | ADVERTISED_10baseT_Full;
318 break;
319 /* All the other defined modes are flavours of
320 * 10G optical */
321 default:
322 ecmd->speed = SPEED_10000;
323 ecmd->port = PORT_FIBRE;
324 ecmd->supported = SUPPORTED_FIBRE;
325 ecmd->advertising = ADVERTISED_FIBRE;
326 break;
327 }
328}
329
330/**
331 * mdio_clause45_set_settings - Set (some of) the PHY settings over MDIO.
332 * @efx: Efx NIC
333 * @ecmd: New settings
334 *
335 * Currently this just enforces that we are _not_ changing the
336 * 'port', 'speed', 'supported' or 'advertising' settings as these
337 * cannot be changed on any currently supported PHY.
338 */
339int mdio_clause45_set_settings(struct efx_nic *efx,
340 struct ethtool_cmd *ecmd)
341{
342 struct ethtool_cmd tmpcmd;
343 mdio_clause45_get_settings(efx, &tmpcmd);
344 /* None of the current PHYs support more than one mode
345 * of operation (and only 10GBT ever will), so keep things
346 * simple for now */
347 if ((ecmd->speed == tmpcmd.speed) && (ecmd->port == tmpcmd.port) &&
348 (ecmd->supported == tmpcmd.supported) &&
349 (ecmd->advertising == tmpcmd.advertising))
350 return 0;
351 return -EOPNOTSUPP;
352}
Ben Hutchings356eebb2008-12-12 21:48:57 -0800353
354void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev,
355 u16 addr, int bit, bool sense)
356{
357 int old_val = mdio_clause45_read(efx, prt, dev, addr);
358 int new_val;
359
360 if (sense)
361 new_val = old_val | (1 << bit);
362 else
363 new_val = old_val & ~(1 << bit);
364 if (old_val != new_val)
365 mdio_clause45_write(efx, prt, dev, addr, new_val);
366}