| Tomasz Figa | 2ec35a4 | 2013-08-26 02:38:41 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Samsung S3C6410 based SMDK6410 board device tree source. |
| 3 | * |
| 4 | * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> |
| 5 | * |
| 6 | * Device tree source file for SAMSUNG SMDK6410 board which is based on |
| 7 | * Samsung's S3C6410 SoC. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as |
| 11 | * published by the Free Software Foundation. |
| 12 | */ |
| 13 | |
| 14 | /dts-v1/; |
| 15 | |
| 16 | #include <dt-bindings/gpio/gpio.h> |
| 17 | #include <dt-bindings/interrupt-controller/irq.h> |
| 18 | |
| 19 | #include "s3c6410.dtsi" |
| 20 | |
| 21 | / { |
| 22 | model = "SAMSUNG SMDK6410 board based on S3C6410"; |
| 23 | compatible = "samsung,mini6410", "samsung,s3c6410"; |
| 24 | |
| 25 | memory { |
| 26 | reg = <0x50000000 0x8000000>; |
| 27 | }; |
| 28 | |
| 29 | chosen { |
| 30 | bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; |
| 31 | }; |
| 32 | |
| 33 | clocks { |
| 34 | compatible = "simple-bus"; |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <0>; |
| 37 | |
| 38 | fin_pll: oscillator@0 { |
| 39 | compatible = "fixed-clock"; |
| 40 | reg = <0>; |
| 41 | clock-frequency = <12000000>; |
| 42 | clock-output-names = "fin_pll"; |
| 43 | #clock-cells = <0>; |
| 44 | }; |
| 45 | |
| 46 | xusbxti: oscillator@1 { |
| 47 | compatible = "fixed-clock"; |
| 48 | reg = <1>; |
| 49 | clock-output-names = "xusbxti"; |
| 50 | clock-frequency = <48000000>; |
| 51 | #clock-cells = <0>; |
| 52 | }; |
| 53 | }; |
| 54 | |
| 55 | srom-cs1@18000000 { |
| 56 | compatible = "simple-bus"; |
| 57 | #address-cells = <1>; |
| 58 | #size-cells = <1>; |
| 59 | reg = <0x18000000 0x8000000>; |
| 60 | ranges; |
| 61 | |
| 62 | ethernet@18000000 { |
| 63 | compatible = "smsc,lan9115"; |
| 64 | reg = <0x18000000 0x10000>; |
| 65 | interrupt-parent = <&gpn>; |
| 66 | interrupts = <10 IRQ_TYPE_LEVEL_LOW>; |
| 67 | phy-mode = "mii"; |
| 68 | reg-io-width = <4>; |
| 69 | smsc,force-internal-phy; |
| 70 | }; |
| 71 | }; |
| 72 | }; |
| 73 | |
| 74 | &sdhci0 { |
| 75 | pinctrl-names = "default"; |
| 76 | pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; |
| 77 | bus-width = <4>; |
| 78 | status = "okay"; |
| 79 | }; |
| 80 | |
| 81 | &uart0 { |
| 82 | pinctrl-names = "default"; |
| 83 | pinctrl-0 = <&uart0_data>, <&uart0_fctl>; |
| 84 | status = "okay"; |
| 85 | }; |
| 86 | |
| 87 | &uart1 { |
| 88 | pinctrl-names = "default"; |
| 89 | pinctrl-0 = <&uart1_data>; |
| 90 | status = "okay"; |
| 91 | }; |
| 92 | |
| 93 | &uart2 { |
| 94 | pinctrl-names = "default"; |
| 95 | pinctrl-0 = <&uart2_data>; |
| 96 | status = "okay"; |
| 97 | }; |
| 98 | |
| 99 | &uart3 { |
| 100 | pinctrl-names = "default"; |
| 101 | pinctrl-0 = <&uart3_data>; |
| 102 | status = "okay"; |
| 103 | }; |