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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 2ff6197f94be2c1c4efddeec9ae1a9065620cfe7 / . / drivers / pinctrl / mediatek / pinctrl-mt7623.c
blob: b8d9d31db74f7c21a0bf7f67a5af9ea265c7eca6 [file] [log] [blame]
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * The MT7623 driver based on Linux generic pinctrl binding.
4 *
5 * Copyright (C) 2015 - 2018 MediaTek Inc.
6 * Author: Biao Huang <biao.huang@mediatek.com>
7 * Ryder Lee <ryder.lee@mediatek.com>
8 * Sean Wang <sean.wang@mediatek.com>
9 */
10
11#include "pinctrl-moore.h"
12
13#define PIN_BOND_REG0 0xb10
14#define PIN_BOND_REG1 0xf20
15#define PIN_BOND_REG2 0xef0
16#define BOND_PCIE_CLR (0x77 << 3)
17#define BOND_I2S_CLR 0x3
18#define BOND_MSDC0E_CLR 0x1
19
20#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
Sean Wang2bc47df2018-09-08 19:07:30 +0800[diff] [blame]21 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]22 _x_bits, 15, false)
23
24#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
Sean Wang2bc47df2018-09-08 19:07:30 +0800[diff] [blame]25 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]26 _x_bits, 16, 0)
27
Sean Wang2bc47df2018-09-08 19:07:30 +0800[diff] [blame]28#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
29 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]30 _x_bits, 16, 1)
31
32#define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \
Sean Wangb7d7f9e2018-09-08 19:07:32 +0800[diff] [blame]33 MTK_PIN(_number, _name, 0, _eint_n, _drv_grp)
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]34
35static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
36 PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
37};
38
39static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
40 PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
41 PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
42};
43
44static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
45 PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
46};
47
48static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
49 PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
50};
51
52static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
53 PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
54 PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
55 PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
56 PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
57 PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
58 PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
59 PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
60 PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
61 PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
62 PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
63 PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
64 PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
65 PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
66 PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
67 PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
68 PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
69 PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
70 PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
71 PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
72 PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
73 PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
74 PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
75 PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
76 PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
77 PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
78 PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
79 PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
80 PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
81 PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
82 PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
83 PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
84 PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
85 PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
86 PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
87 PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
88 PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1),
89 PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1),
90 PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1),
91 PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1),
92 PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1),
93 PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1),
94 PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1),
95 PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1),
96 PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1),
97 PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1),
98 PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1),
99 PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1),
100 PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1),
101 PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1),
102 PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1),
103 PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1),
104 PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1),
105 PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1),
106 PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1),
107 PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1),
108 PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1),
109 PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1),
110 PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1),
111 PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1),
112 PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1),
113 PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1),
114 PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1),
115 PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1),
116 PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1),
117};
118
119static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = {
120 PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1),
121 PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1),
122 PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1),
123 PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1),
124 PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1),
125 PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1),
126 PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1),
127 PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1),
128 PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1),
129 PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1),
130 PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1),
131 PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1),
132 PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1),
133 PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1),
134 PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1),
135 PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1),
136 PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1),
137 PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1),
138 PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1),
139 PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1),
140 PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1),
141 PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1),
142 PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1),
143 PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1),
144 PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1),
145 PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1),
146 PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1),
147 PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1),
148 PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1),
149 PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1),
150 PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1),
151 PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1),
152 PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1),
153 PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1),
154 PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1),
155 PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1),
156 PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1),
157 PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1),
158 PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1),
159 PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1),
160 PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1),
161 PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1),
162 PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1),
163 PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1),
164 PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1),
165 PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1),
166 PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1),
167 PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1),
168 PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1),
169 PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1),
170 PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1),
171 PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1),
172 PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1),
173 PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1),
174 PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1),
175 PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1),
176 PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1),
177 PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1),
178 PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1),
179 PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1),
180 PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1),
181 PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1),
182 PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1),
183 PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1),
184 PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1),
185 PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1),
186 PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1),
187 PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1),
188 PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1),
189 PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10),
190 PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1),
191 PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1),
192 PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1),
193 PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1),
194 PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1),
195 PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1),
196 PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1),
197 PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1),
198 PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1),
199 PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1),
200 PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1),
201 PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1),
202 PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1),
203 PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1),
204 PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1),
205};
206
207static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = {
208 PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1),
209};
210
211static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = {
212 PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1),
213};
214
215static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {
216 PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4),
217 PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4),
218 PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4),
219 PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4),
220 PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4),
221 PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4),
222 PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4),
223 PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4),
224 PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4),
225 PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4),
226 PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4),
227 PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4),
228 PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4),
229 PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4),
230 PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4),
231 PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4),
232 PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4),
233 PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4),
234 PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4),
235 PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4),
236 PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4),
237 PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4),
238 PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4),
239 PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4),
240 PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4),
241 PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4),
242 PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4),
243 PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4),
244 PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4),
245 PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4),
246 PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4),
247 PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4),
248 PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4),
249 PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4),
250 PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4),
251 PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4),
252 PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4),
253 PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4),
254 PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4),
255 PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4),
256 PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4),
257 PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4),
258 PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4),
259 PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4),
260 PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4),
261 PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4),
262 PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4),
263 PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4),
264 PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4),
265 PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4),
266 PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4),
267 PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4),
268};
269
270static const struct mtk_pin_field_calc mt7623_pin_tdsel_range[] = {
271 PINS_FIELD16(262, 276, 0x4c0, 0x10, 0, 4),
272};
273
274static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = {
275 /* MSDC0 */
276 PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1),
277 PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1),
278 PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1),
279 PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1),
280 PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1),
281 PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1),
282 PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1),
283 PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1),
284 PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1),
285 PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1),
286 PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1),
287 /* MSDC1 */
288 PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1),
289 PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1),
290 PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1),
291 PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1),
292 PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1),
293 PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1),
294 /* MSDC1 */
295 PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1),
296 PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1),
297 PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1),
298 PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1),
299 PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1),
300 PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1),
301 /* MSDC0E */
302 PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1),
303 PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1),
304 PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1),
305 PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1),
306 PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1),
307 PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1),
308 PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1),
309 PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1),
310 PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1),
311 PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1),
312 PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1),
313 PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1),
314};
315
316static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = {
317 /* MSDC0 */
318 PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1),
319 PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1),
320 PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1),
321 PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1),
322 PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1),
323 PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1),
324 PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1),
325 PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1),
326 PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1),
327 PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1),
328 PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1),
329 /* MSDC1 */
330 PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1),
331 PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1),
332 PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1),
333 PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1),
334 PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1),
335 PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1),
336 /* MSDC2 */
337 PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1),
338 PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1),
339 PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1),
340 PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1),
341 PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1),
342 PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1),
343 /* MSDC0E */
344 PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1),
345 PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1),
346 PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1),
347 PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1),
348 PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1),
349 PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1),
350 PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1),
351 PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1),
352 PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1),
353 PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1),
354 PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1),
355 PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1),
356};
357
358static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {
359 /* MSDC0 */
360 PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1),
361 PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1),
362 PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1),
363 PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1),
364 PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1),
365 PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1),
366 PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1),
367 PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1),
368 PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1),
369 PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1),
370 PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1),
371 /* MSDC1 */
372 PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1),
373 PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1),
374 PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1),
375 PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1),
376 PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1),
377 PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1),
378 /* MSDC2 */
379 PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1),
380 PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1),
381 PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1),
382 PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1),
383 PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1),
384 PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1),
385 /* MSDC0E */
386 PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1),
387 PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1),
388 PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1),
389 PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1),
390 PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1),
391 PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1),
392 PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1),
393 PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1),
394 PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1),
395 PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1),
396 PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1),
397 PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
398};
399
400static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
401 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
402 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
403 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),
404 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range),
405 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range),
406 [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range),
407 [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range),
408 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range),
409 [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7623_pin_tdsel_range),
410 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range),
411 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range),
412 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range),
413 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range),
414};
415
416static const struct mtk_pin_desc mt7623_pins[] = {
417 MT7623_PIN(0, "PWRAP_SPI0_MI", 148, DRV_GRP3),
418 MT7623_PIN(1, "PWRAP_SPI0_MO", 149, DRV_GRP3),
419 MT7623_PIN(2, "PWRAP_INT", 150, DRV_GRP3),
420 MT7623_PIN(3, "PWRAP_SPI0_CK", 151, DRV_GRP3),
421 MT7623_PIN(4, "PWRAP_SPI0_CSN", 152, DRV_GRP3),
422 MT7623_PIN(5, "PWRAP_SPI0_CK2", 153, DRV_GRP3),
423 MT7623_PIN(6, "PWRAP_SPI0_CSN2", 154, DRV_GRP3),
424 MT7623_PIN(7, "SPI1_CSN", 155, DRV_GRP3),
425 MT7623_PIN(8, "SPI1_MI", 156, DRV_GRP3),
426 MT7623_PIN(9, "SPI1_MO", 157, DRV_GRP3),
427 MT7623_PIN(10, "RTC32K_CK", 158, DRV_GRP3),
428 MT7623_PIN(11, "WATCHDOG", 159, DRV_GRP3),
429 MT7623_PIN(12, "SRCLKENA", 160, DRV_GRP3),
430 MT7623_PIN(13, "SRCLKENAI", 161, DRV_GRP3),
431 MT7623_PIN(14, "URXD2", 162, DRV_GRP1),
432 MT7623_PIN(15, "UTXD2", 163, DRV_GRP1),
433 MT7623_PIN(16, "I2S5_DATA_IN", 164, DRV_GRP1),
434 MT7623_PIN(17, "I2S5_BCK", 165, DRV_GRP1),
435 MT7623_PIN(18, "PCM_CLK", 166, DRV_GRP1),
436 MT7623_PIN(19, "PCM_SYNC", 167, DRV_GRP1),
437 MT7623_PIN(20, "PCM_RX", EINT_NA, DRV_GRP1),
438 MT7623_PIN(21, "PCM_TX", EINT_NA, DRV_GRP1),
439 MT7623_PIN(22, "EINT0", 0, DRV_GRP1),
440 MT7623_PIN(23, "EINT1", 1, DRV_GRP1),
441 MT7623_PIN(24, "EINT2", 2, DRV_GRP1),
442 MT7623_PIN(25, "EINT3", 3, DRV_GRP1),
443 MT7623_PIN(26, "EINT4", 4, DRV_GRP1),
444 MT7623_PIN(27, "EINT5", 5, DRV_GRP1),
445 MT7623_PIN(28, "EINT6", 6, DRV_GRP1),
446 MT7623_PIN(29, "EINT7", 7, DRV_GRP1),
447 MT7623_PIN(30, "I2S5_LRCK", 12, DRV_GRP1),
448 MT7623_PIN(31, "I2S5_MCLK", 13, DRV_GRP1),
449 MT7623_PIN(32, "I2S5_DATA", 14, DRV_GRP1),
450 MT7623_PIN(33, "I2S1_DATA", 15, DRV_GRP1),
451 MT7623_PIN(34, "I2S1_DATA_IN", 16, DRV_GRP1),
452 MT7623_PIN(35, "I2S1_BCK", 17, DRV_GRP1),
453 MT7623_PIN(36, "I2S1_LRCK", 18, DRV_GRP1),
454 MT7623_PIN(37, "I2S1_MCLK", 19, DRV_GRP1),
455 MT7623_PIN(38, "I2S2_DATA", 20, DRV_GRP1),
456 MT7623_PIN(39, "JTMS", 21, DRV_GRP3),
457 MT7623_PIN(40, "JTCK", 22, DRV_GRP3),
458 MT7623_PIN(41, "JTDI", 23, DRV_GRP3),
459 MT7623_PIN(42, "JTDO", 24, DRV_GRP3),
460 MT7623_PIN(43, "NCLE", 25, DRV_GRP1),
461 MT7623_PIN(44, "NCEB1", 26, DRV_GRP1),
462 MT7623_PIN(45, "NCEB0", 27, DRV_GRP1),
463 MT7623_PIN(46, "IR", 28, DRV_FIXED),
464 MT7623_PIN(47, "NREB", 29, DRV_GRP1),
465 MT7623_PIN(48, "NRNB", 30, DRV_GRP1),
466 MT7623_PIN(49, "I2S0_DATA", 31, DRV_GRP1),
467 MT7623_PIN(50, "I2S2_BCK", 32, DRV_GRP1),
468 MT7623_PIN(51, "I2S2_DATA_IN", 33, DRV_GRP1),
469 MT7623_PIN(52, "I2S2_LRCK", 34, DRV_GRP1),
470 MT7623_PIN(53, "SPI0_CSN", 35, DRV_GRP1),
471 MT7623_PIN(54, "SPI0_CK", 36, DRV_GRP1),
472 MT7623_PIN(55, "SPI0_MI", 37, DRV_GRP1),
473 MT7623_PIN(56, "SPI0_MO", 38, DRV_GRP1),
474 MT7623_PIN(57, "SDA1", 39, DRV_FIXED),
475 MT7623_PIN(58, "SCL1", 40, DRV_FIXED),
476 MT7623_PIN(59, "RAMBUF_I_CLK", EINT_NA, DRV_FIXED),
477 MT7623_PIN(60, "WB_RSTB", 41, DRV_GRP3),
478 MT7623_PIN(61, "F2W_DATA", 42, DRV_GRP3),
479 MT7623_PIN(62, "F2W_CLK", 43, DRV_GRP3),
480 MT7623_PIN(63, "WB_SCLK", 44, DRV_GRP3),
481 MT7623_PIN(64, "WB_SDATA", 45, DRV_GRP3),
482 MT7623_PIN(65, "WB_SEN", 46, DRV_GRP3),
483 MT7623_PIN(66, "WB_CRTL0", 47, DRV_GRP3),
484 MT7623_PIN(67, "WB_CRTL1", 48, DRV_GRP3),
485 MT7623_PIN(68, "WB_CRTL2", 49, DRV_GRP3),
486 MT7623_PIN(69, "WB_CRTL3", 50, DRV_GRP3),
487 MT7623_PIN(70, "WB_CRTL4", 51, DRV_GRP3),
488 MT7623_PIN(71, "WB_CRTL5", 52, DRV_GRP3),
489 MT7623_PIN(72, "I2S0_DATA_IN", 53, DRV_GRP1),
490 MT7623_PIN(73, "I2S0_LRCK", 54, DRV_GRP1),
491 MT7623_PIN(74, "I2S0_BCK", 55, DRV_GRP1),
492 MT7623_PIN(75, "SDA0", 56, DRV_FIXED),
493 MT7623_PIN(76, "SCL0", 57, DRV_FIXED),
494 MT7623_PIN(77, "SDA2", 58, DRV_FIXED),
495 MT7623_PIN(78, "SCL2", 59, DRV_FIXED),
496 MT7623_PIN(79, "URXD0", 60, DRV_FIXED),
497 MT7623_PIN(80, "UTXD0", 61, DRV_FIXED),
498 MT7623_PIN(81, "URXD1", 62, DRV_FIXED),
499 MT7623_PIN(82, "UTXD1", 63, DRV_FIXED),
500 MT7623_PIN(83, "LCM_RST", 64, DRV_FIXED),
501 MT7623_PIN(84, "DSI_TE", 65, DRV_FIXED),
502 MT7623_PIN(85, "MSDC2_CMD", 66, DRV_GRP4),
503 MT7623_PIN(86, "MSDC2_CLK", 67, DRV_GRP4),
504 MT7623_PIN(87, "MSDC2_DAT0", 68, DRV_GRP4),
505 MT7623_PIN(88, "MSDC2_DAT1", 69, DRV_GRP4),
506 MT7623_PIN(89, "MSDC2_DAT2", 70, DRV_GRP4),
507 MT7623_PIN(90, "MSDC2_DAT3", 71, DRV_GRP4),
508 MT7623_PIN(91, "TDN3", EINT_NA, DRV_FIXED),
509 MT7623_PIN(92, "TDP3", EINT_NA, DRV_FIXED),
510 MT7623_PIN(93, "TDN2", EINT_NA, DRV_FIXED),
511 MT7623_PIN(94, "TDP2", EINT_NA, DRV_FIXED),
512 MT7623_PIN(95, "TCN", EINT_NA, DRV_FIXED),
513 MT7623_PIN(96, "TCP", EINT_NA, DRV_FIXED),
514 MT7623_PIN(97, "TDN1", EINT_NA, DRV_FIXED),
515 MT7623_PIN(98, "TDP1", EINT_NA, DRV_FIXED),
516 MT7623_PIN(99, "TDN0", EINT_NA, DRV_FIXED),
517 MT7623_PIN(100, "TDP0", EINT_NA, DRV_FIXED),
518 MT7623_PIN(101, "SPI2_CSN", 74, DRV_FIXED),
519 MT7623_PIN(102, "SPI2_MI", 75, DRV_FIXED),
520 MT7623_PIN(103, "SPI2_MO", 76, DRV_FIXED),
521 MT7623_PIN(104, "SPI2_CLK", 77, DRV_FIXED),
522 MT7623_PIN(105, "MSDC1_CMD", 78, DRV_GRP4),
523 MT7623_PIN(106, "MSDC1_CLK", 79, DRV_GRP4),
524 MT7623_PIN(107, "MSDC1_DAT0", 80, DRV_GRP4),
525 MT7623_PIN(108, "MSDC1_DAT1", 81, DRV_GRP4),
526 MT7623_PIN(109, "MSDC1_DAT2", 82, DRV_GRP4),
527 MT7623_PIN(110, "MSDC1_DAT3", 83, DRV_GRP4),
528 MT7623_PIN(111, "MSDC0_DAT7", 84, DRV_GRP4),
529 MT7623_PIN(112, "MSDC0_DAT6", 85, DRV_GRP4),
530 MT7623_PIN(113, "MSDC0_DAT5", 86, DRV_GRP4),
531 MT7623_PIN(114, "MSDC0_DAT4", 87, DRV_GRP4),
532 MT7623_PIN(115, "MSDC0_RSTB", 88, DRV_GRP4),
533 MT7623_PIN(116, "MSDC0_CMD", 89, DRV_GRP4),
534 MT7623_PIN(117, "MSDC0_CLK", 90, DRV_GRP4),
535 MT7623_PIN(118, "MSDC0_DAT3", 91, DRV_GRP4),
536 MT7623_PIN(119, "MSDC0_DAT2", 92, DRV_GRP4),
537 MT7623_PIN(120, "MSDC0_DAT1", 93, DRV_GRP4),
538 MT7623_PIN(121, "MSDC0_DAT0", 94, DRV_GRP4),
539 MT7623_PIN(122, "CEC", 95, DRV_FIXED),
540 MT7623_PIN(123, "HTPLG", 96, DRV_FIXED),
541 MT7623_PIN(124, "HDMISCK", 97, DRV_FIXED),
542 MT7623_PIN(125, "HDMISD", 98, DRV_FIXED),
543 MT7623_PIN(126, "I2S0_MCLK", 99, DRV_GRP1),
544 MT7623_PIN(127, "RAMBUF_IDATA0", EINT_NA, DRV_FIXED),
545 MT7623_PIN(128, "RAMBUF_IDATA1", EINT_NA, DRV_FIXED),
546 MT7623_PIN(129, "RAMBUF_IDATA2", EINT_NA, DRV_FIXED),
547 MT7623_PIN(130, "RAMBUF_IDATA3", EINT_NA, DRV_FIXED),
548 MT7623_PIN(131, "RAMBUF_IDATA4", EINT_NA, DRV_FIXED),
549 MT7623_PIN(132, "RAMBUF_IDATA5", EINT_NA, DRV_FIXED),
550 MT7623_PIN(133, "RAMBUF_IDATA6", EINT_NA, DRV_FIXED),
551 MT7623_PIN(134, "RAMBUF_IDATA7", EINT_NA, DRV_FIXED),
552 MT7623_PIN(135, "RAMBUF_IDATA8", EINT_NA, DRV_FIXED),
553 MT7623_PIN(136, "RAMBUF_IDATA9", EINT_NA, DRV_FIXED),
554 MT7623_PIN(137, "RAMBUF_IDATA10", EINT_NA, DRV_FIXED),
555 MT7623_PIN(138, "RAMBUF_IDATA11", EINT_NA, DRV_FIXED),
556 MT7623_PIN(139, "RAMBUF_IDATA12", EINT_NA, DRV_FIXED),
557 MT7623_PIN(140, "RAMBUF_IDATA13", EINT_NA, DRV_FIXED),
558 MT7623_PIN(141, "RAMBUF_IDATA14", EINT_NA, DRV_FIXED),
559 MT7623_PIN(142, "RAMBUF_IDATA15", EINT_NA, DRV_FIXED),
560 MT7623_PIN(143, "RAMBUF_ODATA0", EINT_NA, DRV_FIXED),
561 MT7623_PIN(144, "RAMBUF_ODATA1", EINT_NA, DRV_FIXED),
562 MT7623_PIN(145, "RAMBUF_ODATA2", EINT_NA, DRV_FIXED),
563 MT7623_PIN(146, "RAMBUF_ODATA3", EINT_NA, DRV_FIXED),
564 MT7623_PIN(147, "RAMBUF_ODATA4", EINT_NA, DRV_FIXED),
565 MT7623_PIN(148, "RAMBUF_ODATA5", EINT_NA, DRV_FIXED),
566 MT7623_PIN(149, "RAMBUF_ODATA6", EINT_NA, DRV_FIXED),
567 MT7623_PIN(150, "RAMBUF_ODATA7", EINT_NA, DRV_FIXED),
568 MT7623_PIN(151, "RAMBUF_ODATA8", EINT_NA, DRV_FIXED),
569 MT7623_PIN(152, "RAMBUF_ODATA9", EINT_NA, DRV_FIXED),
570 MT7623_PIN(153, "RAMBUF_ODATA10", EINT_NA, DRV_FIXED),
571 MT7623_PIN(154, "RAMBUF_ODATA11", EINT_NA, DRV_FIXED),
572 MT7623_PIN(155, "RAMBUF_ODATA12", EINT_NA, DRV_FIXED),
573 MT7623_PIN(156, "RAMBUF_ODATA13", EINT_NA, DRV_FIXED),
574 MT7623_PIN(157, "RAMBUF_ODATA14", EINT_NA, DRV_FIXED),
575 MT7623_PIN(158, "RAMBUF_ODATA15", EINT_NA, DRV_FIXED),
576 MT7623_PIN(159, "RAMBUF_BE0", EINT_NA, DRV_FIXED),
577 MT7623_PIN(160, "RAMBUF_BE1", EINT_NA, DRV_FIXED),
578 MT7623_PIN(161, "AP2PT_INT", EINT_NA, DRV_FIXED),
579 MT7623_PIN(162, "AP2PT_INT_CLR", EINT_NA, DRV_FIXED),
580 MT7623_PIN(163, "PT2AP_INT", EINT_NA, DRV_FIXED),
581 MT7623_PIN(164, "PT2AP_INT_CLR", EINT_NA, DRV_FIXED),
582 MT7623_PIN(165, "AP2UP_INT", EINT_NA, DRV_FIXED),
583 MT7623_PIN(166, "AP2UP_INT_CLR", EINT_NA, DRV_FIXED),
584 MT7623_PIN(167, "UP2AP_INT", EINT_NA, DRV_FIXED),
585 MT7623_PIN(168, "UP2AP_INT_CLR", EINT_NA, DRV_FIXED),
586 MT7623_PIN(169, "RAMBUF_ADDR0", EINT_NA, DRV_FIXED),
587 MT7623_PIN(170, "RAMBUF_ADDR1", EINT_NA, DRV_FIXED),
588 MT7623_PIN(171, "RAMBUF_ADDR2", EINT_NA, DRV_FIXED),
589 MT7623_PIN(172, "RAMBUF_ADDR3", EINT_NA, DRV_FIXED),
590 MT7623_PIN(173, "RAMBUF_ADDR4", EINT_NA, DRV_FIXED),
591 MT7623_PIN(174, "RAMBUF_ADDR5", EINT_NA, DRV_FIXED),
592 MT7623_PIN(175, "RAMBUF_ADDR6", EINT_NA, DRV_FIXED),
593 MT7623_PIN(176, "RAMBUF_ADDR7", EINT_NA, DRV_FIXED),
594 MT7623_PIN(177, "RAMBUF_ADDR8", EINT_NA, DRV_FIXED),
595 MT7623_PIN(178, "RAMBUF_ADDR9", EINT_NA, DRV_FIXED),
596 MT7623_PIN(179, "RAMBUF_ADDR10", EINT_NA, DRV_FIXED),
597 MT7623_PIN(180, "RAMBUF_RW", EINT_NA, DRV_FIXED),
598 MT7623_PIN(181, "RAMBUF_LAST", EINT_NA, DRV_FIXED),
599 MT7623_PIN(182, "RAMBUF_HP", EINT_NA, DRV_FIXED),
600 MT7623_PIN(183, "RAMBUF_REQ", EINT_NA, DRV_FIXED),
601 MT7623_PIN(184, "RAMBUF_ALE", EINT_NA, DRV_FIXED),
602 MT7623_PIN(185, "RAMBUF_DLE", EINT_NA, DRV_FIXED),
603 MT7623_PIN(186, "RAMBUF_WDLE", EINT_NA, DRV_FIXED),
604 MT7623_PIN(187, "RAMBUF_O_CLK", EINT_NA, DRV_FIXED),
605 MT7623_PIN(188, "I2S2_MCLK", 100, DRV_GRP1),
606 MT7623_PIN(189, "I2S3_DATA", 101, DRV_GRP1),
607 MT7623_PIN(190, "I2S3_DATA_IN", 102, DRV_GRP1),
608 MT7623_PIN(191, "I2S3_BCK", 103, DRV_GRP1),
609 MT7623_PIN(192, "I2S3_LRCK", 104, DRV_GRP1),
610 MT7623_PIN(193, "I2S3_MCLK", 105, DRV_GRP1),
611 MT7623_PIN(194, "I2S4_DATA", 106, DRV_GRP1),
612 MT7623_PIN(195, "I2S4_DATA_IN", 107, DRV_GRP1),
613 MT7623_PIN(196, "I2S4_BCK", 108, DRV_GRP1),
614 MT7623_PIN(197, "I2S4_LRCK", 109, DRV_GRP1),
615 MT7623_PIN(198, "I2S4_MCLK", 110, DRV_GRP1),
616 MT7623_PIN(199, "SPI1_CLK", 111, DRV_GRP3),
617 MT7623_PIN(200, "SPDIF_OUT", 112, DRV_GRP1),
618 MT7623_PIN(201, "SPDIF_IN0", 113, DRV_GRP1),
619 MT7623_PIN(202, "SPDIF_IN1", 114, DRV_GRP1),
620 MT7623_PIN(203, "PWM0", 115, DRV_GRP1),
621 MT7623_PIN(204, "PWM1", 116, DRV_GRP1),
622 MT7623_PIN(205, "PWM2", 117, DRV_GRP1),
623 MT7623_PIN(206, "PWM3", 118, DRV_GRP1),
624 MT7623_PIN(207, "PWM4", 119, DRV_GRP1),
625 MT7623_PIN(208, "AUD_EXT_CK1", 120, DRV_GRP1),
626 MT7623_PIN(209, "AUD_EXT_CK2", 121, DRV_GRP1),
627 MT7623_PIN(210, "AUD_CLOCK", EINT_NA, DRV_GRP3),
628 MT7623_PIN(211, "DVP_RESET", EINT_NA, DRV_GRP3),
629 MT7623_PIN(212, "DVP_CLOCK", EINT_NA, DRV_GRP3),
630 MT7623_PIN(213, "DVP_CS", EINT_NA, DRV_GRP3),
631 MT7623_PIN(214, "DVP_CK", EINT_NA, DRV_GRP3),
632 MT7623_PIN(215, "DVP_DI", EINT_NA, DRV_GRP3),
633 MT7623_PIN(216, "DVP_DO", EINT_NA, DRV_GRP3),
634 MT7623_PIN(217, "AP_CS", EINT_NA, DRV_GRP3),
635 MT7623_PIN(218, "AP_CK", EINT_NA, DRV_GRP3),
636 MT7623_PIN(219, "AP_DI", EINT_NA, DRV_GRP3),
637 MT7623_PIN(220, "AP_DO", EINT_NA, DRV_GRP3),
638 MT7623_PIN(221, "DVD_BCLK", EINT_NA, DRV_GRP3),
639 MT7623_PIN(222, "T8032_CLK", EINT_NA, DRV_GRP3),
640 MT7623_PIN(223, "AP_BCLK", EINT_NA, DRV_GRP3),
641 MT7623_PIN(224, "HOST_CS", EINT_NA, DRV_GRP3),
642 MT7623_PIN(225, "HOST_CK", EINT_NA, DRV_GRP3),
643 MT7623_PIN(226, "HOST_DO0", EINT_NA, DRV_GRP3),
644 MT7623_PIN(227, "HOST_DO1", EINT_NA, DRV_GRP3),
645 MT7623_PIN(228, "SLV_CS", EINT_NA, DRV_GRP3),
646 MT7623_PIN(229, "SLV_CK", EINT_NA, DRV_GRP3),
647 MT7623_PIN(230, "SLV_DI0", EINT_NA, DRV_GRP3),
648 MT7623_PIN(231, "SLV_DI1", EINT_NA, DRV_GRP3),
649 MT7623_PIN(232, "AP2DSP_INT", EINT_NA, DRV_GRP3),
650 MT7623_PIN(233, "AP2DSP_INT_CLR", EINT_NA, DRV_GRP3),
651 MT7623_PIN(234, "DSP2AP_INT", EINT_NA, DRV_GRP3),
652 MT7623_PIN(235, "DSP2AP_INT_CLR", EINT_NA, DRV_GRP3),
653 MT7623_PIN(236, "EXT_SDIO3", 122, DRV_GRP1),
654 MT7623_PIN(237, "EXT_SDIO2", 123, DRV_GRP1),
655 MT7623_PIN(238, "EXT_SDIO1", 124, DRV_GRP1),
656 MT7623_PIN(239, "EXT_SDIO0", 125, DRV_GRP1),
657 MT7623_PIN(240, "EXT_XCS", 126, DRV_GRP1),
658 MT7623_PIN(241, "EXT_SCK", 127, DRV_GRP1),
659 MT7623_PIN(242, "URTS2", 128, DRV_GRP1),
660 MT7623_PIN(243, "UCTS2", 129, DRV_GRP1),
661 MT7623_PIN(244, "HDMI_SDA_RX", 130, DRV_FIXED),
662 MT7623_PIN(245, "HDMI_SCL_RX", 131, DRV_FIXED),
663 MT7623_PIN(246, "MHL_SENCE", 132, DRV_FIXED),
664 MT7623_PIN(247, "HDMI_HPD_CBUS_RX", 69, DRV_FIXED),
665 MT7623_PIN(248, "HDMI_TESTOUTP_RX", 133, DRV_GRP1),
666 MT7623_PIN(249, "MSDC0E_RSTB", 134, DRV_GRP4),
667 MT7623_PIN(250, "MSDC0E_DAT7", 135, DRV_GRP4),
668 MT7623_PIN(251, "MSDC0E_DAT6", 136, DRV_GRP4),
669 MT7623_PIN(252, "MSDC0E_DAT5", 137, DRV_GRP4),
670 MT7623_PIN(253, "MSDC0E_DAT4", 138, DRV_GRP4),
671 MT7623_PIN(254, "MSDC0E_DAT3", 139, DRV_GRP4),
672 MT7623_PIN(255, "MSDC0E_DAT2", 140, DRV_GRP4),
673 MT7623_PIN(256, "MSDC0E_DAT1", 141, DRV_GRP4),
674 MT7623_PIN(257, "MSDC0E_DAT0", 142, DRV_GRP4),
675 MT7623_PIN(258, "MSDC0E_CMD", 143, DRV_GRP4),
676 MT7623_PIN(259, "MSDC0E_CLK", 144, DRV_GRP4),
677 MT7623_PIN(260, "MSDC0E_DSL", 145, DRV_GRP4),
678 MT7623_PIN(261, "MSDC1_INS", 146, DRV_GRP4),
679 MT7623_PIN(262, "G2_TXEN", 8, DRV_GRP1),
680 MT7623_PIN(263, "G2_TXD3", 9, DRV_GRP1),
681 MT7623_PIN(264, "G2_TXD2", 10, DRV_GRP1),
682 MT7623_PIN(265, "G2_TXD1", 11, DRV_GRP1),
683 MT7623_PIN(266, "G2_TXD0", EINT_NA, DRV_GRP1),
684 MT7623_PIN(267, "G2_TXC", EINT_NA, DRV_GRP1),
685 MT7623_PIN(268, "G2_RXC", EINT_NA, DRV_GRP1),
686 MT7623_PIN(269, "G2_RXD0", EINT_NA, DRV_GRP1),
687 MT7623_PIN(270, "G2_RXD1", EINT_NA, DRV_GRP1),
688 MT7623_PIN(271, "G2_RXD2", EINT_NA, DRV_GRP1),
689 MT7623_PIN(272, "G2_RXD3", EINT_NA, DRV_GRP1),
690 MT7623_PIN(273, "ESW_INT", 168, DRV_GRP1),
691 MT7623_PIN(274, "G2_RXDV", EINT_NA, DRV_GRP1),
692 MT7623_PIN(275, "MDC", EINT_NA, DRV_GRP1),
693 MT7623_PIN(276, "MDIO", EINT_NA, DRV_GRP1),
694 MT7623_PIN(277, "ESW_RST", EINT_NA, DRV_GRP1),
695 MT7623_PIN(278, "JTAG_RESET", 147, DRV_GRP3),
696 MT7623_PIN(279, "USB3_RES_BOND", EINT_NA, DRV_GRP1),
697};
698
699/* List all groups consisting of these pins dedicated to the enablement of
700 * certain hardware block and the corresponding mode for all of the pins.
701 * The hardware probably has multiple combinations of these pinouts.
702 */
703
704/* AUDIO EXT CLK */
705static int mt7623_aud_ext_clk0_pins[] = { 208, };
706static int mt7623_aud_ext_clk0_funcs[] = { 1, };
707static int mt7623_aud_ext_clk1_pins[] = { 209, };
708static int mt7623_aud_ext_clk1_funcs[] = { 1, };
709
710/* DISP PWM */
711static int mt7623_disp_pwm_0_pins[] = { 72, };
712static int mt7623_disp_pwm_0_funcs[] = { 5, };
713static int mt7623_disp_pwm_1_pins[] = { 203, };
714static int mt7623_disp_pwm_1_funcs[] = { 2, };
715static int mt7623_disp_pwm_2_pins[] = { 208, };
716static int mt7623_disp_pwm_2_funcs[] = { 5, };
717
718/* ESW */
719static int mt7623_esw_int_pins[] = { 273, };
720static int mt7623_esw_int_funcs[] = { 1, };
721static int mt7623_esw_rst_pins[] = { 277, };
722static int mt7623_esw_rst_funcs[] = { 1, };
723
724/* EPHY */
725static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
726 269, 270, 271, 272, 274, };
727static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
728
729/* EXT_SDIO */
730static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
731static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
732
733/* HDMI RX */
734static int mt7623_hdmi_rx_pins[] = { 247, 248, };
735static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
736static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
737static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
738
739/* HDMI TX */
740static int mt7623_hdmi_cec_pins[] = { 122, };
741static int mt7623_hdmi_cec_funcs[] = { 1, };
742static int mt7623_hdmi_htplg_pins[] = { 123, };
743static int mt7623_hdmi_htplg_funcs[] = { 1, };
744static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
745static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
746
747/* I2C */
748static int mt7623_i2c0_pins[] = { 75, 76, };
749static int mt7623_i2c0_funcs[] = { 1, 1, };
750static int mt7623_i2c1_0_pins[] = { 57, 58, };
751static int mt7623_i2c1_0_funcs[] = { 1, 1, };
752static int mt7623_i2c1_1_pins[] = { 242, 243, };
753static int mt7623_i2c1_1_funcs[] = { 4, 4, };
754static int mt7623_i2c1_2_pins[] = { 85, 86, };
755static int mt7623_i2c1_2_funcs[] = { 3, 3, };
756static int mt7623_i2c1_3_pins[] = { 105, 106, };
757static int mt7623_i2c1_3_funcs[] = { 3, 3, };
758static int mt7623_i2c1_4_pins[] = { 124, 125, };
759static int mt7623_i2c1_4_funcs[] = { 4, 4, };
760static int mt7623_i2c2_0_pins[] = { 77, 78, };
761static int mt7623_i2c2_0_funcs[] = { 1, 1, };
762static int mt7623_i2c2_1_pins[] = { 89, 90, };
763static int mt7623_i2c2_1_funcs[] = { 3, 3, };
764static int mt7623_i2c2_2_pins[] = { 109, 110, };
765static int mt7623_i2c2_2_funcs[] = { 3, 3, };
766static int mt7623_i2c2_3_pins[] = { 122, 123, };
767static int mt7623_i2c2_3_funcs[] = { 4, 4, };
768
769/* I2S */
770static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
771static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
772static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
773static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
774static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
775static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
776static int mt7623_i2s2_data_in_pins[] = { 51, };
777static int mt7623_i2s2_data_in_funcs[] = { 1, };
778static int mt7623_i2s2_data_0_pins[] = { 203, };
779static int mt7623_i2s2_data_0_funcs[] = { 9, };
780static int mt7623_i2s2_data_1_pins[] = { 38, };
781static int mt7623_i2s2_data_1_funcs[] = { 4, };
782static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
783static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
784static int mt7623_i2s3_data_in_pins[] = { 190, };
785static int mt7623_i2s3_data_in_funcs[] = { 1, };
786static int mt7623_i2s3_data_0_pins[] = { 204, };
787static int mt7623_i2s3_data_0_funcs[] = { 9, };
788static int mt7623_i2s3_data_1_pins[] = { 2, };
789static int mt7623_i2s3_data_1_funcs[] = { 0, };
790static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
791static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
792static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
793static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
794
795/* IR */
796static int mt7623_ir_pins[] = { 46, };
797static int mt7623_ir_funcs[] = { 1, };
798
799/* LCD */
800static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
801 99, 100, };
802static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
803static int mt7623_dsi_te_pins[] = { 84, };
804static int mt7623_dsi_te_funcs[] = { 1, };
805static int mt7623_lcm_rst_pins[] = { 83, };
806static int mt7623_lcm_rst_funcs[] = { 1, };
807
808/* MDC/MDIO */
809static int mt7623_mdc_mdio_pins[] = { 275, 276, };
810static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
811
812/* MSDC */
813static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
814 119, 120, 121, };
815static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
816static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
817static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
818static int mt7623_msdc1_ins_pins[] = { 261, };
819static int mt7623_msdc1_ins_funcs[] = { 1, };
820static int mt7623_msdc1_wp_0_pins[] = { 29, };
821static int mt7623_msdc1_wp_0_funcs[] = { 1, };
822static int mt7623_msdc1_wp_1_pins[] = { 55, };
823static int mt7623_msdc1_wp_1_funcs[] = { 3, };
824static int mt7623_msdc1_wp_2_pins[] = { 209, };
825static int mt7623_msdc1_wp_2_funcs[] = { 2, };
826static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
827static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
828static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
829 257, 258, 259, 260, };
830static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
831
832/* NAND */
833static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
834 116, 117, 118, 119, 120, 121, };
835static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
836 4, 4, };
837static int mt7623_nandc_ceb0_pins[] = { 45, };
838static int mt7623_nandc_ceb0_funcs[] = { 1, };
839static int mt7623_nandc_ceb1_pins[] = { 44, };
840static int mt7623_nandc_ceb1_funcs[] = { 1, };
841
842/* RTC */
843static int mt7623_rtc_pins[] = { 10, };
844static int mt7623_rtc_funcs[] = { 1, };
845
846/* OTG */
847static int mt7623_otg_iddig0_0_pins[] = { 29, };
848static int mt7623_otg_iddig0_0_funcs[] = { 1, };
849static int mt7623_otg_iddig0_1_pins[] = { 44, };
850static int mt7623_otg_iddig0_1_funcs[] = { 2, };
851static int mt7623_otg_iddig0_2_pins[] = { 236, };
852static int mt7623_otg_iddig0_2_funcs[] = { 2, };
853static int mt7623_otg_iddig1_0_pins[] = { 27, };
854static int mt7623_otg_iddig1_0_funcs[] = { 2, };
855static int mt7623_otg_iddig1_1_pins[] = { 47, };
856static int mt7623_otg_iddig1_1_funcs[] = { 2, };
857static int mt7623_otg_iddig1_2_pins[] = { 238, };
858static int mt7623_otg_iddig1_2_funcs[] = { 2, };
859static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
860static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
861static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
862static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
863static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
864static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
865static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
866static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
867static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
868static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
869static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
870static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
871
872/* PCIE */
873static int mt7623_pcie0_0_perst_pins[] = { 208, };
874static int mt7623_pcie0_0_perst_funcs[] = { 3, };
875static int mt7623_pcie0_1_perst_pins[] = { 22, };
876static int mt7623_pcie0_1_perst_funcs[] = { 2, };
877static int mt7623_pcie1_0_perst_pins[] = { 209, };
878static int mt7623_pcie1_0_perst_funcs[] = { 3, };
879static int mt7623_pcie1_1_perst_pins[] = { 23, };
880static int mt7623_pcie1_1_perst_funcs[] = { 2, };
881static int mt7623_pcie2_0_perst_pins[] = { 24, };
882static int mt7623_pcie2_0_perst_funcs[] = { 2, };
883static int mt7623_pcie2_1_perst_pins[] = { 29, };
884static int mt7623_pcie2_1_perst_funcs[] = { 6, };
885static int mt7623_pcie0_0_wake_pins[] = { 28, };
886static int mt7623_pcie0_0_wake_funcs[] = { 6, };
887static int mt7623_pcie0_1_wake_pins[] = { 251, };
888static int mt7623_pcie0_1_wake_funcs[] = { 6, };
889static int mt7623_pcie1_0_wake_pins[] = { 27, };
890static int mt7623_pcie1_0_wake_funcs[] = { 6, };
891static int mt7623_pcie1_1_wake_pins[] = { 253, };
892static int mt7623_pcie1_1_wake_funcs[] = { 6, };
893static int mt7623_pcie2_0_wake_pins[] = { 26, };
894static int mt7623_pcie2_0_wake_funcs[] = { 6, };
895static int mt7623_pcie2_1_wake_pins[] = { 255, };
896static int mt7623_pcie2_1_wake_funcs[] = { 6, };
897static int mt7623_pcie0_clkreq_pins[] = { 250, };
898static int mt7623_pcie0_clkreq_funcs[] = { 6, };
899static int mt7623_pcie1_clkreq_pins[] = { 252, };
900static int mt7623_pcie1_clkreq_funcs[] = { 6, };
901static int mt7623_pcie2_clkreq_pins[] = { 254, };
902static int mt7623_pcie2_clkreq_funcs[] = { 6, };
903
904/* the pcie_*_rev are only used for MT7623 */
905static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
906static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
907static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
908static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
909static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
910static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
911static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
912static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
913static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
914static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
915static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
916static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
917
918/* PCM */
919static int mt7623_pcm_clk_0_pins[] = { 18, };
920static int mt7623_pcm_clk_0_funcs[] = { 1, };
921static int mt7623_pcm_clk_1_pins[] = { 17, };
922static int mt7623_pcm_clk_1_funcs[] = { 3, };
923static int mt7623_pcm_clk_2_pins[] = { 35, };
924static int mt7623_pcm_clk_2_funcs[] = { 3, };
925static int mt7623_pcm_clk_3_pins[] = { 50, };
926static int mt7623_pcm_clk_3_funcs[] = { 3, };
927static int mt7623_pcm_clk_4_pins[] = { 74, };
928static int mt7623_pcm_clk_4_funcs[] = { 3, };
929static int mt7623_pcm_clk_5_pins[] = { 191, };
930static int mt7623_pcm_clk_5_funcs[] = { 3, };
931static int mt7623_pcm_clk_6_pins[] = { 196, };
932static int mt7623_pcm_clk_6_funcs[] = { 3, };
933static int mt7623_pcm_sync_0_pins[] = { 19, };
934static int mt7623_pcm_sync_0_funcs[] = { 1, };
935static int mt7623_pcm_sync_1_pins[] = { 30, };
936static int mt7623_pcm_sync_1_funcs[] = { 3, };
937static int mt7623_pcm_sync_2_pins[] = { 36, };
938static int mt7623_pcm_sync_2_funcs[] = { 3, };
939static int mt7623_pcm_sync_3_pins[] = { 52, };
940static int mt7623_pcm_sync_3_funcs[] = { 31, };
941static int mt7623_pcm_sync_4_pins[] = { 73, };
942static int mt7623_pcm_sync_4_funcs[] = { 3, };
943static int mt7623_pcm_sync_5_pins[] = { 192, };
944static int mt7623_pcm_sync_5_funcs[] = { 3, };
945static int mt7623_pcm_sync_6_pins[] = { 197, };
946static int mt7623_pcm_sync_6_funcs[] = { 3, };
947static int mt7623_pcm_rx_0_pins[] = { 20, };
948static int mt7623_pcm_rx_0_funcs[] = { 1, };
949static int mt7623_pcm_rx_1_pins[] = { 16, };
950static int mt7623_pcm_rx_1_funcs[] = { 3, };
951static int mt7623_pcm_rx_2_pins[] = { 34, };
952static int mt7623_pcm_rx_2_funcs[] = { 3, };
953static int mt7623_pcm_rx_3_pins[] = { 51, };
954static int mt7623_pcm_rx_3_funcs[] = { 3, };
955static int mt7623_pcm_rx_4_pins[] = { 72, };
956static int mt7623_pcm_rx_4_funcs[] = { 3, };
957static int mt7623_pcm_rx_5_pins[] = { 190, };
958static int mt7623_pcm_rx_5_funcs[] = { 3, };
959static int mt7623_pcm_rx_6_pins[] = { 195, };
960static int mt7623_pcm_rx_6_funcs[] = { 3, };
961static int mt7623_pcm_tx_0_pins[] = { 21, };
962static int mt7623_pcm_tx_0_funcs[] = { 1, };
963static int mt7623_pcm_tx_1_pins[] = { 32, };
964static int mt7623_pcm_tx_1_funcs[] = { 3, };
965static int mt7623_pcm_tx_2_pins[] = { 33, };
966static int mt7623_pcm_tx_2_funcs[] = { 3, };
967static int mt7623_pcm_tx_3_pins[] = { 38, };
968static int mt7623_pcm_tx_3_funcs[] = { 3, };
969static int mt7623_pcm_tx_4_pins[] = { 49, };
970static int mt7623_pcm_tx_4_funcs[] = { 3, };
971static int mt7623_pcm_tx_5_pins[] = { 189, };
972static int mt7623_pcm_tx_5_funcs[] = { 3, };
973static int mt7623_pcm_tx_6_pins[] = { 194, };
974static int mt7623_pcm_tx_6_funcs[] = { 3, };
975
976/* PWM */
977static int mt7623_pwm_ch1_0_pins[] = { 203, };
978static int mt7623_pwm_ch1_0_funcs[] = { 1, };
979static int mt7623_pwm_ch1_1_pins[] = { 208, };
980static int mt7623_pwm_ch1_1_funcs[] = { 2, };
981static int mt7623_pwm_ch1_2_pins[] = { 72, };
982static int mt7623_pwm_ch1_2_funcs[] = { 4, };
983static int mt7623_pwm_ch1_3_pins[] = { 88, };
984static int mt7623_pwm_ch1_3_funcs[] = { 3, };
985static int mt7623_pwm_ch1_4_pins[] = { 108, };
986static int mt7623_pwm_ch1_4_funcs[] = { 3, };
987static int mt7623_pwm_ch2_0_pins[] = { 204, };
988static int mt7623_pwm_ch2_0_funcs[] = { 1, };
989static int mt7623_pwm_ch2_1_pins[] = { 53, };
990static int mt7623_pwm_ch2_1_funcs[] = { 5, };
991static int mt7623_pwm_ch2_2_pins[] = { 88, };
992static int mt7623_pwm_ch2_2_funcs[] = { 6, };
993static int mt7623_pwm_ch2_3_pins[] = { 108, };
994static int mt7623_pwm_ch2_3_funcs[] = { 6, };
995static int mt7623_pwm_ch2_4_pins[] = { 209, };
996static int mt7623_pwm_ch2_4_funcs[] = { 5, };
997static int mt7623_pwm_ch3_0_pins[] = { 205, };
998static int mt7623_pwm_ch3_0_funcs[] = { 1, };
999static int mt7623_pwm_ch3_1_pins[] = { 55, };
1000static int mt7623_pwm_ch3_1_funcs[] = { 5, };
1001static int mt7623_pwm_ch3_2_pins[] = { 89, };
1002static int mt7623_pwm_ch3_2_funcs[] = { 6, };
1003static int mt7623_pwm_ch3_3_pins[] = { 109, };
1004static int mt7623_pwm_ch3_3_funcs[] = { 6, };
1005static int mt7623_pwm_ch4_0_pins[] = { 206, };
1006static int mt7623_pwm_ch4_0_funcs[] = { 1, };
1007static int mt7623_pwm_ch4_1_pins[] = { 90, };
1008static int mt7623_pwm_ch4_1_funcs[] = { 6, };
1009static int mt7623_pwm_ch4_2_pins[] = { 110, };
1010static int mt7623_pwm_ch4_2_funcs[] = { 6, };
1011static int mt7623_pwm_ch4_3_pins[] = { 124, };
1012static int mt7623_pwm_ch4_3_funcs[] = { 5, };
1013static int mt7623_pwm_ch5_0_pins[] = { 207, };
1014static int mt7623_pwm_ch5_0_funcs[] = { 1, };
1015static int mt7623_pwm_ch5_1_pins[] = { 125, };
1016static int mt7623_pwm_ch5_1_funcs[] = { 5, };
1017
1018/* PWRAP */
1019static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
1020static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
1021
1022/* SPDIF */
1023static int mt7623_spdif_in0_0_pins[] = { 56, };
1024static int mt7623_spdif_in0_0_funcs[] = { 3, };
1025static int mt7623_spdif_in0_1_pins[] = { 201, };
1026static int mt7623_spdif_in0_1_funcs[] = { 1, };
1027static int mt7623_spdif_in1_0_pins[] = { 54, };
1028static int mt7623_spdif_in1_0_funcs[] = { 3, };
1029static int mt7623_spdif_in1_1_pins[] = { 202, };
1030static int mt7623_spdif_in1_1_funcs[] = { 1, };
1031static int mt7623_spdif_out_pins[] = { 202, };
1032static int mt7623_spdif_out_funcs[] = { 1, };
1033
1034/* SPI */
1035static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
1036static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
1037static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
1038static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
1039static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
1040static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
1041
1042/* UART */
1043static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
1044static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
1045static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
1046static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
1047static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
1048static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
1049static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
1050static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
1051static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
1052static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
1053static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
1054static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
1055static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
1056static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
1057static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
1058static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
1059static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
1060static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
1061static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
1062static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
1063static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
1064static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
1065static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
1066static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
1067static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
1068static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
1069static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
1070static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
1071
1072/* Watchdog */
1073static int mt7623_watchdog_0_pins[] = { 11, };
1074static int mt7623_watchdog_0_funcs[] = { 1, };
1075static int mt7623_watchdog_1_pins[] = { 121, };
1076static int mt7623_watchdog_1_funcs[] = { 5, };
1077
1078static const struct group_desc mt7623_groups[] = {
1079 PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
1080 PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1),
1081 PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te),
1082 PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0),
1083 PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1),
1084 PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2),
1085 PINCTRL_PIN_GROUP("ephy", mt7623_ephy),
1086 PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int),
1087 PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst),
1088 PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio),
1089 PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec),
1090 PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg),
1091 PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c),
1092 PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx),
1093 PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c),
1094 PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0),
1095 PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0),
1096 PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1),
1097 PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2),
1098 PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3),
1099 PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4),
1100 PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0),
1101 PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1),
1102 PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2),
1103 PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3),
1104 PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0),
1105 PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1),
1106 PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4),
1107 PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5),
1108 PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk),
1109 PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk),
1110 PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in),
1111 PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in),
1112 PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0),
1113 PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1),
1114 PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0),
1115 PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1),
1116 PINCTRL_PIN_GROUP("ir", mt7623_ir),
1117 PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst),
1118 PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio),
1119 PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx),
1120 PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0),
1121 PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1),
1122 PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins),
1123 PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0),
1124 PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1),
1125 PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2),
1126 PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2),
1127 PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3),
1128 PINCTRL_PIN_GROUP("nandc", mt7623_nandc),
1129 PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0),
1130 PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1),
1131 PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0),
1132 PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1),
1133 PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2),
1134 PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0),
1135 PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1),
1136 PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2),
1137 PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0),
1138 PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1),
1139 PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2),
1140 PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0),
1141 PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1),
1142 PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2),
1143 PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst),
1144 PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst),
1145 PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst),
1146 PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
1147 PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
1148 PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst),
1149 PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst),
1150 PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst),
1151 PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst),
1152 PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst),
1153 PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst),
1154 PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst),
1155 PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst),
1156 PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake),
1157 PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake),
1158 PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake),
1159 PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake),
1160 PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake),
1161 PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake),
1162 PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq),
1163 PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq),
1164 PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq),
1165 PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0),
1166 PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1),
1167 PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2),
1168 PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3),
1169 PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4),
1170 PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5),
1171 PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6),
1172 PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0),
1173 PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1),
1174 PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2),
1175 PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3),
1176 PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4),
1177 PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5),
1178 PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6),
1179 PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0),
1180 PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1),
1181 PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2),
1182 PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3),
1183 PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4),
1184 PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5),
1185 PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6),
1186 PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0),
1187 PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1),
1188 PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2),
1189 PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3),
1190 PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4),
1191 PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5),
1192 PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6),
1193 PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0),
1194 PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1),
1195 PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2),
1196 PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3),
1197 PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4),
1198 PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0),
1199 PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1),
1200 PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2),
1201 PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3),
1202 PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4),
1203 PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0),
1204 PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1),
1205 PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2),
1206 PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3),
1207 PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0),
1208 PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1),
1209 PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2),
1210 PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3),
1211 PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0),
1212 PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1),
1213 PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap),
1214 PINCTRL_PIN_GROUP("rtc", mt7623_rtc),
1215 PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0),
1216 PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1),
1217 PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0),
1218 PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1),
1219 PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out),
1220 PINCTRL_PIN_GROUP("spi0", mt7623_spi0),
1221 PINCTRL_PIN_GROUP("spi1", mt7623_spi1),
1222 PINCTRL_PIN_GROUP("spi2", mt7623_spi2),
1223 PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd),
1224 PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd),
1225 PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd),
1226 PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd),
1227 PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd),
1228 PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd),
1229 PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd),
1230 PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd),
1231 PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd),
1232 PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd),
1233 PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts),
1234 PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts),
1235 PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts),
1236 PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts),
1237 PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0),
1238 PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1),
1239};
1240
1241/* Joint those groups owning the same capability in user point of view which
1242 * allows that people tend to use through the device tree.
1243 */
1244static const char *mt7623_aud_clk_groups[] = { "aud_ext_clk0",
1245 "aud_ext_clk1", };
1246static const char *mt7623_disp_pwm_groups[] = { "disp_pwm_0", "disp_pwm_1",
1247 "disp_pwm_2", };
1248static const char *mt7623_ethernet_groups[] = { "esw_int", "esw_rst",
1249 "ephy", "mdc_mdio", };
1250static const char *mt7623_ext_sdio_groups[] = { "ext_sdio", };
1251static const char *mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg",
1252 "hdmi_i2c", "hdmi_rx",
1253 "hdmi_rx_i2c", };
1254static const char *mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
1255 "i2c1_2", "i2c1_3", "i2c1_4",
1256 "i2c2_0", "i2c2_1", "i2c2_2",
1257 "i2c2_3", };
1258static const char *mt7623_i2s_groups[] = { "i2s0", "i2s1",
1259 "i2s2_bclk_lrclk_mclk",
1260 "i2s3_bclk_lrclk_mclk",
1261 "i2s4", "i2s5",
1262 "i2s2_data_in", "i2s3_data_in",
1263 "i2s2_data_0", "i2s2_data_1",
1264 "i2s3_data_0", "i2s3_data_1", };
1265static const char *mt7623_ir_groups[] = { "ir", };
1266static const char *mt7623_lcd_groups[] = { "dsi_te", "lcm_rst", "mipi_tx", };
1267static const char *mt7623_msdc_groups[] = { "msdc0", "msdc1", "msdc1_ins",
1268 "msdc1_wp_0", "msdc1_wp_1",
1269 "msdc1_wp_2", "msdc2",
1270 "msdc3", };
1271static const char *mt7623_nandc_groups[] = { "nandc", "nandc_ceb0",
1272 "nandc_ceb1", };
1273static const char *mt7623_otg_groups[] = { "otg_iddig0_0", "otg_iddig0_1",
1274 "otg_iddig0_2", "otg_iddig1_0",
1275 "otg_iddig1_1", "otg_iddig1_2",
1276 "otg_drv_vbus0_0",
1277 "otg_drv_vbus0_1",
1278 "otg_drv_vbus0_2",
1279 "otg_drv_vbus1_0",
1280 "otg_drv_vbus1_1",
1281 "otg_drv_vbus1_2", };
1282static const char *mt7623_pcie_groups[] = { "pcie0_0_perst", "pcie0_1_perst",
1283 "pcie1_0_perst", "pcie1_1_perst",
1284 "pcie2_0_perst", "pcie2_1_perst",
1285 "pcie0_0_rev_perst",
1286 "pcie0_1_rev_perst",
1287 "pcie1_0_rev_perst",
1288 "pcie1_1_rev_perst",
1289 "pcie2_0_rev_perst",
1290 "pcie2_1_rev_perst",
1291 "pcie0_0_wake", "pcie0_1_wake",
1292 "pcie2_0_wake", "pcie2_1_wake",
1293 "pcie0_clkreq", "pcie1_clkreq",
1294 "pcie2_clkreq", };
1295static const char *mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1",
1296 "pcm_clk_2", "pcm_clk_3",
1297 "pcm_clk_4", "pcm_clk_5",
1298 "pcm_clk_6", "pcm_sync_0",
1299 "pcm_sync_1", "pcm_sync_2",
1300 "pcm_sync_3", "pcm_sync_4",
1301 "pcm_sync_5", "pcm_sync_6",
1302 "pcm_rx_0", "pcm_rx_1",
1303 "pcm_rx_2", "pcm_rx_3",
1304 "pcm_rx_4", "pcm_rx_5",
1305 "pcm_rx_6", "pcm_tx_0",
1306 "pcm_tx_1", "pcm_tx_2",
1307 "pcm_tx_3", "pcm_tx_4",
1308 "pcm_tx_5", "pcm_tx_6", };
1309static const char *mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
1310 "pwm_ch1_2", "pwm_ch2_0",
1311 "pwm_ch2_1", "pwm_ch2_2",
1312 "pwm_ch3_0", "pwm_ch3_1",
1313 "pwm_ch3_2", "pwm_ch4_0",
1314 "pwm_ch4_1", "pwm_ch4_2",
1315 "pwm_ch4_3", "pwm_ch5_0",
1316 "pwm_ch5_1", "pwm_ch5_2",
1317 "pwm_ch6_0", "pwm_ch6_1",
1318 "pwm_ch6_2", "pwm_ch6_3",
1319 "pwm_ch7_0", "pwm_ch7_1",
1320 "pwm_ch7_2", };
1321static const char *mt7623_pwrap_groups[] = { "pwrap", };
1322static const char *mt7623_rtc_groups[] = { "rtc", };
1323static const char *mt7623_spi_groups[] = { "spi0", "spi2", "spi2", };
1324static const char *mt7623_spdif_groups[] = { "spdif_in0_0", "spdif_in0_1",
1325 "spdif_in1_0", "spdif_in1_1",
1326 "spdif_out", };
1327static const char *mt7623_uart_groups[] = { "uart0_0_txd_rxd",
1328 "uart0_1_txd_rxd",
1329 "uart0_2_txd_rxd",
1330 "uart0_3_txd_rxd",
1331 "uart1_0_txd_rxd",
1332 "uart1_1_txd_rxd",
1333 "uart1_2_txd_rxd",
1334 "uart2_0_txd_rxd",
1335 "uart2_1_txd_rxd",
1336 "uart3_txd_rxd",
1337 "uart0_rts_cts",
1338 "uart1_rts_cts",
1339 "uart2_rts_cts",
1340 "uart3_rts_cts", };
1341static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
1342
1343static const struct function_desc mt7623_functions[] = {
1344 {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
1345 {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
1346 {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
1347 {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
1348 {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
1349 {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
1350 {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
1351 {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
1352 {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
1353 {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
1354 {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
1355 {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
1356 {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
1357 {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
1358 {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
1359 {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
1360 {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
1361 {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
1362 {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
1363 {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
1364 {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
1365};
1366
1367static const struct mtk_eint_hw mt7623_eint_hw = {
1368 .port_mask = 6,
1369 .ports = 6,
1370 .ap_num = 169,
1371 .db_cnt = 20,
1372};
1373
1374static struct mtk_pin_soc mt7623_data = {
1375 .reg_cal = mt7623_reg_cals,
Sean Wangb7d7f9e2018-09-08 19:07:32 +0800[diff] [blame]1376 .pins = mt7623_pins,
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]1377 .npins = ARRAY_SIZE(mt7623_pins),
1378 .grps = mt7623_groups,
1379 .ngrps = ARRAY_SIZE(mt7623_groups),
1380 .funcs = mt7623_functions,
1381 .nfuncs = ARRAY_SIZE(mt7623_functions),
1382 .eint_hw = &mt7623_eint_hw,
1383 .gpio_m = 0,
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]1384 .ies_present = true,
Sean Wang2bc47df2018-09-08 19:07:30 +0800[diff] [blame]1385 .base_names = mtk_default_register_base_names,
1386 .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]1387 .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
1388 .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
1389 .bias_set = mtk_pinconf_bias_set_rev1,
1390 .bias_get = mtk_pinconf_bias_get_rev1,
1391 .drive_set = mtk_pinconf_drive_set_rev1,
1392 .drive_get = mtk_pinconf_drive_get_rev1,
1393 .adv_pull_get = mtk_pinconf_adv_pull_get,
1394 .adv_pull_set = mtk_pinconf_adv_pull_set,
1395};
1396
1397/*
1398 * There are some specific pins have mux functions greater than 8,
1399 * and if we want to switch thees high modes we need to disable
1400 * bonding constraints firstly.
1401 */
1402static void mt7623_bonding_disable(struct platform_device *pdev)
1403{
1404 struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
1405
Sean Wang2bc47df2018-09-08 19:07:30 +0800[diff] [blame]1406 mtk_rmw(hw, 0, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
1407 mtk_rmw(hw, 0, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
1408 mtk_rmw(hw, 0, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
Sean Wange7507f52018-09-08 19:07:28 +0800[diff] [blame]1409}
1410
1411static const struct of_device_id mt7623_pctrl_match[] = {
1412 { .compatible = "mediatek,mt7623-moore-pinctrl", },
1413 {}
1414};
1415
1416static int mt7623_pinctrl_probe(struct platform_device *pdev)
1417{
1418 int err;
1419
1420 err = mtk_moore_pinctrl_probe(pdev, &mt7623_data);
1421 if (err)
1422 return err;
1423
1424 mt7623_bonding_disable(pdev);
1425
1426 return 0;
1427}
1428
1429static struct platform_driver mtk_pinctrl_driver = {
1430 .probe = mt7623_pinctrl_probe,
1431 .driver = {
1432 .name = "mt7623-moore-pinctrl",
1433 .of_match_table = mt7623_pctrl_match,
1434 },
1435};
1436
1437static int __init mtk_pinctrl_init(void)
1438{
1439 return platform_driver_register(&mtk_pinctrl_driver);
1440}
1441arch_initcall(mtk_pinctrl_init);