blob: de38952dab1abf749a7c1390b38e2b73d22aee92 [file] [log] [blame]
Shawn Guo95ceafd2012-09-06 07:09:11 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
Viresh Kumar748c8762014-08-28 11:22:24 +05304 * Copyright (C) 2014 Linaro.
5 * Viresh Kumar <viresh.kumar@linaro.org>
6 *
Shawn Guo95ceafd2012-09-06 07:09:11 +00007 * The OPP code in function cpu0_set_target() is reused from
8 * drivers/cpufreq/omap-cpufreq.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/clk.h>
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +010018#include <linux/cpu.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040019#include <linux/cpu_cooling.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000020#include <linux/cpufreq.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040021#include <linux/cpumask.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000022#include <linux/err.h>
23#include <linux/module.h>
24#include <linux/of.h>
Nishanth Menone4db1c72013-09-19 16:03:52 -050025#include <linux/pm_opp.h>
Shawn Guo5553f9e2013-01-30 14:27:49 +000026#include <linux/platform_device.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000027#include <linux/regulator/consumer.h>
28#include <linux/slab.h>
Eduardo Valentin77cff592013-07-15 09:09:14 -040029#include <linux/thermal.h>
Shawn Guo95ceafd2012-09-06 07:09:11 +000030
Viresh Kumard2f31f12014-08-28 11:22:28 +053031struct private_data {
32 struct device *cpu_dev;
33 struct regulator *cpu_reg;
34 struct thermal_cooling_device *cdev;
35 unsigned int voltage_tolerance; /* in percentage */
36};
Shawn Guo95ceafd2012-09-06 07:09:11 +000037
Viresh Kumar9c0ebcf2013-10-25 19:45:48 +053038static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
Shawn Guo95ceafd2012-09-06 07:09:11 +000039{
Nishanth Menon47d43ba2013-09-19 16:03:51 -050040 struct dev_pm_opp *opp;
Viresh Kumard2f31f12014-08-28 11:22:28 +053041 struct cpufreq_frequency_table *freq_table = policy->freq_table;
42 struct clk *cpu_clk = policy->clk;
43 struct private_data *priv = policy->driver_data;
44 struct device *cpu_dev = priv->cpu_dev;
45 struct regulator *cpu_reg = priv->cpu_reg;
jhbird.choi@samsung.com5df60552013-03-18 08:09:42 +000046 unsigned long volt = 0, volt_old = 0, tol = 0;
Viresh Kumard4019f02013-08-14 19:38:24 +053047 unsigned int old_freq, new_freq;
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010048 long freq_Hz, freq_exact;
Shawn Guo95ceafd2012-09-06 07:09:11 +000049 int ret;
50
Shawn Guo95ceafd2012-09-06 07:09:11 +000051 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
Paul Walmsley2209b0c2013-11-25 18:01:18 -080052 if (freq_Hz <= 0)
Shawn Guo95ceafd2012-09-06 07:09:11 +000053 freq_Hz = freq_table[index].frequency * 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000054
Viresh Kumard4019f02013-08-14 19:38:24 +053055 freq_exact = freq_Hz;
56 new_freq = freq_Hz / 1000;
57 old_freq = clk_get_rate(cpu_clk) / 1000;
Shawn Guo95ceafd2012-09-06 07:09:11 +000058
Mark Brown4a511de2013-08-13 14:58:24 +020059 if (!IS_ERR(cpu_reg)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000060 rcu_read_lock();
Nishanth Menon5d4879c2013-09-19 16:03:50 -050061 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
Shawn Guo95ceafd2012-09-06 07:09:11 +000062 if (IS_ERR(opp)) {
Nishanth Menon78e8eb82013-01-18 19:52:33 +000063 rcu_read_unlock();
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053064 dev_err(cpu_dev, "failed to find OPP for %ld\n",
65 freq_Hz);
Viresh Kumard4019f02013-08-14 19:38:24 +053066 return PTR_ERR(opp);
Shawn Guo95ceafd2012-09-06 07:09:11 +000067 }
Nishanth Menon5d4879c2013-09-19 16:03:50 -050068 volt = dev_pm_opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +000069 rcu_read_unlock();
Viresh Kumard2f31f12014-08-28 11:22:28 +053070 tol = volt * priv->voltage_tolerance / 100;
Shawn Guo95ceafd2012-09-06 07:09:11 +000071 volt_old = regulator_get_voltage(cpu_reg);
72 }
73
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053074 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
75 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
76 new_freq / 1000, volt ? volt / 1000 : -1);
Shawn Guo95ceafd2012-09-06 07:09:11 +000077
78 /* scaling up? scale voltage before frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +053079 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000080 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
81 if (ret) {
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053082 dev_err(cpu_dev, "failed to scale voltage up: %d\n",
83 ret);
Viresh Kumard4019f02013-08-14 19:38:24 +053084 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000085 }
86 }
87
Guennadi Liakhovetski0ca68432013-02-25 18:22:37 +010088 ret = clk_set_rate(cpu_clk, freq_exact);
Shawn Guo95ceafd2012-09-06 07:09:11 +000089 if (ret) {
Viresh Kumarfbd48ca2014-08-28 11:22:27 +053090 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
Mark Brown4a511de2013-08-13 14:58:24 +020091 if (!IS_ERR(cpu_reg))
Shawn Guo95ceafd2012-09-06 07:09:11 +000092 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
Viresh Kumard4019f02013-08-14 19:38:24 +053093 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +000094 }
95
96 /* scaling down? scale voltage after frequency */
Viresh Kumard4019f02013-08-14 19:38:24 +053097 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
Shawn Guo95ceafd2012-09-06 07:09:11 +000098 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
99 if (ret) {
Viresh Kumarfbd48ca2014-08-28 11:22:27 +0530100 dev_err(cpu_dev, "failed to scale voltage down: %d\n",
101 ret);
Viresh Kumard4019f02013-08-14 19:38:24 +0530102 clk_set_rate(cpu_clk, old_freq * 1000);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000103 }
104 }
105
Viresh Kumarfd143b42013-04-01 12:57:44 +0000106 return ret;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000107}
108
Viresh Kumard2f31f12014-08-28 11:22:28 +0530109static int allocate_resources(struct device **cdev,
110 struct regulator **creg, struct clk **cclk)
Shawn Guo95ceafd2012-09-06 07:09:11 +0000111{
Viresh Kumard2f31f12014-08-28 11:22:28 +0530112 struct device *cpu_dev;
113 struct regulator *cpu_reg;
114 struct clk *cpu_clk;
115 int ret = 0;
Viresh Kumar2d2c5e02014-08-28 11:22:29 +0530116 char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000117
Sudeep KarkadaNageshae1825b22013-09-10 18:59:46 +0100118 cpu_dev = get_cpu_device(0);
119 if (!cpu_dev) {
120 pr_err("failed to get cpu0 device\n");
121 return -ENODEV;
122 }
Paolo Pisatif5c3ef22013-03-28 09:24:29 +0000123
Viresh Kumar2d2c5e02014-08-28 11:22:29 +0530124 /* Try "cpu0" for older DTs */
125 reg = reg_cpu0;
126
127try_again:
128 cpu_reg = regulator_get_optional(cpu_dev, reg);
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000129 if (IS_ERR(cpu_reg)) {
130 /*
131 * If cpu0 regulator supply node is present, but regulator is
132 * not yet registered, we should try defering probe.
133 */
134 if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
Markus Pargmann713a3fa2014-08-04 14:48:03 +0200135 dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");
Viresh Kumard2f31f12014-08-28 11:22:28 +0530136 return -EPROBE_DEFER;
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000137 }
Viresh Kumar2d2c5e02014-08-28 11:22:29 +0530138
139 /* Try with "cpu-supply" */
140 if (reg == reg_cpu0) {
141 reg = reg_cpu;
142 goto try_again;
143 }
144
Viresh Kumarfbd48ca2014-08-28 11:22:27 +0530145 dev_warn(cpu_dev, "failed to get cpu0 regulator: %ld\n",
146 PTR_ERR(cpu_reg));
Nishanth Menonfc31d6f2013-05-01 13:38:12 +0000147 }
148
Lucas Stache3beb0a2014-05-16 12:20:42 +0200149 cpu_clk = clk_get(cpu_dev, NULL);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000150 if (IS_ERR(cpu_clk)) {
Viresh Kumard2f31f12014-08-28 11:22:28 +0530151 /* put regulator */
152 if (!IS_ERR(cpu_reg))
153 regulator_put(cpu_reg);
154
Shawn Guo95ceafd2012-09-06 07:09:11 +0000155 ret = PTR_ERR(cpu_clk);
Viresh Kumar48a86242014-08-28 11:22:26 +0530156
157 /*
158 * If cpu's clk node is present, but clock is not yet
159 * registered, we should try defering probe.
160 */
161 if (ret == -EPROBE_DEFER)
162 dev_dbg(cpu_dev, "cpu0 clock not ready, retry\n");
163 else
164 dev_err(cpu_dev, "failed to get cpu0 clock: %d\n", ret);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530165 } else {
166 *cdev = cpu_dev;
167 *creg = cpu_reg;
168 *cclk = cpu_clk;
169 }
Viresh Kumar48a86242014-08-28 11:22:26 +0530170
Viresh Kumard2f31f12014-08-28 11:22:28 +0530171 return ret;
172}
173
174static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
175{
176 struct cpufreq_frequency_table *freq_table;
177 struct thermal_cooling_device *cdev;
178 struct device_node *np;
179 struct private_data *priv;
180 struct device *cpu_dev;
181 struct regulator *cpu_reg;
182 struct clk *cpu_clk;
183 unsigned int transition_latency;
184 int ret;
185
186 /* We only support cpu0 currently */
187 ret = allocate_resources(&cpu_dev, &cpu_reg, &cpu_clk);
188 if (ret) {
189 pr_err("%s: Failed to allocate resources\n: %d", __func__, ret);
190 return ret;
191 }
192
193 np = of_node_get(cpu_dev->of_node);
194 if (!np) {
195 dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
196 ret = -ENOENT;
197 goto out_put_reg_clk;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000198 }
199
Viresh Kumar1bf8cc32014-07-11 20:24:19 +0530200 /* OPPs might be populated at runtime, don't check for error here */
201 of_init_opp_table(cpu_dev);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000202
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500203 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000204 if (ret) {
Viresh Kumarfbd48ca2014-08-28 11:22:27 +0530205 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530206 goto out_put_node;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000207 }
208
Viresh Kumard2f31f12014-08-28 11:22:28 +0530209 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
210 if (!priv) {
211 ret = -ENOMEM;
212 goto out_free_table;
213 }
214
215 of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000216
217 if (of_property_read_u32(np, "clock-latency", &transition_latency))
218 transition_latency = CPUFREQ_ETERNAL;
219
Philipp Zabel43c638e2013-09-26 11:19:37 +0200220 if (!IS_ERR(cpu_reg)) {
Nishanth Menon47d43ba2013-09-19 16:03:51 -0500221 struct dev_pm_opp *opp;
Shawn Guo95ceafd2012-09-06 07:09:11 +0000222 unsigned long min_uV, max_uV;
223 int i;
224
225 /*
226 * OPP is maintained in order of increasing frequency, and
227 * freq_table initialised from OPP is therefore sorted in the
228 * same order.
229 */
230 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
231 ;
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000232 rcu_read_lock();
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500233 opp = dev_pm_opp_find_freq_exact(cpu_dev,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000234 freq_table[0].frequency * 1000, true);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500235 min_uV = dev_pm_opp_get_voltage(opp);
236 opp = dev_pm_opp_find_freq_exact(cpu_dev,
Shawn Guo95ceafd2012-09-06 07:09:11 +0000237 freq_table[i-1].frequency * 1000, true);
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500238 max_uV = dev_pm_opp_get_voltage(opp);
Nishanth Menon78e8eb82013-01-18 19:52:33 +0000239 rcu_read_unlock();
Shawn Guo95ceafd2012-09-06 07:09:11 +0000240 ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
241 if (ret > 0)
242 transition_latency += ret * 1000;
243 }
244
Eduardo Valentin77cff592013-07-15 09:09:14 -0400245 /*
246 * For now, just loading the cooling device;
247 * thermal DT code takes care of matching them.
248 */
249 if (of_find_property(np, "#cooling-cells", NULL)) {
250 cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
251 if (IS_ERR(cdev))
Viresh Kumarfbd48ca2014-08-28 11:22:27 +0530252 dev_err(cpu_dev,
253 "running cpufreq without cooling device: %ld\n",
254 PTR_ERR(cdev));
Viresh Kumard2f31f12014-08-28 11:22:28 +0530255 else
256 priv->cdev = cdev;
Eduardo Valentin77cff592013-07-15 09:09:14 -0400257 }
Shawn Guo95ceafd2012-09-06 07:09:11 +0000258 of_node_put(np);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530259
260 priv->cpu_dev = cpu_dev;
261 priv->cpu_reg = cpu_reg;
262 policy->driver_data = priv;
263
264 policy->clk = cpu_clk;
265 ret = cpufreq_generic_init(policy, freq_table, transition_latency);
266 if (ret)
267 goto out_cooling_unregister;
268
Shawn Guo95ceafd2012-09-06 07:09:11 +0000269 return 0;
270
Viresh Kumard2f31f12014-08-28 11:22:28 +0530271out_cooling_unregister:
272 cpufreq_cooling_unregister(priv->cdev);
273 kfree(priv);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000274out_free_table:
Nishanth Menon5d4879c2013-09-19 16:03:50 -0500275 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000276out_put_node:
277 of_node_put(np);
Viresh Kumard2f31f12014-08-28 11:22:28 +0530278out_put_reg_clk:
279 clk_put(cpu_clk);
280 if (!IS_ERR(cpu_reg))
281 regulator_put(cpu_reg);
282
283 return ret;
284}
285
286static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
287{
288 struct private_data *priv = policy->driver_data;
289
290 cpufreq_cooling_unregister(priv->cdev);
291 dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
292 clk_put(policy->clk);
293 if (!IS_ERR(priv->cpu_reg))
294 regulator_put(priv->cpu_reg);
295 kfree(priv);
296
297 return 0;
298}
299
300static struct cpufreq_driver cpu0_cpufreq_driver = {
301 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
302 .verify = cpufreq_generic_frequency_table_verify,
303 .target_index = cpu0_set_target,
304 .get = cpufreq_generic_get,
305 .init = cpu0_cpufreq_init,
306 .exit = cpu0_cpufreq_exit,
307 .name = "generic_cpu0",
308 .attr = cpufreq_generic_attr,
309};
310
311static int cpu0_cpufreq_probe(struct platform_device *pdev)
312{
313 struct device *cpu_dev;
314 struct regulator *cpu_reg;
315 struct clk *cpu_clk;
316 int ret;
317
318 /*
319 * All per-cluster (CPUs sharing clock/voltages) initialization is done
320 * from ->init(). In probe(), we just need to make sure that clk and
321 * regulators are available. Else defer probe and retry.
322 *
323 * FIXME: Is checking this only for CPU0 sufficient ?
324 */
325 ret = allocate_resources(&cpu_dev, &cpu_reg, &cpu_clk);
326 if (ret)
327 return ret;
328
329 clk_put(cpu_clk);
330 if (!IS_ERR(cpu_reg))
331 regulator_put(cpu_reg);
332
333 ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
334 if (ret)
335 dev_err(cpu_dev, "failed register driver: %d\n", ret);
336
Shawn Guo95ceafd2012-09-06 07:09:11 +0000337 return ret;
338}
Shawn Guo5553f9e2013-01-30 14:27:49 +0000339
340static int cpu0_cpufreq_remove(struct platform_device *pdev)
341{
342 cpufreq_unregister_driver(&cpu0_cpufreq_driver);
Shawn Guo5553f9e2013-01-30 14:27:49 +0000343 return 0;
344}
345
346static struct platform_driver cpu0_cpufreq_platdrv = {
347 .driver = {
348 .name = "cpufreq-cpu0",
349 .owner = THIS_MODULE,
350 },
351 .probe = cpu0_cpufreq_probe,
352 .remove = cpu0_cpufreq_remove,
353};
354module_platform_driver(cpu0_cpufreq_platdrv);
Shawn Guo95ceafd2012-09-06 07:09:11 +0000355
Viresh Kumar748c8762014-08-28 11:22:24 +0530356MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
Shawn Guo95ceafd2012-09-06 07:09:11 +0000357MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
358MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
359MODULE_LICENSE("GPL");