Boris BREZILLON | ea4abe7 | 2015-03-12 15:54:27 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 Atmel |
| 3 | * |
| 4 | * Boris Brezillon <boris.brezillon@free-electrons.com |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #ifndef __AT91_SOC_H |
| 13 | #define __AT91_SOC_H |
| 14 | |
| 15 | #include <linux/sys_soc.h> |
| 16 | |
| 17 | struct at91_soc { |
| 18 | u32 cidr_match; |
| 19 | u32 exid_match; |
| 20 | const char *name; |
| 21 | const char *family; |
| 22 | }; |
| 23 | |
| 24 | #define AT91_SOC(__cidr, __exid, __name, __family) \ |
| 25 | { \ |
| 26 | .cidr_match = (__cidr), \ |
| 27 | .exid_match = (__exid), \ |
| 28 | .name = (__name), \ |
| 29 | .family = (__family), \ |
| 30 | } |
| 31 | |
| 32 | struct soc_device * __init |
| 33 | at91_soc_init(const struct at91_soc *socs); |
| 34 | |
Alexandre Belloni | 7735f03 | 2015-03-12 15:54:28 +0100 | [diff] [blame] | 35 | #define AT91RM9200_CIDR_MATCH 0x09290780 |
| 36 | |
Alexandre Belloni | d18032d | 2015-03-12 15:54:29 +0100 | [diff] [blame] | 37 | #define AT91SAM9260_CIDR_MATCH 0x019803a0 |
| 38 | #define AT91SAM9261_CIDR_MATCH 0x019703a0 |
| 39 | #define AT91SAM9263_CIDR_MATCH 0x019607a0 |
| 40 | #define AT91SAM9G20_CIDR_MATCH 0x019905a0 |
| 41 | #define AT91SAM9RL64_CIDR_MATCH 0x019b03a0 |
| 42 | #define AT91SAM9G45_CIDR_MATCH 0x019b05a0 |
| 43 | #define AT91SAM9X5_CIDR_MATCH 0x019a05a0 |
| 44 | #define AT91SAM9N12_CIDR_MATCH 0x019a07a0 |
Sandeep Sheriker Mallikarjun | 446e898 | 2018-12-12 11:41:10 +0100 | [diff] [blame] | 45 | #define SAM9X60_CIDR_MATCH 0x019b35a0 |
Alexandre Belloni | d18032d | 2015-03-12 15:54:29 +0100 | [diff] [blame] | 46 | |
| 47 | #define AT91SAM9M11_EXID_MATCH 0x00000001 |
| 48 | #define AT91SAM9M10_EXID_MATCH 0x00000002 |
| 49 | #define AT91SAM9G46_EXID_MATCH 0x00000003 |
| 50 | #define AT91SAM9G45_EXID_MATCH 0x00000004 |
| 51 | |
| 52 | #define AT91SAM9G15_EXID_MATCH 0x00000000 |
| 53 | #define AT91SAM9G35_EXID_MATCH 0x00000001 |
| 54 | #define AT91SAM9X35_EXID_MATCH 0x00000002 |
| 55 | #define AT91SAM9G25_EXID_MATCH 0x00000003 |
| 56 | #define AT91SAM9X25_EXID_MATCH 0x00000004 |
| 57 | |
| 58 | #define AT91SAM9CN12_EXID_MATCH 0x00000005 |
| 59 | #define AT91SAM9N12_EXID_MATCH 0x00000006 |
| 60 | #define AT91SAM9CN11_EXID_MATCH 0x00000009 |
| 61 | |
Sandeep Sheriker Mallikarjun | 446e898 | 2018-12-12 11:41:10 +0100 | [diff] [blame] | 62 | #define SAM9X60_EXID_MATCH 0x00000000 |
| 63 | |
Alexandre Belloni | d18032d | 2015-03-12 15:54:29 +0100 | [diff] [blame] | 64 | #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 |
| 65 | #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 |
| 66 | #define AT91SAM9XE512_CIDR_MATCH 0x329aa3a0 |
| 67 | |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 68 | #define SAMA5D2_CIDR_MATCH 0x0a5c08c0 |
Ludovic Desroches | c07f98a | 2016-03-18 08:21:20 +0100 | [diff] [blame] | 69 | #define SAMA5D21CU_EXID_MATCH 0x0000005a |
Cristian Birsan | cd2e9be | 2017-07-06 11:35:27 +0300 | [diff] [blame] | 70 | #define SAMA5D225C_D1M_EXID_MATCH 0x00000053 |
Ludovic Desroches | c07f98a | 2016-03-18 08:21:20 +0100 | [diff] [blame] | 71 | #define SAMA5D22CU_EXID_MATCH 0x00000059 |
| 72 | #define SAMA5D22CN_EXID_MATCH 0x00000069 |
| 73 | #define SAMA5D23CU_EXID_MATCH 0x00000058 |
| 74 | #define SAMA5D24CX_EXID_MATCH 0x00000004 |
| 75 | #define SAMA5D24CU_EXID_MATCH 0x00000014 |
| 76 | #define SAMA5D26CU_EXID_MATCH 0x00000012 |
Cristian Birsan | cd2e9be | 2017-07-06 11:35:27 +0300 | [diff] [blame] | 77 | #define SAMA5D27C_D1G_EXID_MATCH 0x00000033 |
| 78 | #define SAMA5D27C_D5M_EXID_MATCH 0x00000032 |
Nicolas Ferre | 15653dc | 2018-11-28 12:00:35 +0100 | [diff] [blame] | 79 | #define SAMA5D27C_LD1G_EXID_MATCH 0x00000061 |
| 80 | #define SAMA5D27C_LD2G_EXID_MATCH 0x00000062 |
Ludovic Desroches | c07f98a | 2016-03-18 08:21:20 +0100 | [diff] [blame] | 81 | #define SAMA5D27CU_EXID_MATCH 0x00000011 |
| 82 | #define SAMA5D27CN_EXID_MATCH 0x00000021 |
Cristian Birsan | cd2e9be | 2017-07-06 11:35:27 +0300 | [diff] [blame] | 83 | #define SAMA5D28C_D1G_EXID_MATCH 0x00000013 |
Nicolas Ferre | 15653dc | 2018-11-28 12:00:35 +0100 | [diff] [blame] | 84 | #define SAMA5D28C_LD1G_EXID_MATCH 0x00000071 |
| 85 | #define SAMA5D28C_LD2G_EXID_MATCH 0x00000072 |
Ludovic Desroches | c07f98a | 2016-03-18 08:21:20 +0100 | [diff] [blame] | 86 | #define SAMA5D28CU_EXID_MATCH 0x00000010 |
| 87 | #define SAMA5D28CN_EXID_MATCH 0x00000020 |
Nicolas Ferre | c268a74 | 2015-07-30 19:12:12 +0200 | [diff] [blame] | 88 | |
Alexandre Belloni | e733608 | 2015-03-12 15:54:30 +0100 | [diff] [blame] | 89 | #define SAMA5D3_CIDR_MATCH 0x0a5c07c0 |
| 90 | #define SAMA5D31_EXID_MATCH 0x00444300 |
| 91 | #define SAMA5D33_EXID_MATCH 0x00414300 |
| 92 | #define SAMA5D34_EXID_MATCH 0x00414301 |
| 93 | #define SAMA5D35_EXID_MATCH 0x00584300 |
| 94 | #define SAMA5D36_EXID_MATCH 0x00004301 |
| 95 | |
| 96 | #define SAMA5D4_CIDR_MATCH 0x0a5c07c0 |
| 97 | #define SAMA5D41_EXID_MATCH 0x00000001 |
| 98 | #define SAMA5D42_EXID_MATCH 0x00000002 |
| 99 | #define SAMA5D43_EXID_MATCH 0x00000003 |
| 100 | #define SAMA5D44_EXID_MATCH 0x00000004 |
| 101 | |
Szemző András | 82208e7 | 2017-05-31 03:06:23 +0200 | [diff] [blame] | 102 | #define SAME70Q21_CIDR_MATCH 0x21020e00 |
| 103 | #define SAME70Q21_EXID_MATCH 0x00000002 |
| 104 | #define SAME70Q20_CIDR_MATCH 0x21020c00 |
| 105 | #define SAME70Q20_EXID_MATCH 0x00000002 |
| 106 | #define SAME70Q19_CIDR_MATCH 0x210d0a00 |
| 107 | #define SAME70Q19_EXID_MATCH 0x00000002 |
| 108 | |
| 109 | #define SAMS70Q21_CIDR_MATCH 0x21120e00 |
| 110 | #define SAMS70Q21_EXID_MATCH 0x00000002 |
| 111 | #define SAMS70Q20_CIDR_MATCH 0x21120c00 |
| 112 | #define SAMS70Q20_EXID_MATCH 0x00000002 |
| 113 | #define SAMS70Q19_CIDR_MATCH 0x211d0a00 |
| 114 | #define SAMS70Q19_EXID_MATCH 0x00000002 |
| 115 | |
| 116 | #define SAMV71Q21_CIDR_MATCH 0x21220e00 |
| 117 | #define SAMV71Q21_EXID_MATCH 0x00000002 |
| 118 | #define SAMV71Q20_CIDR_MATCH 0x21220c00 |
| 119 | #define SAMV71Q20_EXID_MATCH 0x00000002 |
| 120 | #define SAMV71Q19_CIDR_MATCH 0x212d0a00 |
| 121 | #define SAMV71Q19_EXID_MATCH 0x00000002 |
| 122 | |
| 123 | #define SAMV70Q20_CIDR_MATCH 0x21320c00 |
| 124 | #define SAMV70Q20_EXID_MATCH 0x00000002 |
| 125 | #define SAMV70Q19_CIDR_MATCH 0x213d0a00 |
| 126 | #define SAMV70Q19_EXID_MATCH 0x00000002 |
| 127 | |
Boris BREZILLON | ea4abe7 | 2015-03-12 15:54:27 +0100 | [diff] [blame] | 128 | #endif /* __AT91_SOC_H */ |