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Gregory CLEMENTca368552018-03-15 12:03:52 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +01002/*
3 * Device Tree file for Marvell Armada XP development board
4 * (DB-MV784MP-GP)
5 *
Thomas Petazzoni91ed3222014-03-04 17:37:01 +01006 * Copyright (C) 2013-2014 Marvell
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +01007 *
8 * Lior Amsalem <alior@marvell.com>
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 *
Thomas Petazzoni91ed3222014-03-04 17:37:01 +010012 * Note: this Device Tree assumes that the bootloader has remapped the
13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
16 * boards were delivered with an older version of the bootloader that
17 * left internal registers mapped at 0xd0000000. If you are in this
18 * situation, you should either update your bootloader (preferred
19 * solution) or the below Device Tree should be adjusted.
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010020 */
21
22/dts-v1/;
Thomas Petazzoni389a3672014-11-21 17:00:11 +010023#include <dt-bindings/gpio/gpio.h>
Ezequiel Garcia38149882013-07-26 10:17:56 -030024#include "armada-xp-mv78460.dtsi"
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010025
26/ {
27 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
28 compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
29
30 chosen {
Thomas Petazzoni95522032015-03-03 15:41:02 +010031 stdout-path = "serial0:115200n8";
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010032 };
33
Gregory CLEMENT6f477f42016-11-06 09:29:35 +010034 memory@0 {
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010035 device_type = "memory";
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010036 /*
Gregory CLEMENT74898362013-04-12 16:29:10 +020037 * 8 GB of plug-in RAM modules by default.The amount
38 * of memory available can be changed by the
39 * bootloader according the size of the module
Thomas Petazzoni91ed3222014-03-04 17:37:01 +010040 * actually plugged. However, memory between
41 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
42 * the address range used for I/O (internal registers,
43 * MBus windows).
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010044 */
Thomas Petazzoni91ed3222014-03-04 17:37:01 +010045 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
Gregory CLEMENT74898362013-04-12 16:29:10 +020046 <0x00000001 0x00000000 0x00000001 0x00000000>;
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010047 };
48
Thomas Petazzoni389a3672014-11-21 17:00:11 +010049 cpus {
50 pm_pic {
51 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
52 <&gpio0 17 GPIO_ACTIVE_LOW>,
53 <&gpio0 18 GPIO_ACTIVE_LOW>;
54 };
55 };
56
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +010057 soc {
Thomas Petazzoni91ed3222014-03-04 17:37:01 +010058 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
Ezequiel Garciade1af8d2013-07-26 10:17:59 -030059 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
Boris Brezillonc466d992015-08-18 10:08:53 +020060 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
Thomas Petazzonid7d5a432016-03-08 16:59:57 +010061 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
Linus Torvalds1200b682016-03-19 10:05:34 -070062 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
Marcin Wojtas9dd7a572016-03-14 09:39:00 +010063 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
Ezequiel Garciade1af8d2013-07-26 10:17:59 -030064
65 devbus-bootcs {
66 status = "okay";
67
68 /* Device Bus parameters are required */
69
70 /* Read parameters */
Thomas Petazzoni1a88f802014-04-14 17:29:19 +020071 devbus,bus-width = <16>;
Ezequiel Garciade1af8d2013-07-26 10:17:59 -030072 devbus,turn-off-ps = <60000>;
73 devbus,badr-skew-ps = <0>;
74 devbus,acc-first-ps = <124000>;
75 devbus,acc-next-ps = <248000>;
76 devbus,rd-setup-ps = <0>;
77 devbus,rd-hold-ps = <0>;
78
79 /* Write parameters */
80 devbus,sync-enable = <0>;
81 devbus,wr-high-ps = <60000>;
82 devbus,wr-low-ps = <60000>;
83 devbus,ale-wr-ps = <60000>;
84
85 /* NOR 16 MiB */
86 nor@0 {
87 compatible = "cfi-flash";
88 reg = <0 0x1000000>;
89 bank-width = <2>;
90 };
91 };
Ezequiel Garciac6c003a2013-05-17 08:09:57 -030092
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020093 internal-regs {
94 serial@12000 {
Thomas Petazzoni513a7912013-04-09 23:06:39 +020095 status = "okay";
96 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +020097 serial@12100 {
Thomas Petazzoni513a7912013-04-09 23:06:39 +020098 status = "okay";
99 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200100 serial@12200 {
Thomas Petazzoni513a7912013-04-09 23:06:39 +0200101 status = "okay";
102 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200103 serial@12300 {
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200104 status = "okay";
105 };
Thomas Petazzoni389a3672014-11-21 17:00:11 +0100106 pinctrl {
107 pinctrl-0 = <&pic_pins>;
108 pinctrl-names = "default";
109 pic_pins: pic-pins-0 {
110 marvell,pins = "mpp16", "mpp17",
111 "mpp18";
112 marvell,function = "gpio";
113 };
114 };
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200115 sata@a0000 {
116 nr-ports = <2>;
117 status = "okay";
118 };
119
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200120 ethernet@70000 {
121 status = "okay";
122 phy = <&phy0>;
Thomas Petazzoni80fa10f2014-04-15 15:50:21 +0200123 phy-mode = "qsgmii";
Marcin Wojtas9dd7a572016-03-14 09:39:00 +0100124 buffer-manager = <&bm>;
125 bm,pool-long = <0>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200126 };
127 ethernet@74000 {
128 status = "okay";
129 phy = <&phy1>;
Thomas Petazzoni80fa10f2014-04-15 15:50:21 +0200130 phy-mode = "qsgmii";
Marcin Wojtas9dd7a572016-03-14 09:39:00 +0100131 buffer-manager = <&bm>;
132 bm,pool-long = <1>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200133 };
134 ethernet@30000 {
135 status = "okay";
136 phy = <&phy2>;
Thomas Petazzoni80fa10f2014-04-15 15:50:21 +0200137 phy-mode = "qsgmii";
Marcin Wojtas9dd7a572016-03-14 09:39:00 +0100138 buffer-manager = <&bm>;
139 bm,pool-long = <2>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200140 };
141 ethernet@34000 {
142 status = "okay";
143 phy = <&phy3>;
Thomas Petazzoni80fa10f2014-04-15 15:50:21 +0200144 phy-mode = "qsgmii";
Marcin Wojtas9dd7a572016-03-14 09:39:00 +0100145 buffer-manager = <&bm>;
146 bm,pool-long = <3>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200147 };
148
Thomas Petazzoni0e99b152013-05-21 19:53:09 +0200149 /* Front-side USB slot */
150 usb@50000 {
151 status = "okay";
152 };
153
154 /* Back-side USB slot */
155 usb@51000 {
156 status = "okay";
157 };
158
Marcin Wojtas9dd7a572016-03-14 09:39:00 +0100159 bm@c0000 {
160 status = "okay";
161 };
162
Ezequiel Garcia2be2bc32013-11-07 12:17:34 -0300163 nand@d0000 {
164 status = "okay";
Miquel Raynal3b799192018-04-25 16:47:59 +0200165 label = "pxa3xx_nand-0";
Ezequiel Garcia2be2bc32013-11-07 12:17:34 -0300166 num-cs = <1>;
167 marvell,nand-keep-config;
Ezequiel Garcia2be2bc32013-11-07 12:17:34 -0300168 nand-on-flash-bbt;
169 };
Thomas Petazzoni513a7912013-04-09 23:06:39 +0200170 };
Marcin Wojtas9dd7a572016-03-14 09:39:00 +0100171
172 bm-bppi {
173 status = "okay";
174 };
Gregory CLEMENT568fc0a2013-01-31 15:50:12 +0100175 };
176};
Stefan Roese0160a4b2016-07-13 11:55:18 +0200177
Gregory CLEMENT007d05d2016-11-05 19:03:50 +0100178&pciec {
179 status = "okay";
180
181 /*
182 * The 3 slots are physically present as
183 * standard PCIe slots on the board.
184 */
185 pcie@1,0 {
186 /* Port 0, Lane 0 */
187 status = "okay";
188 };
189 pcie@9,0 {
190 /* Port 2, Lane 0 */
191 status = "okay";
192 };
Rob Herring28fbb9c2017-07-26 16:09:37 -0500193 pcie@a,0 {
Gregory CLEMENT007d05d2016-11-05 19:03:50 +0100194 /* Port 3, Lane 0 */
195 status = "okay";
196 };
197};
198
Gregory CLEMENT1fc21292016-11-04 17:54:54 +0100199&mdio {
200 phy0: ethernet-phy@0 {
201 reg = <16>;
202 };
203
204 phy1: ethernet-phy@1 {
205 reg = <17>;
206 };
207
208 phy2: ethernet-phy@2 {
209 reg = <18>;
210 };
211
212 phy3: ethernet-phy@3 {
213 reg = <19>;
214 };
215};
216
Stefan Roese0160a4b2016-07-13 11:55:18 +0200217&spi0 {
218 status = "okay";
219
220 spi-flash@0 {
221 #address-cells = <1>;
222 #size-cells = <1>;
223 compatible = "n25q128a13", "jedec,spi-nor";
224 reg = <0>; /* Chip select 0 */
225 spi-max-frequency = <108000000>;
226 };
227};