Thomas Gleixner | 5b497af | 2019-05-29 07:18:09 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 2 | /* |
| 3 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 4 | */ |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 5 | #include <linux/scatterlist.h> |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 6 | #include <linux/highmem.h> |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 7 | #include <linux/sched.h> |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 8 | #include <linux/slab.h> |
Dan Williams | 0c27af6 | 2016-05-27 09:23:01 -0700 | [diff] [blame] | 9 | #include <linux/hash.h> |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 10 | #include <linux/sort.h> |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 11 | #include <linux/io.h> |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 12 | #include <linux/nd.h> |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 13 | #include "nd-core.h" |
| 14 | #include "nd.h" |
| 15 | |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 16 | /* |
| 17 | * For readq() and writeq() on 32-bit builds, the hi-lo, lo-hi order is |
| 18 | * irrelevant. |
| 19 | */ |
| 20 | #include <linux/io-64-nonatomic-hi-lo.h> |
| 21 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 22 | static DEFINE_IDA(region_ida); |
Dan Williams | 0c27af6 | 2016-05-27 09:23:01 -0700 | [diff] [blame] | 23 | static DEFINE_PER_CPU(int, flush_idx); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 24 | |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 25 | static int nvdimm_map_flush(struct device *dev, struct nvdimm *nvdimm, int dimm, |
| 26 | struct nd_region_data *ndrd) |
| 27 | { |
| 28 | int i, j; |
| 29 | |
| 30 | dev_dbg(dev, "%s: map %d flush address%s\n", nvdimm_name(nvdimm), |
| 31 | nvdimm->num_flush, nvdimm->num_flush == 1 ? "" : "es"); |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 32 | for (i = 0; i < (1 << ndrd->hints_shift); i++) { |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 33 | struct resource *res = &nvdimm->flush_wpq[i]; |
| 34 | unsigned long pfn = PHYS_PFN(res->start); |
| 35 | void __iomem *flush_page; |
| 36 | |
| 37 | /* check if flush hints share a page */ |
| 38 | for (j = 0; j < i; j++) { |
| 39 | struct resource *res_j = &nvdimm->flush_wpq[j]; |
| 40 | unsigned long pfn_j = PHYS_PFN(res_j->start); |
| 41 | |
| 42 | if (pfn == pfn_j) |
| 43 | break; |
| 44 | } |
| 45 | |
| 46 | if (j < i) |
| 47 | flush_page = (void __iomem *) ((unsigned long) |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 48 | ndrd_get_flush_wpq(ndrd, dimm, j) |
| 49 | & PAGE_MASK); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 50 | else |
| 51 | flush_page = devm_nvdimm_ioremap(dev, |
Oliver O'Halloran | 480b683 | 2016-09-19 20:19:00 +1000 | [diff] [blame] | 52 | PFN_PHYS(pfn), PAGE_SIZE); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 53 | if (!flush_page) |
| 54 | return -ENXIO; |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 55 | ndrd_set_flush_wpq(ndrd, dimm, i, flush_page |
| 56 | + (res->start & ~PAGE_MASK)); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 57 | } |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
| 62 | int nd_region_activate(struct nd_region *nd_region) |
| 63 | { |
Dave Jiang | db58028 | 2016-09-26 11:06:50 -0700 | [diff] [blame] | 64 | int i, j, num_flush = 0; |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 65 | struct nd_region_data *ndrd; |
| 66 | struct device *dev = &nd_region->dev; |
| 67 | size_t flush_data_size = sizeof(void *); |
| 68 | |
| 69 | nvdimm_bus_lock(&nd_region->dev); |
| 70 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
| 71 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
| 72 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
| 73 | |
Dave Jiang | 7d98809 | 2018-12-13 15:36:18 -0700 | [diff] [blame] | 74 | if (test_bit(NDD_SECURITY_OVERWRITE, &nvdimm->flags)) { |
| 75 | nvdimm_bus_unlock(&nd_region->dev); |
| 76 | return -EBUSY; |
| 77 | } |
| 78 | |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 79 | /* at least one null hint slot per-dimm for the "no-hint" case */ |
| 80 | flush_data_size += sizeof(void *); |
Dan Williams | 0c27af6 | 2016-05-27 09:23:01 -0700 | [diff] [blame] | 81 | num_flush = min_not_zero(num_flush, nvdimm->num_flush); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 82 | if (!nvdimm->num_flush) |
| 83 | continue; |
| 84 | flush_data_size += nvdimm->num_flush * sizeof(void *); |
| 85 | } |
| 86 | nvdimm_bus_unlock(&nd_region->dev); |
| 87 | |
| 88 | ndrd = devm_kzalloc(dev, sizeof(*ndrd) + flush_data_size, GFP_KERNEL); |
| 89 | if (!ndrd) |
| 90 | return -ENOMEM; |
| 91 | dev_set_drvdata(dev, ndrd); |
| 92 | |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 93 | if (!num_flush) |
| 94 | return 0; |
| 95 | |
| 96 | ndrd->hints_shift = ilog2(num_flush); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 97 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
| 98 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
| 99 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
| 100 | int rc = nvdimm_map_flush(&nd_region->dev, nvdimm, i, ndrd); |
| 101 | |
| 102 | if (rc) |
| 103 | return rc; |
| 104 | } |
| 105 | |
Dave Jiang | db58028 | 2016-09-26 11:06:50 -0700 | [diff] [blame] | 106 | /* |
| 107 | * Clear out entries that are duplicates. This should prevent the |
| 108 | * extra flushings. |
| 109 | */ |
| 110 | for (i = 0; i < nd_region->ndr_mappings - 1; i++) { |
| 111 | /* ignore if NULL already */ |
| 112 | if (!ndrd_get_flush_wpq(ndrd, i, 0)) |
| 113 | continue; |
| 114 | |
| 115 | for (j = i + 1; j < nd_region->ndr_mappings; j++) |
| 116 | if (ndrd_get_flush_wpq(ndrd, i, 0) == |
| 117 | ndrd_get_flush_wpq(ndrd, j, 0)) |
| 118 | ndrd_set_flush_wpq(ndrd, j, 0, NULL); |
| 119 | } |
| 120 | |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 121 | return 0; |
| 122 | } |
| 123 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 124 | static void nd_region_release(struct device *dev) |
| 125 | { |
| 126 | struct nd_region *nd_region = to_nd_region(dev); |
| 127 | u16 i; |
| 128 | |
| 129 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
| 130 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
| 131 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
| 132 | |
| 133 | put_device(&nvdimm->dev); |
| 134 | } |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 135 | free_percpu(nd_region->lane); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 136 | ida_simple_remove(®ion_ida, nd_region->id); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 137 | if (is_nd_blk(dev)) |
| 138 | kfree(to_nd_blk_region(dev)); |
| 139 | else |
| 140 | kfree(nd_region); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | static struct device_type nd_blk_device_type = { |
| 144 | .name = "nd_blk", |
| 145 | .release = nd_region_release, |
| 146 | }; |
| 147 | |
| 148 | static struct device_type nd_pmem_device_type = { |
| 149 | .name = "nd_pmem", |
| 150 | .release = nd_region_release, |
| 151 | }; |
| 152 | |
| 153 | static struct device_type nd_volatile_device_type = { |
| 154 | .name = "nd_volatile", |
| 155 | .release = nd_region_release, |
| 156 | }; |
| 157 | |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 158 | bool is_nd_pmem(struct device *dev) |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 159 | { |
| 160 | return dev ? dev->type == &nd_pmem_device_type : false; |
| 161 | } |
| 162 | |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 163 | bool is_nd_blk(struct device *dev) |
| 164 | { |
| 165 | return dev ? dev->type == &nd_blk_device_type : false; |
| 166 | } |
| 167 | |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 168 | bool is_nd_volatile(struct device *dev) |
| 169 | { |
| 170 | return dev ? dev->type == &nd_volatile_device_type : false; |
| 171 | } |
| 172 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 173 | struct nd_region *to_nd_region(struct device *dev) |
| 174 | { |
| 175 | struct nd_region *nd_region = container_of(dev, struct nd_region, dev); |
| 176 | |
| 177 | WARN_ON(dev->type->release != nd_region_release); |
| 178 | return nd_region; |
| 179 | } |
| 180 | EXPORT_SYMBOL_GPL(to_nd_region); |
| 181 | |
Dan Williams | 243f29f | 2018-04-02 13:14:25 -0700 | [diff] [blame] | 182 | struct device *nd_region_dev(struct nd_region *nd_region) |
| 183 | { |
| 184 | if (!nd_region) |
| 185 | return NULL; |
| 186 | return &nd_region->dev; |
| 187 | } |
| 188 | EXPORT_SYMBOL_GPL(nd_region_dev); |
| 189 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 190 | struct nd_blk_region *to_nd_blk_region(struct device *dev) |
| 191 | { |
| 192 | struct nd_region *nd_region = to_nd_region(dev); |
| 193 | |
| 194 | WARN_ON(!is_nd_blk(dev)); |
| 195 | return container_of(nd_region, struct nd_blk_region, nd_region); |
| 196 | } |
| 197 | EXPORT_SYMBOL_GPL(to_nd_blk_region); |
| 198 | |
| 199 | void *nd_region_provider_data(struct nd_region *nd_region) |
| 200 | { |
| 201 | return nd_region->provider_data; |
| 202 | } |
| 203 | EXPORT_SYMBOL_GPL(nd_region_provider_data); |
| 204 | |
| 205 | void *nd_blk_region_provider_data(struct nd_blk_region *ndbr) |
| 206 | { |
| 207 | return ndbr->blk_provider_data; |
| 208 | } |
| 209 | EXPORT_SYMBOL_GPL(nd_blk_region_provider_data); |
| 210 | |
| 211 | void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data) |
| 212 | { |
| 213 | ndbr->blk_provider_data = data; |
| 214 | } |
| 215 | EXPORT_SYMBOL_GPL(nd_blk_region_set_provider_data); |
| 216 | |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 217 | /** |
| 218 | * nd_region_to_nstype() - region to an integer namespace type |
| 219 | * @nd_region: region-device to interrogate |
| 220 | * |
| 221 | * This is the 'nstype' attribute of a region as well, an input to the |
| 222 | * MODALIAS for namespace devices, and bit number for a nvdimm_bus to match |
| 223 | * namespace devices with namespace drivers. |
| 224 | */ |
| 225 | int nd_region_to_nstype(struct nd_region *nd_region) |
| 226 | { |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 227 | if (is_memory(&nd_region->dev)) { |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 228 | u16 i, alias; |
| 229 | |
| 230 | for (i = 0, alias = 0; i < nd_region->ndr_mappings; i++) { |
| 231 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
| 232 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
| 233 | |
Dan Williams | 8f078b3 | 2017-05-04 14:01:24 -0700 | [diff] [blame] | 234 | if (test_bit(NDD_ALIASING, &nvdimm->flags)) |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 235 | alias++; |
| 236 | } |
| 237 | if (alias) |
| 238 | return ND_DEVICE_NAMESPACE_PMEM; |
| 239 | else |
| 240 | return ND_DEVICE_NAMESPACE_IO; |
| 241 | } else if (is_nd_blk(&nd_region->dev)) { |
| 242 | return ND_DEVICE_NAMESPACE_BLK; |
| 243 | } |
| 244 | |
| 245 | return 0; |
| 246 | } |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 247 | EXPORT_SYMBOL(nd_region_to_nstype); |
| 248 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 249 | static ssize_t size_show(struct device *dev, |
| 250 | struct device_attribute *attr, char *buf) |
| 251 | { |
| 252 | struct nd_region *nd_region = to_nd_region(dev); |
| 253 | unsigned long long size = 0; |
| 254 | |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 255 | if (is_memory(dev)) { |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 256 | size = nd_region->ndr_size; |
| 257 | } else if (nd_region->ndr_mappings == 1) { |
| 258 | struct nd_mapping *nd_mapping = &nd_region->mapping[0]; |
| 259 | |
| 260 | size = nd_mapping->size; |
| 261 | } |
| 262 | |
| 263 | return sprintf(buf, "%llu\n", size); |
| 264 | } |
| 265 | static DEVICE_ATTR_RO(size); |
| 266 | |
Dan Williams | ab63089 | 2017-04-21 13:28:12 -0700 | [diff] [blame] | 267 | static ssize_t deep_flush_show(struct device *dev, |
| 268 | struct device_attribute *attr, char *buf) |
| 269 | { |
| 270 | struct nd_region *nd_region = to_nd_region(dev); |
| 271 | |
| 272 | /* |
| 273 | * NOTE: in the nvdimm_has_flush() error case this attribute is |
| 274 | * not visible. |
| 275 | */ |
| 276 | return sprintf(buf, "%d\n", nvdimm_has_flush(nd_region)); |
| 277 | } |
| 278 | |
| 279 | static ssize_t deep_flush_store(struct device *dev, struct device_attribute *attr, |
| 280 | const char *buf, size_t len) |
| 281 | { |
| 282 | bool flush; |
| 283 | int rc = strtobool(buf, &flush); |
| 284 | struct nd_region *nd_region = to_nd_region(dev); |
| 285 | |
| 286 | if (rc) |
| 287 | return rc; |
| 288 | if (!flush) |
| 289 | return -EINVAL; |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 290 | rc = nvdimm_flush(nd_region, NULL); |
| 291 | if (rc) |
| 292 | return rc; |
Dan Williams | ab63089 | 2017-04-21 13:28:12 -0700 | [diff] [blame] | 293 | |
| 294 | return len; |
| 295 | } |
| 296 | static DEVICE_ATTR_RW(deep_flush); |
| 297 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 298 | static ssize_t mappings_show(struct device *dev, |
| 299 | struct device_attribute *attr, char *buf) |
| 300 | { |
| 301 | struct nd_region *nd_region = to_nd_region(dev); |
| 302 | |
| 303 | return sprintf(buf, "%d\n", nd_region->ndr_mappings); |
| 304 | } |
| 305 | static DEVICE_ATTR_RO(mappings); |
| 306 | |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 307 | static ssize_t nstype_show(struct device *dev, |
| 308 | struct device_attribute *attr, char *buf) |
| 309 | { |
| 310 | struct nd_region *nd_region = to_nd_region(dev); |
| 311 | |
| 312 | return sprintf(buf, "%d\n", nd_region_to_nstype(nd_region)); |
| 313 | } |
| 314 | static DEVICE_ATTR_RO(nstype); |
| 315 | |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 316 | static ssize_t set_cookie_show(struct device *dev, |
| 317 | struct device_attribute *attr, char *buf) |
| 318 | { |
| 319 | struct nd_region *nd_region = to_nd_region(dev); |
| 320 | struct nd_interleave_set *nd_set = nd_region->nd_set; |
Dan Williams | c12c48c | 2017-06-04 10:59:15 +0900 | [diff] [blame] | 321 | ssize_t rc = 0; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 322 | |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 323 | if (is_memory(dev) && nd_set) |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 324 | /* pass, should be precluded by region_visible */; |
| 325 | else |
| 326 | return -ENXIO; |
| 327 | |
Dan Williams | c12c48c | 2017-06-04 10:59:15 +0900 | [diff] [blame] | 328 | /* |
| 329 | * The cookie to show depends on which specification of the |
| 330 | * labels we are using. If there are not labels then default to |
| 331 | * the v1.1 namespace label cookie definition. To read all this |
| 332 | * data we need to wait for probing to settle. |
| 333 | */ |
| 334 | device_lock(dev); |
| 335 | nvdimm_bus_lock(dev); |
| 336 | wait_nvdimm_bus_probe_idle(dev); |
| 337 | if (nd_region->ndr_mappings) { |
| 338 | struct nd_mapping *nd_mapping = &nd_region->mapping[0]; |
| 339 | struct nvdimm_drvdata *ndd = to_ndd(nd_mapping); |
| 340 | |
| 341 | if (ndd) { |
| 342 | struct nd_namespace_index *nsindex; |
| 343 | |
| 344 | nsindex = to_namespace_index(ndd, ndd->ns_current); |
| 345 | rc = sprintf(buf, "%#llx\n", |
| 346 | nd_region_interleave_set_cookie(nd_region, |
| 347 | nsindex)); |
| 348 | } |
| 349 | } |
| 350 | nvdimm_bus_unlock(dev); |
| 351 | device_unlock(dev); |
| 352 | |
| 353 | if (rc) |
| 354 | return rc; |
| 355 | return sprintf(buf, "%#llx\n", nd_set->cookie1); |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 356 | } |
| 357 | static DEVICE_ATTR_RO(set_cookie); |
| 358 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 359 | resource_size_t nd_region_available_dpa(struct nd_region *nd_region) |
| 360 | { |
| 361 | resource_size_t blk_max_overlap = 0, available, overlap; |
| 362 | int i; |
| 363 | |
| 364 | WARN_ON(!is_nvdimm_bus_locked(&nd_region->dev)); |
| 365 | |
| 366 | retry: |
| 367 | available = 0; |
| 368 | overlap = blk_max_overlap; |
| 369 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
| 370 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
| 371 | struct nvdimm_drvdata *ndd = to_ndd(nd_mapping); |
| 372 | |
| 373 | /* if a dimm is disabled the available capacity is zero */ |
| 374 | if (!ndd) |
| 375 | return 0; |
| 376 | |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 377 | if (is_memory(&nd_region->dev)) { |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 378 | available += nd_pmem_available_dpa(nd_region, |
| 379 | nd_mapping, &overlap); |
| 380 | if (overlap > blk_max_overlap) { |
| 381 | blk_max_overlap = overlap; |
| 382 | goto retry; |
| 383 | } |
Dan Williams | a1f3e4d | 2016-09-30 17:28:58 -0700 | [diff] [blame] | 384 | } else if (is_nd_blk(&nd_region->dev)) |
| 385 | available += nd_blk_available_dpa(nd_region); |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | return available; |
| 389 | } |
| 390 | |
Keith Busch | 12e3129 | 2018-07-24 15:07:57 -0600 | [diff] [blame] | 391 | resource_size_t nd_region_allocatable_dpa(struct nd_region *nd_region) |
| 392 | { |
| 393 | resource_size_t available = 0; |
| 394 | int i; |
| 395 | |
| 396 | if (is_memory(&nd_region->dev)) |
| 397 | available = PHYS_ADDR_MAX; |
| 398 | |
| 399 | WARN_ON(!is_nvdimm_bus_locked(&nd_region->dev)); |
| 400 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
| 401 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
| 402 | |
| 403 | if (is_memory(&nd_region->dev)) |
| 404 | available = min(available, |
| 405 | nd_pmem_max_contiguous_dpa(nd_region, |
| 406 | nd_mapping)); |
| 407 | else if (is_nd_blk(&nd_region->dev)) |
| 408 | available += nd_blk_available_dpa(nd_region); |
| 409 | } |
| 410 | if (is_memory(&nd_region->dev)) |
| 411 | return available * nd_region->ndr_mappings; |
| 412 | return available; |
| 413 | } |
| 414 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 415 | static ssize_t available_size_show(struct device *dev, |
| 416 | struct device_attribute *attr, char *buf) |
| 417 | { |
| 418 | struct nd_region *nd_region = to_nd_region(dev); |
| 419 | unsigned long long available = 0; |
| 420 | |
| 421 | /* |
| 422 | * Flush in-flight updates and grab a snapshot of the available |
| 423 | * size. Of course, this value is potentially invalidated the |
| 424 | * memory nvdimm_bus_lock() is dropped, but that's userspace's |
| 425 | * problem to not race itself. |
| 426 | */ |
| 427 | nvdimm_bus_lock(dev); |
| 428 | wait_nvdimm_bus_probe_idle(dev); |
| 429 | available = nd_region_available_dpa(nd_region); |
| 430 | nvdimm_bus_unlock(dev); |
| 431 | |
| 432 | return sprintf(buf, "%llu\n", available); |
| 433 | } |
| 434 | static DEVICE_ATTR_RO(available_size); |
| 435 | |
Keith Busch | 1e68722 | 2018-07-24 15:07:58 -0600 | [diff] [blame] | 436 | static ssize_t max_available_extent_show(struct device *dev, |
| 437 | struct device_attribute *attr, char *buf) |
| 438 | { |
| 439 | struct nd_region *nd_region = to_nd_region(dev); |
| 440 | unsigned long long available = 0; |
| 441 | |
| 442 | nvdimm_bus_lock(dev); |
| 443 | wait_nvdimm_bus_probe_idle(dev); |
| 444 | available = nd_region_allocatable_dpa(nd_region); |
| 445 | nvdimm_bus_unlock(dev); |
| 446 | |
| 447 | return sprintf(buf, "%llu\n", available); |
| 448 | } |
| 449 | static DEVICE_ATTR_RO(max_available_extent); |
| 450 | |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 451 | static ssize_t init_namespaces_show(struct device *dev, |
| 452 | struct device_attribute *attr, char *buf) |
| 453 | { |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 454 | struct nd_region_data *ndrd = dev_get_drvdata(dev); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 455 | ssize_t rc; |
| 456 | |
| 457 | nvdimm_bus_lock(dev); |
Dan Williams | e5ae3b2 | 2016-06-07 17:00:04 -0700 | [diff] [blame] | 458 | if (ndrd) |
| 459 | rc = sprintf(buf, "%d/%d\n", ndrd->ns_active, ndrd->ns_count); |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 460 | else |
| 461 | rc = -ENXIO; |
| 462 | nvdimm_bus_unlock(dev); |
| 463 | |
| 464 | return rc; |
| 465 | } |
| 466 | static DEVICE_ATTR_RO(init_namespaces); |
| 467 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 468 | static ssize_t namespace_seed_show(struct device *dev, |
| 469 | struct device_attribute *attr, char *buf) |
| 470 | { |
| 471 | struct nd_region *nd_region = to_nd_region(dev); |
| 472 | ssize_t rc; |
| 473 | |
| 474 | nvdimm_bus_lock(dev); |
| 475 | if (nd_region->ns_seed) |
| 476 | rc = sprintf(buf, "%s\n", dev_name(nd_region->ns_seed)); |
| 477 | else |
| 478 | rc = sprintf(buf, "\n"); |
| 479 | nvdimm_bus_unlock(dev); |
| 480 | return rc; |
| 481 | } |
| 482 | static DEVICE_ATTR_RO(namespace_seed); |
| 483 | |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 484 | static ssize_t btt_seed_show(struct device *dev, |
| 485 | struct device_attribute *attr, char *buf) |
| 486 | { |
| 487 | struct nd_region *nd_region = to_nd_region(dev); |
| 488 | ssize_t rc; |
| 489 | |
| 490 | nvdimm_bus_lock(dev); |
| 491 | if (nd_region->btt_seed) |
| 492 | rc = sprintf(buf, "%s\n", dev_name(nd_region->btt_seed)); |
| 493 | else |
| 494 | rc = sprintf(buf, "\n"); |
| 495 | nvdimm_bus_unlock(dev); |
| 496 | |
| 497 | return rc; |
| 498 | } |
| 499 | static DEVICE_ATTR_RO(btt_seed); |
| 500 | |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 501 | static ssize_t pfn_seed_show(struct device *dev, |
| 502 | struct device_attribute *attr, char *buf) |
| 503 | { |
| 504 | struct nd_region *nd_region = to_nd_region(dev); |
| 505 | ssize_t rc; |
| 506 | |
| 507 | nvdimm_bus_lock(dev); |
| 508 | if (nd_region->pfn_seed) |
| 509 | rc = sprintf(buf, "%s\n", dev_name(nd_region->pfn_seed)); |
| 510 | else |
| 511 | rc = sprintf(buf, "\n"); |
| 512 | nvdimm_bus_unlock(dev); |
| 513 | |
| 514 | return rc; |
| 515 | } |
| 516 | static DEVICE_ATTR_RO(pfn_seed); |
| 517 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 518 | static ssize_t dax_seed_show(struct device *dev, |
| 519 | struct device_attribute *attr, char *buf) |
| 520 | { |
| 521 | struct nd_region *nd_region = to_nd_region(dev); |
| 522 | ssize_t rc; |
| 523 | |
| 524 | nvdimm_bus_lock(dev); |
| 525 | if (nd_region->dax_seed) |
| 526 | rc = sprintf(buf, "%s\n", dev_name(nd_region->dax_seed)); |
| 527 | else |
| 528 | rc = sprintf(buf, "\n"); |
| 529 | nvdimm_bus_unlock(dev); |
| 530 | |
| 531 | return rc; |
| 532 | } |
| 533 | static DEVICE_ATTR_RO(dax_seed); |
| 534 | |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 535 | static ssize_t read_only_show(struct device *dev, |
| 536 | struct device_attribute *attr, char *buf) |
| 537 | { |
| 538 | struct nd_region *nd_region = to_nd_region(dev); |
| 539 | |
| 540 | return sprintf(buf, "%d\n", nd_region->ro); |
| 541 | } |
| 542 | |
| 543 | static ssize_t read_only_store(struct device *dev, |
| 544 | struct device_attribute *attr, const char *buf, size_t len) |
| 545 | { |
| 546 | bool ro; |
| 547 | int rc = strtobool(buf, &ro); |
| 548 | struct nd_region *nd_region = to_nd_region(dev); |
| 549 | |
| 550 | if (rc) |
| 551 | return rc; |
| 552 | |
| 553 | nd_region->ro = ro; |
| 554 | return len; |
| 555 | } |
| 556 | static DEVICE_ATTR_RW(read_only); |
| 557 | |
Dan Williams | 23f4984 | 2017-04-29 15:24:03 -0700 | [diff] [blame] | 558 | static ssize_t region_badblocks_show(struct device *dev, |
Dave Jiang | 6a6bef9 | 2017-04-07 15:33:20 -0700 | [diff] [blame] | 559 | struct device_attribute *attr, char *buf) |
| 560 | { |
| 561 | struct nd_region *nd_region = to_nd_region(dev); |
Dan Williams | 5d394ee | 2018-09-27 15:01:55 -0700 | [diff] [blame] | 562 | ssize_t rc; |
Dave Jiang | 6a6bef9 | 2017-04-07 15:33:20 -0700 | [diff] [blame] | 563 | |
Dan Williams | 5d394ee | 2018-09-27 15:01:55 -0700 | [diff] [blame] | 564 | device_lock(dev); |
| 565 | if (dev->driver) |
| 566 | rc = badblocks_show(&nd_region->bb, buf, 0); |
| 567 | else |
| 568 | rc = -ENXIO; |
| 569 | device_unlock(dev); |
| 570 | |
| 571 | return rc; |
Dave Jiang | 6a6bef9 | 2017-04-07 15:33:20 -0700 | [diff] [blame] | 572 | } |
Dan Williams | 23f4984 | 2017-04-29 15:24:03 -0700 | [diff] [blame] | 573 | static DEVICE_ATTR(badblocks, 0444, region_badblocks_show, NULL); |
Dave Jiang | 6a6bef9 | 2017-04-07 15:33:20 -0700 | [diff] [blame] | 574 | |
Dave Jiang | 802f4be | 2017-04-07 15:33:25 -0700 | [diff] [blame] | 575 | static ssize_t resource_show(struct device *dev, |
| 576 | struct device_attribute *attr, char *buf) |
| 577 | { |
| 578 | struct nd_region *nd_region = to_nd_region(dev); |
| 579 | |
| 580 | return sprintf(buf, "%#llx\n", nd_region->ndr_start); |
| 581 | } |
| 582 | static DEVICE_ATTR_RO(resource); |
| 583 | |
Dave Jiang | 96c3a23 | 2018-01-31 12:45:49 -0700 | [diff] [blame] | 584 | static ssize_t persistence_domain_show(struct device *dev, |
| 585 | struct device_attribute *attr, char *buf) |
| 586 | { |
| 587 | struct nd_region *nd_region = to_nd_region(dev); |
Dave Jiang | 96c3a23 | 2018-01-31 12:45:49 -0700 | [diff] [blame] | 588 | |
Dan Williams | fe9a552 | 2018-03-21 15:12:07 -0700 | [diff] [blame] | 589 | if (test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags)) |
| 590 | return sprintf(buf, "cpu_cache\n"); |
| 591 | else if (test_bit(ND_REGION_PERSIST_MEMCTRL, &nd_region->flags)) |
| 592 | return sprintf(buf, "memory_controller\n"); |
| 593 | else |
| 594 | return sprintf(buf, "\n"); |
Dave Jiang | 96c3a23 | 2018-01-31 12:45:49 -0700 | [diff] [blame] | 595 | } |
| 596 | static DEVICE_ATTR_RO(persistence_domain); |
| 597 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 598 | static struct attribute *nd_region_attributes[] = { |
| 599 | &dev_attr_size.attr, |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 600 | &dev_attr_nstype.attr, |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 601 | &dev_attr_mappings.attr, |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 602 | &dev_attr_btt_seed.attr, |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 603 | &dev_attr_pfn_seed.attr, |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 604 | &dev_attr_dax_seed.attr, |
Dan Williams | ab63089 | 2017-04-21 13:28:12 -0700 | [diff] [blame] | 605 | &dev_attr_deep_flush.attr, |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 606 | &dev_attr_read_only.attr, |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 607 | &dev_attr_set_cookie.attr, |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 608 | &dev_attr_available_size.attr, |
Keith Busch | 1e68722 | 2018-07-24 15:07:58 -0600 | [diff] [blame] | 609 | &dev_attr_max_available_extent.attr, |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 610 | &dev_attr_namespace_seed.attr, |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 611 | &dev_attr_init_namespaces.attr, |
Dan Williams | 23f4984 | 2017-04-29 15:24:03 -0700 | [diff] [blame] | 612 | &dev_attr_badblocks.attr, |
Dave Jiang | 802f4be | 2017-04-07 15:33:25 -0700 | [diff] [blame] | 613 | &dev_attr_resource.attr, |
Dave Jiang | 96c3a23 | 2018-01-31 12:45:49 -0700 | [diff] [blame] | 614 | &dev_attr_persistence_domain.attr, |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 615 | NULL, |
| 616 | }; |
| 617 | |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 618 | static umode_t region_visible(struct kobject *kobj, struct attribute *a, int n) |
| 619 | { |
| 620 | struct device *dev = container_of(kobj, typeof(*dev), kobj); |
| 621 | struct nd_region *nd_region = to_nd_region(dev); |
| 622 | struct nd_interleave_set *nd_set = nd_region->nd_set; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 623 | int type = nd_region_to_nstype(nd_region); |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 624 | |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 625 | if (!is_memory(dev) && a == &dev_attr_pfn_seed.attr) |
Dmitry Krivenok | 6bb691a | 2015-12-02 09:39:29 +0300 | [diff] [blame] | 626 | return 0; |
| 627 | |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 628 | if (!is_memory(dev) && a == &dev_attr_dax_seed.attr) |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 629 | return 0; |
| 630 | |
Dan Williams | 23f4984 | 2017-04-29 15:24:03 -0700 | [diff] [blame] | 631 | if (!is_nd_pmem(dev) && a == &dev_attr_badblocks.attr) |
Dave Jiang | 6a6bef9 | 2017-04-07 15:33:20 -0700 | [diff] [blame] | 632 | return 0; |
| 633 | |
Dan Williams | b8ff981 | 2017-09-26 11:17:52 -0700 | [diff] [blame] | 634 | if (a == &dev_attr_resource.attr) { |
| 635 | if (is_nd_pmem(dev)) |
| 636 | return 0400; |
| 637 | else |
| 638 | return 0; |
| 639 | } |
Dave Jiang | 802f4be | 2017-04-07 15:33:25 -0700 | [diff] [blame] | 640 | |
Dan Williams | ab63089 | 2017-04-21 13:28:12 -0700 | [diff] [blame] | 641 | if (a == &dev_attr_deep_flush.attr) { |
| 642 | int has_flush = nvdimm_has_flush(nd_region); |
| 643 | |
| 644 | if (has_flush == 1) |
| 645 | return a->mode; |
| 646 | else if (has_flush == 0) |
| 647 | return 0444; |
| 648 | else |
| 649 | return 0; |
| 650 | } |
| 651 | |
Dan Williams | 896196dc | 2018-03-21 14:06:23 -0700 | [diff] [blame] | 652 | if (a == &dev_attr_persistence_domain.attr) { |
| 653 | if ((nd_region->flags & (BIT(ND_REGION_PERSIST_CACHE) |
| 654 | | BIT(ND_REGION_PERSIST_MEMCTRL))) == 0) |
| 655 | return 0; |
| 656 | return a->mode; |
| 657 | } |
| 658 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 659 | if (a != &dev_attr_set_cookie.attr |
| 660 | && a != &dev_attr_available_size.attr) |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 661 | return a->mode; |
| 662 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 663 | if ((type == ND_DEVICE_NAMESPACE_PMEM |
| 664 | || type == ND_DEVICE_NAMESPACE_BLK) |
| 665 | && a == &dev_attr_available_size.attr) |
| 666 | return a->mode; |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 667 | else if (is_memory(dev) && nd_set) |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 668 | return a->mode; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 669 | |
| 670 | return 0; |
| 671 | } |
| 672 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 673 | struct attribute_group nd_region_attribute_group = { |
| 674 | .attrs = nd_region_attributes, |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 675 | .is_visible = region_visible, |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 676 | }; |
| 677 | EXPORT_SYMBOL_GPL(nd_region_attribute_group); |
| 678 | |
Dan Williams | c12c48c | 2017-06-04 10:59:15 +0900 | [diff] [blame] | 679 | u64 nd_region_interleave_set_cookie(struct nd_region *nd_region, |
| 680 | struct nd_namespace_index *nsindex) |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 681 | { |
| 682 | struct nd_interleave_set *nd_set = nd_region->nd_set; |
| 683 | |
Dan Williams | c12c48c | 2017-06-04 10:59:15 +0900 | [diff] [blame] | 684 | if (!nd_set) |
| 685 | return 0; |
| 686 | |
| 687 | if (nsindex && __le16_to_cpu(nsindex->major) == 1 |
| 688 | && __le16_to_cpu(nsindex->minor) == 1) |
| 689 | return nd_set->cookie1; |
| 690 | return nd_set->cookie2; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 691 | } |
| 692 | |
Dan Williams | 86ef58a | 2017-02-28 18:32:48 -0800 | [diff] [blame] | 693 | u64 nd_region_interleave_set_altcookie(struct nd_region *nd_region) |
| 694 | { |
| 695 | struct nd_interleave_set *nd_set = nd_region->nd_set; |
| 696 | |
| 697 | if (nd_set) |
| 698 | return nd_set->altcookie; |
| 699 | return 0; |
| 700 | } |
| 701 | |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 702 | void nd_mapping_free_labels(struct nd_mapping *nd_mapping) |
| 703 | { |
| 704 | struct nd_label_ent *label_ent, *e; |
| 705 | |
Dan Williams | 9cf8bd5 | 2016-12-15 20:04:31 -0800 | [diff] [blame] | 706 | lockdep_assert_held(&nd_mapping->lock); |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 707 | list_for_each_entry_safe(label_ent, e, &nd_mapping->labels, list) { |
| 708 | list_del(&label_ent->list); |
| 709 | kfree(label_ent); |
| 710 | } |
| 711 | } |
| 712 | |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 713 | /* |
| 714 | * Upon successful probe/remove, take/release a reference on the |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 715 | * associated interleave set (if present), and plant new btt + namespace |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 716 | * seeds. Also, on the removal of a BLK region, notify the provider to |
| 717 | * disable the region. |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 718 | */ |
| 719 | static void nd_region_notify_driver_action(struct nvdimm_bus *nvdimm_bus, |
| 720 | struct device *dev, bool probe) |
| 721 | { |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 722 | struct nd_region *nd_region; |
| 723 | |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 724 | if (!probe && is_nd_region(dev)) { |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 725 | int i; |
| 726 | |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 727 | nd_region = to_nd_region(dev); |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 728 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
| 729 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 730 | struct nvdimm_drvdata *ndd = nd_mapping->ndd; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 731 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
| 732 | |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 733 | mutex_lock(&nd_mapping->lock); |
| 734 | nd_mapping_free_labels(nd_mapping); |
| 735 | mutex_unlock(&nd_mapping->lock); |
| 736 | |
Dan Williams | bf9bccc | 2015-06-17 17:14:46 -0400 | [diff] [blame] | 737 | put_ndd(ndd); |
| 738 | nd_mapping->ndd = NULL; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 739 | if (ndd) |
| 740 | atomic_dec(&nvdimm->busy); |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 741 | } |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 742 | } |
Dan Williams | c9e582a | 2017-05-29 23:12:19 -0700 | [diff] [blame] | 743 | if (dev->parent && is_nd_region(dev->parent) && probe) { |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 744 | nd_region = to_nd_region(dev->parent); |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 745 | nvdimm_bus_lock(dev); |
| 746 | if (nd_region->ns_seed == dev) |
Dan Williams | 98a29c3 | 2016-09-30 15:28:27 -0700 | [diff] [blame] | 747 | nd_region_create_ns_seed(nd_region); |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 748 | nvdimm_bus_unlock(dev); |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 749 | } |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 750 | if (is_nd_btt(dev) && probe) { |
Dan Williams | 8ca2435 | 2015-07-24 23:42:34 -0400 | [diff] [blame] | 751 | struct nd_btt *nd_btt = to_nd_btt(dev); |
| 752 | |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 753 | nd_region = to_nd_region(dev->parent); |
| 754 | nvdimm_bus_lock(dev); |
| 755 | if (nd_region->btt_seed == dev) |
| 756 | nd_region_create_btt_seed(nd_region); |
Dan Williams | 98a29c3 | 2016-09-30 15:28:27 -0700 | [diff] [blame] | 757 | if (nd_region->ns_seed == &nd_btt->ndns->dev) |
| 758 | nd_region_create_ns_seed(nd_region); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 759 | nvdimm_bus_unlock(dev); |
| 760 | } |
Dan Williams | 2dc4333 | 2015-12-13 11:41:36 -0800 | [diff] [blame] | 761 | if (is_nd_pfn(dev) && probe) { |
Dan Williams | 98a29c3 | 2016-09-30 15:28:27 -0700 | [diff] [blame] | 762 | struct nd_pfn *nd_pfn = to_nd_pfn(dev); |
| 763 | |
Dan Williams | 2dc4333 | 2015-12-13 11:41:36 -0800 | [diff] [blame] | 764 | nd_region = to_nd_region(dev->parent); |
| 765 | nvdimm_bus_lock(dev); |
| 766 | if (nd_region->pfn_seed == dev) |
| 767 | nd_region_create_pfn_seed(nd_region); |
Dan Williams | 98a29c3 | 2016-09-30 15:28:27 -0700 | [diff] [blame] | 768 | if (nd_region->ns_seed == &nd_pfn->ndns->dev) |
| 769 | nd_region_create_ns_seed(nd_region); |
Dan Williams | 2dc4333 | 2015-12-13 11:41:36 -0800 | [diff] [blame] | 770 | nvdimm_bus_unlock(dev); |
| 771 | } |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 772 | if (is_nd_dax(dev) && probe) { |
Dan Williams | 98a29c3 | 2016-09-30 15:28:27 -0700 | [diff] [blame] | 773 | struct nd_dax *nd_dax = to_nd_dax(dev); |
| 774 | |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 775 | nd_region = to_nd_region(dev->parent); |
| 776 | nvdimm_bus_lock(dev); |
| 777 | if (nd_region->dax_seed == dev) |
| 778 | nd_region_create_dax_seed(nd_region); |
Dan Williams | 98a29c3 | 2016-09-30 15:28:27 -0700 | [diff] [blame] | 779 | if (nd_region->ns_seed == &nd_dax->nd_pfn.ndns->dev) |
| 780 | nd_region_create_ns_seed(nd_region); |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 781 | nvdimm_bus_unlock(dev); |
| 782 | } |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 783 | } |
| 784 | |
| 785 | void nd_region_probe_success(struct nvdimm_bus *nvdimm_bus, struct device *dev) |
| 786 | { |
| 787 | nd_region_notify_driver_action(nvdimm_bus, dev, true); |
| 788 | } |
| 789 | |
| 790 | void nd_region_disable(struct nvdimm_bus *nvdimm_bus, struct device *dev) |
| 791 | { |
| 792 | nd_region_notify_driver_action(nvdimm_bus, dev, false); |
| 793 | } |
| 794 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 795 | static ssize_t mappingN(struct device *dev, char *buf, int n) |
| 796 | { |
| 797 | struct nd_region *nd_region = to_nd_region(dev); |
| 798 | struct nd_mapping *nd_mapping; |
| 799 | struct nvdimm *nvdimm; |
| 800 | |
| 801 | if (n >= nd_region->ndr_mappings) |
| 802 | return -ENXIO; |
| 803 | nd_mapping = &nd_region->mapping[n]; |
| 804 | nvdimm = nd_mapping->nvdimm; |
| 805 | |
Dan Williams | 401c0a1 | 2017-08-04 17:20:16 -0700 | [diff] [blame] | 806 | return sprintf(buf, "%s,%llu,%llu,%d\n", dev_name(&nvdimm->dev), |
| 807 | nd_mapping->start, nd_mapping->size, |
| 808 | nd_mapping->position); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 809 | } |
| 810 | |
| 811 | #define REGION_MAPPING(idx) \ |
| 812 | static ssize_t mapping##idx##_show(struct device *dev, \ |
| 813 | struct device_attribute *attr, char *buf) \ |
| 814 | { \ |
| 815 | return mappingN(dev, buf, idx); \ |
| 816 | } \ |
| 817 | static DEVICE_ATTR_RO(mapping##idx) |
| 818 | |
| 819 | /* |
| 820 | * 32 should be enough for a while, even in the presence of socket |
| 821 | * interleave a 32-way interleave set is a degenerate case. |
| 822 | */ |
| 823 | REGION_MAPPING(0); |
| 824 | REGION_MAPPING(1); |
| 825 | REGION_MAPPING(2); |
| 826 | REGION_MAPPING(3); |
| 827 | REGION_MAPPING(4); |
| 828 | REGION_MAPPING(5); |
| 829 | REGION_MAPPING(6); |
| 830 | REGION_MAPPING(7); |
| 831 | REGION_MAPPING(8); |
| 832 | REGION_MAPPING(9); |
| 833 | REGION_MAPPING(10); |
| 834 | REGION_MAPPING(11); |
| 835 | REGION_MAPPING(12); |
| 836 | REGION_MAPPING(13); |
| 837 | REGION_MAPPING(14); |
| 838 | REGION_MAPPING(15); |
| 839 | REGION_MAPPING(16); |
| 840 | REGION_MAPPING(17); |
| 841 | REGION_MAPPING(18); |
| 842 | REGION_MAPPING(19); |
| 843 | REGION_MAPPING(20); |
| 844 | REGION_MAPPING(21); |
| 845 | REGION_MAPPING(22); |
| 846 | REGION_MAPPING(23); |
| 847 | REGION_MAPPING(24); |
| 848 | REGION_MAPPING(25); |
| 849 | REGION_MAPPING(26); |
| 850 | REGION_MAPPING(27); |
| 851 | REGION_MAPPING(28); |
| 852 | REGION_MAPPING(29); |
| 853 | REGION_MAPPING(30); |
| 854 | REGION_MAPPING(31); |
| 855 | |
| 856 | static umode_t mapping_visible(struct kobject *kobj, struct attribute *a, int n) |
| 857 | { |
| 858 | struct device *dev = container_of(kobj, struct device, kobj); |
| 859 | struct nd_region *nd_region = to_nd_region(dev); |
| 860 | |
| 861 | if (n < nd_region->ndr_mappings) |
| 862 | return a->mode; |
| 863 | return 0; |
| 864 | } |
| 865 | |
| 866 | static struct attribute *mapping_attributes[] = { |
| 867 | &dev_attr_mapping0.attr, |
| 868 | &dev_attr_mapping1.attr, |
| 869 | &dev_attr_mapping2.attr, |
| 870 | &dev_attr_mapping3.attr, |
| 871 | &dev_attr_mapping4.attr, |
| 872 | &dev_attr_mapping5.attr, |
| 873 | &dev_attr_mapping6.attr, |
| 874 | &dev_attr_mapping7.attr, |
| 875 | &dev_attr_mapping8.attr, |
| 876 | &dev_attr_mapping9.attr, |
| 877 | &dev_attr_mapping10.attr, |
| 878 | &dev_attr_mapping11.attr, |
| 879 | &dev_attr_mapping12.attr, |
| 880 | &dev_attr_mapping13.attr, |
| 881 | &dev_attr_mapping14.attr, |
| 882 | &dev_attr_mapping15.attr, |
| 883 | &dev_attr_mapping16.attr, |
| 884 | &dev_attr_mapping17.attr, |
| 885 | &dev_attr_mapping18.attr, |
| 886 | &dev_attr_mapping19.attr, |
| 887 | &dev_attr_mapping20.attr, |
| 888 | &dev_attr_mapping21.attr, |
| 889 | &dev_attr_mapping22.attr, |
| 890 | &dev_attr_mapping23.attr, |
| 891 | &dev_attr_mapping24.attr, |
| 892 | &dev_attr_mapping25.attr, |
| 893 | &dev_attr_mapping26.attr, |
| 894 | &dev_attr_mapping27.attr, |
| 895 | &dev_attr_mapping28.attr, |
| 896 | &dev_attr_mapping29.attr, |
| 897 | &dev_attr_mapping30.attr, |
| 898 | &dev_attr_mapping31.attr, |
| 899 | NULL, |
| 900 | }; |
| 901 | |
| 902 | struct attribute_group nd_mapping_attribute_group = { |
| 903 | .is_visible = mapping_visible, |
| 904 | .attrs = mapping_attributes, |
| 905 | }; |
| 906 | EXPORT_SYMBOL_GPL(nd_mapping_attribute_group); |
| 907 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 908 | int nd_blk_region_init(struct nd_region *nd_region) |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 909 | { |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 910 | struct device *dev = &nd_region->dev; |
| 911 | struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(dev); |
| 912 | |
| 913 | if (!is_nd_blk(dev)) |
| 914 | return 0; |
| 915 | |
| 916 | if (nd_region->ndr_mappings < 1) { |
Dan Williams | d5d51fe | 2017-06-29 09:02:10 -0700 | [diff] [blame] | 917 | dev_dbg(dev, "invalid BLK region\n"); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 918 | return -ENXIO; |
| 919 | } |
| 920 | |
| 921 | return to_nd_blk_region(dev)->enable(nvdimm_bus, dev); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 922 | } |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 923 | |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 924 | /** |
| 925 | * nd_region_acquire_lane - allocate and lock a lane |
| 926 | * @nd_region: region id and number of lanes possible |
| 927 | * |
| 928 | * A lane correlates to a BLK-data-window and/or a log slot in the BTT. |
| 929 | * We optimize for the common case where there are 256 lanes, one |
| 930 | * per-cpu. For larger systems we need to lock to share lanes. For now |
| 931 | * this implementation assumes the cost of maintaining an allocator for |
| 932 | * free lanes is on the order of the lock hold time, so it implements a |
| 933 | * static lane = cpu % num_lanes mapping. |
| 934 | * |
| 935 | * In the case of a BTT instance on top of a BLK namespace a lane may be |
| 936 | * acquired recursively. We lock on the first instance. |
| 937 | * |
| 938 | * In the case of a BTT instance on top of PMEM, we only acquire a lane |
| 939 | * for the BTT metadata updates. |
| 940 | */ |
| 941 | unsigned int nd_region_acquire_lane(struct nd_region *nd_region) |
| 942 | { |
| 943 | unsigned int cpu, lane; |
| 944 | |
| 945 | cpu = get_cpu(); |
| 946 | if (nd_region->num_lanes < nr_cpu_ids) { |
| 947 | struct nd_percpu_lane *ndl_lock, *ndl_count; |
| 948 | |
| 949 | lane = cpu % nd_region->num_lanes; |
| 950 | ndl_count = per_cpu_ptr(nd_region->lane, cpu); |
| 951 | ndl_lock = per_cpu_ptr(nd_region->lane, lane); |
| 952 | if (ndl_count->count++ == 0) |
| 953 | spin_lock(&ndl_lock->lock); |
| 954 | } else |
| 955 | lane = cpu; |
| 956 | |
| 957 | return lane; |
| 958 | } |
| 959 | EXPORT_SYMBOL(nd_region_acquire_lane); |
| 960 | |
| 961 | void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) |
| 962 | { |
| 963 | if (nd_region->num_lanes < nr_cpu_ids) { |
| 964 | unsigned int cpu = get_cpu(); |
| 965 | struct nd_percpu_lane *ndl_lock, *ndl_count; |
| 966 | |
| 967 | ndl_count = per_cpu_ptr(nd_region->lane, cpu); |
| 968 | ndl_lock = per_cpu_ptr(nd_region->lane, lane); |
| 969 | if (--ndl_count->count == 0) |
| 970 | spin_unlock(&ndl_lock->lock); |
| 971 | put_cpu(); |
| 972 | } |
| 973 | put_cpu(); |
| 974 | } |
| 975 | EXPORT_SYMBOL(nd_region_release_lane); |
| 976 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 977 | static struct nd_region *nd_region_create(struct nvdimm_bus *nvdimm_bus, |
| 978 | struct nd_region_desc *ndr_desc, struct device_type *dev_type, |
| 979 | const char *caller) |
| 980 | { |
| 981 | struct nd_region *nd_region; |
| 982 | struct device *dev; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 983 | void *region_buf; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 984 | unsigned int i; |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 985 | int ro = 0; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 986 | |
| 987 | for (i = 0; i < ndr_desc->num_mappings; i++) { |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 988 | struct nd_mapping_desc *mapping = &ndr_desc->mapping[i]; |
| 989 | struct nvdimm *nvdimm = mapping->nvdimm; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 990 | |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 991 | if ((mapping->start | mapping->size) % SZ_4K) { |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 992 | dev_err(&nvdimm_bus->dev, "%s: %s mapping%d is not 4K aligned\n", |
| 993 | caller, dev_name(&nvdimm->dev), i); |
| 994 | |
| 995 | return NULL; |
| 996 | } |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 997 | |
Dan Williams | 8f078b3 | 2017-05-04 14:01:24 -0700 | [diff] [blame] | 998 | if (test_bit(NDD_UNARMED, &nvdimm->flags)) |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 999 | ro = 1; |
Dan Williams | d5d30d5 | 2019-02-02 16:35:26 -0800 | [diff] [blame] | 1000 | |
| 1001 | if (test_bit(NDD_NOBLK, &nvdimm->flags) |
| 1002 | && dev_type == &nd_blk_device_type) { |
| 1003 | dev_err(&nvdimm_bus->dev, "%s: %s mapping%d is not BLK capable\n", |
| 1004 | caller, dev_name(&nvdimm->dev), i); |
| 1005 | return NULL; |
| 1006 | } |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1007 | } |
| 1008 | |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 1009 | if (dev_type == &nd_blk_device_type) { |
| 1010 | struct nd_blk_region_desc *ndbr_desc; |
| 1011 | struct nd_blk_region *ndbr; |
| 1012 | |
| 1013 | ndbr_desc = to_blk_region_desc(ndr_desc); |
| 1014 | ndbr = kzalloc(sizeof(*ndbr) + sizeof(struct nd_mapping) |
| 1015 | * ndr_desc->num_mappings, |
| 1016 | GFP_KERNEL); |
| 1017 | if (ndbr) { |
| 1018 | nd_region = &ndbr->nd_region; |
| 1019 | ndbr->enable = ndbr_desc->enable; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 1020 | ndbr->do_io = ndbr_desc->do_io; |
| 1021 | } |
| 1022 | region_buf = ndbr; |
| 1023 | } else { |
| 1024 | nd_region = kzalloc(sizeof(struct nd_region) |
| 1025 | + sizeof(struct nd_mapping) |
| 1026 | * ndr_desc->num_mappings, |
| 1027 | GFP_KERNEL); |
| 1028 | region_buf = nd_region; |
| 1029 | } |
| 1030 | |
| 1031 | if (!region_buf) |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1032 | return NULL; |
| 1033 | nd_region->id = ida_simple_get(®ion_ida, 0, 0, GFP_KERNEL); |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 1034 | if (nd_region->id < 0) |
| 1035 | goto err_id; |
| 1036 | |
| 1037 | nd_region->lane = alloc_percpu(struct nd_percpu_lane); |
| 1038 | if (!nd_region->lane) |
| 1039 | goto err_percpu; |
| 1040 | |
| 1041 | for (i = 0; i < nr_cpu_ids; i++) { |
| 1042 | struct nd_percpu_lane *ndl; |
| 1043 | |
| 1044 | ndl = per_cpu_ptr(nd_region->lane, i); |
| 1045 | spin_lock_init(&ndl->lock); |
| 1046 | ndl->count = 0; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1047 | } |
| 1048 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1049 | for (i = 0; i < ndr_desc->num_mappings; i++) { |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 1050 | struct nd_mapping_desc *mapping = &ndr_desc->mapping[i]; |
| 1051 | struct nvdimm *nvdimm = mapping->nvdimm; |
| 1052 | |
| 1053 | nd_region->mapping[i].nvdimm = nvdimm; |
| 1054 | nd_region->mapping[i].start = mapping->start; |
| 1055 | nd_region->mapping[i].size = mapping->size; |
Dan Williams | 401c0a1 | 2017-08-04 17:20:16 -0700 | [diff] [blame] | 1056 | nd_region->mapping[i].position = mapping->position; |
Dan Williams | ae8219f | 2016-09-19 16:04:21 -0700 | [diff] [blame] | 1057 | INIT_LIST_HEAD(&nd_region->mapping[i].labels); |
| 1058 | mutex_init(&nd_region->mapping[i].lock); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1059 | |
| 1060 | get_device(&nvdimm->dev); |
| 1061 | } |
| 1062 | nd_region->ndr_mappings = ndr_desc->num_mappings; |
| 1063 | nd_region->provider_data = ndr_desc->provider_data; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 1064 | nd_region->nd_set = ndr_desc->nd_set; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 1065 | nd_region->num_lanes = ndr_desc->num_lanes; |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 1066 | nd_region->flags = ndr_desc->flags; |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 1067 | nd_region->ro = ro; |
Toshi Kani | 41d7a6d | 2015-06-19 12:18:33 -0600 | [diff] [blame] | 1068 | nd_region->numa_node = ndr_desc->numa_node; |
Dan Williams | 8fc5c73 | 2018-11-09 12:43:07 -0800 | [diff] [blame] | 1069 | nd_region->target_node = ndr_desc->target_node; |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 1070 | ida_init(&nd_region->ns_ida); |
Dan Williams | 8c2f7e8 | 2015-06-25 04:20:04 -0400 | [diff] [blame] | 1071 | ida_init(&nd_region->btt_ida); |
Dan Williams | e145574 | 2015-07-30 17:57:47 -0400 | [diff] [blame] | 1072 | ida_init(&nd_region->pfn_ida); |
Dan Williams | cd03412 | 2016-03-11 10:15:36 -0800 | [diff] [blame] | 1073 | ida_init(&nd_region->dax_ida); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1074 | dev = &nd_region->dev; |
| 1075 | dev_set_name(dev, "region%d", nd_region->id); |
| 1076 | dev->parent = &nvdimm_bus->dev; |
| 1077 | dev->type = dev_type; |
| 1078 | dev->groups = ndr_desc->attr_groups; |
Oliver O'Halloran | 1ff19f4 | 2018-04-06 15:21:13 +1000 | [diff] [blame] | 1079 | dev->of_node = ndr_desc->of_node; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1080 | nd_region->ndr_size = resource_size(ndr_desc->res); |
| 1081 | nd_region->ndr_start = ndr_desc->res->start; |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 1082 | if (ndr_desc->flush) |
| 1083 | nd_region->flush = ndr_desc->flush; |
| 1084 | else |
| 1085 | nd_region->flush = NULL; |
| 1086 | |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1087 | nd_device_register(dev); |
| 1088 | |
| 1089 | return nd_region; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 1090 | |
| 1091 | err_percpu: |
| 1092 | ida_simple_remove(®ion_ida, nd_region->id); |
| 1093 | err_id: |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 1094 | kfree(region_buf); |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 1095 | return NULL; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1096 | } |
| 1097 | |
| 1098 | struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, |
| 1099 | struct nd_region_desc *ndr_desc) |
| 1100 | { |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 1101 | ndr_desc->num_lanes = ND_MAX_LANES; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1102 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_pmem_device_type, |
| 1103 | __func__); |
| 1104 | } |
| 1105 | EXPORT_SYMBOL_GPL(nvdimm_pmem_region_create); |
| 1106 | |
| 1107 | struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, |
| 1108 | struct nd_region_desc *ndr_desc) |
| 1109 | { |
| 1110 | if (ndr_desc->num_mappings > 1) |
| 1111 | return NULL; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 1112 | ndr_desc->num_lanes = min(ndr_desc->num_lanes, ND_MAX_LANES); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1113 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_blk_device_type, |
| 1114 | __func__); |
| 1115 | } |
| 1116 | EXPORT_SYMBOL_GPL(nvdimm_blk_region_create); |
| 1117 | |
| 1118 | struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, |
| 1119 | struct nd_region_desc *ndr_desc) |
| 1120 | { |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 1121 | ndr_desc->num_lanes = ND_MAX_LANES; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 1122 | return nd_region_create(nvdimm_bus, ndr_desc, &nd_volatile_device_type, |
| 1123 | __func__); |
| 1124 | } |
| 1125 | EXPORT_SYMBOL_GPL(nvdimm_volatile_region_create); |
Dan Williams | b354aba | 2016-05-17 20:24:16 -0700 | [diff] [blame] | 1126 | |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 1127 | int nvdimm_flush(struct nd_region *nd_region, struct bio *bio) |
| 1128 | { |
| 1129 | int rc = 0; |
| 1130 | |
| 1131 | if (!nd_region->flush) |
| 1132 | rc = generic_nvdimm_flush(nd_region); |
| 1133 | else { |
| 1134 | if (nd_region->flush(nd_region, bio)) |
| 1135 | rc = -EIO; |
| 1136 | } |
| 1137 | |
| 1138 | return rc; |
| 1139 | } |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1140 | /** |
| 1141 | * nvdimm_flush - flush any posted write queues between the cpu and pmem media |
| 1142 | * @nd_region: blk or interleaved pmem region |
| 1143 | */ |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 1144 | int generic_nvdimm_flush(struct nd_region *nd_region) |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1145 | { |
| 1146 | struct nd_region_data *ndrd = dev_get_drvdata(&nd_region->dev); |
Dan Williams | 0c27af6 | 2016-05-27 09:23:01 -0700 | [diff] [blame] | 1147 | int i, idx; |
| 1148 | |
| 1149 | /* |
| 1150 | * Try to encourage some diversity in flush hint addresses |
| 1151 | * across cpus assuming a limited number of flush hints. |
| 1152 | */ |
| 1153 | idx = this_cpu_read(flush_idx); |
| 1154 | idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8)); |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1155 | |
| 1156 | /* |
| 1157 | * The first wmb() is needed to 'sfence' all previous writes |
| 1158 | * such that they are architecturally visible for the platform |
| 1159 | * buffer flush. Note that we've already arranged for pmem |
Dan Williams | 0aed55a | 2017-05-29 12:22:50 -0700 | [diff] [blame] | 1160 | * writes to avoid the cache via memcpy_flushcache(). The final |
| 1161 | * wmb() ensures ordering for the NVDIMM flush write. |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1162 | */ |
| 1163 | wmb(); |
| 1164 | for (i = 0; i < nd_region->ndr_mappings; i++) |
Dan Williams | 595c730 | 2016-09-23 17:53:52 -0700 | [diff] [blame] | 1165 | if (ndrd_get_flush_wpq(ndrd, i, 0)) |
| 1166 | writeq(1, ndrd_get_flush_wpq(ndrd, i, idx)); |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1167 | wmb(); |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 1168 | |
| 1169 | return 0; |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1170 | } |
| 1171 | EXPORT_SYMBOL_GPL(nvdimm_flush); |
| 1172 | |
| 1173 | /** |
| 1174 | * nvdimm_has_flush - determine write flushing requirements |
| 1175 | * @nd_region: blk or interleaved pmem region |
| 1176 | * |
| 1177 | * Returns 1 if writes require flushing |
| 1178 | * Returns 0 if writes do not require flushing |
| 1179 | * Returns -ENXIO if flushing capability can not be determined |
| 1180 | */ |
| 1181 | int nvdimm_has_flush(struct nd_region *nd_region) |
| 1182 | { |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1183 | int i; |
| 1184 | |
Dan Williams | c00b396 | 2017-05-29 23:11:57 -0700 | [diff] [blame] | 1185 | /* no nvdimm or pmem api == flushing capability unknown */ |
| 1186 | if (nd_region->ndr_mappings == 0 |
| 1187 | || !IS_ENABLED(CONFIG_ARCH_HAS_PMEM_API)) |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1188 | return -ENXIO; |
| 1189 | |
Dan Williams | bc042fd | 2017-04-24 15:43:05 -0700 | [diff] [blame] | 1190 | for (i = 0; i < nd_region->ndr_mappings; i++) { |
| 1191 | struct nd_mapping *nd_mapping = &nd_region->mapping[i]; |
| 1192 | struct nvdimm *nvdimm = nd_mapping->nvdimm; |
| 1193 | |
| 1194 | /* flush hints present / available */ |
| 1195 | if (nvdimm->num_flush) |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1196 | return 1; |
Dan Williams | bc042fd | 2017-04-24 15:43:05 -0700 | [diff] [blame] | 1197 | } |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 1198 | |
| 1199 | /* |
| 1200 | * The platform defines dimm devices without hints, assume |
| 1201 | * platform persistence mechanism like ADR |
| 1202 | */ |
| 1203 | return 0; |
| 1204 | } |
| 1205 | EXPORT_SYMBOL_GPL(nvdimm_has_flush); |
| 1206 | |
Dan Williams | 0b27796 | 2017-06-09 09:46:50 -0700 | [diff] [blame] | 1207 | int nvdimm_has_cache(struct nd_region *nd_region) |
| 1208 | { |
Ross Zwisler | 546eb03 | 2018-06-06 10:45:15 -0600 | [diff] [blame] | 1209 | return is_nd_pmem(&nd_region->dev) && |
| 1210 | !test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags); |
Dan Williams | 0b27796 | 2017-06-09 09:46:50 -0700 | [diff] [blame] | 1211 | } |
| 1212 | EXPORT_SYMBOL_GPL(nvdimm_has_cache); |
| 1213 | |
Pankaj Gupta | fefc1d9 | 2019-07-05 19:33:24 +0530 | [diff] [blame] | 1214 | bool is_nvdimm_sync(struct nd_region *nd_region) |
| 1215 | { |
| 1216 | return is_nd_pmem(&nd_region->dev) && |
| 1217 | !test_bit(ND_REGION_ASYNC, &nd_region->flags); |
| 1218 | } |
| 1219 | EXPORT_SYMBOL_GPL(is_nvdimm_sync); |
| 1220 | |
Dan Williams | ae86cbf | 2018-11-24 10:47:04 -0800 | [diff] [blame] | 1221 | struct conflict_context { |
| 1222 | struct nd_region *nd_region; |
| 1223 | resource_size_t start, size; |
| 1224 | }; |
| 1225 | |
| 1226 | static int region_conflict(struct device *dev, void *data) |
| 1227 | { |
| 1228 | struct nd_region *nd_region; |
| 1229 | struct conflict_context *ctx = data; |
| 1230 | resource_size_t res_end, region_end, region_start; |
| 1231 | |
| 1232 | if (!is_memory(dev)) |
| 1233 | return 0; |
| 1234 | |
| 1235 | nd_region = to_nd_region(dev); |
| 1236 | if (nd_region == ctx->nd_region) |
| 1237 | return 0; |
| 1238 | |
| 1239 | res_end = ctx->start + ctx->size; |
| 1240 | region_start = nd_region->ndr_start; |
| 1241 | region_end = region_start + nd_region->ndr_size; |
| 1242 | if (ctx->start >= region_start && ctx->start < region_end) |
| 1243 | return -EBUSY; |
| 1244 | if (res_end > region_start && res_end <= region_end) |
| 1245 | return -EBUSY; |
| 1246 | return 0; |
| 1247 | } |
| 1248 | |
| 1249 | int nd_region_conflict(struct nd_region *nd_region, resource_size_t start, |
| 1250 | resource_size_t size) |
| 1251 | { |
| 1252 | struct nvdimm_bus *nvdimm_bus = walk_to_nvdimm_bus(&nd_region->dev); |
| 1253 | struct conflict_context ctx = { |
| 1254 | .nd_region = nd_region, |
| 1255 | .start = start, |
| 1256 | .size = size, |
| 1257 | }; |
| 1258 | |
| 1259 | return device_for_each_child(&nvdimm_bus->dev, &ctx, region_conflict); |
| 1260 | } |
| 1261 | |
Dan Williams | b354aba | 2016-05-17 20:24:16 -0700 | [diff] [blame] | 1262 | void __exit nd_region_devs_exit(void) |
| 1263 | { |
| 1264 | ida_destroy(®ion_ida); |
| 1265 | } |