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Carlo Caionecfb61a42014-05-01 14:29:27 +02001/*
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08002 * MFD core driver for the X-Powers' Power Management ICs
Carlo Caionecfb61a42014-05-01 14:29:27 +02003 *
Jacob Panaf7e9062014-10-06 21:17:14 -07004 * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC
5 * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
6 * as well as configurable GPIOs.
Carlo Caionecfb61a42014-05-01 14:29:27 +02007 *
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +08008 * This file contains the interface independent core functions.
9 *
Chen-Yu Tsaie7402352016-02-12 10:02:41 +080010 * Copyright (C) 2014 Carlo Caione
11 *
Carlo Caionecfb61a42014-05-01 14:29:27 +020012 * Author: Carlo Caione <carlo@caione.org>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/err.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020020#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020025#include <linux/regulator/consumer.h>
26#include <linux/mfd/axp20x.h>
27#include <linux/mfd/core.h>
28#include <linux/of_device.h>
Jacob Panaf7e9062014-10-06 21:17:14 -070029#include <linux/acpi.h>
Carlo Caionecfb61a42014-05-01 14:29:27 +020030
31#define AXP20X_OFF 0x80
32
Krzysztof Kozlowskic31e8582015-03-24 11:21:17 +010033static const char * const axp20x_model_names[] = {
Michal Suchanekd8d79f82015-07-11 14:59:56 +020034 "AXP152",
Jacob Panaf7e9062014-10-06 21:17:14 -070035 "AXP202",
36 "AXP209",
Boris BREZILLONf05be582015-04-10 12:09:01 +080037 "AXP221",
Chen-Yu Tsai02071f02016-02-12 10:02:44 +080038 "AXP223",
Jacob Panaf7e9062014-10-06 21:17:14 -070039 "AXP288",
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080040 "AXP809",
Jacob Panaf7e9062014-10-06 21:17:14 -070041};
42
Michal Suchanekd8d79f82015-07-11 14:59:56 +020043static const struct regmap_range axp152_writeable_ranges[] = {
44 regmap_reg_range(AXP152_LDO3456_DC1234_CTRL, AXP152_IRQ3_STATE),
45 regmap_reg_range(AXP152_DCDC_MODE, AXP152_PWM1_DUTY_CYCLE),
46};
47
48static const struct regmap_range axp152_volatile_ranges[] = {
49 regmap_reg_range(AXP152_PWR_OP_MODE, AXP152_PWR_OP_MODE),
50 regmap_reg_range(AXP152_IRQ1_EN, AXP152_IRQ3_STATE),
51 regmap_reg_range(AXP152_GPIO_INPUT, AXP152_GPIO_INPUT),
52};
53
54static const struct regmap_access_table axp152_writeable_table = {
55 .yes_ranges = axp152_writeable_ranges,
56 .n_yes_ranges = ARRAY_SIZE(axp152_writeable_ranges),
57};
58
59static const struct regmap_access_table axp152_volatile_table = {
60 .yes_ranges = axp152_volatile_ranges,
61 .n_yes_ranges = ARRAY_SIZE(axp152_volatile_ranges),
62};
63
Carlo Caionecfb61a42014-05-01 14:29:27 +020064static const struct regmap_range axp20x_writeable_ranges[] = {
65 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
66 regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020067 regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
Carlo Caionecfb61a42014-05-01 14:29:27 +020068};
69
70static const struct regmap_range axp20x_volatile_ranges[] = {
Bruno Prémont553ed4b2015-08-08 17:58:40 +020071 regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
72 regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
Carlo Caionecfb61a42014-05-01 14:29:27 +020073 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
Bruno Prémont553ed4b2015-08-08 17:58:40 +020074 regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
75 regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
76 regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
Carlo Caionecfb61a42014-05-01 14:29:27 +020077};
78
79static const struct regmap_access_table axp20x_writeable_table = {
80 .yes_ranges = axp20x_writeable_ranges,
81 .n_yes_ranges = ARRAY_SIZE(axp20x_writeable_ranges),
82};
83
84static const struct regmap_access_table axp20x_volatile_table = {
85 .yes_ranges = axp20x_volatile_ranges,
86 .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges),
87};
88
Chen-Yu Tsai20147f02016-03-29 17:22:26 +080089/* AXP22x ranges are shared with the AXP809, as they cover the same range */
Boris BREZILLONf05be582015-04-10 12:09:01 +080090static const struct regmap_range axp22x_writeable_ranges[] = {
91 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
92 regmap_reg_range(AXP20X_DCDC_MODE, AXP22X_BATLOW_THRES1),
93};
94
95static const struct regmap_range axp22x_volatile_ranges[] = {
96 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
97};
98
99static const struct regmap_access_table axp22x_writeable_table = {
100 .yes_ranges = axp22x_writeable_ranges,
101 .n_yes_ranges = ARRAY_SIZE(axp22x_writeable_ranges),
102};
103
104static const struct regmap_access_table axp22x_volatile_table = {
105 .yes_ranges = axp22x_volatile_ranges,
106 .n_yes_ranges = ARRAY_SIZE(axp22x_volatile_ranges),
107};
108
Jacob Panaf7e9062014-10-06 21:17:14 -0700109static const struct regmap_range axp288_writeable_ranges[] = {
110 regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE),
111 regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5),
112};
113
114static const struct regmap_range axp288_volatile_ranges[] = {
115 regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L),
116};
117
118static const struct regmap_access_table axp288_writeable_table = {
119 .yes_ranges = axp288_writeable_ranges,
120 .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges),
121};
122
123static const struct regmap_access_table axp288_volatile_table = {
124 .yes_ranges = axp288_volatile_ranges,
125 .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges),
126};
127
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200128static struct resource axp152_pek_resources[] = {
129 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
130 DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
131};
132
Carlo Caionecfb61a42014-05-01 14:29:27 +0200133static struct resource axp20x_pek_resources[] = {
134 {
135 .name = "PEK_DBR",
136 .start = AXP20X_IRQ_PEK_RIS_EDGE,
137 .end = AXP20X_IRQ_PEK_RIS_EDGE,
138 .flags = IORESOURCE_IRQ,
139 }, {
140 .name = "PEK_DBF",
141 .start = AXP20X_IRQ_PEK_FAL_EDGE,
142 .end = AXP20X_IRQ_PEK_FAL_EDGE,
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
Hans de Goede8de4efd2015-08-08 17:58:41 +0200147static struct resource axp20x_usb_power_supply_resources[] = {
148 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
149 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
150 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"),
151 DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"),
152};
153
Boris BREZILLONf05be582015-04-10 12:09:01 +0800154static struct resource axp22x_pek_resources[] = {
155 {
156 .name = "PEK_DBR",
157 .start = AXP22X_IRQ_PEK_RIS_EDGE,
158 .end = AXP22X_IRQ_PEK_RIS_EDGE,
159 .flags = IORESOURCE_IRQ,
160 }, {
161 .name = "PEK_DBF",
162 .start = AXP22X_IRQ_PEK_FAL_EDGE,
163 .end = AXP22X_IRQ_PEK_FAL_EDGE,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
Borun Fue56e5ad2015-10-14 16:16:26 +0800168static struct resource axp288_power_button_resources[] = {
169 {
170 .name = "PEK_DBR",
171 .start = AXP288_IRQ_POKN,
172 .end = AXP288_IRQ_POKN,
173 .flags = IORESOURCE_IRQ,
174 },
175 {
176 .name = "PEK_DBF",
177 .start = AXP288_IRQ_POKP,
178 .end = AXP288_IRQ_POKP,
179 .flags = IORESOURCE_IRQ,
180 },
181};
182
Todd Brandtd63878742015-02-02 15:41:41 -0800183static struct resource axp288_fuel_gauge_resources[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700184 {
185 .start = AXP288_IRQ_QWBTU,
186 .end = AXP288_IRQ_QWBTU,
187 .flags = IORESOURCE_IRQ,
188 },
189 {
190 .start = AXP288_IRQ_WBTU,
191 .end = AXP288_IRQ_WBTU,
192 .flags = IORESOURCE_IRQ,
193 },
194 {
195 .start = AXP288_IRQ_QWBTO,
196 .end = AXP288_IRQ_QWBTO,
197 .flags = IORESOURCE_IRQ,
198 },
199 {
200 .start = AXP288_IRQ_WBTO,
201 .end = AXP288_IRQ_WBTO,
202 .flags = IORESOURCE_IRQ,
203 },
204 {
205 .start = AXP288_IRQ_WL2,
206 .end = AXP288_IRQ_WL2,
207 .flags = IORESOURCE_IRQ,
208 },
209 {
210 .start = AXP288_IRQ_WL1,
211 .end = AXP288_IRQ_WL1,
212 .flags = IORESOURCE_IRQ,
213 },
214};
215
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800216static struct resource axp809_pek_resources[] = {
217 {
218 .name = "PEK_DBR",
219 .start = AXP809_IRQ_PEK_RIS_EDGE,
220 .end = AXP809_IRQ_PEK_RIS_EDGE,
221 .flags = IORESOURCE_IRQ,
222 }, {
223 .name = "PEK_DBF",
224 .start = AXP809_IRQ_PEK_FAL_EDGE,
225 .end = AXP809_IRQ_PEK_FAL_EDGE,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200230static const struct regmap_config axp152_regmap_config = {
231 .reg_bits = 8,
232 .val_bits = 8,
233 .wr_table = &axp152_writeable_table,
234 .volatile_table = &axp152_volatile_table,
235 .max_register = AXP152_PWM1_DUTY_CYCLE,
236 .cache_type = REGCACHE_RBTREE,
237};
238
Carlo Caionecfb61a42014-05-01 14:29:27 +0200239static const struct regmap_config axp20x_regmap_config = {
240 .reg_bits = 8,
241 .val_bits = 8,
242 .wr_table = &axp20x_writeable_table,
243 .volatile_table = &axp20x_volatile_table,
Bruno Prémont553ed4b2015-08-08 17:58:40 +0200244 .max_register = AXP20X_OCV(AXP20X_OCV_MAX),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200245 .cache_type = REGCACHE_RBTREE,
246};
247
Boris BREZILLONf05be582015-04-10 12:09:01 +0800248static const struct regmap_config axp22x_regmap_config = {
249 .reg_bits = 8,
250 .val_bits = 8,
251 .wr_table = &axp22x_writeable_table,
252 .volatile_table = &axp22x_volatile_table,
253 .max_register = AXP22X_BATLOW_THRES1,
254 .cache_type = REGCACHE_RBTREE,
255};
256
Jacob Panaf7e9062014-10-06 21:17:14 -0700257static const struct regmap_config axp288_regmap_config = {
258 .reg_bits = 8,
259 .val_bits = 8,
260 .wr_table = &axp288_writeable_table,
261 .volatile_table = &axp288_volatile_table,
262 .max_register = AXP288_FG_TUNE5,
263 .cache_type = REGCACHE_RBTREE,
264};
265
266#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \
267 [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) }
Carlo Caionecfb61a42014-05-01 14:29:27 +0200268
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200269static const struct regmap_irq axp152_regmap_irqs[] = {
270 INIT_REGMAP_IRQ(AXP152, LDO0IN_CONNECT, 0, 6),
271 INIT_REGMAP_IRQ(AXP152, LDO0IN_REMOVAL, 0, 5),
272 INIT_REGMAP_IRQ(AXP152, ALDO0IN_CONNECT, 0, 3),
273 INIT_REGMAP_IRQ(AXP152, ALDO0IN_REMOVAL, 0, 2),
274 INIT_REGMAP_IRQ(AXP152, DCDC1_V_LOW, 1, 5),
275 INIT_REGMAP_IRQ(AXP152, DCDC2_V_LOW, 1, 4),
276 INIT_REGMAP_IRQ(AXP152, DCDC3_V_LOW, 1, 3),
277 INIT_REGMAP_IRQ(AXP152, DCDC4_V_LOW, 1, 2),
278 INIT_REGMAP_IRQ(AXP152, PEK_SHORT, 1, 1),
279 INIT_REGMAP_IRQ(AXP152, PEK_LONG, 1, 0),
280 INIT_REGMAP_IRQ(AXP152, TIMER, 2, 7),
281 INIT_REGMAP_IRQ(AXP152, PEK_RIS_EDGE, 2, 6),
282 INIT_REGMAP_IRQ(AXP152, PEK_FAL_EDGE, 2, 5),
283 INIT_REGMAP_IRQ(AXP152, GPIO3_INPUT, 2, 3),
284 INIT_REGMAP_IRQ(AXP152, GPIO2_INPUT, 2, 2),
285 INIT_REGMAP_IRQ(AXP152, GPIO1_INPUT, 2, 1),
286 INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0),
287};
288
Carlo Caionecfb61a42014-05-01 14:29:27 +0200289static const struct regmap_irq axp20x_regmap_irqs[] = {
Jacob Panaf7e9062014-10-06 21:17:14 -0700290 INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7),
291 INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6),
292 INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5),
293 INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4),
294 INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3),
295 INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2),
296 INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1),
297 INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7),
298 INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6),
299 INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5),
300 INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4),
301 INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3),
302 INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2),
303 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1),
304 INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0),
305 INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7),
306 INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6),
307 INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5),
308 INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4),
309 INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3),
310 INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1),
311 INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0),
312 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7),
313 INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6),
314 INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5),
315 INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4),
316 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3),
317 INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2),
318 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1),
319 INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0),
320 INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7),
321 INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6),
322 INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5),
323 INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3),
324 INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2),
325 INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1),
326 INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0),
327};
328
Boris BREZILLONf05be582015-04-10 12:09:01 +0800329static const struct regmap_irq axp22x_regmap_irqs[] = {
330 INIT_REGMAP_IRQ(AXP22X, ACIN_OVER_V, 0, 7),
331 INIT_REGMAP_IRQ(AXP22X, ACIN_PLUGIN, 0, 6),
332 INIT_REGMAP_IRQ(AXP22X, ACIN_REMOVAL, 0, 5),
333 INIT_REGMAP_IRQ(AXP22X, VBUS_OVER_V, 0, 4),
334 INIT_REGMAP_IRQ(AXP22X, VBUS_PLUGIN, 0, 3),
335 INIT_REGMAP_IRQ(AXP22X, VBUS_REMOVAL, 0, 2),
336 INIT_REGMAP_IRQ(AXP22X, VBUS_V_LOW, 0, 1),
337 INIT_REGMAP_IRQ(AXP22X, BATT_PLUGIN, 1, 7),
338 INIT_REGMAP_IRQ(AXP22X, BATT_REMOVAL, 1, 6),
339 INIT_REGMAP_IRQ(AXP22X, BATT_ENT_ACT_MODE, 1, 5),
340 INIT_REGMAP_IRQ(AXP22X, BATT_EXIT_ACT_MODE, 1, 4),
341 INIT_REGMAP_IRQ(AXP22X, CHARG, 1, 3),
342 INIT_REGMAP_IRQ(AXP22X, CHARG_DONE, 1, 2),
343 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_HIGH, 1, 1),
344 INIT_REGMAP_IRQ(AXP22X, BATT_TEMP_LOW, 1, 0),
345 INIT_REGMAP_IRQ(AXP22X, DIE_TEMP_HIGH, 2, 7),
346 INIT_REGMAP_IRQ(AXP22X, PEK_SHORT, 2, 1),
347 INIT_REGMAP_IRQ(AXP22X, PEK_LONG, 2, 0),
348 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL1, 3, 1),
349 INIT_REGMAP_IRQ(AXP22X, LOW_PWR_LVL2, 3, 0),
350 INIT_REGMAP_IRQ(AXP22X, TIMER, 4, 7),
351 INIT_REGMAP_IRQ(AXP22X, PEK_RIS_EDGE, 4, 6),
352 INIT_REGMAP_IRQ(AXP22X, PEK_FAL_EDGE, 4, 5),
353 INIT_REGMAP_IRQ(AXP22X, GPIO1_INPUT, 4, 1),
354 INIT_REGMAP_IRQ(AXP22X, GPIO0_INPUT, 4, 0),
355};
356
Jacob Panaf7e9062014-10-06 21:17:14 -0700357/* some IRQs are compatible with axp20x models */
358static const struct regmap_irq axp288_regmap_irqs[] = {
Jacob Panff3bbc52014-11-11 11:30:09 -0800359 INIT_REGMAP_IRQ(AXP288, VBUS_FALL, 0, 2),
360 INIT_REGMAP_IRQ(AXP288, VBUS_RISE, 0, 3),
361 INIT_REGMAP_IRQ(AXP288, OV, 0, 4),
Jacob Panaf7e9062014-10-06 21:17:14 -0700362
Jacob Panff3bbc52014-11-11 11:30:09 -0800363 INIT_REGMAP_IRQ(AXP288, DONE, 1, 2),
364 INIT_REGMAP_IRQ(AXP288, CHARGING, 1, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700365 INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4),
366 INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5),
Jacob Panff3bbc52014-11-11 11:30:09 -0800367 INIT_REGMAP_IRQ(AXP288, ABSENT, 1, 6),
368 INIT_REGMAP_IRQ(AXP288, APPEND, 1, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700369
370 INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0),
371 INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1),
372 INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2),
Jacob Panff3bbc52014-11-11 11:30:09 -0800373 INIT_REGMAP_IRQ(AXP288, WBTO, 2, 3),
Jacob Panaf7e9062014-10-06 21:17:14 -0700374 INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4),
375 INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5),
376 INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6),
377 INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7),
378
379 INIT_REGMAP_IRQ(AXP288, WL2, 3, 0),
380 INIT_REGMAP_IRQ(AXP288, WL1, 3, 1),
381 INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2),
382 INIT_REGMAP_IRQ(AXP288, OT, 3, 7),
383
384 INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0),
385 INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1),
386 INIT_REGMAP_IRQ(AXP288, POKO, 4, 2),
387 INIT_REGMAP_IRQ(AXP288, POKL, 4, 3),
388 INIT_REGMAP_IRQ(AXP288, POKS, 4, 4),
389 INIT_REGMAP_IRQ(AXP288, POKN, 4, 5),
390 INIT_REGMAP_IRQ(AXP288, POKP, 4, 6),
Jacob Panff3bbc52014-11-11 11:30:09 -0800391 INIT_REGMAP_IRQ(AXP288, TIMER, 4, 7),
Jacob Panaf7e9062014-10-06 21:17:14 -0700392
393 INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0),
394 INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1),
Carlo Caionecfb61a42014-05-01 14:29:27 +0200395};
396
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800397static const struct regmap_irq axp809_regmap_irqs[] = {
398 INIT_REGMAP_IRQ(AXP809, ACIN_OVER_V, 0, 7),
399 INIT_REGMAP_IRQ(AXP809, ACIN_PLUGIN, 0, 6),
400 INIT_REGMAP_IRQ(AXP809, ACIN_REMOVAL, 0, 5),
401 INIT_REGMAP_IRQ(AXP809, VBUS_OVER_V, 0, 4),
402 INIT_REGMAP_IRQ(AXP809, VBUS_PLUGIN, 0, 3),
403 INIT_REGMAP_IRQ(AXP809, VBUS_REMOVAL, 0, 2),
404 INIT_REGMAP_IRQ(AXP809, VBUS_V_LOW, 0, 1),
405 INIT_REGMAP_IRQ(AXP809, BATT_PLUGIN, 1, 7),
406 INIT_REGMAP_IRQ(AXP809, BATT_REMOVAL, 1, 6),
407 INIT_REGMAP_IRQ(AXP809, BATT_ENT_ACT_MODE, 1, 5),
408 INIT_REGMAP_IRQ(AXP809, BATT_EXIT_ACT_MODE, 1, 4),
409 INIT_REGMAP_IRQ(AXP809, CHARG, 1, 3),
410 INIT_REGMAP_IRQ(AXP809, CHARG_DONE, 1, 2),
411 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH, 2, 7),
412 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_HIGH_END, 2, 6),
413 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW, 2, 5),
414 INIT_REGMAP_IRQ(AXP809, BATT_CHG_TEMP_LOW_END, 2, 4),
415 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH, 2, 3),
416 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_HIGH_END, 2, 2),
417 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW, 2, 1),
418 INIT_REGMAP_IRQ(AXP809, BATT_ACT_TEMP_LOW_END, 2, 0),
419 INIT_REGMAP_IRQ(AXP809, DIE_TEMP_HIGH, 3, 7),
420 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL1, 3, 1),
421 INIT_REGMAP_IRQ(AXP809, LOW_PWR_LVL2, 3, 0),
422 INIT_REGMAP_IRQ(AXP809, TIMER, 4, 7),
423 INIT_REGMAP_IRQ(AXP809, PEK_RIS_EDGE, 4, 6),
424 INIT_REGMAP_IRQ(AXP809, PEK_FAL_EDGE, 4, 5),
425 INIT_REGMAP_IRQ(AXP809, PEK_SHORT, 4, 4),
426 INIT_REGMAP_IRQ(AXP809, PEK_LONG, 4, 3),
427 INIT_REGMAP_IRQ(AXP809, PEK_OVER_OFF, 4, 2),
428 INIT_REGMAP_IRQ(AXP809, GPIO1_INPUT, 4, 1),
429 INIT_REGMAP_IRQ(AXP809, GPIO0_INPUT, 4, 0),
430};
431
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200432static const struct regmap_irq_chip axp152_regmap_irq_chip = {
433 .name = "axp152_irq_chip",
434 .status_base = AXP152_IRQ1_STATE,
435 .ack_base = AXP152_IRQ1_STATE,
436 .mask_base = AXP152_IRQ1_EN,
437 .mask_invert = true,
438 .init_ack_masked = true,
439 .irqs = axp152_regmap_irqs,
440 .num_irqs = ARRAY_SIZE(axp152_regmap_irqs),
441 .num_regs = 3,
442};
443
Carlo Caionecfb61a42014-05-01 14:29:27 +0200444static const struct regmap_irq_chip axp20x_regmap_irq_chip = {
445 .name = "axp20x_irq_chip",
446 .status_base = AXP20X_IRQ1_STATE,
447 .ack_base = AXP20X_IRQ1_STATE,
448 .mask_base = AXP20X_IRQ1_EN,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200449 .mask_invert = true,
450 .init_ack_masked = true,
Jacob Panaf7e9062014-10-06 21:17:14 -0700451 .irqs = axp20x_regmap_irqs,
452 .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs),
453 .num_regs = 5,
454
455};
456
Boris BREZILLONf05be582015-04-10 12:09:01 +0800457static const struct regmap_irq_chip axp22x_regmap_irq_chip = {
458 .name = "axp22x_irq_chip",
459 .status_base = AXP20X_IRQ1_STATE,
460 .ack_base = AXP20X_IRQ1_STATE,
461 .mask_base = AXP20X_IRQ1_EN,
462 .mask_invert = true,
463 .init_ack_masked = true,
464 .irqs = axp22x_regmap_irqs,
465 .num_irqs = ARRAY_SIZE(axp22x_regmap_irqs),
466 .num_regs = 5,
467};
468
Jacob Panaf7e9062014-10-06 21:17:14 -0700469static const struct regmap_irq_chip axp288_regmap_irq_chip = {
470 .name = "axp288_irq_chip",
471 .status_base = AXP20X_IRQ1_STATE,
472 .ack_base = AXP20X_IRQ1_STATE,
473 .mask_base = AXP20X_IRQ1_EN,
474 .mask_invert = true,
475 .init_ack_masked = true,
476 .irqs = axp288_regmap_irqs,
477 .num_irqs = ARRAY_SIZE(axp288_regmap_irqs),
478 .num_regs = 6,
479
Carlo Caionecfb61a42014-05-01 14:29:27 +0200480};
481
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800482static const struct regmap_irq_chip axp809_regmap_irq_chip = {
483 .name = "axp809",
484 .status_base = AXP20X_IRQ1_STATE,
485 .ack_base = AXP20X_IRQ1_STATE,
486 .mask_base = AXP20X_IRQ1_EN,
487 .mask_invert = true,
488 .init_ack_masked = true,
489 .irqs = axp809_regmap_irqs,
490 .num_irqs = ARRAY_SIZE(axp809_regmap_irqs),
491 .num_regs = 5,
492};
493
Carlo Caionecfb61a42014-05-01 14:29:27 +0200494static struct mfd_cell axp20x_cells[] = {
495 {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200496 .name = "axp20x-pek",
497 .num_resources = ARRAY_SIZE(axp20x_pek_resources),
498 .resources = axp20x_pek_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200499 }, {
Hans de Goede8de4efd2015-08-08 17:58:41 +0200500 .name = "axp20x-regulator",
501 }, {
502 .name = "axp20x-usb-power-supply",
503 .of_compatible = "x-powers,axp202-usb-power-supply",
504 .num_resources = ARRAY_SIZE(axp20x_usb_power_supply_resources),
505 .resources = axp20x_usb_power_supply_resources,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200506 },
507};
508
Boris BREZILLONf05be582015-04-10 12:09:01 +0800509static struct mfd_cell axp22x_cells[] = {
510 {
511 .name = "axp20x-pek",
512 .num_resources = ARRAY_SIZE(axp22x_pek_resources),
513 .resources = axp22x_pek_resources,
Chen-Yu Tsai6d4fa892015-04-10 12:09:06 +0800514 }, {
515 .name = "axp20x-regulator",
Boris BREZILLONf05be582015-04-10 12:09:01 +0800516 },
517};
518
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200519static struct mfd_cell axp152_cells[] = {
520 {
521 .name = "axp20x-pek",
522 .num_resources = ARRAY_SIZE(axp152_pek_resources),
523 .resources = axp152_pek_resources,
524 },
525};
526
Jacob Panaf7e9062014-10-06 21:17:14 -0700527static struct resource axp288_adc_resources[] = {
528 {
529 .name = "GPADC",
530 .start = AXP288_IRQ_GPADC,
531 .end = AXP288_IRQ_GPADC,
532 .flags = IORESOURCE_IRQ,
533 },
534};
535
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530536static struct resource axp288_extcon_resources[] = {
537 {
538 .start = AXP288_IRQ_VBUS_FALL,
539 .end = AXP288_IRQ_VBUS_FALL,
540 .flags = IORESOURCE_IRQ,
541 },
542 {
543 .start = AXP288_IRQ_VBUS_RISE,
544 .end = AXP288_IRQ_VBUS_RISE,
545 .flags = IORESOURCE_IRQ,
546 },
547 {
548 .start = AXP288_IRQ_MV_CHNG,
549 .end = AXP288_IRQ_MV_CHNG,
550 .flags = IORESOURCE_IRQ,
551 },
552 {
553 .start = AXP288_IRQ_BC_USB_CHNG,
554 .end = AXP288_IRQ_BC_USB_CHNG,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
Jacob Panaf7e9062014-10-06 21:17:14 -0700559static struct resource axp288_charger_resources[] = {
560 {
561 .start = AXP288_IRQ_OV,
562 .end = AXP288_IRQ_OV,
563 .flags = IORESOURCE_IRQ,
564 },
565 {
566 .start = AXP288_IRQ_DONE,
567 .end = AXP288_IRQ_DONE,
568 .flags = IORESOURCE_IRQ,
569 },
570 {
571 .start = AXP288_IRQ_CHARGING,
572 .end = AXP288_IRQ_CHARGING,
573 .flags = IORESOURCE_IRQ,
574 },
575 {
576 .start = AXP288_IRQ_SAFE_QUIT,
577 .end = AXP288_IRQ_SAFE_QUIT,
578 .flags = IORESOURCE_IRQ,
579 },
580 {
581 .start = AXP288_IRQ_SAFE_ENTER,
582 .end = AXP288_IRQ_SAFE_ENTER,
583 .flags = IORESOURCE_IRQ,
584 },
585 {
586 .start = AXP288_IRQ_QCBTU,
587 .end = AXP288_IRQ_QCBTU,
588 .flags = IORESOURCE_IRQ,
589 },
590 {
591 .start = AXP288_IRQ_CBTU,
592 .end = AXP288_IRQ_CBTU,
593 .flags = IORESOURCE_IRQ,
594 },
595 {
596 .start = AXP288_IRQ_QCBTO,
597 .end = AXP288_IRQ_QCBTO,
598 .flags = IORESOURCE_IRQ,
599 },
600 {
601 .start = AXP288_IRQ_CBTO,
602 .end = AXP288_IRQ_CBTO,
603 .flags = IORESOURCE_IRQ,
604 },
605};
606
607static struct mfd_cell axp288_cells[] = {
608 {
609 .name = "axp288_adc",
610 .num_resources = ARRAY_SIZE(axp288_adc_resources),
611 .resources = axp288_adc_resources,
612 },
613 {
Ramakrishna Pallalabdb01f72015-04-03 00:49:47 +0530614 .name = "axp288_extcon",
615 .num_resources = ARRAY_SIZE(axp288_extcon_resources),
616 .resources = axp288_extcon_resources,
617 },
618 {
Jacob Panaf7e9062014-10-06 21:17:14 -0700619 .name = "axp288_charger",
620 .num_resources = ARRAY_SIZE(axp288_charger_resources),
621 .resources = axp288_charger_resources,
622 },
623 {
Todd Brandtd63878742015-02-02 15:41:41 -0800624 .name = "axp288_fuel_gauge",
625 .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources),
626 .resources = axp288_fuel_gauge_resources,
Jacob Panaf7e9062014-10-06 21:17:14 -0700627 },
Aaron Lud8139f62014-11-24 17:24:47 +0800628 {
Borun Fue56e5ad2015-10-14 16:16:26 +0800629 .name = "axp20x-pek",
630 .num_resources = ARRAY_SIZE(axp288_power_button_resources),
631 .resources = axp288_power_button_resources,
632 },
633 {
Aaron Lud8139f62014-11-24 17:24:47 +0800634 .name = "axp288_pmic_acpi",
635 },
Jacob Panaf7e9062014-10-06 21:17:14 -0700636};
637
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800638static struct mfd_cell axp809_cells[] = {
639 {
640 .name = "axp20x-pek",
641 .num_resources = ARRAY_SIZE(axp809_pek_resources),
642 .resources = axp809_pek_resources,
643 }, {
644 .name = "axp20x-regulator",
645 },
646};
647
Carlo Caionecfb61a42014-05-01 14:29:27 +0200648static struct axp20x_dev *axp20x_pm_power_off;
649static void axp20x_power_off(void)
650{
Jacob Panaf7e9062014-10-06 21:17:14 -0700651 if (axp20x_pm_power_off->variant == AXP288_ID)
652 return;
653
Carlo Caionecfb61a42014-05-01 14:29:27 +0200654 regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL,
655 AXP20X_OFF);
656}
657
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800658int axp20x_match_device(struct axp20x_dev *axp20x)
Jacob Panaf7e9062014-10-06 21:17:14 -0700659{
Chen-Yu Tsaie47a3cf2016-02-12 10:02:39 +0800660 struct device *dev = axp20x->dev;
Jacob Panaf7e9062014-10-06 21:17:14 -0700661 const struct acpi_device_id *acpi_id;
662 const struct of_device_id *of_id;
663
664 if (dev->of_node) {
Chen-Yu Tsaiaf7acc32016-02-12 10:02:40 +0800665 of_id = of_match_device(dev->driver->of_match_table, dev);
Jacob Panaf7e9062014-10-06 21:17:14 -0700666 if (!of_id) {
667 dev_err(dev, "Unable to match OF ID\n");
668 return -ENODEV;
669 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800670 axp20x->variant = (long)of_id->data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700671 } else {
672 acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
673 if (!acpi_id || !acpi_id->driver_data) {
674 dev_err(dev, "Unable to match ACPI ID and data\n");
675 return -ENODEV;
676 }
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800677 axp20x->variant = (long)acpi_id->driver_data;
Jacob Panaf7e9062014-10-06 21:17:14 -0700678 }
679
680 switch (axp20x->variant) {
Michal Suchanekd8d79f82015-07-11 14:59:56 +0200681 case AXP152_ID:
682 axp20x->nr_cells = ARRAY_SIZE(axp152_cells);
683 axp20x->cells = axp152_cells;
684 axp20x->regmap_cfg = &axp152_regmap_config;
685 axp20x->regmap_irq_chip = &axp152_regmap_irq_chip;
686 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700687 case AXP202_ID:
688 case AXP209_ID:
689 axp20x->nr_cells = ARRAY_SIZE(axp20x_cells);
690 axp20x->cells = axp20x_cells;
691 axp20x->regmap_cfg = &axp20x_regmap_config;
692 axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip;
693 break;
Boris BREZILLONf05be582015-04-10 12:09:01 +0800694 case AXP221_ID:
Chen-Yu Tsai02071f02016-02-12 10:02:44 +0800695 case AXP223_ID:
Boris BREZILLONf05be582015-04-10 12:09:01 +0800696 axp20x->nr_cells = ARRAY_SIZE(axp22x_cells);
697 axp20x->cells = axp22x_cells;
698 axp20x->regmap_cfg = &axp22x_regmap_config;
699 axp20x->regmap_irq_chip = &axp22x_regmap_irq_chip;
700 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700701 case AXP288_ID:
702 axp20x->cells = axp288_cells;
703 axp20x->nr_cells = ARRAY_SIZE(axp288_cells);
704 axp20x->regmap_cfg = &axp288_regmap_config;
705 axp20x->regmap_irq_chip = &axp288_regmap_irq_chip;
706 break;
Chen-Yu Tsai20147f02016-03-29 17:22:26 +0800707 case AXP809_ID:
708 axp20x->nr_cells = ARRAY_SIZE(axp809_cells);
709 axp20x->cells = axp809_cells;
710 axp20x->regmap_cfg = &axp22x_regmap_config;
711 axp20x->regmap_irq_chip = &axp809_regmap_irq_chip;
712 break;
Jacob Panaf7e9062014-10-06 21:17:14 -0700713 default:
714 dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant);
715 return -EINVAL;
716 }
717 dev_info(dev, "AXP20x variant %s found\n",
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800718 axp20x_model_names[axp20x->variant]);
Jacob Panaf7e9062014-10-06 21:17:14 -0700719
720 return 0;
721}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800722EXPORT_SYMBOL(axp20x_match_device);
Jacob Panaf7e9062014-10-06 21:17:14 -0700723
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800724int axp20x_device_probe(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200725{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200726 int ret;
727
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800728 ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200729 IRQF_ONESHOT | IRQF_SHARED, -1,
Jacob Panaf7e9062014-10-06 21:17:14 -0700730 axp20x->regmap_irq_chip,
Carlo Caionecfb61a42014-05-01 14:29:27 +0200731 &axp20x->regmap_irqc);
732 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800733 dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200734 return ret;
735 }
736
Jacob Panaf7e9062014-10-06 21:17:14 -0700737 ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
Chen-Yu Tsai2260a452016-02-12 10:02:43 +0800738 axp20x->nr_cells, NULL, 0, NULL);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200739
740 if (ret) {
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800741 dev_err(axp20x->dev, "failed to add MFD devices: %d\n", ret);
742 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200743 return ret;
744 }
745
746 if (!pm_power_off) {
747 axp20x_pm_power_off = axp20x;
748 pm_power_off = axp20x_power_off;
749 }
750
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800751 dev_info(axp20x->dev, "AXP20X driver loaded\n");
Carlo Caionecfb61a42014-05-01 14:29:27 +0200752
753 return 0;
754}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800755EXPORT_SYMBOL(axp20x_device_probe);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200756
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800757int axp20x_device_remove(struct axp20x_dev *axp20x)
Carlo Caionecfb61a42014-05-01 14:29:27 +0200758{
Carlo Caionecfb61a42014-05-01 14:29:27 +0200759 if (axp20x == axp20x_pm_power_off) {
760 axp20x_pm_power_off = NULL;
761 pm_power_off = NULL;
762 }
763
764 mfd_remove_devices(axp20x->dev);
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800765 regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200766
767 return 0;
768}
Chen-Yu Tsai4fd41152016-02-12 10:02:42 +0800769EXPORT_SYMBOL(axp20x_device_remove);
Carlo Caionecfb61a42014-05-01 14:29:27 +0200770
771MODULE_DESCRIPTION("PMIC MFD core driver for AXP20X");
772MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
773MODULE_LICENSE("GPL");