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Shawn Guoabfafc22011-06-30 15:44:44 +08001* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
2
3The Enhanced Secure Digital Host Controller on Freescale i.MX family
4provides an interface for MMC, SD, and SDIO types of memory cards.
5
Chris Ball4efafee2012-06-11 21:48:16 -04006This file documents differences between the core properties described
7by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
8
Shawn Guoabfafc22011-06-30 15:44:44 +08009Required properties:
Dong Aishenge4a51ce2015-05-27 18:13:29 +080010- compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11 "fsl,imx25-esdhc"
12 "fsl,imx35-esdhc"
13 "fsl,imx51-esdhc"
14 "fsl,imx53-esdhc"
15 "fsl,imx6q-usdhc"
16 "fsl,imx6sl-usdhc"
17 "fsl,imx6sx-usdhc"
Haibo Chen2a2a7ea2015-08-11 19:38:28 +080018 "fsl,imx7d-usdhc"
Shawn Guoabfafc22011-06-30 15:44:44 +080019
20Optional properties:
Shawn Guoa46d2612012-08-22 21:46:39 +080021- fsl,wp-controller : Indicate to use controller internal write protection
Dong Aisheng602519b2013-10-18 19:48:47 +080022- fsl,delay-line : Specify the number of delay cells for override mode.
23 This is used to set the clock delay for DLL(Delay Line) on override mode
24 to select a proper data sampling window in case the clock quality is not good
25 due to signal path is too long on the board. Please refer to eSDHC/uSDHC
26 chapter, DLL (Delay Line) section in RM for details.
Sascha Hauer07bf2b52015-03-24 14:45:04 +010027- voltage-ranges : Specify the voltage range in case there are software
28 transparent level shifters on the outputs of the controller. Two cells are
29 required, first cell specifies minimum slot voltage (mV), second cell
30 specifies maximum slot voltage (mV). Several ranges could be specified.
Haibo Chen2a2a7ea2015-08-11 19:38:28 +080031- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
32 The uSDHC use one delay cell as default increasing step to do tuning process.
33 This property allows user to change the tuning step to more than one delay
34 cells which is useful for some special boards or cards when the default
35 tuning step can't find the proper delay window within limited tuning retries.
Shawn Guoabfafc22011-06-30 15:44:44 +080036
37Examples:
38
39esdhc@70004000 {
40 compatible = "fsl,imx51-esdhc";
41 reg = <0x70004000 0x4000>;
42 interrupts = <1>;
Shawn Guoa46d2612012-08-22 21:46:39 +080043 fsl,wp-controller;
Shawn Guoabfafc22011-06-30 15:44:44 +080044};
45
46esdhc@70008000 {
47 compatible = "fsl,imx51-esdhc";
48 reg = <0x70008000 0x4000>;
49 interrupts = <2>;
Fabio Estevam06693fc2012-06-10 14:24:07 -030050 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
51 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
Shawn Guoabfafc22011-06-30 15:44:44 +080052};