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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02005 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
Sergei Shtylyov38b66f82007-04-20 22:16:58 +02006 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
Alan Coxb39b01f2005-06-27 15:24:27 -070013 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080014 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
Alan Coxb39b01f2005-06-27 15:24:27 -070019 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
55 * Alan Cox <alan@redhat.com>
56 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -080057 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010062 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -080066 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
Sergei Shtylyov26c068d2006-12-13 00:35:52 -080069 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
Sergei Shtylyov72931362007-09-11 22:28:35 +020070 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
Sergei Shtylyov33b18a62006-12-13 00:35:50 -080072 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
Sergei Shtylyov73d1dd92006-12-13 00:35:51 -080074 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010076 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
Sergei Shtylyov90778572007-02-07 18:17:51 +010078 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +020080 * - optimize the UltraDMA filtering and the drive list lookup code
Sergei Shtylyovb4586712007-02-07 18:17:54 +010081 * - use pci_get_slot() to get to the function 1 of HPT36x/374
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010082 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +010086 * - rename all the register related variables consistently
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010087 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
Sergei Shtylyov866664d2008-01-25 22:17:05 +010089 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010090 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +010094 * - clean up DMA timeout handling for HPT370
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +010095 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
Sergei Shtylyov278978e2007-06-08 15:14:32 +0200109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
Sergei Shtylyov6273d262007-02-07 18:18:20 +0100111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200115 * - set the correct hwif->ultra_mask for each individual chip
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100117 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 */
119
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120#include <linux/types.h>
121#include <linux/module.h>
122#include <linux/kernel.h>
123#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124#include <linux/blkdev.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125#include <linux/interrupt.h>
126#include <linux/pci.h>
127#include <linux/init.h>
128#include <linux/ide.h>
129
130#include <asm/uaccess.h>
131#include <asm/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +0200133#define DRV_NAME "hpt366"
134
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135/* various tuning parameters */
136#define HPT_RESET_STATE_ENGINE
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800137#undef HPT_DELAY_INTERRUPT
138#define HPT_SERIALIZE_IO 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
140static const char *quirk_drives[] = {
141 "QUANTUM FIREBALLlct08 08",
142 "QUANTUM FIREBALLP KA6.4",
143 "QUANTUM FIREBALLP LM20.4",
144 "QUANTUM FIREBALLP LM20.5",
145 NULL
146};
147
148static const char *bad_ata100_5[] = {
149 "IBM-DTLA-307075",
150 "IBM-DTLA-307060",
151 "IBM-DTLA-307045",
152 "IBM-DTLA-307030",
153 "IBM-DTLA-307020",
154 "IBM-DTLA-307015",
155 "IBM-DTLA-305040",
156 "IBM-DTLA-305030",
157 "IBM-DTLA-305020",
158 "IC35L010AVER07-0",
159 "IC35L020AVER07-0",
160 "IC35L030AVER07-0",
161 "IC35L040AVER07-0",
162 "IC35L060AVER07-0",
163 "WDC AC310200R",
164 NULL
165};
166
167static const char *bad_ata66_4[] = {
168 "IBM-DTLA-307075",
169 "IBM-DTLA-307060",
170 "IBM-DTLA-307045",
171 "IBM-DTLA-307030",
172 "IBM-DTLA-307020",
173 "IBM-DTLA-307015",
174 "IBM-DTLA-305040",
175 "IBM-DTLA-305030",
176 "IBM-DTLA-305020",
177 "IC35L010AVER07-0",
178 "IC35L020AVER07-0",
179 "IC35L030AVER07-0",
180 "IC35L040AVER07-0",
181 "IC35L060AVER07-0",
182 "WDC AC310200R",
Sergei Shtylyov783353b2007-07-03 22:28:35 +0200183 "MAXTOR STM3320620A",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 NULL
185};
186
187static const char *bad_ata66_3[] = {
188 "WDC AC310200R",
189 NULL
190};
191
192static const char *bad_ata33[] = {
193 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
194 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
195 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
196 "Maxtor 90510D4",
197 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
198 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
199 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
200 NULL
201};
202
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800203static u8 xfer_speeds[] = {
204 XFER_UDMA_6,
205 XFER_UDMA_5,
206 XFER_UDMA_4,
207 XFER_UDMA_3,
208 XFER_UDMA_2,
209 XFER_UDMA_1,
210 XFER_UDMA_0,
211
212 XFER_MW_DMA_2,
213 XFER_MW_DMA_1,
214 XFER_MW_DMA_0,
215
216 XFER_PIO_4,
217 XFER_PIO_3,
218 XFER_PIO_2,
219 XFER_PIO_1,
220 XFER_PIO_0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221};
222
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800223/* Key for bus clock timings
224 * 36x 37x
225 * bits bits
226 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
227 * cycles = value + 1
228 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
229 * cycles = value + 1
230 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
231 * register access.
232 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
233 * register access.
234 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
235 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
236 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
237 * MW DMA xfer.
238 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
239 * task file register access.
240 * 28 28 UDMA enable.
241 * 29 29 DMA enable.
242 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
243 * PIO xfer.
244 * 31 31 FIFO enable.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800247static u32 forty_base_hpt36x[] = {
248 /* XFER_UDMA_6 */ 0x900fd943,
249 /* XFER_UDMA_5 */ 0x900fd943,
250 /* XFER_UDMA_4 */ 0x900fd943,
251 /* XFER_UDMA_3 */ 0x900ad943,
252 /* XFER_UDMA_2 */ 0x900bd943,
253 /* XFER_UDMA_1 */ 0x9008d943,
254 /* XFER_UDMA_0 */ 0x9008d943,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800256 /* XFER_MW_DMA_2 */ 0xa008d943,
257 /* XFER_MW_DMA_1 */ 0xa010d955,
258 /* XFER_MW_DMA_0 */ 0xa010d9fc,
259
260 /* XFER_PIO_4 */ 0xc008d963,
261 /* XFER_PIO_3 */ 0xc010d974,
262 /* XFER_PIO_2 */ 0xc010d997,
263 /* XFER_PIO_1 */ 0xc010d9c7,
264 /* XFER_PIO_0 */ 0xc018d9d9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265};
266
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800267static u32 thirty_three_base_hpt36x[] = {
268 /* XFER_UDMA_6 */ 0x90c9a731,
269 /* XFER_UDMA_5 */ 0x90c9a731,
270 /* XFER_UDMA_4 */ 0x90c9a731,
271 /* XFER_UDMA_3 */ 0x90cfa731,
272 /* XFER_UDMA_2 */ 0x90caa731,
273 /* XFER_UDMA_1 */ 0x90cba731,
274 /* XFER_UDMA_0 */ 0x90c8a731,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800276 /* XFER_MW_DMA_2 */ 0xa0c8a731,
277 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
278 /* XFER_MW_DMA_0 */ 0xa0c8a797,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800280 /* XFER_PIO_4 */ 0xc0c8a731,
281 /* XFER_PIO_3 */ 0xc0c8a742,
282 /* XFER_PIO_2 */ 0xc0d0a753,
283 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
284 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285};
286
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800287static u32 twenty_five_base_hpt36x[] = {
288 /* XFER_UDMA_6 */ 0x90c98521,
289 /* XFER_UDMA_5 */ 0x90c98521,
290 /* XFER_UDMA_4 */ 0x90c98521,
291 /* XFER_UDMA_3 */ 0x90cf8521,
292 /* XFER_UDMA_2 */ 0x90cf8521,
293 /* XFER_UDMA_1 */ 0x90cb8521,
294 /* XFER_UDMA_0 */ 0x90cb8521,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800296 /* XFER_MW_DMA_2 */ 0xa0ca8521,
297 /* XFER_MW_DMA_1 */ 0xa0ca8532,
298 /* XFER_MW_DMA_0 */ 0xa0ca8575,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800300 /* XFER_PIO_4 */ 0xc0ca8521,
301 /* XFER_PIO_3 */ 0xc0ca8532,
302 /* XFER_PIO_2 */ 0xc0ca8542,
303 /* XFER_PIO_1 */ 0xc0d08572,
304 /* XFER_PIO_0 */ 0xc0d08585
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305};
306
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100307#if 0
308/* These are the timing tables from the HighPoint open source drivers... */
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800309static u32 thirty_three_base_hpt37x[] = {
310 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
311 /* XFER_UDMA_5 */ 0x12446231,
312 /* XFER_UDMA_4 */ 0x12446231,
313 /* XFER_UDMA_3 */ 0x126c6231,
314 /* XFER_UDMA_2 */ 0x12486231,
315 /* XFER_UDMA_1 */ 0x124c6233,
316 /* XFER_UDMA_0 */ 0x12506297,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800318 /* XFER_MW_DMA_2 */ 0x22406c31,
319 /* XFER_MW_DMA_1 */ 0x22406c33,
320 /* XFER_MW_DMA_0 */ 0x22406c97,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800322 /* XFER_PIO_4 */ 0x06414e31,
323 /* XFER_PIO_3 */ 0x06414e42,
324 /* XFER_PIO_2 */ 0x06414e53,
325 /* XFER_PIO_1 */ 0x06814e93,
326 /* XFER_PIO_0 */ 0x06814ea7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327};
328
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800329static u32 fifty_base_hpt37x[] = {
330 /* XFER_UDMA_6 */ 0x12848242,
331 /* XFER_UDMA_5 */ 0x12848242,
332 /* XFER_UDMA_4 */ 0x12ac8242,
333 /* XFER_UDMA_3 */ 0x128c8242,
334 /* XFER_UDMA_2 */ 0x120c8242,
335 /* XFER_UDMA_1 */ 0x12148254,
336 /* XFER_UDMA_0 */ 0x121882ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800338 /* XFER_MW_DMA_2 */ 0x22808242,
339 /* XFER_MW_DMA_1 */ 0x22808254,
340 /* XFER_MW_DMA_0 */ 0x228082ea,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800342 /* XFER_PIO_4 */ 0x0a81f442,
343 /* XFER_PIO_3 */ 0x0a81f443,
344 /* XFER_PIO_2 */ 0x0a81f454,
345 /* XFER_PIO_1 */ 0x0ac1f465,
346 /* XFER_PIO_0 */ 0x0ac1f48a
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347};
348
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800349static u32 sixty_six_base_hpt37x[] = {
350 /* XFER_UDMA_6 */ 0x1c869c62,
351 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
352 /* XFER_UDMA_4 */ 0x1c8a9c62,
353 /* XFER_UDMA_3 */ 0x1c8e9c62,
354 /* XFER_UDMA_2 */ 0x1c929c62,
355 /* XFER_UDMA_1 */ 0x1c9a9c62,
356 /* XFER_UDMA_0 */ 0x1c829c62,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800358 /* XFER_MW_DMA_2 */ 0x2c829c62,
359 /* XFER_MW_DMA_1 */ 0x2c829c66,
360 /* XFER_MW_DMA_0 */ 0x2c829d2e,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800362 /* XFER_PIO_4 */ 0x0c829c62,
363 /* XFER_PIO_3 */ 0x0c829c84,
364 /* XFER_PIO_2 */ 0x0c829ca6,
365 /* XFER_PIO_1 */ 0x0d029d26,
366 /* XFER_PIO_0 */ 0x0d029d5e
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367};
Sergei Shtylyov809b53c2007-12-12 23:31:58 +0100368#else
369/*
370 * The following are the new timing tables with PIO mode data/taskfile transfer
371 * overclocking fixed...
372 */
373
374/* This table is taken from the HPT370 data manual rev. 1.02 */
375static u32 thirty_three_base_hpt37x[] = {
376 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
377 /* XFER_UDMA_5 */ 0x16455031,
378 /* XFER_UDMA_4 */ 0x16455031,
379 /* XFER_UDMA_3 */ 0x166d5031,
380 /* XFER_UDMA_2 */ 0x16495031,
381 /* XFER_UDMA_1 */ 0x164d5033,
382 /* XFER_UDMA_0 */ 0x16515097,
383
384 /* XFER_MW_DMA_2 */ 0x26515031,
385 /* XFER_MW_DMA_1 */ 0x26515033,
386 /* XFER_MW_DMA_0 */ 0x26515097,
387
388 /* XFER_PIO_4 */ 0x06515021,
389 /* XFER_PIO_3 */ 0x06515022,
390 /* XFER_PIO_2 */ 0x06515033,
391 /* XFER_PIO_1 */ 0x06915065,
392 /* XFER_PIO_0 */ 0x06d1508a
393};
394
395static u32 fifty_base_hpt37x[] = {
396 /* XFER_UDMA_6 */ 0x1a861842,
397 /* XFER_UDMA_5 */ 0x1a861842,
398 /* XFER_UDMA_4 */ 0x1aae1842,
399 /* XFER_UDMA_3 */ 0x1a8e1842,
400 /* XFER_UDMA_2 */ 0x1a0e1842,
401 /* XFER_UDMA_1 */ 0x1a161854,
402 /* XFER_UDMA_0 */ 0x1a1a18ea,
403
404 /* XFER_MW_DMA_2 */ 0x2a821842,
405 /* XFER_MW_DMA_1 */ 0x2a821854,
406 /* XFER_MW_DMA_0 */ 0x2a8218ea,
407
408 /* XFER_PIO_4 */ 0x0a821842,
409 /* XFER_PIO_3 */ 0x0a821843,
410 /* XFER_PIO_2 */ 0x0a821855,
411 /* XFER_PIO_1 */ 0x0ac218a8,
412 /* XFER_PIO_0 */ 0x0b02190c
413};
414
415static u32 sixty_six_base_hpt37x[] = {
416 /* XFER_UDMA_6 */ 0x1c86fe62,
417 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
418 /* XFER_UDMA_4 */ 0x1c8afe62,
419 /* XFER_UDMA_3 */ 0x1c8efe62,
420 /* XFER_UDMA_2 */ 0x1c92fe62,
421 /* XFER_UDMA_1 */ 0x1c9afe62,
422 /* XFER_UDMA_0 */ 0x1c82fe62,
423
424 /* XFER_MW_DMA_2 */ 0x2c82fe62,
425 /* XFER_MW_DMA_1 */ 0x2c82fe66,
426 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
427
428 /* XFER_PIO_4 */ 0x0c82fe62,
429 /* XFER_PIO_3 */ 0x0c82fe84,
430 /* XFER_PIO_2 */ 0x0c82fea6,
431 /* XFER_PIO_1 */ 0x0d02ff26,
432 /* XFER_PIO_0 */ 0x0d42ff7f
433};
434#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436#define HPT366_DEBUG_DRIVE_INFO 0
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100437#define HPT371_ALLOW_ATA133_6 1
438#define HPT302_ALLOW_ATA133_6 1
439#define HPT372_ALLOW_ATA133_6 1
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100440#define HPT370_ALLOW_ATA100_5 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441#define HPT366_ALLOW_ATA66_4 1
442#define HPT366_ALLOW_ATA66_3 1
443#define HPT366_MAX_DEVS 8
444
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100445/* Supported ATA clock frequencies */
446enum ata_clock {
447 ATA_CLOCK_25MHZ,
448 ATA_CLOCK_33MHZ,
449 ATA_CLOCK_40MHZ,
450 ATA_CLOCK_50MHZ,
451 ATA_CLOCK_66MHZ,
452 NUM_ATA_CLOCKS
Alan Coxb39b01f2005-06-27 15:24:27 -0700453};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100455struct hpt_timings {
456 u32 pio_mask;
457 u32 dma_mask;
458 u32 ultra_mask;
459 u32 *clock_table[NUM_ATA_CLOCKS];
460};
461
Alan Coxb39b01f2005-06-27 15:24:27 -0700462/*
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100463 * Hold all the HighPoint chip information in one place.
Alan Coxb39b01f2005-06-27 15:24:27 -0700464 */
465
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100466struct hpt_info {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200467 char *chip_name; /* Chip name */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100468 u8 chip_type; /* Chip type */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200469 u8 udma_mask; /* Allowed UltraDMA modes mask. */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100470 u8 dpll_clk; /* DPLL clock in MHz */
471 u8 pci_clk; /* PCI clock in MHz */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100472 struct hpt_timings *timings; /* Chipset timing data */
473 u8 clock; /* ATA clock selected */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100474};
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100475
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100476/* Supported HighPoint chips */
477enum {
478 HPT36x,
479 HPT370,
480 HPT370A,
481 HPT374,
482 HPT372,
483 HPT372A,
484 HPT302,
485 HPT371,
486 HPT372N,
487 HPT302N,
488 HPT371N
489};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100491static struct hpt_timings hpt36x_timings = {
492 .pio_mask = 0xc1f8ffff,
493 .dma_mask = 0x303800ff,
494 .ultra_mask = 0x30070000,
495 .clock_table = {
496 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
497 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
498 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
499 [ATA_CLOCK_50MHZ] = NULL,
500 [ATA_CLOCK_66MHZ] = NULL
501 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100502};
503
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100504static struct hpt_timings hpt37x_timings = {
505 .pio_mask = 0xcfc3ffff,
506 .dma_mask = 0x31c001ff,
507 .ultra_mask = 0x303c0000,
508 .clock_table = {
509 [ATA_CLOCK_25MHZ] = NULL,
510 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
511 [ATA_CLOCK_40MHZ] = NULL,
512 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
513 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
514 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100515};
516
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200517static const struct hpt_info hpt36x __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200518 .chip_name = "HPT36x",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100519 .chip_type = HPT36x,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200520 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100521 .dpll_clk = 0, /* no DPLL */
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100522 .timings = &hpt36x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100523};
524
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200525static const struct hpt_info hpt370 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200526 .chip_name = "HPT370",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100527 .chip_type = HPT370,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200528 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100529 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100530 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100531};
532
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200533static const struct hpt_info hpt370a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200534 .chip_name = "HPT370A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100535 .chip_type = HPT370A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200536 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100537 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100538 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100539};
540
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200541static const struct hpt_info hpt374 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200542 .chip_name = "HPT374",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100543 .chip_type = HPT374,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200544 .udma_mask = ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100545 .dpll_clk = 48,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100546 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100547};
548
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200549static const struct hpt_info hpt372 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200550 .chip_name = "HPT372",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100551 .chip_type = HPT372,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200552 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100553 .dpll_clk = 55,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100554 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100555};
556
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200557static const struct hpt_info hpt372a __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200558 .chip_name = "HPT372A",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100559 .chip_type = HPT372A,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200560 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100561 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100562 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100563};
564
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200565static const struct hpt_info hpt302 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200566 .chip_name = "HPT302",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100567 .chip_type = HPT302,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200568 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100569 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100570 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100571};
572
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200573static const struct hpt_info hpt371 __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200574 .chip_name = "HPT371",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100575 .chip_type = HPT371,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200576 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100577 .dpll_clk = 66,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100578 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100579};
580
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200581static const struct hpt_info hpt372n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200582 .chip_name = "HPT372N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100583 .chip_type = HPT372N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200584 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100585 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100586 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100587};
588
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200589static const struct hpt_info hpt302n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200590 .chip_name = "HPT302N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100591 .chip_type = HPT302N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200592 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100593 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100594 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100595};
596
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +0200597static const struct hpt_info hpt371n __devinitdata = {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200598 .chip_name = "HPT371N",
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100599 .chip_type = HPT371N,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +0200600 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100601 .dpll_clk = 77,
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100602 .timings = &hpt37x_timings
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100603};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100605static int check_in_drive_list(ide_drive_t *drive, const char **list)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200607 char *m = (char *)&drive->id[ATA_ID_PROD];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100609 while (*list)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200610 if (!strcmp(*list++, m))
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100611 return 1;
612 return 0;
613}
Alan Coxb39b01f2005-06-27 15:24:27 -0700614
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200615static struct hpt_info *hpt3xx_get_info(struct device *dev)
616{
617 struct ide_host *host = dev_get_drvdata(dev);
618 struct hpt_info *info = (struct hpt_info *)host->host_priv;
619
620 return dev == host->dev[1] ? info + 1 : info;
621}
622
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623/*
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200624 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
625 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
Linus Torvalds1da177e2005-04-16 15:20:36 -0700626 */
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200627
628static u8 hpt3xx_udma_filter(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629{
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200630 ide_hwif_t *hwif = HWIF(drive);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200631 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200632 u8 mask = hwif->ultra_mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200634 switch (info->chip_type) {
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200635 case HPT36x:
636 if (!HPT366_ALLOW_ATA66_4 ||
637 check_in_drive_list(drive, bad_ata66_4))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200638 mask = ATA_UDMA3;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100639
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200640 if (!HPT366_ALLOW_ATA66_3 ||
641 check_in_drive_list(drive, bad_ata66_3))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200642 mask = ATA_UDMA2;
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200643 break;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200644 case HPT370:
645 if (!HPT370_ALLOW_ATA100_5 ||
646 check_in_drive_list(drive, bad_ata100_5))
647 mask = ATA_UDMA4;
648 break;
649 case HPT370A:
650 if (!HPT370_ALLOW_ATA100_5 ||
651 check_in_drive_list(drive, bad_ata100_5))
652 return ATA_UDMA4;
653 case HPT372 :
654 case HPT372A:
655 case HPT372N:
656 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200657 if (ata_id_is_sata(drive->id))
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200658 mask &= ~0x0e;
659 /* Fall thru */
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200660 default:
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +0200661 return mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 }
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +0200663
664 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665}
666
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200667static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
668{
669 ide_hwif_t *hwif = HWIF(drive);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200670 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200671
672 switch (info->chip_type) {
673 case HPT372 :
674 case HPT372A:
675 case HPT372N:
676 case HPT374 :
Bartlomiej Zolnierkiewicz367d7e72008-10-10 22:39:30 +0200677 if (ata_id_is_sata(drive->id))
Sergei Shtylyovb4e44362007-10-11 23:53:58 +0200678 return 0x00;
679 /* Fall thru */
680 default:
681 return 0x07;
682 }
683}
684
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100685static u32 get_speed_setting(u8 speed, struct hpt_info *info)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686{
Sergei Shtylyov471a0bd2006-12-13 00:35:49 -0800687 int i;
688
689 /*
690 * Lookup the transfer mode table to get the index into
691 * the timing table.
692 *
693 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
694 */
695 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
696 if (xfer_speeds[i] == speed)
697 break;
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100698
699 return info->timings->clock_table[info->clock][i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700}
701
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100702static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703{
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +0200704 ide_hwif_t *hwif = drive->hwif;
705 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200706 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100707 struct hpt_timings *t = info->timings;
708 u8 itr_addr = 0x40 + (drive->dn * 4);
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100709 u32 old_itr = 0;
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100710 u32 new_itr = get_speed_setting(speed, info);
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100711 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
712 (speed < XFER_UDMA_0 ? t->dma_mask :
713 t->ultra_mask);
Bartlomiej Zolnierkiewicz2d5eaa62007-05-10 00:01:08 +0200714
Sergei Shtylyovceb1b2c2008-01-25 22:17:04 +0100715 pci_read_config_dword(dev, itr_addr, &old_itr);
716 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 /*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100718 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
719 * to avoid problems handling I/O errors later
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100721 new_itr &= ~0xc0000000;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700722
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100723 pci_write_config_dword(dev, itr_addr, new_itr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700724}
725
Bartlomiej Zolnierkiewicz26bcb872007-10-11 23:54:00 +0200726static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727{
Sergei Shtylyov866664d2008-01-25 22:17:05 +0100728 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729}
730
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100731static void hpt3xx_quirkproc(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732{
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200733 char *m = (char *)&drive->id[ATA_ID_PROD];
Sergei Shtylyove139b0b2007-02-07 18:17:37 +0100734 const char **list = quirk_drives;
735
736 while (*list)
Bartlomiej Zolnierkiewicz4dde4492008-10-10 22:39:19 +0200737 if (strstr(m, *list++)) {
Bartlomiej Zolnierkiewiczf01393e2008-01-26 20:13:03 +0100738 drive->quirk_list = 1;
739 return;
740 }
741
742 drive->quirk_list = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743}
744
Sergei Shtylyov26ccb802007-02-07 18:18:11 +0100745static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100747 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100748 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +0200749 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750
751 if (drive->quirk_list) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100752 if (info->chip_type >= HPT370) {
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100753 u8 scr1 = 0;
754
755 pci_read_config_byte(dev, 0x5a, &scr1);
756 if (((scr1 & 0x10) >> 4) != mask) {
757 if (mask)
758 scr1 |= 0x10;
759 else
760 scr1 &= ~0x10;
761 pci_write_config_byte(dev, 0x5a, scr1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762 }
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100763 } else {
764 if (mask)
765 disable_irq(hwif->irq);
766 else
767 enable_irq (hwif->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768 }
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100769 } else
Bartlomiej Zolnierkiewiczff074882008-07-15 21:21:50 +0200770 outb(ATA_DEVCTL_OBS | (mask ? 2 : 0), hwif->io_ports.ctl_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771}
772
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773/*
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100774 * This is specific to the HPT366 UDMA chipset
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 * by HighPoint|Triones Technologies, Inc.
776 */
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200777static void hpt366_dma_lost_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100779 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100780 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100782 pci_read_config_byte(dev, 0x50, &mcr1);
783 pci_read_config_byte(dev, 0x52, &mcr3);
784 pci_read_config_byte(dev, 0x5a, &scr1);
785 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
Harvey Harrisoneb639632008-04-26 22:25:20 +0200786 drive->name, __func__, mcr1, mcr3, scr1);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100787 if (scr1 & 0x10)
788 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov841d2a92007-07-09 23:17:54 +0200789 ide_dma_lost_irq(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790}
791
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100792static void hpt370_clear_engine(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700793{
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100794 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100795 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100796
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100797 pci_write_config_byte(dev, hwif->select_data, 0x37);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798 udelay(10);
799}
800
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100801static void hpt370_irq_timeout(ide_drive_t *drive)
802{
803 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100804 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100805 u16 bfifo = 0;
806 u8 dma_cmd;
807
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100808 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100809 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
810
811 /* get DMA command mode */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200812 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100813 /* stop DMA */
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200814 outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100815 hpt370_clear_engine(drive);
816}
817
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200818static void hpt370_dma_start(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819{
820#ifdef HPT_RESET_STATE_ENGINE
821 hpt370_clear_engine(drive);
822#endif
823 ide_dma_start(drive);
824}
825
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200826static int hpt370_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827{
828 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200829 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830
831 if (dma_stat & 0x01) {
832 /* wait a little */
833 udelay(20);
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200834 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100835 if (dma_stat & 0x01)
836 hpt370_irq_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700837 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 return __ide_dma_end(drive);
839}
840
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200841static void hpt370_dma_timeout(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842{
Sergei Shtylyov4bf63de2007-02-07 18:18:13 +0100843 hpt370_irq_timeout(drive);
Sergei Shtylyovc283f5d2007-07-09 23:17:54 +0200844 ide_dma_timeout(drive);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845}
846
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847/* returns 1 if DMA IRQ issued, 0 otherwise */
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200848static int hpt374_dma_test_irq(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849{
850 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100851 struct pci_dev *dev = to_pci_dev(hwif->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852 u16 bfifo = 0;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100853 u8 dma_stat;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100855 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700856 if (bfifo & 0x1FF) {
857// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
858 return 0;
859 }
860
Bartlomiej Zolnierkiewiczcab7f8e2008-07-23 19:55:51 +0200861 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 /* return 1 if INTR asserted */
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100863 if (dma_stat & 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864 return 1;
865
866 if (!drive->waiting_for_dma)
867 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
Harvey Harrisoneb639632008-04-26 22:25:20 +0200868 drive->name, __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869 return 0;
870}
871
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +0200872static int hpt374_dma_end(ide_drive_t *drive)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874 ide_hwif_t *hwif = HWIF(drive);
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +0100875 struct pci_dev *dev = to_pci_dev(hwif->dev);
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100876 u8 mcr = 0, mcr_addr = hwif->select_data;
877 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +0100879 pci_read_config_byte(dev, 0x6a, &bwsr);
880 pci_read_config_byte(dev, mcr_addr, &mcr);
881 if (bwsr & mask)
882 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 return __ide_dma_end(drive);
884}
885
886/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800887 * hpt3xxn_set_clock - perform clock switching dance
888 * @hwif: hwif to switch
889 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800891 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 */
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800893
894static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895{
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100896 unsigned long base = hwif->extra_base;
897 u8 scr2 = inb(base + 0x6b);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800898
899 if ((scr2 & 0x7f) == mode)
900 return;
901
Linus Torvalds1da177e2005-04-16 15:20:36 -0700902 /* Tristate the bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100903 outb(0x80, base + 0x63);
904 outb(0x80, base + 0x67);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800905
Linus Torvalds1da177e2005-04-16 15:20:36 -0700906 /* Switch clock and reset channels */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100907 outb(mode, base + 0x6b);
908 outb(0xc0, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800909
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100910 /*
911 * Reset the state machines.
912 * NOTE: avoid accidentally enabling the disabled channels.
913 */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100914 outb(inb(base + 0x60) | 0x32, base + 0x60);
915 outb(inb(base + 0x64) | 0x32, base + 0x64);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800916
Linus Torvalds1da177e2005-04-16 15:20:36 -0700917 /* Complete reset */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100918 outb(0x00, base + 0x69);
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800919
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 /* Reconnect channels to bus */
Bartlomiej Zolnierkiewicz1c029fd2008-01-25 22:17:05 +0100921 outb(0x00, base + 0x63);
922 outb(0x00, base + 0x67);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700923}
924
925/**
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800926 * hpt3xxn_rw_disk - prepare for I/O
Linus Torvalds1da177e2005-04-16 15:20:36 -0700927 * @drive: drive for command
928 * @rq: block request structure
929 *
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800930 * This is called when a disk I/O is issued to HPT3xxN.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931 * We need it because of the clock switching.
932 */
933
Sergei Shtylyov836c0062006-12-13 00:35:47 -0800934static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100936 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700937}
938
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100939/**
940 * hpt37x_calibrate_dpll - calibrate the DPLL
941 * @dev: PCI device
942 *
943 * Perform a calibration cycle on the DPLL.
944 * Returns 1 if this succeeds
945 */
946static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700947{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100948 u32 dpll = (f_high << 16) | f_low | 0x100;
949 u8 scr2;
950 int i;
Alan Coxb39b01f2005-06-27 15:24:27 -0700951
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100952 pci_write_config_dword(dev, 0x5c, dpll);
Alan Coxb39b01f2005-06-27 15:24:27 -0700953
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100954 /* Wait for oscillator ready */
955 for(i = 0; i < 0x5000; ++i) {
956 udelay(50);
957 pci_read_config_byte(dev, 0x5b, &scr2);
958 if (scr2 & 0x80)
Alan Coxb39b01f2005-06-27 15:24:27 -0700959 break;
960 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100961 /* See if it stays ready (we'll just bail out if it's not yet) */
962 for(i = 0; i < 0x1000; ++i) {
963 pci_read_config_byte(dev, 0x5b, &scr2);
964 /* DPLL destabilized? */
965 if(!(scr2 & 0x80))
966 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +0100967 }
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +0100968 /* Turn off tuning, we have the DPLL set */
969 pci_read_config_dword (dev, 0x5c, &dpll);
970 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
971 return 1;
Alan Coxb39b01f2005-06-27 15:24:27 -0700972}
973
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +0200974static void __devinit hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
975{
976 struct ide_host *host = pci_get_drvdata(dev);
977 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
978 u8 chip_type = info->chip_type;
979 u8 new_mcr, old_mcr = 0;
980
981 /*
982 * Disable the "fast interrupt" prediction. Don't hold off
983 * on interrupts. (== 0x01 despite what the docs say)
984 */
985 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
986
987 if (chip_type >= HPT374)
988 new_mcr = old_mcr & ~0x07;
989 else if (chip_type >= HPT370) {
990 new_mcr = old_mcr;
991 new_mcr &= ~0x02;
992#ifdef HPT_DELAY_INTERRUPT
993 new_mcr &= ~0x01;
994#else
995 new_mcr |= 0x01;
996#endif
997 } else /* HPT366 and HPT368 */
998 new_mcr = old_mcr & ~0x80;
999
1000 if (new_mcr != old_mcr)
1001 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
1002}
1003
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +02001004static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005{
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001006 unsigned long io_base = pci_resource_start(dev, 4);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001007 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
Bartlomiej Zolnierkiewicza326b022008-07-24 22:53:33 +02001008 const char *name = DRV_NAME;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001009 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001010 u8 chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001011 enum ata_clock clock;
1012
Sergei Shtylyov72931362007-09-11 22:28:35 +02001013 chip_type = info->chip_type;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001014
Alan Coxb39b01f2005-06-27 15:24:27 -07001015 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1016 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1017 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1018 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001019
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001020 /*
1021 * First, try to estimate the PCI clock frequency...
1022 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001023 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001024 u8 scr1 = 0;
1025 u16 f_cnt = 0;
1026 u32 temp = 0;
Alan Coxb39b01f2005-06-27 15:24:27 -07001027
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001028 /* Interrupt force enable. */
1029 pci_read_config_byte(dev, 0x5a, &scr1);
1030 if (scr1 & 0x10)
1031 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001032
1033 /*
1034 * HighPoint does this for HPT372A.
1035 * NOTE: This register is only writeable via I/O space.
1036 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001037 if (chip_type == HPT372A)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001038 outb(0x0e, io_base + 0x9c);
1039
1040 /*
1041 * Default to PCI clock. Make sure MA15/16 are set to output
1042 * to prevent drives having problems with 40-pin cables.
1043 */
1044 pci_write_config_byte(dev, 0x5b, 0x23);
1045
1046 /*
1047 * We'll have to read f_CNT value in order to determine
1048 * the PCI clock frequency according to the following ratio:
1049 *
1050 * f_CNT = Fpci * 192 / Fdpll
1051 *
1052 * First try reading the register in which the HighPoint BIOS
1053 * saves f_CNT value before reprogramming the DPLL from its
1054 * default setting (which differs for the various chips).
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001055 *
Sergei Shtylyov72931362007-09-11 22:28:35 +02001056 * NOTE: This register is only accessible via I/O space;
1057 * HPT374 BIOS only saves it for the function 0, so we have to
1058 * always read it from there -- no need to check the result of
1059 * pci_get_slot() for the function 0 as the whole device has
1060 * been already "pinned" (via function 1) in init_setup_hpt374()
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001061 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001062 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1063 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1064 dev->devfn - 1);
1065 unsigned long io_base = pci_resource_start(dev1, 4);
1066
1067 temp = inl(io_base + 0x90);
1068 pci_dev_put(dev1);
1069 } else
1070 temp = inl(io_base + 0x90);
1071
1072 /*
1073 * In case the signature check fails, we'll have to
1074 * resort to reading the f_CNT register itself in hopes
1075 * that nobody has touched the DPLL yet...
1076 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001077 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1078 int i;
1079
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001080 printk(KERN_WARNING "%s %s: no clock data saved by "
1081 "BIOS\n", name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001082
1083 /* Calculate the average value of f_CNT. */
1084 for (temp = i = 0; i < 128; i++) {
1085 pci_read_config_word(dev, 0x78, &f_cnt);
1086 temp += f_cnt & 0x1ff;
1087 mdelay(1);
1088 }
1089 f_cnt = temp / 128;
1090 } else
1091 f_cnt = temp & 0x1ff;
1092
1093 dpll_clk = info->dpll_clk;
1094 pci_clk = (f_cnt * dpll_clk) / 192;
1095
1096 /* Clamp PCI clock to bands. */
1097 if (pci_clk < 40)
1098 pci_clk = 33;
1099 else if(pci_clk < 45)
1100 pci_clk = 40;
1101 else if(pci_clk < 55)
1102 pci_clk = 50;
1103 else
1104 pci_clk = 66;
1105
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001106 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1107 "assuming %d MHz PCI\n", name, pci_name(dev),
1108 dpll_clk, f_cnt, pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001109 } else {
1110 u32 itr1 = 0;
1111
1112 pci_read_config_dword(dev, 0x40, &itr1);
1113
1114 /* Detect PCI clock by looking at cmd_high_time. */
1115 switch((itr1 >> 8) & 0x07) {
1116 case 0x09:
1117 pci_clk = 40;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001118 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001119 case 0x05:
1120 pci_clk = 25;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001121 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001122 case 0x07:
1123 default:
1124 pci_clk = 33;
Sergei Shtylyov6273d262007-02-07 18:18:20 +01001125 break;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001126 }
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001127 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001128
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001129 /* Let's assume we'll use PCI clock for the ATA clock... */
1130 switch (pci_clk) {
1131 case 25:
1132 clock = ATA_CLOCK_25MHZ;
1133 break;
1134 case 33:
1135 default:
1136 clock = ATA_CLOCK_33MHZ;
1137 break;
1138 case 40:
1139 clock = ATA_CLOCK_40MHZ;
1140 break;
1141 case 50:
1142 clock = ATA_CLOCK_50MHZ;
1143 break;
1144 case 66:
1145 clock = ATA_CLOCK_66MHZ;
1146 break;
1147 }
1148
1149 /*
1150 * Only try the DPLL if we don't have a table for the PCI clock that
1151 * we are running at for HPT370/A, always use it for anything newer...
1152 *
1153 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1154 * We also don't like using the DPLL because this causes glitches
1155 * on PRST-/SRST- when the state engine gets reset...
1156 */
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001157 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001158 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1159 int adjust;
1160
1161 /*
1162 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1163 * supported/enabled, use 50 MHz DPLL clock otherwise...
1164 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001165 if (info->udma_mask == ATA_UDMA6) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001166 dpll_clk = 66;
1167 clock = ATA_CLOCK_66MHZ;
1168 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1169 dpll_clk = 50;
1170 clock = ATA_CLOCK_50MHZ;
1171 }
1172
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001173 if (info->timings->clock_table[clock] == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001174 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1175 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001176 return -EIO;
1177 }
1178
1179 /* Select the DPLL clock. */
1180 pci_write_config_byte(dev, 0x5b, 0x21);
1181
1182 /*
1183 * Adjust the DPLL based upon PCI clock, enable it,
1184 * and wait for stabilization...
1185 */
1186 f_low = (pci_clk * 48) / dpll_clk;
1187
1188 for (adjust = 0; adjust < 8; adjust++) {
1189 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1190 break;
1191
1192 /*
1193 * See if it'll settle at a fractionally different clock
1194 */
1195 if (adjust & 1)
1196 f_low -= adjust >> 1;
1197 else
1198 f_low += adjust >> 1;
1199 }
1200 if (adjust == 8) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001201 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1202 name, pci_name(dev));
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001203 return -EIO;
1204 }
1205
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001206 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1207 name, pci_name(dev), dpll_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001208 } else {
1209 /* Mark the fact that we're not using the DPLL. */
1210 dpll_clk = 0;
1211
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001212 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1213 name, pci_name(dev), pci_clk);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001214 }
1215
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001216 /* Store the clock frequencies. */
1217 info->dpll_clk = dpll_clk;
1218 info->pci_clk = pci_clk;
Sergei Shtylyov866664d2008-01-25 22:17:05 +01001219 info->clock = clock;
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001220
Sergei Shtylyov72931362007-09-11 22:28:35 +02001221 if (chip_type >= HPT370) {
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001222 u8 mcr1, mcr4;
1223
1224 /*
1225 * Reset the state engines.
1226 * NOTE: Avoid accidentally enabling the disabled channels.
1227 */
1228 pci_read_config_byte (dev, 0x50, &mcr1);
1229 pci_read_config_byte (dev, 0x54, &mcr4);
1230 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1231 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1232 udelay(100);
1233 }
1234
1235 /*
1236 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1237 * the MISC. register to stretch the UltraDMA Tss timing.
1238 * NOTE: This register is only writeable via I/O space.
1239 */
Sergei Shtylyov72931362007-09-11 22:28:35 +02001240 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001241 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1242
Bartlomiej Zolnierkiewicz17851922008-10-10 22:39:32 +02001243 hpt3xx_disable_fast_irq(dev, 0x50);
1244 hpt3xx_disable_fast_irq(dev, 0x54);
1245
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 return dev->irq;
1247}
1248
Bartlomiej Zolnierkiewiczf454cbe2008-08-05 18:17:04 +02001249static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001250{
1251 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001252 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Bartlomiej Zolnierkiewiczbfa14b42008-02-02 19:56:31 +01001253 u8 chip_type = info->chip_type;
1254 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1255
1256 /*
1257 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1258 * address lines to access an external EEPROM. To read valid
1259 * cable detect state the pins must be enabled as inputs.
1260 */
1261 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1262 /*
1263 * HPT374 PCI function 1
1264 * - set bit 15 of reg 0x52 to enable TCBLID as input
1265 * - set bit 15 of reg 0x56 to enable FCBLID as input
1266 */
1267 u8 mcr_addr = hwif->select_data + 2;
1268 u16 mcr;
1269
1270 pci_read_config_word(dev, mcr_addr, &mcr);
1271 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1272 /* now read cable id register */
1273 pci_read_config_byte(dev, 0x5a, &scr1);
1274 pci_write_config_word(dev, mcr_addr, mcr);
1275 } else if (chip_type >= HPT370) {
1276 /*
1277 * HPT370/372 and 374 pcifn 0
1278 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1279 */
1280 u8 scr2 = 0;
1281
1282 pci_read_config_byte(dev, 0x5b, &scr2);
1283 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1284 /* now read cable id register */
1285 pci_read_config_byte(dev, 0x5a, &scr1);
1286 pci_write_config_byte(dev, 0x5b, scr2);
1287 } else
1288 pci_read_config_byte(dev, 0x5a, &scr1);
1289
1290 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1291}
1292
Linus Torvalds1da177e2005-04-16 15:20:36 -07001293static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1294{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001295 struct pci_dev *dev = to_pci_dev(hwif->dev);
Masoud Sharbiani62ff2ec2008-09-10 22:22:34 +02001296 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001297 int serialize = HPT_SERIALIZE_IO;
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001298 u8 chip_type = info->chip_type;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001299
1300 /* Cache the channel's MISC. control registers' offset */
Sergei Shtylyov2808b0a2007-09-11 22:28:36 +02001301 hwif->select_data = hwif->channel ? 0x54 : 0x50;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001302
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001303 /*
1304 * HPT3xxN chips have some complications:
1305 *
1306 * - on 33 MHz PCI we must clock switch
1307 * - on 66 MHz PCI we must NOT use the PCI clock
1308 */
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001309 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001310 /*
1311 * Clock is shared between the channels,
1312 * so we'll have to serialize them... :-(
1313 */
1314 serialize = 1;
1315 hwif->rw_disk = &hpt3xxn_rw_disk;
1316 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001317
Sergei Shtylyov26ccb802007-02-07 18:18:11 +01001318 /* Serialize access to this device if needed */
1319 if (serialize && hwif->mate)
1320 hwif->serialized = hwif->mate->serialized = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321}
1322
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001323static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1324 const struct ide_port_info *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001325{
Bartlomiej Zolnierkiewicz36501652008-02-01 23:09:31 +01001326 struct pci_dev *dev = to_pci_dev(hwif->dev);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001327 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1328 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001329
Bartlomiej Zolnierkiewiczebb00fb2008-07-23 19:55:51 +02001330 if (base == 0)
1331 return -1;
1332
1333 hwif->dma_base = base;
1334
1335 if (ide_pci_check_simplex(hwif, d) < 0)
1336 return -1;
1337
1338 if (ide_pci_set_master(dev, d->name) < 0)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001339 return -1;
1340
1341 dma_old = inb(base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001342
1343 local_irq_save(flags);
1344
1345 dma_new = dma_old;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001346 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1347 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348
1349 if (masterdma & 0x30) dma_new |= 0x20;
Sergei Shtylyovabc4ad42007-02-07 18:18:05 +01001350 if ( slavedma & 0x30) dma_new |= 0x40;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351 if (dma_new != dma_old)
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001352 outb(dma_new, base + 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001353
1354 local_irq_restore(flags);
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001355
1356 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1357 hwif->name, base, base + 7);
1358
1359 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1360
1361 if (ide_allocate_dma_engine(hwif))
1362 return -1;
1363
Bartlomiej Zolnierkiewicz81e8d5a2008-07-23 19:55:51 +02001364 hwif->dma_ops = &sff_dma_ops;
Bartlomiej Zolnierkiewiczb123f562008-04-26 22:25:22 +02001365
1366 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001367}
1368
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001369static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001371 if (dev2->irq != dev->irq) {
1372 /* FIXME: we need a core pci_set_interrupt() */
1373 dev2->irq = dev->irq;
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001374 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001375 "fixed\n", pci_name(dev2));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001376 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377}
1378
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001379static void __devinit hpt371_init(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380{
Auke Kok44c10132007-06-08 15:46:36 -07001381 u8 mcr1 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001382
Sergei Shtylyov836c0062006-12-13 00:35:47 -08001383 /*
1384 * HPT371 chips physically have only one channel, the secondary one,
1385 * but the primary channel registers do exist! Go figure...
1386 * So, we manually disable the non-existing channel here
1387 * (if the BIOS hasn't done this already).
1388 */
1389 pci_read_config_byte(dev, 0x50, &mcr1);
1390 if (mcr1 & 0x04)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001391 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001392}
1393
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001394static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
Sergei Shtylyov90778572007-02-07 18:17:51 +01001395{
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001396 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001397
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001398 /*
1399 * Now we'll have to force both channels enabled if
1400 * at least one of them has been enabled by BIOS...
1401 */
1402 pci_read_config_byte(dev, 0x50, &mcr1);
1403 if (mcr1 & 0x30)
1404 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
Sergei Shtylyov90778572007-02-07 18:17:51 +01001405
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001406 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1407 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001408
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001409 if (pin1 != pin2 && dev->irq == dev2->irq) {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001410 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001411 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001412 return 1;
1413 }
1414
1415 return 0;
Sergei Shtylyov90778572007-02-07 18:17:51 +01001416}
1417
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001418#define IDE_HFLAGS_HPT3XX \
1419 (IDE_HFLAG_NO_ATAPI_DMA | \
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001420 IDE_HFLAG_OFF_BOARD)
1421
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001422static const struct ide_port_ops hpt3xx_port_ops = {
1423 .set_pio_mode = hpt3xx_set_pio_mode,
1424 .set_dma_mode = hpt3xx_set_mode,
1425 .quirkproc = hpt3xx_quirkproc,
1426 .maskproc = hpt3xx_maskproc,
1427 .mdma_filter = hpt3xx_mdma_filter,
1428 .udma_filter = hpt3xx_udma_filter,
1429 .cable_detect = hpt3xx_cable_detect,
1430};
1431
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001432static const struct ide_dma_ops hpt37x_dma_ops = {
1433 .dma_host_set = ide_dma_host_set,
1434 .dma_setup = ide_dma_setup,
1435 .dma_exec_cmd = ide_dma_exec_cmd,
1436 .dma_start = ide_dma_start,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001437 .dma_end = hpt374_dma_end,
1438 .dma_test_irq = hpt374_dma_test_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001439 .dma_lost_irq = ide_dma_lost_irq,
1440 .dma_timeout = ide_dma_timeout,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001441};
1442
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001443static const struct ide_dma_ops hpt370_dma_ops = {
1444 .dma_host_set = ide_dma_host_set,
1445 .dma_setup = ide_dma_setup,
1446 .dma_exec_cmd = ide_dma_exec_cmd,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001447 .dma_start = hpt370_dma_start,
1448 .dma_end = hpt370_dma_end,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001449 .dma_test_irq = ide_dma_test_irq,
1450 .dma_lost_irq = ide_dma_lost_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001451 .dma_timeout = hpt370_dma_timeout,
1452};
1453
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001454static const struct ide_dma_ops hpt36x_dma_ops = {
1455 .dma_host_set = ide_dma_host_set,
1456 .dma_setup = ide_dma_setup,
1457 .dma_exec_cmd = ide_dma_exec_cmd,
1458 .dma_start = ide_dma_start,
1459 .dma_end = __ide_dma_end,
1460 .dma_test_irq = ide_dma_test_irq,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001461 .dma_lost_irq = hpt366_dma_lost_irq,
Bartlomiej Zolnierkiewiczf37afda2008-04-26 22:25:24 +02001462 .dma_timeout = ide_dma_timeout,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001463};
1464
Bartlomiej Zolnierkiewicz85620432007-10-20 00:32:34 +02001465static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001466 { /* 0: HPT36x */
1467 .name = DRV_NAME,
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001468 .init_chipset = init_chipset_hpt366,
1469 .init_hwif = init_hwif_hpt366,
1470 .init_dma = init_dma_hpt366,
Sergei Shtylyov2648e5d2007-07-09 23:17:55 +02001471 /*
1472 * HPT36x chips have one channel per function and have
1473 * both channel enable bits located differently and visible
1474 * to both functions -- really stupid design decision... :-(
1475 * Bit 4 is for the primary channel, bit 5 for the secondary.
1476 */
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001477 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001478 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001479 .dma_ops = &hpt36x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001480 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001481 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001482 .mwdma_mask = ATA_MWDMA2,
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001483 },
1484 { /* 1: HPT3xx */
1485 .name = DRV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486 .init_chipset = init_chipset_hpt366,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487 .init_hwif = init_hwif_hpt366,
1488 .init_dma = init_dma_hpt366,
Sergei Shtylyov7b73ee02007-02-07 18:18:16 +01001489 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
Bartlomiej Zolnierkiewiczac95bee2008-04-26 22:25:14 +02001490 .port_ops = &hpt3xx_port_ops,
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001491 .dma_ops = &hpt37x_dma_ops,
Bartlomiej Zolnierkiewicz4db90a12008-01-25 22:17:18 +01001492 .host_flags = IDE_HFLAGS_HPT3XX,
Bartlomiej Zolnierkiewicz4099d142007-07-20 01:11:59 +02001493 .pio_mask = ATA_PIO4,
Bartlomiej Zolnierkiewicz5f8b6c32007-10-19 00:30:07 +02001494 .mwdma_mask = ATA_MWDMA2,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495 }
1496};
1497
1498/**
1499 * hpt366_init_one - called when an HPT366 is found
1500 * @dev: the hpt366 device
1501 * @id: the matching pci id
1502 *
1503 * Called when the PCI registration layer (or the IDE initialization)
1504 * finds a device matching our IDE device tables.
1505 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001506static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1507{
Bartlomiej Zolnierkiewicz282037f2007-10-26 20:31:15 +02001508 const struct hpt_info *info = NULL;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001509 struct hpt_info *dyn_info;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001510 struct pci_dev *dev2 = NULL;
Bartlomiej Zolnierkiewicz039788e2007-10-20 00:32:34 +02001511 struct ide_port_info d;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001512 u8 idx = id->driver_data;
1513 u8 rev = dev->revision;
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001514 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001516 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1517 return -ENODEV;
1518
1519 switch (idx) {
1520 case 0:
1521 if (rev < 3)
1522 info = &hpt36x;
1523 else {
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001524 switch (min_t(u8, rev, 6)) {
1525 case 3: info = &hpt370; break;
1526 case 4: info = &hpt370a; break;
1527 case 5: info = &hpt372; break;
1528 case 6: info = &hpt372n; break;
1529 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001530 idx++;
1531 }
1532 break;
1533 case 1:
1534 info = (rev > 1) ? &hpt372n : &hpt372a;
1535 break;
1536 case 2:
1537 info = (rev > 1) ? &hpt302n : &hpt302;
1538 break;
1539 case 3:
1540 hpt371_init(dev);
1541 info = (rev > 1) ? &hpt371n : &hpt371;
1542 break;
1543 case 4:
1544 info = &hpt374;
1545 break;
1546 case 5:
1547 info = &hpt372n;
1548 break;
1549 }
1550
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001551 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001552
Bartlomiej Zolnierkiewiczced3ec82008-07-24 22:53:32 +02001553 d = hpt366_chipsets[min_t(u8, idx, 1)];
1554
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001555 d.udma_mask = info->udma_mask;
1556
Bartlomiej Zolnierkiewicz5e37bdc2008-04-26 22:25:24 +02001557 /* fixup ->dma_ops for HPT370/HPT370A */
1558 if (info == &hpt370 || info == &hpt370a)
1559 d.dma_ops = &hpt370_dma_ops;
1560
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001561 if (info == &hpt36x || info == &hpt374)
1562 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1563
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001564 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1565 if (dyn_info == NULL) {
Bartlomiej Zolnierkiewicz28cfd8a2008-07-24 22:53:31 +02001566 printk(KERN_ERR "%s %s: out of memory!\n",
1567 d.name, pci_name(dev));
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001568 pci_dev_put(dev2);
1569 return -ENOMEM;
1570 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001571
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001572 /*
1573 * Copy everything from a static "template" structure
1574 * to just allocated per-chip hpt_info structure.
1575 */
1576 memcpy(dyn_info, info, sizeof(*dyn_info));
1577
1578 if (dev2) {
1579 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001580
1581 if (info == &hpt374)
1582 hpt374_init(dev, dev2);
1583 else {
1584 if (hpt36x_init(dev, dev2))
Bartlomiej Zolnierkiewicz5e71d9c2008-04-26 17:36:35 +02001585 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001586 }
1587
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001588 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1589 if (ret < 0) {
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001590 pci_dev_put(dev2);
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001591 kfree(dyn_info);
1592 }
Bartlomiej Zolnierkiewiczfbf47842007-10-19 00:30:09 +02001593 return ret;
1594 }
1595
Bartlomiej Zolnierkiewicz74811f32008-07-24 22:53:15 +02001596 ret = ide_pci_init_one(dev, &d, dyn_info);
1597 if (ret < 0)
1598 kfree(dyn_info);
1599
1600 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601}
1602
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001603static void __devexit hpt366_remove(struct pci_dev *dev)
1604{
1605 struct ide_host *host = pci_get_drvdata(dev);
1606 struct ide_info *info = host->host_priv;
1607 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1608
1609 ide_pci_remove(dev);
1610 pci_dev_put(dev2);
1611 kfree(info);
1612}
1613
Sam Ravnborgb66cae72008-02-26 21:50:33 +01001614static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
Bartlomiej Zolnierkiewicz9cbcc5e2007-10-16 22:29:56 +02001615 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1616 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1617 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1618 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1619 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1620 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001621 { 0, },
1622};
1623MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1624
1625static struct pci_driver driver = {
1626 .name = "HPT366_IDE",
1627 .id_table = hpt366_pci_tbl,
1628 .probe = hpt366_init_one,
Adrian Bunka69999e2008-08-18 21:40:03 +02001629 .remove = __devexit_p(hpt366_remove),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630};
1631
Bartlomiej Zolnierkiewicz82ab1ee2007-01-27 13:46:56 +01001632static int __init hpt366_ide_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633{
1634 return ide_pci_register_driver(&driver);
1635}
1636
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001637static void __exit hpt366_ide_exit(void)
1638{
1639 pci_unregister_driver(&driver);
1640}
1641
Linus Torvalds1da177e2005-04-16 15:20:36 -07001642module_init(hpt366_ide_init);
Bartlomiej Zolnierkiewicza6c43a22008-07-24 22:53:21 +02001643module_exit(hpt366_ide_exit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001644
1645MODULE_AUTHOR("Andre Hedrick");
1646MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1647MODULE_LICENSE("GPL");