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Daniel Schellera96e5ab2017-07-29 07:28:36 -04001/*
Daniel Scheller22e74382017-08-12 07:55:52 -04002 * ddbridge-i2c.c: Digital Devices bridge i2c driver
Daniel Schellera96e5ab2017-07-29 07:28:36 -04003 *
Daniel Scheller22e74382017-08-12 07:55:52 -04004 * Copyright (C) 2010-2017 Digital Devices GmbH
5 * Ralph Metzler <rjkm@metzlerbros.de>
6 * Marcus Metzler <mocm@metzlerbros.de>
Daniel Schellera96e5ab2017-07-29 07:28:36 -04007 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 only, as published by the Free Software Foundation.
11 *
Daniel Schellera96e5ab2017-07-29 07:28:36 -040012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
Daniel Schellera96e5ab2017-07-29 07:28:36 -040017 */
18
Daniel Schellera96e5ab2017-07-29 07:28:36 -040019#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/delay.h>
23#include <linux/slab.h>
24#include <linux/poll.h>
25#include <linux/io.h>
26#include <linux/pci.h>
27#include <linux/pci_ids.h>
28#include <linux/timer.h>
29#include <linux/i2c.h>
30#include <linux/swab.h>
31#include <linux/vmalloc.h>
32
33#include "ddbridge.h"
Daniel Schellera96e5ab2017-07-29 07:28:36 -040034#include "ddbridge-i2c.h"
Daniel Scheller22e74382017-08-12 07:55:52 -040035#include "ddbridge-regs.h"
Daniel Scheller14e27a12017-08-12 07:55:53 -040036#include "ddbridge-io.h"
Daniel Schellera96e5ab2017-07-29 07:28:36 -040037
38/******************************************************************************/
39
40static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd)
41{
42 struct ddb *dev = i2c->dev;
Daniel Scheller22e74382017-08-12 07:55:52 -040043 unsigned long stat;
Daniel Schellera96e5ab2017-07-29 07:28:36 -040044 u32 val;
45
Daniel Scheller22e74382017-08-12 07:55:52 -040046 ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND);
47 stat = wait_for_completion_timeout(&i2c->completion, HZ);
48 val = ddbreadl(dev, i2c->regs + I2C_COMMAND);
Daniel Schellera96e5ab2017-07-29 07:28:36 -040049 if (stat == 0) {
Daniel Scheller22e74382017-08-12 07:55:52 -040050 dev_err(dev->dev, "I2C timeout, card %d, port %d, link %u\n",
51 dev->nr, i2c->nr, i2c->link);
52 {
53 u32 istat = ddbreadl(dev, INTERRUPT_STATUS);
54
55 dev_err(dev->dev, "DDBridge IRS %08x\n", istat);
56 if (i2c->link) {
57 u32 listat = ddbreadl(dev,
58 DDB_LINK_TAG(i2c->link) |
59 INTERRUPT_STATUS);
60
61 dev_err(dev->dev, "DDBridge link %u IRS %08x\n",
62 i2c->link, listat);
63 }
64 if (istat & 1) {
65 ddbwritel(dev, istat & 1, INTERRUPT_ACK);
66 } else {
67 u32 mon = ddbreadl(dev,
68 i2c->regs + I2C_MONITOR);
69
70 dev_err(dev->dev, "I2C cmd=%08x mon=%08x\n",
71 val, mon);
72 }
Daniel Schellera96e5ab2017-07-29 07:28:36 -040073 }
74 return -EIO;
75 }
Daniel Schellera96e5ab2017-07-29 07:28:36 -040076 if (val & 0x70000)
77 return -EIO;
78 return 0;
79}
80
81static int ddb_i2c_master_xfer(struct i2c_adapter *adapter,
82 struct i2c_msg msg[], int num)
83{
Daniel Scheller22e74382017-08-12 07:55:52 -040084 struct ddb_i2c *i2c = (struct ddb_i2c *) i2c_get_adapdata(adapter);
Daniel Schellera96e5ab2017-07-29 07:28:36 -040085 struct ddb *dev = i2c->dev;
86 u8 addr = 0;
87
Daniel Scheller22e74382017-08-12 07:55:52 -040088 addr = msg[0].addr;
89 if (msg[0].len > i2c->bsize)
90 return -EIO;
91 switch (num) {
92 case 1:
93 if (msg[0].flags & I2C_M_RD) {
94 ddbwritel(dev, msg[0].len << 16,
95 i2c->regs + I2C_TASKLENGTH);
96 if (ddb_i2c_cmd(i2c, addr, 3))
97 break;
98 ddbcpyfrom(dev, msg[0].buf,
99 i2c->rbuf, msg[0].len);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400100 return num;
101 }
Daniel Scheller22e74382017-08-12 07:55:52 -0400102 ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
103 ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH);
104 if (ddb_i2c_cmd(i2c, addr, 2))
105 break;
106 return num;
107 case 2:
108 if ((msg[0].flags & I2C_M_RD) == I2C_M_RD)
109 break;
110 if ((msg[1].flags & I2C_M_RD) != I2C_M_RD)
111 break;
112 if (msg[1].len > i2c->bsize)
113 break;
114 ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len);
115 ddbwritel(dev, msg[0].len | (msg[1].len << 16),
116 i2c->regs + I2C_TASKLENGTH);
117 if (ddb_i2c_cmd(i2c, addr, 1))
118 break;
119 ddbcpyfrom(dev, msg[1].buf,
120 i2c->rbuf,
121 msg[1].len);
122 return num;
123 default:
124 break;
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400125 }
126 return -EIO;
127}
128
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400129static u32 ddb_i2c_functionality(struct i2c_adapter *adap)
130{
Daniel Scheller22e74382017-08-12 07:55:52 -0400131 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400132}
133
134static const struct i2c_algorithm ddb_i2c_algo = {
135 .master_xfer = ddb_i2c_master_xfer,
136 .functionality = ddb_i2c_functionality,
137};
138
139void ddb_i2c_release(struct ddb *dev)
140{
141 int i;
142 struct ddb_i2c *i2c;
Daniel Scheller22e74382017-08-12 07:55:52 -0400143
144 for (i = 0; i < dev->i2c_num; i++) {
145 i2c = &dev->i2c[i];
146 i2c_del_adapter(&i2c->adap);
147 }
148}
149
150static void i2c_handler(unsigned long priv)
151{
152 struct ddb_i2c *i2c = (struct ddb_i2c *) priv;
153
154 complete(&i2c->completion);
155}
156
157static int ddb_i2c_add(struct ddb *dev, struct ddb_i2c *i2c,
158 struct ddb_regmap *regmap, int link, int i, int num)
159{
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400160 struct i2c_adapter *adap;
161
Daniel Scheller22e74382017-08-12 07:55:52 -0400162 i2c->nr = i;
163 i2c->dev = dev;
164 i2c->link = link;
165 i2c->bsize = regmap->i2c_buf->size;
166 i2c->wbuf = DDB_LINK_TAG(link) |
167 (regmap->i2c_buf->base + i2c->bsize * i);
168 i2c->rbuf = i2c->wbuf; /* + i2c->bsize / 2 */
169 i2c->regs = DDB_LINK_TAG(link) |
170 (regmap->i2c->base + regmap->i2c->size * i);
171 ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING);
172 ddbwritel(dev, ((i2c->rbuf & 0xffff) << 16) | (i2c->wbuf & 0xffff),
173 i2c->regs + I2C_TASKADDRESS);
174 init_completion(&i2c->completion);
175
176 adap = &i2c->adap;
177 i2c_set_adapdata(adap, i2c);
178#ifdef I2C_ADAP_CLASS_TV_DIGITAL
179 adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG;
180#else
181#ifdef I2C_CLASS_TV_ANALOG
182 adap->class = I2C_CLASS_TV_ANALOG;
183#endif
184#endif
185 snprintf(adap->name, I2C_NAME_SIZE, "ddbridge_%02x.%x.%x",
186 dev->nr, i2c->link, i);
187 adap->algo = &ddb_i2c_algo;
188 adap->algo_data = (void *)i2c;
189 adap->dev.parent = dev->dev;
190 return i2c_add_adapter(adap);
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400191}
192
193int ddb_i2c_init(struct ddb *dev)
194{
Daniel Scheller22e74382017-08-12 07:55:52 -0400195 int stat = 0;
196 u32 i, j, num = 0, l, base;
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400197 struct ddb_i2c *i2c;
198 struct i2c_adapter *adap;
Daniel Scheller22e74382017-08-12 07:55:52 -0400199 struct ddb_regmap *regmap;
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400200
Daniel Scheller22e74382017-08-12 07:55:52 -0400201 for (l = 0; l < DDB_MAX_LINK; l++) {
202 if (!dev->link[l].info)
203 continue;
204 regmap = dev->link[l].info->regmap;
205 if (!regmap || !regmap->i2c)
206 continue;
207 base = regmap->irq_base_i2c;
208 for (i = 0; i < regmap->i2c->num; i++) {
209 if (!(dev->link[l].info->i2c_mask & (1 << i)))
210 continue;
211 i2c = &dev->i2c[num];
212 dev->handler_data[l][i + base] = (unsigned long) i2c;
213 dev->handler[l][i + base] = i2c_handler;
214 stat = ddb_i2c_add(dev, i2c, regmap, l, i, num);
215 if (stat)
216 break;
217 num++;
218 }
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400219 }
Daniel Scheller22e74382017-08-12 07:55:52 -0400220 if (stat) {
221 for (j = 0; j < num; j++) {
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400222 i2c = &dev->i2c[j];
223 adap = &i2c->adap;
224 i2c_del_adapter(adap);
225 }
Daniel Scheller22e74382017-08-12 07:55:52 -0400226 } else
227 dev->i2c_num = num;
Daniel Schellera96e5ab2017-07-29 07:28:36 -0400228 return stat;
229}