blob: 7d29893f833c32f2350d6771e65e3c3ded6ae2a6 [file] [log] [blame]
Carlo Caionedfe7a1b2014-04-11 11:38:10 +02001/*
2 * AXP20x regulators driver.
3 *
4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file "COPYING" in the main directory of this
8 * archive for more details.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/err.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23#include <linux/mfd/axp20x.h>
24#include <linux/regulator/driver.h>
25#include <linux/regulator/of_regulator.h>
26
27#define AXP20X_IO_ENABLED 0x03
28#define AXP20X_IO_DISABLED 0x07
29
Chen-Yu Tsai3cb99e22015-12-22 17:08:06 +080030#define AXP22X_IO_ENABLED 0x03
31#define AXP22X_IO_DISABLED 0x04
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +080032
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020033#define AXP20X_WORKMODE_DCDC2_MASK BIT(2)
34#define AXP20X_WORKMODE_DCDC3_MASK BIT(1)
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +080035#define AXP22X_WORKMODE_DCDCX_MASK(x) BIT(x)
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020036
37#define AXP20X_FREQ_DCDC_MASK 0x0f
38
Boris BREZILLON866bd952015-04-10 12:09:03 +080039#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
40 _vmask, _ereg, _emask, _enable_val, _disable_val) \
41 [_family##_##_id] = { \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020042 .name = #_id, \
43 .supply_name = (_supply), \
Chen-Yu Tsai880fe822015-01-10 00:23:43 +080044 .of_match = of_match_ptr(_match), \
45 .regulators_node = of_match_ptr("regulators"), \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020046 .type = REGULATOR_VOLTAGE, \
Boris BREZILLON866bd952015-04-10 12:09:03 +080047 .id = _family##_##_id, \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020048 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
49 .owner = THIS_MODULE, \
50 .min_uV = (_min) * 1000, \
51 .uV_step = (_step) * 1000, \
52 .vsel_reg = (_vreg), \
53 .vsel_mask = (_vmask), \
54 .enable_reg = (_ereg), \
55 .enable_mask = (_emask), \
56 .enable_val = (_enable_val), \
57 .disable_val = (_disable_val), \
58 .ops = &axp20x_ops, \
59 }
60
Boris BREZILLON866bd952015-04-10 12:09:03 +080061#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
62 _vmask, _ereg, _emask) \
63 [_family##_##_id] = { \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020064 .name = #_id, \
65 .supply_name = (_supply), \
Chen-Yu Tsai880fe822015-01-10 00:23:43 +080066 .of_match = of_match_ptr(_match), \
67 .regulators_node = of_match_ptr("regulators"), \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020068 .type = REGULATOR_VOLTAGE, \
Boris BREZILLON866bd952015-04-10 12:09:03 +080069 .id = _family##_##_id, \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020070 .n_voltages = (((_max) - (_min)) / (_step) + 1), \
71 .owner = THIS_MODULE, \
72 .min_uV = (_min) * 1000, \
73 .uV_step = (_step) * 1000, \
74 .vsel_reg = (_vreg), \
75 .vsel_mask = (_vmask), \
76 .enable_reg = (_ereg), \
77 .enable_mask = (_emask), \
78 .ops = &axp20x_ops, \
79 }
80
Chen-Yu Tsai94c39042016-02-02 18:27:37 +080081#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +080082 [_family##_##_id] = { \
83 .name = #_id, \
84 .supply_name = (_supply), \
85 .of_match = of_match_ptr(_match), \
86 .regulators_node = of_match_ptr("regulators"), \
87 .type = REGULATOR_VOLTAGE, \
88 .id = _family##_##_id, \
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +080089 .owner = THIS_MODULE, \
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +080090 .enable_reg = (_ereg), \
91 .enable_mask = (_emask), \
92 .ops = &axp20x_ops_sw, \
93 }
94
Boris BREZILLON866bd952015-04-10 12:09:03 +080095#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
96 [_family##_##_id] = { \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +020097 .name = #_id, \
98 .supply_name = (_supply), \
Chen-Yu Tsai880fe822015-01-10 00:23:43 +080099 .of_match = of_match_ptr(_match), \
100 .regulators_node = of_match_ptr("regulators"), \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200101 .type = REGULATOR_VOLTAGE, \
Boris BREZILLON866bd952015-04-10 12:09:03 +0800102 .id = _family##_##_id, \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200103 .n_voltages = 1, \
104 .owner = THIS_MODULE, \
105 .min_uV = (_volt) * 1000, \
106 .ops = &axp20x_ops_fixed \
107 }
108
Chen-Yu Tsai13d57e62016-02-02 18:27:38 +0800109#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
110 _vreg, _vmask, _ereg, _emask) \
Boris BREZILLON866bd952015-04-10 12:09:03 +0800111 [_family##_##_id] = { \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200112 .name = #_id, \
113 .supply_name = (_supply), \
Chen-Yu Tsai880fe822015-01-10 00:23:43 +0800114 .of_match = of_match_ptr(_match), \
115 .regulators_node = of_match_ptr("regulators"), \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200116 .type = REGULATOR_VOLTAGE, \
Boris BREZILLON866bd952015-04-10 12:09:03 +0800117 .id = _family##_##_id, \
Chen-Yu Tsai13d57e62016-02-02 18:27:38 +0800118 .n_voltages = (_n_voltages), \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200119 .owner = THIS_MODULE, \
120 .vsel_reg = (_vreg), \
121 .vsel_mask = (_vmask), \
122 .enable_reg = (_ereg), \
123 .enable_mask = (_emask), \
Chen-Yu Tsai13d57e62016-02-02 18:27:38 +0800124 .linear_ranges = (_ranges), \
125 .n_linear_ranges = ARRAY_SIZE(_ranges), \
126 .ops = &axp20x_ops_range, \
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200127 }
128
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200129static struct regulator_ops axp20x_ops_fixed = {
130 .list_voltage = regulator_list_voltage_linear,
131};
132
Chen-Yu Tsai13d57e62016-02-02 18:27:38 +0800133static struct regulator_ops axp20x_ops_range = {
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200134 .set_voltage_sel = regulator_set_voltage_sel_regmap,
135 .get_voltage_sel = regulator_get_voltage_sel_regmap,
Chen-Yu Tsai13d57e62016-02-02 18:27:38 +0800136 .list_voltage = regulator_list_voltage_linear_range,
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200137 .enable = regulator_enable_regmap,
138 .disable = regulator_disable_regmap,
139 .is_enabled = regulator_is_enabled_regmap,
140};
141
142static struct regulator_ops axp20x_ops = {
143 .set_voltage_sel = regulator_set_voltage_sel_regmap,
144 .get_voltage_sel = regulator_get_voltage_sel_regmap,
145 .list_voltage = regulator_list_voltage_linear,
146 .enable = regulator_enable_regmap,
147 .disable = regulator_disable_regmap,
148 .is_enabled = regulator_is_enabled_regmap,
149};
150
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800151static struct regulator_ops axp20x_ops_sw = {
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800152 .enable = regulator_enable_regmap,
153 .disable = regulator_disable_regmap,
154 .is_enabled = regulator_is_enabled_regmap,
155};
156
Chen-Yu Tsai13d57e62016-02-02 18:27:38 +0800157static const struct regulator_linear_range axp20x_ldo4_ranges[] = {
158 REGULATOR_LINEAR_RANGE(1250000, 0x0, 0x0, 0),
159 REGULATOR_LINEAR_RANGE(1300000, 0x1, 0x8, 100000),
160 REGULATOR_LINEAR_RANGE(2500000, 0x9, 0xf, 100000),
161};
162
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200163static const struct regulator_desc axp20x_regulators[] = {
Boris BREZILLON866bd952015-04-10 12:09:03 +0800164 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
165 AXP20X_DCDC2_V_OUT, 0x3f, AXP20X_PWR_OUT_CTRL, 0x10),
166 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
167 AXP20X_DCDC3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x02),
168 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
169 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
170 AXP20X_LDO24_V_OUT, 0xf0, AXP20X_PWR_OUT_CTRL, 0x04),
171 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
172 AXP20X_LDO3_V_OUT, 0x7f, AXP20X_PWR_OUT_CTRL, 0x40),
Chen-Yu Tsai13d57e62016-02-02 18:27:38 +0800173 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in", axp20x_ldo4_ranges,
174 16, AXP20X_LDO24_V_OUT, 0x0f, AXP20X_PWR_OUT_CTRL,
175 0x08),
Boris BREZILLON866bd952015-04-10 12:09:03 +0800176 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
177 AXP20X_LDO5_V_OUT, 0xf0, AXP20X_GPIO0_CTRL, 0x07,
178 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200179};
180
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800181static const struct regulator_desc axp22x_regulators[] = {
182 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
183 AXP22X_DCDC1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(1)),
184 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
185 AXP22X_DCDC2_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(2)),
186 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
187 AXP22X_DCDC3_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(3)),
188 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
Chen-Yu Tsai6b3600b2015-09-26 21:21:12 +0800189 AXP22X_DCDC4_V_OUT, 0x3f, AXP22X_PWR_OUT_CTRL1, BIT(4)),
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800190 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
Chen-Yu Tsai6b3600b2015-09-26 21:21:12 +0800191 AXP22X_DCDC5_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(5)),
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800192 /* secondary switchable output of DCDC1 */
Chen-Yu Tsai94c39042016-02-02 18:27:37 +0800193 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL, AXP22X_PWR_OUT_CTRL2,
194 BIT(7)),
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800195 /* LDO regulator internally chained to DCDC5 */
Chen-Yu Tsai7118f192015-09-30 14:39:46 +0800196 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800197 AXP22X_DC5LDO_V_OUT, 0x7, AXP22X_PWR_OUT_CTRL1, BIT(0)),
198 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
199 AXP22X_ALDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(6)),
200 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
201 AXP22X_ALDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL1, BIT(7)),
202 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
203 AXP22X_ALDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL3, BIT(7)),
204 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
205 AXP22X_DLDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(3)),
206 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
207 AXP22X_DLDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(4)),
208 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
209 AXP22X_DLDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(5)),
210 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
211 AXP22X_DLDO4_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(6)),
212 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
213 AXP22X_ELDO1_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(0)),
214 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
215 AXP22X_ELDO2_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(1)),
216 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
217 AXP22X_ELDO3_V_OUT, 0x1f, AXP22X_PWR_OUT_CTRL2, BIT(2)),
218 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 1800, 3300, 100,
219 AXP22X_LDO_IO0_V_OUT, 0x1f, AXP20X_GPIO0_CTRL, 0x07,
220 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
221 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 1800, 3300, 100,
222 AXP22X_LDO_IO1_V_OUT, 0x1f, AXP20X_GPIO1_CTRL, 0x07,
223 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
224 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
225};
226
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200227static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
228{
229 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
Boris BREZILLON866bd952015-04-10 12:09:03 +0800230 u32 min, max, def, step;
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200231
Boris BREZILLON866bd952015-04-10 12:09:03 +0800232 switch (axp20x->variant) {
233 case AXP202_ID:
234 case AXP209_ID:
235 min = 750;
236 max = 1875;
237 def = 1500;
238 step = 75;
239 break;
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800240 case AXP221_ID:
241 min = 1800;
242 max = 4050;
243 def = 3000;
244 step = 150;
245 break;
Boris BREZILLON866bd952015-04-10 12:09:03 +0800246 default:
247 dev_err(&pdev->dev,
248 "Setting DCDC frequency for unsupported AXP variant\n");
249 return -EINVAL;
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200250 }
251
Boris BREZILLON866bd952015-04-10 12:09:03 +0800252 if (dcdcfreq == 0)
253 dcdcfreq = def;
254
255 if (dcdcfreq < min) {
256 dcdcfreq = min;
257 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
258 min);
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200259 }
260
Boris BREZILLON866bd952015-04-10 12:09:03 +0800261 if (dcdcfreq > max) {
262 dcdcfreq = max;
263 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
264 max);
265 }
266
267 dcdcfreq = (dcdcfreq - min) / step;
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200268
269 return regmap_update_bits(axp20x->regmap, AXP20X_DCDC_FREQ,
270 AXP20X_FREQ_DCDC_MASK, dcdcfreq);
271}
272
273static int axp20x_regulator_parse_dt(struct platform_device *pdev)
274{
275 struct device_node *np, *regulators;
276 int ret;
Boris BREZILLON866bd952015-04-10 12:09:03 +0800277 u32 dcdcfreq = 0;
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200278
279 np = of_node_get(pdev->dev.parent->of_node);
280 if (!np)
281 return 0;
282
Boris BREZILLONa6016c52014-05-19 10:25:30 +0200283 regulators = of_get_child_by_name(np, "regulators");
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200284 if (!regulators) {
285 dev_warn(&pdev->dev, "regulators node not found\n");
286 } else {
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200287 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
288 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
289 if (ret < 0) {
290 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
291 return ret;
292 }
293
294 of_node_put(regulators);
295 }
296
297 return 0;
298}
299
300static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
301{
Boris BREZILLON866bd952015-04-10 12:09:03 +0800302 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
303 unsigned int mask;
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200304
Boris BREZILLON866bd952015-04-10 12:09:03 +0800305 switch (axp20x->variant) {
306 case AXP202_ID:
307 case AXP209_ID:
308 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
309 return -EINVAL;
310
311 mask = AXP20X_WORKMODE_DCDC2_MASK;
312 if (id == AXP20X_DCDC3)
313 mask = AXP20X_WORKMODE_DCDC3_MASK;
314
315 workmode <<= ffs(mask) - 1;
316 break;
317
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800318 case AXP221_ID:
319 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
320 return -EINVAL;
321
322 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
323 workmode <<= id - AXP22X_DCDC1;
324 break;
325
Boris BREZILLON866bd952015-04-10 12:09:03 +0800326 default:
327 /* should not happen */
328 WARN_ON(1);
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200329 return -EINVAL;
Boris BREZILLON866bd952015-04-10 12:09:03 +0800330 }
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200331
332 return regmap_update_bits(rdev->regmap, AXP20X_DCDC_MODE, mask, workmode);
333}
334
335static int axp20x_regulator_probe(struct platform_device *pdev)
336{
337 struct regulator_dev *rdev;
338 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
Boris BREZILLON866bd952015-04-10 12:09:03 +0800339 const struct regulator_desc *regulators;
Chen-Yu Tsai765e8022015-01-10 00:23:44 +0800340 struct regulator_config config = {
341 .dev = pdev->dev.parent,
342 .regmap = axp20x->regmap,
Boris BREZILLON866bd952015-04-10 12:09:03 +0800343 .driver_data = axp20x,
Chen-Yu Tsai765e8022015-01-10 00:23:44 +0800344 };
Boris BREZILLON866bd952015-04-10 12:09:03 +0800345 int ret, i, nregulators;
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200346 u32 workmode;
Chen-Yu Tsai7118f192015-09-30 14:39:46 +0800347 const char *axp22x_dc1_name = axp22x_regulators[AXP22X_DCDC1].name;
348 const char *axp22x_dc5_name = axp22x_regulators[AXP22X_DCDC5].name;
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200349
Boris BREZILLON866bd952015-04-10 12:09:03 +0800350 switch (axp20x->variant) {
351 case AXP202_ID:
352 case AXP209_ID:
353 regulators = axp20x_regulators;
354 nregulators = AXP20X_REG_ID_MAX;
355 break;
Boris BREZILLON1b82b4e2015-04-10 12:09:04 +0800356 case AXP221_ID:
357 regulators = axp22x_regulators;
358 nregulators = AXP22X_REG_ID_MAX;
359 break;
Boris BREZILLON866bd952015-04-10 12:09:03 +0800360 default:
361 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
362 axp20x->variant);
363 return -EINVAL;
364 }
365
Chen-Yu Tsai765e8022015-01-10 00:23:44 +0800366 /* This only sets the dcdc freq. Ignore any errors */
367 axp20x_regulator_parse_dt(pdev);
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200368
Boris BREZILLON866bd952015-04-10 12:09:03 +0800369 for (i = 0; i < nregulators; i++) {
Chen-Yu Tsai7118f192015-09-30 14:39:46 +0800370 const struct regulator_desc *desc = &regulators[i];
371 struct regulator_desc *new_desc;
372
373 /*
374 * Regulators DC1SW and DC5LDO are connected internally,
375 * so we have to handle their supply names separately.
376 *
377 * We always register the regulators in proper sequence,
378 * so the supply names are correctly read. See the last
379 * part of this loop to see where we save the DT defined
380 * name.
381 */
382 if (regulators == axp22x_regulators) {
383 if (i == AXP22X_DC1SW) {
384 new_desc = devm_kzalloc(&pdev->dev,
385 sizeof(*desc),
386 GFP_KERNEL);
387 *new_desc = regulators[i];
388 new_desc->supply_name = axp22x_dc1_name;
389 desc = new_desc;
390 } else if (i == AXP22X_DC5LDO) {
391 new_desc = devm_kzalloc(&pdev->dev,
392 sizeof(*desc),
393 GFP_KERNEL);
394 *new_desc = regulators[i];
395 new_desc->supply_name = axp22x_dc5_name;
396 desc = new_desc;
397 }
398 }
399
400 rdev = devm_regulator_register(&pdev->dev, desc, &config);
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200401 if (IS_ERR(rdev)) {
402 dev_err(&pdev->dev, "Failed to register %s\n",
Boris BREZILLON866bd952015-04-10 12:09:03 +0800403 regulators[i].name);
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200404
405 return PTR_ERR(rdev);
406 }
407
Chen-Yu Tsai765e8022015-01-10 00:23:44 +0800408 ret = of_property_read_u32(rdev->dev.of_node,
409 "x-powers,dcdc-workmode",
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200410 &workmode);
411 if (!ret) {
412 if (axp20x_set_dcdc_workmode(rdev, i, workmode))
413 dev_err(&pdev->dev, "Failed to set workmode on %s\n",
Boris BREZILLON866bd952015-04-10 12:09:03 +0800414 rdev->desc->name);
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200415 }
Chen-Yu Tsai7118f192015-09-30 14:39:46 +0800416
417 /*
418 * Save AXP22X DCDC1 / DCDC5 regulator names for later.
419 */
420 if (regulators == axp22x_regulators) {
421 /* Can we use rdev->constraints->name instead? */
422 if (i == AXP22X_DCDC1)
423 of_property_read_string(rdev->dev.of_node,
424 "regulator-name",
425 &axp22x_dc1_name);
426 else if (i == AXP22X_DCDC5)
427 of_property_read_string(rdev->dev.of_node,
428 "regulator-name",
429 &axp22x_dc5_name);
430 }
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200431 }
432
433 return 0;
434}
435
436static struct platform_driver axp20x_regulator_driver = {
437 .probe = axp20x_regulator_probe,
438 .driver = {
439 .name = "axp20x-regulator",
Carlo Caionedfe7a1b2014-04-11 11:38:10 +0200440 },
441};
442
443module_platform_driver(axp20x_regulator_driver);
444
445MODULE_LICENSE("GPL v2");
446MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
447MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
Ian Campbelld4ea7d82015-08-01 18:13:25 +0100448MODULE_ALIAS("platform:axp20x-regulator");