Thomas Gleixner | caab277 | 2019-06-03 07:44:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 ARM Ltd. |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __ASM_MMU_H |
| 6 | #define __ASM_MMU_H |
| 7 | |
Will Deacon | b89d82e | 2019-01-08 16:19:01 +0000 | [diff] [blame] | 8 | #include <asm/cputype.h> |
| 9 | |
Yury Norov | 5ce93ab6 | 2017-08-20 13:20:47 +0300 | [diff] [blame] | 10 | #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ |
James Morse | 79e9aa5 | 2018-01-08 15:38:18 +0000 | [diff] [blame] | 11 | #define USER_ASID_BIT 48 |
| 12 | #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT) |
Will Deacon | b519538 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 13 | #define TTBR_ASID_MASK (UL(0xffff) << 48) |
Yury Norov | 5ce93ab6 | 2017-08-20 13:20:47 +0300 | [diff] [blame] | 14 | |
Marc Zyngier | 4205a89 | 2018-03-13 12:40:39 +0000 | [diff] [blame] | 15 | #define BP_HARDEN_EL2_SLOTS 4 |
Mark Brown | 6e52aab | 2020-02-18 19:58:38 +0000 | [diff] [blame] | 16 | #define __BP_HARDEN_HYP_VECS_SZ (BP_HARDEN_EL2_SLOTS * SZ_2K) |
Marc Zyngier | 4205a89 | 2018-03-13 12:40:39 +0000 | [diff] [blame] | 17 | |
Will Deacon | fc0e129 | 2017-11-14 13:58:08 +0000 | [diff] [blame] | 18 | #ifndef __ASSEMBLY__ |
| 19 | |
Jean-Philippe Brucker | 4811815 | 2020-09-18 12:18:44 +0200 | [diff] [blame] | 20 | #include <linux/refcount.h> |
| 21 | |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 22 | typedef struct { |
Will Deacon | 5aec715 | 2015-10-06 18:46:24 +0100 | [diff] [blame] | 23 | atomic64_t id; |
Will Deacon | a39060b | 2020-06-22 12:35:41 +0100 | [diff] [blame] | 24 | #ifdef CONFIG_COMPAT |
| 25 | void *sigpage; |
| 26 | #endif |
Jean-Philippe Brucker | 4811815 | 2020-09-18 12:18:44 +0200 | [diff] [blame] | 27 | refcount_t pinned; |
Will Deacon | 5aec715 | 2015-10-06 18:46:24 +0100 | [diff] [blame] | 28 | void *vdso; |
Pratyush Anand | 06beb72 | 2016-11-02 14:40:45 +0530 | [diff] [blame] | 29 | unsigned long flags; |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 30 | } mm_context_t; |
| 31 | |
Will Deacon | 5aec715 | 2015-10-06 18:46:24 +0100 | [diff] [blame] | 32 | /* |
Will Deacon | 90765f7 | 2020-02-28 12:43:55 +0000 | [diff] [blame] | 33 | * This macro is only used by the TLBI and low-level switch_mm() code, |
| 34 | * neither of which can race with an ASID change. We therefore don't |
| 35 | * need to reload the counter using atomic64_read(). |
Will Deacon | 5aec715 | 2015-10-06 18:46:24 +0100 | [diff] [blame] | 36 | */ |
| 37 | #define ASID(mm) ((mm)->context.id.counter & 0xffff) |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 38 | |
Will Deacon | fc0e129 | 2017-11-14 13:58:08 +0000 | [diff] [blame] | 39 | static inline bool arm64_kernel_unmapped_at_el0(void) |
| 40 | { |
Will Deacon | c835578 | 2020-03-18 20:38:29 +0000 | [diff] [blame] | 41 | return cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0); |
Will Deacon | b89d82e | 2019-01-08 16:19:01 +0000 | [diff] [blame] | 42 | } |
| 43 | |
Will Deacon | 0f15adb | 2018-01-03 11:17:58 +0000 | [diff] [blame] | 44 | typedef void (*bp_hardening_cb_t)(void); |
| 45 | |
| 46 | struct bp_hardening_data { |
| 47 | int hyp_vectors_slot; |
| 48 | bp_hardening_cb_t fn; |
| 49 | }; |
| 50 | |
Will Deacon | 0f15adb | 2018-01-03 11:17:58 +0000 | [diff] [blame] | 51 | DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); |
| 52 | |
| 53 | static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) |
| 54 | { |
| 55 | return this_cpu_ptr(&bp_hardening_data); |
| 56 | } |
| 57 | |
| 58 | static inline void arm64_apply_bp_hardening(void) |
| 59 | { |
| 60 | struct bp_hardening_data *d; |
| 61 | |
Will Deacon | 688f1e4 | 2020-09-15 23:00:31 +0100 | [diff] [blame] | 62 | if (!cpus_have_const_cap(ARM64_SPECTRE_V2)) |
Will Deacon | 0f15adb | 2018-01-03 11:17:58 +0000 | [diff] [blame] | 63 | return; |
| 64 | |
| 65 | d = arm64_get_bp_hardening_data(); |
| 66 | if (d->fn) |
| 67 | d->fn(); |
| 68 | } |
Will Deacon | 0f15adb | 2018-01-03 11:17:58 +0000 | [diff] [blame] | 69 | |
Will Deacon | 8350403 | 2019-01-14 14:22:24 +0000 | [diff] [blame] | 70 | extern void arm64_memblock_init(void); |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 71 | extern void paging_init(void); |
David Daney | 3194ac6 | 2016-04-08 15:50:26 -0700 | [diff] [blame] | 72 | extern void bootmem_init(void); |
Catalin Marinas | 2475ff9 | 2012-10-23 14:55:08 +0100 | [diff] [blame] | 73 | extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); |
Mark Salter | 0bf757c | 2014-04-07 15:39:51 -0700 | [diff] [blame] | 74 | extern void init_mem_pgprot(void); |
Ard Biesheuvel | 8ce837c | 2014-10-20 15:42:07 +0200 | [diff] [blame] | 75 | extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, |
| 76 | unsigned long virt, phys_addr_t size, |
Ard Biesheuvel | f14c66c | 2016-10-21 12:22:57 +0100 | [diff] [blame] | 77 | pgprot_t prot, bool page_mappings_only); |
Hsin-Yi Wang | e112b03 | 2019-08-23 14:24:50 +0800 | [diff] [blame] | 78 | extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot); |
Ard Biesheuvel | 5ea5306 | 2017-03-09 21:52:01 +0100 | [diff] [blame] | 79 | extern void mark_linear_text_alias_ro(void); |
Mark Brown | 09e3c22 | 2019-12-09 18:12:17 +0000 | [diff] [blame] | 80 | extern bool kaslr_requires_kpti(void); |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 81 | |
Jun Yao | 2b5548b | 2018-09-24 15:47:49 +0100 | [diff] [blame] | 82 | #define INIT_MM_CONTEXT(name) \ |
| 83 | .pgd = init_pg_dir, |
| 84 | |
Will Deacon | fc0e129 | 2017-11-14 13:58:08 +0000 | [diff] [blame] | 85 | #endif /* !__ASSEMBLY__ */ |
Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame] | 86 | #endif |