| commit | 4ee3fd4abeca30d530fe67972f1964f7454259d6 | [log] [tgz] |
|---|---|---|
| author | Derek Basehore <dbasehore@chromium.org> | Tue Mar 13 13:37:19 2018 -0700 |
| committer | Heiko Stuebner <heiko@sntech.de> | Wed Mar 14 00:37:22 2018 +0100 |
| tree | 466579a6610cb0f25a0b836c27dad771367c36aa | |
| parent | 60cf09e45fbcbbbb3162f02e0923a25ae7f5627e [diff] |
clk: rockchip: Add 1.6GHz PLL rate for rk3399 We need this rate to generate 100, 200, and 228.57MHz from the same PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for an external display. Signed-off-by: Derek Basehore <dbasehore@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>