tree 466579a6610cb0f25a0b836c27dad771367c36aa
parent 60cf09e45fbcbbbb3162f02e0923a25ae7f5627e
author Derek Basehore <dbasehore@chromium.org> 1520973439 -0700
committer Heiko Stuebner <heiko@sntech.de> 1520984242 +0100

clk: rockchip: Add 1.6GHz PLL rate for rk3399

We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>