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review.shift-gmbh.com / SHIFTPHONES / kernel / common / fe50dcab7ae21c88bdde199e04978903b3ebff4d / drivers / clk / tegra / clk.h
  1. dec15c9 clk: tegra: cclk: Add helpers for handling PLLX rate changes by Dmitry Osipenko · 4 years, 10 months ago
  2. 9157abe clk: tegra: pll: Add pre/post rate-change hooks by Dmitry Osipenko · 4 years, 10 months ago
  3. 1641567 clk: tegra: Add custom CCLK implementation by Dmitry Osipenko · 4 years, 10 months ago
  4. 0ac65fc clk: tegra: Implement Tegra210 EMC clock by Joseph Lo · 6 years ago
  5. 3dcbd36 clk: tegra: Rename Tegra124 EMC clock source file by Thierry Reding · 5 years ago
  6. acbeec3 clk: tegra: Remove tegra_pmc_clk_init along with clk ids by Sowjanya Komatineni · 5 years ago
  7. 535f296d clk: tegra: Add suspend and resume support on Tegra210 by Sowjanya Komatineni · 5 years ago
  8. 3214be6 clk: tegra: Share clk and rst register defines with Tegra clock driver by Sowjanya Komatineni · 5 years ago
  9. 68a14a5 clk: tegra: clk-super: Fix to enable PLLP branches to CPU by Sowjanya Komatineni · 5 years ago
  10. 50d4da9 clk: tegra: Support for OSC context save and restore by Sowjanya Komatineni · 5 years ago
  11. ed1a245 clk: tegra: Add Tegra20/30 EMC clock implementation by Dmitry Osipenko · 5 years ago
  12. 9952f69 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201 by Thomas Gleixner · 6 years ago
  13. 845d782 clk: tegra: Fix maximum audio sync clock for Tegra124/210 by Jon Hunter · 6 years ago
  14. 633e796 clk: tegra: Add sdmmc mux divider clock by Peter De-Schrijver · 7 years ago
  15. cb3ac59 clk: tegra: Refactor fractional divider calculation by Peter De Schrijver · 7 years ago
  16. 0cbb61a clk: tegra: Fix includes required by fence_udelay() by Aapo Vienamo · 7 years ago
  17. 5d79711 clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 by Dmitry Osipenko · 7 years ago
  18. cbfc8d0 clk: tegra: add fence_delay for clock registers by Peter De Schrijver · 7 years ago
  19. 8be9519 clk: tegra: Add peripheral clock registration helper by Thierry Reding · 7 years ago
  20. ac99afe clk: tegra: Re-factor T210 PLLX registration by Alex Frid · 7 years ago
  21. 3913350 clk: tegra: Fix build warnings on Tegra20/Tegra30 by Thierry Reding · 8 years ago
  22. e827ba18 clk: tegra: Add super clock mux/divider by Peter De Schrijver · 8 years ago
  23. 9e8c93e clk: tegra: Fix constness for peripheral clocks by Peter De Schrijver · 8 years ago
  24. e589376 clk: tegra: Fix type for m field by Peter De Schrijver · 8 years ago
  25. 15d68e8 clk: tegra: Initialize UTMI PLL when enabling PLLU by Andrew Bresticker · 9 years ago
  26. 926655f clk: tegra: Fix pllre Tegra210 and add pll_re_out1 by Rhyland Klein · 9 years ago
  27. 1ec7032 clk: tegra: Add fixed factor peripheral clock type by Thierry Reding · 10 years ago
  28. 7e14f22 clk: tegra: Constify peripheral clock registers by Thierry Reding · 10 years ago
  29. 6b301a0 clk: tegra: Add support for Tegra210 clocks by Rhyland Klein · 10 years ago
  30. 139fd30 clk: tegra: Add Super Gen5 Logic by Bill Huang · 10 years ago
  31. 0ef9db6 clk: tegra: pll: Add logic for SS by Bill Huang · 10 years ago
  32. 17e9273 clk: tegra: pll: Add dyn_ramp callback by Rhyland Klein · 10 years ago
  33. b985114 clk: tegra: pll: Add Set_default logic by Bill Huang · 10 years ago
  34. b5512b4 clk: tegra: pll: Adjust vco_min if SDM present by Bill Huang · 10 years ago
  35. 6929715 clk: tegra: pll: Add support for PLLMB for Tegra210 by Rhyland Klein · 10 years ago
  36. dd322f0 clk: tegra: pll: Add specialized logic for Tegra210 by Rhyland Klein · 10 years ago
  37. fde207e clk: tegra: pll: Add code to handle if resets are supported by PLL by Bill Huang · 10 years ago
  38. 407254d clk: tegra: pll: Add logic for out-of-table rates for T210 by Rhyland Klein · 10 years ago
  39. d907f4b clk: tegra: pll: Add logic for handling SDM data by Rhyland Klein · 10 years ago
  40. 56fd27b clk: tegra: pll: Change misc_reg count from 3 to 6 by Bill Huang · 10 years ago
  41. 6583a63 clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header by Rhyland Klein · 10 years ago
  42. 385f9ad clk: tegra: Constify pdiv-to-hw mappings by Thierry Reding · 9 years ago
  43. 88d909b clk: tegra: Modify tegra_audio_clk_init to accept more plls by Rhyland Klein · 10 years ago
  44. db592c4 clk: tegra: Update struct tegra_clk_pll_params kerneldoc by Thierry Reding · 10 years ago
  45. fdc1fea clk: tegra: Fix comments for structure definitions by Rhyland Klein · 10 years ago
  46. 66b6f3d clk: tegra: Introduce ability for SoC-specific reset control callbacks by Mikko Perttunen · 10 years ago
  47. 31b52ba clk: tegra: EMC clock driver depends on EMC driver by Thierry Reding · 10 years ago
  48. 2db04f1 clk: tegra: Add EMC clock driver by Mikko Perttunen · 10 years ago
  49. 63cc5a4 clk: tegra: Model oscillator as clock by Thierry Reding · 10 years ago
  50. 8106462 clk: tegra: Fix typo tabel -> table by Thierry Reding · 10 years ago
  51. 4f4f85f clk: tegra: Implement memory-controller clock by Thierry Reding · 10 years ago
  52. 2ae7752 clk: tegra: remove legacy reset APIs by Stephen Warren · 11 years ago
  53. 6d5b988 clk: tegra: implement a reset driver by Stephen Warren · 11 years ago
  54. b29f9e9 clk: tegra: add TEGRA_PERIPH_NO_GATE by Peter De Schrijver · 11 years ago
  55. bc44275 clk: tegra: add locking to periph clks by Peter De Schrijver · 11 years ago
  56. 798e910 clk: tegra: Add support for PLLSS by Peter De Schrijver · 11 years ago
  57. a7c8485 clk: tegra: introduce common gen4 super clock by Peter De Schrijver · 11 years ago
  58. de4f30f clk: tegra: move PMC, fixed clocks to common files by Peter De Schrijver · 11 years ago
  59. 76ebc13 clk: tegra: move periph clocks to common file by Peter De Schrijver · 11 years ago
  60. 6609dbe clk: tegra: move audio clk to common file by Peter De Schrijver · 11 years ago
  61. 73d37e4 clk: tegra: add clkdev registration infra by Peter De Schrijver · 11 years ago
  62. b8700d5 clk: tegra: add common infra for DT clocks by Peter De Schrijver · 11 years ago
  63. ebe142b clk: tegra: move fields to tegra_clk_pll_params by Peter De Schrijver · 11 years ago
  64. 5bb9d26 clk: tegra: Add TEGRA_PERIPH_NO_DIV flag by Peter De Schrijver · 11 years ago
  65. 343a607 clk: tegra: common periph_clk_enb_refcnt and clks by Peter De Schrijver · 11 years ago
  66. d5ff89a clk: tegra: simplify periph clock data by Peter De Schrijver · 11 years ago
  67. 1c472d8 clk: tegra: T114: add DFLL DVCO reset control by Paul Walmsley · 12 years ago
  68. 25c9ded clk: tegra: T114: add FCPU clock shaper programming, needed by the DFLL by Paul Walmsley · 12 years ago
  69. 7b781c7 clk: tegra: Add fields for override bits by Peter De Schrijver · 12 years ago
  70. aa6fefd clk: tegra: allow PLL m,n,p init from SoC files by Peter De Schrijver · 12 years ago
  71. 061cec9 clk: tegra: Use common of_clk_init function by Prashant Gaikwad · 12 years ago
  72. 27aa99d clk: tegra: devicetree match for nvidia,tegra114-car by Peter De Schrijver · 12 years ago
  73. fdcccbd clk: tegra: Workaround for Tegra114 MSENC problem by Peter De Schrijver · 12 years ago
  74. a26a029 clk: tegra: Add flags to tegra_clk_periph() by Peter De Schrijver · 12 years ago
  75. c1d1939 clk: tegra: Add new fields and PLL types for Tegra114 by Peter De Schrijver · 12 years ago
  76. 3e72771 clk: tegra: move from a lock bit idx to a lock mask by Peter De Schrijver · 12 years ago
  77. 0b6525a clk: tegra: Add PLL post divider table by Peter De Schrijver · 12 years ago
  78. 7ba2881 clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE by Peter De Schrijver · 12 years ago
  79. dd93587 clk: tegra: Add TEGRA_PLL_BYPASS flag by Peter De Schrijver · 12 years ago
  80. dba4072 clk: tegra: Refactor PLL programming code by Peter De Schrijver · 12 years ago
  81. 441f199 clk: tegra: defer application of init table by Stephen Warren · 12 years ago
  82. ce4f331 clk: add table lookup to mux by Peter De Schrijver · 12 years ago
  83. b08e8c0 clk: tegra: add clock support for Tegra30 by Prashant Gaikwad · 12 years ago
  84. 37c26a9 clk: tegra: add clock support for Tegra20 by Prashant Gaikwad · 12 years ago
  85. 8f8f484 clk: tegra: add Tegra specific clocks by Prashant Gaikwad · 12 years ago