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Thomas Gleixnerc942fdd2019-05-27 08:55:06 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Alban Bedelff591a92015-08-03 19:23:52 +02002/*
Paul Gortmaker90ce95a2017-02-07 19:18:44 -05003 * AR71xx Reset Controller Driver
4 * Author: Alban Bedel
5 *
Alban Bedelff591a92015-08-03 19:23:52 +02006 * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
Alban Bedelff591a92015-08-03 19:23:52 +02007 */
8
Philipp Zabel9e9ba092016-08-09 11:17:22 +02009#include <linux/io.h>
Paul Gortmaker90ce95a2017-02-07 19:18:44 -050010#include <linux/init.h>
Randy Dunlapac316722018-06-19 22:47:28 -070011#include <linux/mod_devicetable.h>
Alban Bedelff591a92015-08-03 19:23:52 +020012#include <linux/platform_device.h>
13#include <linux/reset-controller.h>
Alban Bedelba64e272015-11-24 01:00:33 +010014#include <linux/reboot.h>
Alban Bedelff591a92015-08-03 19:23:52 +020015
16struct ath79_reset {
17 struct reset_controller_dev rcdev;
Alban Bedelba64e272015-11-24 01:00:33 +010018 struct notifier_block restart_nb;
Alban Bedelff591a92015-08-03 19:23:52 +020019 void __iomem *base;
20 spinlock_t lock;
21};
22
Alban Bedelba64e272015-11-24 01:00:33 +010023#define FULL_CHIP_RESET 24
24
Alban Bedelff591a92015-08-03 19:23:52 +020025static int ath79_reset_update(struct reset_controller_dev *rcdev,
26 unsigned long id, bool assert)
27{
28 struct ath79_reset *ath79_reset =
29 container_of(rcdev, struct ath79_reset, rcdev);
30 unsigned long flags;
31 u32 val;
32
33 spin_lock_irqsave(&ath79_reset->lock, flags);
34 val = readl(ath79_reset->base);
35 if (assert)
36 val |= BIT(id);
37 else
38 val &= ~BIT(id);
39 writel(val, ath79_reset->base);
40 spin_unlock_irqrestore(&ath79_reset->lock, flags);
41
42 return 0;
43}
44
45static int ath79_reset_assert(struct reset_controller_dev *rcdev,
46 unsigned long id)
47{
48 return ath79_reset_update(rcdev, id, true);
49}
50
51static int ath79_reset_deassert(struct reset_controller_dev *rcdev,
52 unsigned long id)
53{
54 return ath79_reset_update(rcdev, id, false);
55}
56
57static int ath79_reset_status(struct reset_controller_dev *rcdev,
58 unsigned long id)
59{
60 struct ath79_reset *ath79_reset =
61 container_of(rcdev, struct ath79_reset, rcdev);
62 u32 val;
63
64 val = readl(ath79_reset->base);
65
66 return !!(val & BIT(id));
67}
68
Philipp Zabeld2f79f22016-01-17 15:12:23 +010069static const struct reset_control_ops ath79_reset_ops = {
Alban Bedelff591a92015-08-03 19:23:52 +020070 .assert = ath79_reset_assert,
71 .deassert = ath79_reset_deassert,
72 .status = ath79_reset_status,
73};
74
Alban Bedelba64e272015-11-24 01:00:33 +010075static int ath79_reset_restart_handler(struct notifier_block *nb,
76 unsigned long action, void *data)
77{
78 struct ath79_reset *ath79_reset =
79 container_of(nb, struct ath79_reset, restart_nb);
80
81 ath79_reset_assert(&ath79_reset->rcdev, FULL_CHIP_RESET);
82
83 return NOTIFY_DONE;
84}
85
Alban Bedelff591a92015-08-03 19:23:52 +020086static int ath79_reset_probe(struct platform_device *pdev)
87{
88 struct ath79_reset *ath79_reset;
89 struct resource *res;
Alban Bedelba64e272015-11-24 01:00:33 +010090 int err;
Alban Bedelff591a92015-08-03 19:23:52 +020091
92 ath79_reset = devm_kzalloc(&pdev->dev,
93 sizeof(*ath79_reset), GFP_KERNEL);
94 if (!ath79_reset)
95 return -ENOMEM;
96
97 platform_set_drvdata(pdev, ath79_reset);
98
99 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
100 ath79_reset->base = devm_ioremap_resource(&pdev->dev, res);
101 if (IS_ERR(ath79_reset->base))
102 return PTR_ERR(ath79_reset->base);
103
Axel Linf319cb82015-09-01 20:15:10 +0800104 spin_lock_init(&ath79_reset->lock);
Alban Bedelff591a92015-08-03 19:23:52 +0200105 ath79_reset->rcdev.ops = &ath79_reset_ops;
106 ath79_reset->rcdev.owner = THIS_MODULE;
107 ath79_reset->rcdev.of_node = pdev->dev.of_node;
108 ath79_reset->rcdev.of_reset_n_cells = 1;
109 ath79_reset->rcdev.nr_resets = 32;
110
Masahiro Yamada56865f42016-05-01 19:36:58 +0900111 err = devm_reset_controller_register(&pdev->dev, &ath79_reset->rcdev);
Alban Bedelba64e272015-11-24 01:00:33 +0100112 if (err)
113 return err;
114
115 ath79_reset->restart_nb.notifier_call = ath79_reset_restart_handler;
116 ath79_reset->restart_nb.priority = 128;
117
118 err = register_restart_handler(&ath79_reset->restart_nb);
119 if (err)
120 dev_warn(&pdev->dev, "Failed to register restart handler\n");
121
122 return 0;
Alban Bedelff591a92015-08-03 19:23:52 +0200123}
124
Alban Bedelff591a92015-08-03 19:23:52 +0200125static const struct of_device_id ath79_reset_dt_ids[] = {
126 { .compatible = "qca,ar7100-reset", },
127 { },
128};
Alban Bedelff591a92015-08-03 19:23:52 +0200129
130static struct platform_driver ath79_reset_driver = {
131 .probe = ath79_reset_probe,
Alban Bedelff591a92015-08-03 19:23:52 +0200132 .driver = {
Paul Gortmaker90ce95a2017-02-07 19:18:44 -0500133 .name = "ath79-reset",
134 .of_match_table = ath79_reset_dt_ids,
135 .suppress_bind_attrs = true,
Alban Bedelff591a92015-08-03 19:23:52 +0200136 },
137};
Paul Gortmaker90ce95a2017-02-07 19:18:44 -0500138builtin_platform_driver(ath79_reset_driver);