| Thomas Gleixner | 386b05e | 2009-06-06 14:56:33 +0200 | [diff] [blame] | 1 | perf-list(1) |
| Ingo Molnar | 6e6b754 | 2008-04-15 22:39:31 +0200 | [diff] [blame] | 2 | ============ |
| Thomas Gleixner | 386b05e | 2009-06-06 14:56:33 +0200 | [diff] [blame] | 3 | |
| 4 | NAME |
| 5 | ---- |
| 6 | perf-list - List all symbolic event types |
| 7 | |
| 8 | SYNOPSIS |
| 9 | -------- |
| 10 | [verse] |
| Ingo Molnar | 6e6b754 | 2008-04-15 22:39:31 +0200 | [diff] [blame] | 11 | 'perf list' |
| Thomas Gleixner | 386b05e | 2009-06-06 14:56:33 +0200 | [diff] [blame] | 12 | |
| 13 | DESCRIPTION |
| 14 | ----------- |
| 15 | This command displays the symbolic event types which can be selected in the |
| 16 | various perf commands with the -e option. |
| 17 | |
| Sonny Rao | ffec516 | 2010-10-14 20:51:00 -0500 | [diff] [blame^] | 18 | EVENT MODIFIERS |
| 19 | --------------- |
| 20 | |
| 21 | Events can optionally have a modifer by appending a colon and one or |
| 22 | more modifiers. Modifiers allow the user to restrict when events are |
| 23 | counted with 'u' for user-space, 'k' for kernel, 'h' for hypervisor. |
| 24 | |
| 25 | The 'p' modifier can be used for specifying how precise the instruction |
| 26 | address should be. The 'p' modifier is currently only implemented for |
| 27 | Intel PEBS and can be specified multiple times: |
| 28 | 0 - SAMPLE_IP can have arbitrary skid |
| 29 | 1 - SAMPLE_IP must have constant skid |
| 30 | 2 - SAMPLE_IP requested to have 0 skid |
| 31 | 3 - SAMPLE_IP must have 0 skid |
| 32 | |
| 33 | The PEBS implementation now supports up to 2. |
| 34 | |
| Arnaldo Carvalho de Melo | 9e32a3c | 2010-05-05 11:20:05 -0300 | [diff] [blame] | 35 | RAW HARDWARE EVENT DESCRIPTOR |
| 36 | ----------------------------- |
| 37 | Even when an event is not available in a symbolic form within perf right now, |
| Arnaldo Carvalho de Melo | 1cf4a06 | 2010-05-07 14:07:05 -0300 | [diff] [blame] | 38 | it can be encoded in a per processor specific way. |
| 39 | |
| 40 | For instance For x86 CPUs NNN represents the raw register encoding with the |
| 41 | layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout |
| 42 | of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, |
| 43 | Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). |
| 44 | |
| 45 | Example: |
| 46 | |
| 47 | If the Intel docs for a QM720 Core i7 describe an event as: |
| Arnaldo Carvalho de Melo | 9e32a3c | 2010-05-05 11:20:05 -0300 | [diff] [blame] | 48 | |
| 49 | Event Umask Event Mask |
| 50 | Num. Value Mnemonic Description Comment |
| 51 | |
| 52 | A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and |
| 53 | delivered by loop stream detector invert to count |
| 54 | cycles |
| 55 | |
| 56 | raw encoding of 0x1A8 can be used: |
| 57 | |
| 58 | perf stat -e r1a8 -a sleep 1 |
| 59 | perf record -e r1a8 ... |
| 60 | |
| Arnaldo Carvalho de Melo | 1cf4a06 | 2010-05-07 14:07:05 -0300 | [diff] [blame] | 61 | You should refer to the processor specific documentation for getting these |
| 62 | details. Some of them are referenced in the SEE ALSO section below. |
| 63 | |
| Thomas Gleixner | 386b05e | 2009-06-06 14:56:33 +0200 | [diff] [blame] | 64 | OPTIONS |
| 65 | ------- |
| 66 | None |
| 67 | |
| 68 | SEE ALSO |
| 69 | -------- |
| 70 | linkperf:perf-stat[1], linkperf:perf-top[1], |
| Arnaldo Carvalho de Melo | 1cf4a06 | 2010-05-07 14:07:05 -0300 | [diff] [blame] | 71 | linkperf:perf-record[1], |
| 72 | http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide], |
| 73 | http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming] |