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Bjorn Helgaas8cfab3c2018-01-26 12:50:27 -06001/* SPDX-License-Identifier: GPL-2.0 */
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +05302/**
3 * PCI Endpoint *Controller* (EPC) header file
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +05307 */
8
9#ifndef __LINUX_PCI_EPC_H
10#define __LINUX_PCI_EPC_H
11
12#include <linux/pci-epf.h>
13
14struct pci_epc;
15
16enum pci_epc_irq_type {
17 PCI_EPC_IRQ_UNKNOWN,
18 PCI_EPC_IRQ_LEGACY,
19 PCI_EPC_IRQ_MSI,
Gustavo Pimentel89631062018-07-19 10:32:12 +020020 PCI_EPC_IRQ_MSIX,
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053021};
22
23/**
24 * struct pci_epc_ops - set of function pointers for performing EPC operations
25 * @write_header: ops to populate configuration space header
26 * @set_bar: ops to configure the BAR
27 * @clear_bar: ops to reset the BAR
28 * @map_addr: ops to map CPU address to PCI address
29 * @unmap_addr: ops to unmap CPU address and PCI address
30 * @set_msi: ops to set the requested number of MSI interrupts in the MSI
31 * capability register
32 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
33 * the MSI capability register
Gustavo Pimentel89631062018-07-19 10:32:12 +020034 * @set_msix: ops to set the requested number of MSI-X interrupts in the
35 * MSI-X capability register
36 * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
37 * from the MSI-X capability register
Gustavo Pimenteld3c70a92018-07-19 10:32:13 +020038 * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053039 * @start: ops to start the PCI link
40 * @stop: ops to stop the PCI link
41 * @owner: the module owner containing the ops
42 */
43struct pci_epc_ops {
Cyrille Pitchen44947382018-01-30 21:56:56 +010044 int (*write_header)(struct pci_epc *epc, u8 func_no,
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053045 struct pci_epf_header *hdr);
Cyrille Pitchen44947382018-01-30 21:56:56 +010046 int (*set_bar)(struct pci_epc *epc, u8 func_no,
Niklas Casselbc4a4892018-03-28 13:50:07 +020047 struct pci_epf_bar *epf_bar);
Cyrille Pitchen44947382018-01-30 21:56:56 +010048 void (*clear_bar)(struct pci_epc *epc, u8 func_no,
Niklas Cassel77d08db2018-03-28 13:50:14 +020049 struct pci_epf_bar *epf_bar);
Cyrille Pitchen44947382018-01-30 21:56:56 +010050 int (*map_addr)(struct pci_epc *epc, u8 func_no,
51 phys_addr_t addr, u64 pci_addr, size_t size);
52 void (*unmap_addr)(struct pci_epc *epc, u8 func_no,
53 phys_addr_t addr);
54 int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
55 int (*get_msi)(struct pci_epc *epc, u8 func_no);
Gustavo Pimentel89631062018-07-19 10:32:12 +020056 int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
57 int (*get_msix)(struct pci_epc *epc, u8 func_no);
Cyrille Pitchen44947382018-01-30 21:56:56 +010058 int (*raise_irq)(struct pci_epc *epc, u8 func_no,
Gustavo Pimenteld3c70a92018-07-19 10:32:13 +020059 enum pci_epc_irq_type type, u16 interrupt_num);
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053060 int (*start)(struct pci_epc *epc);
61 void (*stop)(struct pci_epc *epc);
Kishon Vijay Abraham I41cb8d12019-01-14 16:44:59 +053062 const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
63 u8 func_no);
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053064 struct module *owner;
65};
66
67/**
68 * struct pci_epc_mem - address space of the endpoint controller
69 * @phys_base: physical base address of the PCI address space
70 * @size: the size of the PCI address space
71 * @bitmap: bitmap to manage the PCI address space
72 * @pages: number of bits representing the address region
Kishon Vijay Abraham I52c92852017-08-18 20:27:56 +053073 * @page_size: size of each page
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053074 */
75struct pci_epc_mem {
76 phys_addr_t phys_base;
77 size_t size;
78 unsigned long *bitmap;
Kishon Vijay Abraham I52c92852017-08-18 20:27:56 +053079 size_t page_size;
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053080 int pages;
81};
82
83/**
84 * struct pci_epc - represents the PCI EPC device
85 * @dev: PCI EPC device
86 * @pci_epf: list of endpoint functions present in this EPC device
87 * @ops: function pointers for performing endpoint operations
88 * @mem: address space of the endpoint controller
89 * @max_functions: max number of functions that can be configured in this EPC
Kishon Vijay Abraham I3a401a22017-03-27 15:15:01 +053090 * @group: configfs group representing the PCI EPC device
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +053091 * @lock: spinlock to protect pci_epc ops
92 */
93struct pci_epc {
94 struct device dev;
95 struct list_head pci_epf;
96 const struct pci_epc_ops *ops;
97 struct pci_epc_mem *mem;
98 u8 max_functions;
Kishon Vijay Abraham I3a401a22017-03-27 15:15:01 +053099 struct config_group *group;
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +0530100 /* spinlock to protect against concurrent access of EP controller */
101 spinlock_t lock;
102};
103
Kishon Vijay Abraham I41cb8d12019-01-14 16:44:59 +0530104/**
105 * struct pci_epc_features - features supported by a EPC device per function
106 * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
107 * @msi_capable: indicate if the endpoint function has MSI capability
108 * @msix_capable: indicate if the endpoint function has MSI-X capability
109 * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
110 * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
111 * @bar_fixed_size: Array specifying the size supported by each BAR
112 */
113struct pci_epc_features {
114 unsigned int linkup_notifier : 1;
115 unsigned int msi_capable : 1;
116 unsigned int msix_capable : 1;
117 u8 reserved_bar;
118 u8 bar_fixed_64bit;
119 u64 bar_fixed_size[BAR_5 + 1];
120};
121
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +0530122#define to_pci_epc(device) container_of((device), struct pci_epc, dev)
123
124#define pci_epc_create(dev, ops) \
125 __pci_epc_create((dev), (ops), THIS_MODULE)
126#define devm_pci_epc_create(dev, ops) \
127 __devm_pci_epc_create((dev), (ops), THIS_MODULE)
128
Kishon Vijay Abraham I52c92852017-08-18 20:27:56 +0530129#define pci_epc_mem_init(epc, phys_addr, size) \
130 __pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE)
131
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +0530132static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
133{
134 dev_set_drvdata(&epc->dev, data);
135}
136
137static inline void *epc_get_drvdata(struct pci_epc *epc)
138{
139 return dev_get_drvdata(&epc->dev);
140}
141
142struct pci_epc *
143__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
144 struct module *owner);
145struct pci_epc *
146__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
147 struct module *owner);
148void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
149void pci_epc_destroy(struct pci_epc *epc);
150int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
151void pci_epc_linkup(struct pci_epc *epc);
152void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
Cyrille Pitchen44947382018-01-30 21:56:56 +0100153int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
154 struct pci_epf_header *hdr);
155int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
Niklas Casselbc4a4892018-03-28 13:50:07 +0200156 struct pci_epf_bar *epf_bar);
Niklas Cassel77d08db2018-03-28 13:50:14 +0200157void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
158 struct pci_epf_bar *epf_bar);
Cyrille Pitchen44947382018-01-30 21:56:56 +0100159int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
160 phys_addr_t phys_addr,
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +0530161 u64 pci_addr, size_t size);
Cyrille Pitchen44947382018-01-30 21:56:56 +0100162void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
163 phys_addr_t phys_addr);
164int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
165int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
Gustavo Pimentel89631062018-07-19 10:32:12 +0200166int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
167int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
Cyrille Pitchen44947382018-01-30 21:56:56 +0100168int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
Gustavo Pimenteld3c70a92018-07-19 10:32:13 +0200169 enum pci_epc_irq_type type, u16 interrupt_num);
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +0530170int pci_epc_start(struct pci_epc *epc);
171void pci_epc_stop(struct pci_epc *epc);
Kishon Vijay Abraham I41cb8d12019-01-14 16:44:59 +0530172const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
173 u8 func_no);
Kishon Vijay Abraham I1e9efe62019-01-14 16:45:05 +0530174unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
175 *epc_features);
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +0530176struct pci_epc *pci_epc_get(const char *epc_name);
177void pci_epc_put(struct pci_epc *epc);
178
Kishon Vijay Abraham I52c92852017-08-18 20:27:56 +0530179int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
180 size_t page_size);
Kishon Vijay Abraham I5e8cb402017-04-10 19:25:10 +0530181void pci_epc_mem_exit(struct pci_epc *epc);
182void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
183 phys_addr_t *phys_addr, size_t size);
184void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
185 void __iomem *virt_addr, size_t size);
186#endif /* __LINUX_PCI_EPC_H */