blob: a94ba1d48c0e7bfc71c2355998b9b7294782dff7 [file] [log] [blame]
Shawn Guo2954ff32012-05-04 21:33:42 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 interrupt-parent = <&icoll>;
16
Shawn Guoce4c6f92012-05-04 14:32:35 +080017 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
Shawn Guoa4508392012-06-28 11:45:00 +080021 serial0 = &auart0;
22 serial1 = &auart1;
Shawn Guoce4c6f92012-05-04 14:32:35 +080023 };
24
Shawn Guo2954ff32012-05-04 21:33:42 +080025 cpus {
26 cpu@0 {
27 compatible = "arm,arm926ejs";
28 };
29 };
30
31 apb@80000000 {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
35 reg = <0x80000000 0x80000>;
36 ranges;
37
38 apbh@80000000 {
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x80000000 0x40000>;
43 ranges;
44
45 icoll: interrupt-controller@80000000 {
46 compatible = "fsl,imx23-icoll", "fsl,mxs-icoll";
47 interrupt-controller;
48 #interrupt-cells = <1>;
49 reg = <0x80000000 0x2000>;
50 };
51
52 dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +080053 compatible = "fsl,imx23-dma-apbh";
Shawn Guo2954ff32012-05-04 21:33:42 +080054 reg = <0x80004000 2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +080055 };
56
57 ecc@80008000 {
58 reg = <0x80008000 2000>;
59 status = "disabled";
60 };
61
62 bch@8000a000 {
63 reg = <0x8000a000 2000>;
64 status = "disabled";
65 };
66
Marek Vasuta217c462012-06-09 01:21:55 +020067 gpmi-nand@8000c000 {
Shawn Guo2954ff32012-05-04 21:33:42 +080068 reg = <0x8000c000 2000>;
69 status = "disabled";
70 };
71
72 ssp0: ssp@80010000 {
73 reg = <0x80010000 2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +080074 interrupts = <15 14>;
75 fsl,ssp-dma-channel = <1>;
Shawn Guo2954ff32012-05-04 21:33:42 +080076 status = "disabled";
77 };
78
79 etm@80014000 {
80 reg = <0x80014000 2000>;
81 status = "disabled";
82 };
83
84 pinctrl@80018000 {
85 #address-cells = <1>;
86 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +080087 compatible = "fsl,imx23-pinctrl", "simple-bus";
Shawn Guo2954ff32012-05-04 21:33:42 +080088 reg = <0x80018000 2000>;
89
Shawn Guoce4c6f92012-05-04 14:32:35 +080090 gpio0: gpio@0 {
91 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
92 interrupts = <16>;
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 };
98
99 gpio1: gpio@1 {
100 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
101 interrupts = <17>;
102 gpio-controller;
103 #gpio-cells = <2>;
104 interrupt-controller;
105 #interrupt-cells = <2>;
106 };
107
108 gpio2: gpio@2 {
109 compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
110 interrupts = <18>;
111 gpio-controller;
112 #gpio-cells = <2>;
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 };
116
Shawn Guo2954ff32012-05-04 21:33:42 +0800117 duart_pins_a: duart@0 {
118 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800119 fsl,pinmux-ids = <
120 0x11a2 /* MX23_PAD_PWM0__DUART_RX */
121 0x11b2 /* MX23_PAD_PWM1__DUART_TX */
122 >;
Shawn Guo2954ff32012-05-04 21:33:42 +0800123 fsl,drive-strength = <0>;
124 fsl,voltage = <1>;
125 fsl,pull-up = <0>;
126 };
Shawn Guobe1ce302012-05-06 16:29:36 +0800127
Shawn Guoa4508392012-06-28 11:45:00 +0800128 auart0_pins_a: auart0@0 {
129 reg = <0>;
130 fsl,pinmux-ids = <
131 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
132 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
133 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
134 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
135 >;
136 fsl,drive-strength = <0>;
137 fsl,voltage = <1>;
138 fsl,pull-up = <0>;
139 };
140
Shawn Guo72beaba2012-06-28 11:44:59 +0800141 mmc0_4bit_pins_a: mmc0-4bit@0 {
142 reg = <0>;
143 fsl,pinmux-ids = <
144 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
145 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
146 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
147 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
148 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
149 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
150 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
151 >;
152 fsl,drive-strength = <1>;
153 fsl,voltage = <1>;
154 fsl,pull-up = <1>;
155 };
156
Shawn Guobe1ce302012-05-06 16:29:36 +0800157 mmc0_8bit_pins_a: mmc0-8bit@0 {
158 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800159 fsl,pinmux-ids = <
160 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
161 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
162 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
163 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
164 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
165 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
166 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
167 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
168 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
169 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
170 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
171 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800172 fsl,drive-strength = <1>;
173 fsl,voltage = <1>;
174 fsl,pull-up = <1>;
175 };
176
177 mmc0_pins_fixup: mmc0-pins-fixup {
Shawn Guof14da762012-06-28 11:44:57 +0800178 fsl,pinmux-ids = <
179 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
180 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
181 >;
Shawn Guobe1ce302012-05-06 16:29:36 +0800182 fsl,pull-up = <0>;
183 };
Shawn Guo2954ff32012-05-04 21:33:42 +0800184 };
185
186 digctl@8001c000 {
187 reg = <0x8001c000 2000>;
188 status = "disabled";
189 };
190
191 emi@80020000 {
192 reg = <0x80020000 2000>;
193 status = "disabled";
194 };
195
196 dma-apbx@80024000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800197 compatible = "fsl,imx23-dma-apbx";
Shawn Guo2954ff32012-05-04 21:33:42 +0800198 reg = <0x80024000 2000>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800199 };
200
201 dcp@80028000 {
202 reg = <0x80028000 2000>;
203 status = "disabled";
204 };
205
206 pxp@8002a000 {
207 reg = <0x8002a000 2000>;
208 status = "disabled";
209 };
210
211 ocotp@8002c000 {
212 reg = <0x8002c000 2000>;
213 status = "disabled";
214 };
215
216 axi-ahb@8002e000 {
217 reg = <0x8002e000 2000>;
218 status = "disabled";
219 };
220
221 lcdif@80030000 {
222 reg = <0x80030000 2000>;
223 status = "disabled";
224 };
225
226 ssp1: ssp@80034000 {
227 reg = <0x80034000 2000>;
Shawn Guobe1ce302012-05-06 16:29:36 +0800228 interrupts = <2 20>;
229 fsl,ssp-dma-channel = <2>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800230 status = "disabled";
231 };
232
233 tvenc@80038000 {
234 reg = <0x80038000 2000>;
235 status = "disabled";
236 };
237 };
238
239 apbx@80040000 {
240 compatible = "simple-bus";
241 #address-cells = <1>;
242 #size-cells = <1>;
243 reg = <0x80040000 0x40000>;
244 ranges;
245
246 clkctl@80040000 {
247 reg = <0x80040000 2000>;
248 status = "disabled";
249 };
250
251 saif0: saif@80042000 {
252 reg = <0x80042000 2000>;
253 status = "disabled";
254 };
255
256 power@80044000 {
257 reg = <0x80044000 2000>;
258 status = "disabled";
259 };
260
261 saif1: saif@80046000 {
262 reg = <0x80046000 2000>;
263 status = "disabled";
264 };
265
266 audio-out@80048000 {
267 reg = <0x80048000 2000>;
268 status = "disabled";
269 };
270
271 audio-in@8004c000 {
272 reg = <0x8004c000 2000>;
273 status = "disabled";
274 };
275
276 lradc@80050000 {
277 reg = <0x80050000 2000>;
278 status = "disabled";
279 };
280
281 spdif@80054000 {
282 reg = <0x80054000 2000>;
283 status = "disabled";
284 };
285
286 i2c@80058000 {
287 reg = <0x80058000 2000>;
288 status = "disabled";
289 };
290
291 rtc@8005c000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800292 compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
Shawn Guo2954ff32012-05-04 21:33:42 +0800293 reg = <0x8005c000 2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800294 interrupts = <22>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800295 };
296
297 pwm@80064000 {
298 reg = <0x80064000 2000>;
299 status = "disabled";
300 };
301
302 timrot@80068000 {
303 reg = <0x80068000 2000>;
304 status = "disabled";
305 };
306
307 auart0: serial@8006c000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800308 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800309 reg = <0x8006c000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800310 interrupts = <24 25 23>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800311 status = "disabled";
312 };
313
314 auart1: serial@8006e000 {
Shawn Guoa4508392012-06-28 11:45:00 +0800315 compatible = "fsl,imx23-auart";
Shawn Guo2954ff32012-05-04 21:33:42 +0800316 reg = <0x8006e000 0x2000>;
Shawn Guoa4508392012-06-28 11:45:00 +0800317 interrupts = <59 60 58>;
Shawn Guo2954ff32012-05-04 21:33:42 +0800318 status = "disabled";
319 };
320
321 duart: serial@80070000 {
322 compatible = "arm,pl011", "arm,primecell";
323 reg = <0x80070000 0x2000>;
324 interrupts = <0>;
325 status = "disabled";
326 };
327
328 usbphy@8007c000 {
329 reg = <0x8007c000 0x2000>;
330 status = "disabled";
331 };
332 };
333 };
334
335 ahb@80080000 {
336 compatible = "simple-bus";
337 #address-cells = <1>;
338 #size-cells = <1>;
339 reg = <0x80080000 0x80000>;
340 ranges;
341
342 usbctrl@80080000 {
343 reg = <0x80080000 0x10000>;
344 status = "disabled";
345 };
346 };
347};