| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Clocks for ux500 platforms |
| 3 | * |
| 4 | * Copyright (C) 2012 ST-Ericsson SA |
| 5 | * Author: Ulf Hansson <ulf.hansson@linaro.org> |
| 6 | * |
| 7 | * License terms: GNU General Public License (GPL) version 2 |
| 8 | */ |
| 9 | |
| 10 | #ifndef __UX500_CLK_H |
| 11 | #define __UX500_CLK_H |
| 12 | |
| Ulf Hansson | 5b82d03 | 2013-04-03 14:26:57 +0200 | [diff] [blame] | 13 | #include <linux/device.h> |
| Mike Turquette | c700835 | 2013-04-22 11:46:10 -0700 | [diff] [blame] | 14 | #include <linux/types.h> |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 15 | |
| Stephen Boyd | a162ca9 | 2015-06-19 15:00:46 -0700 | [diff] [blame] | 16 | struct clk; |
| 17 | |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 18 | struct clk *clk_reg_prcc_pclk(const char *name, |
| 19 | const char *parent_name, |
| Mike Turquette | c700835 | 2013-04-22 11:46:10 -0700 | [diff] [blame] | 20 | resource_size_t phy_base, |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 21 | u32 cg_sel, |
| 22 | unsigned long flags); |
| 23 | |
| 24 | struct clk *clk_reg_prcc_kclk(const char *name, |
| 25 | const char *parent_name, |
| Mike Turquette | c700835 | 2013-04-22 11:46:10 -0700 | [diff] [blame] | 26 | resource_size_t phy_base, |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 27 | u32 cg_sel, |
| 28 | unsigned long flags); |
| 29 | |
| 30 | struct clk *clk_reg_prcmu_scalable(const char *name, |
| 31 | const char *parent_name, |
| 32 | u8 cg_sel, |
| 33 | unsigned long rate, |
| 34 | unsigned long flags); |
| 35 | |
| 36 | struct clk *clk_reg_prcmu_gate(const char *name, |
| 37 | const char *parent_name, |
| 38 | u8 cg_sel, |
| 39 | unsigned long flags); |
| 40 | |
| Ulf Hansson | a816d25 | 2012-10-10 13:42:27 +0200 | [diff] [blame] | 41 | struct clk *clk_reg_prcmu_scalable_rate(const char *name, |
| 42 | const char *parent_name, |
| 43 | u8 cg_sel, |
| 44 | unsigned long rate, |
| 45 | unsigned long flags); |
| 46 | |
| Ulf Hansson | 70b1fce | 2012-08-31 14:21:29 +0200 | [diff] [blame] | 47 | struct clk *clk_reg_prcmu_rate(const char *name, |
| 48 | const char *parent_name, |
| 49 | u8 cg_sel, |
| 50 | unsigned long flags); |
| 51 | |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 52 | struct clk *clk_reg_prcmu_opp_gate(const char *name, |
| 53 | const char *parent_name, |
| 54 | u8 cg_sel, |
| 55 | unsigned long flags); |
| 56 | |
| Ulf Hansson | b0ea0fc | 2012-09-24 16:43:18 +0200 | [diff] [blame] | 57 | struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, |
| 58 | const char *parent_name, |
| 59 | u8 cg_sel, |
| 60 | unsigned long rate, |
| 61 | unsigned long flags); |
| 62 | |
| Ulf Hansson | 5b82d03 | 2013-04-03 14:26:57 +0200 | [diff] [blame] | 63 | struct clk *clk_reg_sysctrl_gate(struct device *dev, |
| 64 | const char *name, |
| 65 | const char *parent_name, |
| 66 | u16 reg_sel, |
| 67 | u8 reg_mask, |
| 68 | u8 reg_bits, |
| 69 | unsigned long enable_delay_us, |
| 70 | unsigned long flags); |
| 71 | |
| 72 | struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, |
| 73 | const char *name, |
| 74 | const char *parent_name, |
| 75 | u16 reg_sel, |
| 76 | u8 reg_mask, |
| 77 | u8 reg_bits, |
| 78 | unsigned long rate, |
| 79 | unsigned long enable_delay_us, |
| 80 | unsigned long flags); |
| 81 | |
| 82 | struct clk *clk_reg_sysctrl_set_parent(struct device *dev, |
| 83 | const char *name, |
| 84 | const char **parent_names, |
| 85 | u8 num_parents, |
| 86 | u16 *reg_sel, |
| 87 | u8 *reg_mask, |
| 88 | u8 *reg_bits, |
| 89 | unsigned long flags); |
| 90 | |
| Ulf Hansson | 3b01f87 | 2012-08-27 15:45:50 +0200 | [diff] [blame] | 91 | #endif /* __UX500_CLK_H */ |