Ben Skeggs | 56d237d | 2014-05-19 14:54:33 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2 | * Copyright 2011 Red Hat Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
| 24 | |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 25 | #include <linux/dma-mapping.h> |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 26 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 28 | #include <drm/drm_atomic.h> |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 29 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drm_crtc_helper.h> |
Ben Skeggs | 4874322 | 2014-05-31 01:48:06 +1000 | [diff] [blame] | 31 | #include <drm/drm_dp_helper.h> |
Daniel Vetter | b516a9e | 2015-12-04 09:45:43 +0100 | [diff] [blame] | 32 | #include <drm/drm_fb_helper.h> |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 33 | #include <drm/drm_plane_helper.h> |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 34 | |
Ben Skeggs | fdb751e | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 35 | #include <nvif/class.h> |
Ben Skeggs | 845f272 | 2015-11-08 12:16:40 +1000 | [diff] [blame] | 36 | #include <nvif/cl0002.h> |
Ben Skeggs | 7568b10 | 2015-11-08 10:44:19 +1000 | [diff] [blame] | 37 | #include <nvif/cl5070.h> |
| 38 | #include <nvif/cl507a.h> |
| 39 | #include <nvif/cl507b.h> |
| 40 | #include <nvif/cl507c.h> |
| 41 | #include <nvif/cl507d.h> |
| 42 | #include <nvif/cl507e.h> |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 43 | #include <nvif/event.h> |
Ben Skeggs | fdb751e | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 44 | |
Ben Skeggs | 4dc2813 | 2016-05-20 09:22:55 +1000 | [diff] [blame] | 45 | #include "nouveau_drv.h" |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 46 | #include "nouveau_dma.h" |
| 47 | #include "nouveau_gem.h" |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 48 | #include "nouveau_connector.h" |
| 49 | #include "nouveau_encoder.h" |
| 50 | #include "nouveau_crtc.h" |
Ben Skeggs | f589be8 | 2012-07-22 11:55:54 +1000 | [diff] [blame] | 51 | #include "nouveau_fence.h" |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 52 | #include "nouveau_fbcon.h" |
Ben Skeggs | 3a89cd0 | 2011-07-07 10:47:10 +1000 | [diff] [blame] | 53 | #include "nv50_display.h" |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 54 | |
Ben Skeggs | 8a46438 | 2011-11-12 23:52:07 +1000 | [diff] [blame] | 55 | #define EVO_DMA_NR 9 |
| 56 | |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 57 | #define EVO_MASTER (0x00) |
Ben Skeggs | a63a97e | 2011-11-16 15:22:34 +1000 | [diff] [blame] | 58 | #define EVO_FLIP(c) (0x01 + (c)) |
Ben Skeggs | 8a46438 | 2011-11-12 23:52:07 +1000 | [diff] [blame] | 59 | #define EVO_OVLY(c) (0x05 + (c)) |
| 60 | #define EVO_OIMM(c) (0x09 + (c)) |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 61 | #define EVO_CURS(c) (0x0d + (c)) |
| 62 | |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 63 | /* offsets in shared sync bo of various structures */ |
| 64 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 65 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
| 66 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) |
| 67 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 68 | #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20) |
| 69 | #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30) |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 70 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 71 | /****************************************************************************** |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 72 | * Atomic state |
| 73 | *****************************************************************************/ |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 74 | #define nv50_atom(p) container_of((p), struct nv50_atom, state) |
| 75 | |
| 76 | struct nv50_atom { |
| 77 | struct drm_atomic_state state; |
| 78 | |
| 79 | struct list_head outp; |
| 80 | bool lock_core; |
| 81 | bool flush_disable; |
| 82 | }; |
| 83 | |
| 84 | struct nv50_outp_atom { |
| 85 | struct list_head head; |
| 86 | |
| 87 | struct drm_encoder *encoder; |
| 88 | bool flush_disable; |
| 89 | |
| 90 | union { |
| 91 | struct { |
| 92 | bool ctrl:1; |
| 93 | }; |
| 94 | u8 mask; |
| 95 | } clr; |
| 96 | |
| 97 | union { |
| 98 | struct { |
| 99 | bool ctrl:1; |
| 100 | }; |
| 101 | u8 mask; |
| 102 | } set; |
| 103 | }; |
| 104 | |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 105 | #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state) |
| 106 | |
| 107 | struct nv50_head_atom { |
| 108 | struct drm_crtc_state state; |
| 109 | |
Ben Skeggs | c4e6812 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 110 | struct { |
| 111 | u16 iW; |
| 112 | u16 iH; |
| 113 | u16 oW; |
| 114 | u16 oH; |
| 115 | } view; |
| 116 | |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 117 | struct nv50_head_mode { |
| 118 | bool interlace; |
| 119 | u32 clock; |
| 120 | struct { |
| 121 | u16 active; |
| 122 | u16 synce; |
| 123 | u16 blanke; |
| 124 | u16 blanks; |
| 125 | } h; |
| 126 | struct { |
| 127 | u32 active; |
| 128 | u16 synce; |
| 129 | u16 blanke; |
| 130 | u16 blanks; |
| 131 | u16 blank2s; |
| 132 | u16 blank2e; |
| 133 | u16 blankus; |
| 134 | } v; |
| 135 | } mode; |
| 136 | |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 137 | struct { |
Ben Skeggs | a7ae156 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 138 | u32 handle; |
| 139 | u64 offset:40; |
| 140 | } lut; |
| 141 | |
| 142 | struct { |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 143 | bool visible; |
| 144 | u32 handle; |
| 145 | u64 offset:40; |
| 146 | u8 format; |
| 147 | u8 kind:7; |
| 148 | u8 layout:1; |
| 149 | u8 block:4; |
| 150 | u32 pitch:20; |
| 151 | u16 x; |
| 152 | u16 y; |
| 153 | u16 w; |
| 154 | u16 h; |
| 155 | } core; |
| 156 | |
| 157 | struct { |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 158 | bool visible; |
| 159 | u32 handle; |
| 160 | u64 offset:40; |
| 161 | u8 layout:1; |
| 162 | u8 format:1; |
| 163 | } curs; |
| 164 | |
| 165 | struct { |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 166 | u8 depth; |
| 167 | u8 cpp; |
| 168 | u16 x; |
| 169 | u16 y; |
| 170 | u16 w; |
| 171 | u16 h; |
| 172 | } base; |
| 173 | |
Ben Skeggs | 6bbab3b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 174 | struct { |
| 175 | u8 cpp; |
| 176 | } ovly; |
| 177 | |
Ben Skeggs | 7e91833 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 178 | struct { |
| 179 | bool enable:1; |
| 180 | u8 bits:2; |
| 181 | u8 mode:4; |
| 182 | } dither; |
| 183 | |
Ben Skeggs | 7e08d67 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 184 | struct { |
| 185 | struct { |
| 186 | u16 cos:12; |
| 187 | u16 sin:12; |
| 188 | } sat; |
| 189 | } procamp; |
| 190 | |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 191 | union { |
| 192 | struct { |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 193 | bool core:1; |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 194 | bool curs:1; |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 195 | }; |
| 196 | u8 mask; |
| 197 | } clr; |
| 198 | |
| 199 | union { |
| 200 | struct { |
| 201 | bool core:1; |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 202 | bool curs:1; |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 203 | bool view:1; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 204 | bool mode:1; |
Ben Skeggs | 6bbab3b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 205 | bool base:1; |
| 206 | bool ovly:1; |
Ben Skeggs | 7e91833 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 207 | bool dither:1; |
Ben Skeggs | 7e08d67 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 208 | bool procamp:1; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 209 | }; |
| 210 | u16 mask; |
| 211 | } set; |
| 212 | }; |
| 213 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 214 | static inline struct nv50_head_atom * |
| 215 | nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) |
| 216 | { |
| 217 | struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc); |
| 218 | if (IS_ERR(statec)) |
| 219 | return (void *)statec; |
| 220 | return nv50_head_atom(statec); |
| 221 | } |
| 222 | |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 223 | #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state) |
| 224 | |
| 225 | struct nv50_wndw_atom { |
| 226 | struct drm_plane_state state; |
| 227 | u8 interval; |
| 228 | |
| 229 | struct drm_rect clip; |
| 230 | |
| 231 | struct { |
| 232 | u32 handle; |
| 233 | u16 offset:12; |
| 234 | bool awaken:1; |
| 235 | } ntfy; |
| 236 | |
| 237 | struct { |
| 238 | u32 handle; |
| 239 | u16 offset:12; |
| 240 | u32 acquire; |
| 241 | u32 release; |
| 242 | } sema; |
| 243 | |
| 244 | struct { |
| 245 | u8 enable:2; |
| 246 | } lut; |
| 247 | |
| 248 | struct { |
| 249 | u8 mode:2; |
| 250 | u8 interval:4; |
| 251 | |
| 252 | u8 format; |
| 253 | u8 kind:7; |
| 254 | u8 layout:1; |
| 255 | u8 block:4; |
| 256 | u32 pitch:20; |
| 257 | u16 w; |
| 258 | u16 h; |
| 259 | |
| 260 | u32 handle; |
| 261 | u64 offset; |
| 262 | } image; |
| 263 | |
| 264 | struct { |
| 265 | u16 x; |
| 266 | u16 y; |
| 267 | } point; |
| 268 | |
| 269 | union { |
| 270 | struct { |
| 271 | bool ntfy:1; |
| 272 | bool sema:1; |
| 273 | bool image:1; |
| 274 | }; |
| 275 | u8 mask; |
| 276 | } clr; |
| 277 | |
| 278 | union { |
| 279 | struct { |
| 280 | bool ntfy:1; |
| 281 | bool sema:1; |
| 282 | bool image:1; |
| 283 | bool lut:1; |
| 284 | bool point:1; |
| 285 | }; |
| 286 | u8 mask; |
| 287 | } set; |
| 288 | }; |
| 289 | |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 290 | /****************************************************************************** |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 291 | * EVO channel |
| 292 | *****************************************************************************/ |
| 293 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 294 | struct nv50_chan { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 295 | struct nvif_object user; |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 296 | struct nvif_device *device; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 297 | }; |
| 298 | |
| 299 | static int |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 300 | nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 301 | const s32 *oclass, u8 head, void *data, u32 size, |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 302 | struct nv50_chan *chan) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 303 | { |
Ben Skeggs | 41a6340 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 304 | struct nvif_sclass *sclass; |
| 305 | int ret, i, n; |
Ben Skeggs | 6af5289 | 2014-11-03 15:01:33 +1000 | [diff] [blame] | 306 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 307 | chan->device = device; |
| 308 | |
Ben Skeggs | 41a6340 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 309 | ret = n = nvif_object_sclass_get(disp, &sclass); |
Ben Skeggs | 6af5289 | 2014-11-03 15:01:33 +1000 | [diff] [blame] | 310 | if (ret < 0) |
| 311 | return ret; |
| 312 | |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 313 | while (oclass[0]) { |
Ben Skeggs | 41a6340 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 314 | for (i = 0; i < n; i++) { |
| 315 | if (sclass[i].oclass == oclass[0]) { |
Ben Skeggs | fcf3f91 | 2015-09-04 14:40:32 +1000 | [diff] [blame] | 316 | ret = nvif_object_init(disp, 0, oclass[0], |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 317 | data, size, &chan->user); |
Ben Skeggs | 6af5289 | 2014-11-03 15:01:33 +1000 | [diff] [blame] | 318 | if (ret == 0) |
| 319 | nvif_object_map(&chan->user); |
Ben Skeggs | 41a6340 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 320 | nvif_object_sclass_put(&sclass); |
Ben Skeggs | 6af5289 | 2014-11-03 15:01:33 +1000 | [diff] [blame] | 321 | return ret; |
| 322 | } |
Ben Skeggs | b76f152 | 2014-08-10 04:10:28 +1000 | [diff] [blame] | 323 | } |
Ben Skeggs | 6af5289 | 2014-11-03 15:01:33 +1000 | [diff] [blame] | 324 | oclass++; |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 325 | } |
Ben Skeggs | 6af5289 | 2014-11-03 15:01:33 +1000 | [diff] [blame] | 326 | |
Ben Skeggs | 41a6340 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 327 | nvif_object_sclass_put(&sclass); |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 328 | return -ENOSYS; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | static void |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 332 | nv50_chan_destroy(struct nv50_chan *chan) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 333 | { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 334 | nvif_object_fini(&chan->user); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | /****************************************************************************** |
| 338 | * PIO EVO channel |
| 339 | *****************************************************************************/ |
| 340 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 341 | struct nv50_pioc { |
| 342 | struct nv50_chan base; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 343 | }; |
| 344 | |
| 345 | static void |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 346 | nv50_pioc_destroy(struct nv50_pioc *pioc) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 347 | { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 348 | nv50_chan_destroy(&pioc->base); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | static int |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 352 | nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp, |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 353 | const s32 *oclass, u8 head, void *data, u32 size, |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 354 | struct nv50_pioc *pioc) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 355 | { |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 356 | return nv50_chan_create(device, disp, oclass, head, data, size, |
| 357 | &pioc->base); |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | /****************************************************************************** |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 361 | * Overlay Immediate |
| 362 | *****************************************************************************/ |
| 363 | |
| 364 | struct nv50_oimm { |
| 365 | struct nv50_pioc base; |
| 366 | }; |
| 367 | |
| 368 | static int |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 369 | nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp, |
| 370 | int head, struct nv50_oimm *oimm) |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 371 | { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 372 | struct nv50_disp_cursor_v0 args = { |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 373 | .head = head, |
| 374 | }; |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 375 | static const s32 oclass[] = { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 376 | GK104_DISP_OVERLAY, |
| 377 | GF110_DISP_OVERLAY, |
| 378 | GT214_DISP_OVERLAY, |
| 379 | G82_DISP_OVERLAY, |
| 380 | NV50_DISP_OVERLAY, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 381 | 0 |
| 382 | }; |
| 383 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 384 | return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args), |
| 385 | &oimm->base); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 386 | } |
| 387 | |
| 388 | /****************************************************************************** |
| 389 | * DMA EVO channel |
| 390 | *****************************************************************************/ |
| 391 | |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 392 | struct nv50_dmac_ctxdma { |
| 393 | struct list_head head; |
| 394 | struct nvif_object object; |
| 395 | }; |
| 396 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 397 | struct nv50_dmac { |
| 398 | struct nv50_chan base; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 399 | dma_addr_t handle; |
| 400 | u32 *ptr; |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 401 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 402 | struct nvif_object sync; |
| 403 | struct nvif_object vram; |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 404 | struct list_head ctxdma; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 405 | |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 406 | /* Protects against concurrent pushbuf access to this channel, lock is |
| 407 | * grabbed by evo_wait (if the pushbuf reservation is successful) and |
| 408 | * dropped again by evo_kick. */ |
| 409 | struct mutex lock; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 410 | }; |
| 411 | |
| 412 | static void |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 413 | nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma) |
| 414 | { |
| 415 | nvif_object_fini(&ctxdma->object); |
| 416 | list_del(&ctxdma->head); |
| 417 | kfree(ctxdma); |
| 418 | } |
| 419 | |
| 420 | static struct nv50_dmac_ctxdma * |
Ben Skeggs | f00f0e2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 421 | nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb) |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 422 | { |
| 423 | struct nouveau_drm *drm = nouveau_drm(fb->base.dev); |
| 424 | struct nv50_dmac_ctxdma *ctxdma; |
Ben Skeggs | f00f0e2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 425 | const u8 kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8; |
| 426 | const u32 handle = 0xfb000000 | kind; |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 427 | struct { |
| 428 | struct nv_dma_v0 base; |
| 429 | union { |
| 430 | struct nv50_dma_v0 nv50; |
| 431 | struct gf100_dma_v0 gf100; |
| 432 | struct gf119_dma_v0 gf119; |
| 433 | }; |
| 434 | } args = {}; |
| 435 | u32 argc = sizeof(args.base); |
| 436 | int ret; |
| 437 | |
| 438 | list_for_each_entry(ctxdma, &dmac->ctxdma, head) { |
| 439 | if (ctxdma->object.handle == handle) |
| 440 | return ctxdma; |
| 441 | } |
| 442 | |
| 443 | if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL))) |
| 444 | return ERR_PTR(-ENOMEM); |
| 445 | list_add(&ctxdma->head, &dmac->ctxdma); |
| 446 | |
| 447 | args.base.target = NV_DMA_V0_TARGET_VRAM; |
| 448 | args.base.access = NV_DMA_V0_ACCESS_RDWR; |
| 449 | args.base.start = 0; |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 450 | args.base.limit = drm->client.device.info.ram_user - 1; |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 451 | |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 452 | if (drm->client.device.info.chipset < 0x80) { |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 453 | args.nv50.part = NV50_DMA_V0_PART_256; |
| 454 | argc += sizeof(args.nv50); |
| 455 | } else |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 456 | if (drm->client.device.info.chipset < 0xc0) { |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 457 | args.nv50.part = NV50_DMA_V0_PART_256; |
| 458 | args.nv50.kind = kind; |
| 459 | argc += sizeof(args.nv50); |
| 460 | } else |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 461 | if (drm->client.device.info.chipset < 0xd0) { |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 462 | args.gf100.kind = kind; |
| 463 | argc += sizeof(args.gf100); |
| 464 | } else { |
| 465 | args.gf119.page = GF119_DMA_V0_PAGE_LP; |
| 466 | args.gf119.kind = kind; |
| 467 | argc += sizeof(args.gf119); |
| 468 | } |
| 469 | |
| 470 | ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY, |
| 471 | &args, argc, &ctxdma->object); |
| 472 | if (ret) { |
| 473 | nv50_dmac_ctxdma_del(ctxdma); |
| 474 | return ERR_PTR(ret); |
| 475 | } |
| 476 | |
| 477 | return ctxdma; |
| 478 | } |
| 479 | |
| 480 | static void |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 481 | nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 482 | { |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 483 | struct nvif_device *device = dmac->base.device; |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 484 | struct nv50_dmac_ctxdma *ctxdma, *ctxtmp; |
| 485 | |
| 486 | list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) { |
| 487 | nv50_dmac_ctxdma_del(ctxdma); |
| 488 | } |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 489 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 490 | nvif_object_fini(&dmac->vram); |
| 491 | nvif_object_fini(&dmac->sync); |
| 492 | |
| 493 | nv50_chan_destroy(&dmac->base); |
| 494 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 495 | if (dmac->ptr) { |
Ben Skeggs | 26c9e8e | 2015-08-20 14:54:23 +1000 | [diff] [blame] | 496 | struct device *dev = nvxx_device(device)->dev; |
| 497 | dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 498 | } |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | static int |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 502 | nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 503 | const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf, |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 504 | struct nv50_dmac *dmac) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 505 | { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 506 | struct nv50_disp_core_channel_dma_v0 *args = data; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 507 | struct nvif_object pushbuf; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 508 | int ret; |
| 509 | |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 510 | mutex_init(&dmac->lock); |
| 511 | |
Ben Skeggs | 26c9e8e | 2015-08-20 14:54:23 +1000 | [diff] [blame] | 512 | dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE, |
| 513 | &dmac->handle, GFP_KERNEL); |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 514 | if (!dmac->ptr) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 515 | return -ENOMEM; |
| 516 | |
Ben Skeggs | fcf3f91 | 2015-09-04 14:40:32 +1000 | [diff] [blame] | 517 | ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, |
| 518 | &(struct nv_dma_v0) { |
Ben Skeggs | 4acfd70 | 2014-08-10 04:10:24 +1000 | [diff] [blame] | 519 | .target = NV_DMA_V0_TARGET_PCI_US, |
| 520 | .access = NV_DMA_V0_ACCESS_RD, |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 521 | .start = dmac->handle + 0x0000, |
| 522 | .limit = dmac->handle + 0x0fff, |
Ben Skeggs | 4acfd70 | 2014-08-10 04:10:24 +1000 | [diff] [blame] | 523 | }, sizeof(struct nv_dma_v0), &pushbuf); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 524 | if (ret) |
| 525 | return ret; |
| 526 | |
Ben Skeggs | bf81df9 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 527 | args->pushbuf = nvif_handle(&pushbuf); |
| 528 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 529 | ret = nv50_chan_create(device, disp, oclass, head, data, size, |
| 530 | &dmac->base); |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 531 | nvif_object_fini(&pushbuf); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 532 | if (ret) |
| 533 | return ret; |
| 534 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 535 | ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY, |
Ben Skeggs | 4acfd70 | 2014-08-10 04:10:24 +1000 | [diff] [blame] | 536 | &(struct nv_dma_v0) { |
| 537 | .target = NV_DMA_V0_TARGET_VRAM, |
| 538 | .access = NV_DMA_V0_ACCESS_RDWR, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 539 | .start = syncbuf + 0x0000, |
| 540 | .limit = syncbuf + 0x0fff, |
Ben Skeggs | 4acfd70 | 2014-08-10 04:10:24 +1000 | [diff] [blame] | 541 | }, sizeof(struct nv_dma_v0), |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 542 | &dmac->sync); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 543 | if (ret) |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 544 | return ret; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 545 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 546 | ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY, |
Ben Skeggs | 4acfd70 | 2014-08-10 04:10:24 +1000 | [diff] [blame] | 547 | &(struct nv_dma_v0) { |
| 548 | .target = NV_DMA_V0_TARGET_VRAM, |
| 549 | .access = NV_DMA_V0_ACCESS_RDWR, |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 550 | .start = 0, |
Ben Skeggs | f392ec4 | 2014-08-10 04:10:28 +1000 | [diff] [blame] | 551 | .limit = device->info.ram_user - 1, |
Ben Skeggs | 4acfd70 | 2014-08-10 04:10:24 +1000 | [diff] [blame] | 552 | }, sizeof(struct nv_dma_v0), |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 553 | &dmac->vram); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 554 | if (ret) |
Ben Skeggs | 4705730 | 2012-11-16 13:58:48 +1000 | [diff] [blame] | 555 | return ret; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 556 | |
Ben Skeggs | accdea2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 557 | INIT_LIST_HEAD(&dmac->ctxdma); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 558 | return ret; |
| 559 | } |
| 560 | |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 561 | /****************************************************************************** |
| 562 | * Core |
| 563 | *****************************************************************************/ |
| 564 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 565 | struct nv50_mast { |
| 566 | struct nv50_dmac base; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 567 | }; |
| 568 | |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 569 | static int |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 570 | nv50_core_create(struct nvif_device *device, struct nvif_object *disp, |
| 571 | u64 syncbuf, struct nv50_mast *core) |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 572 | { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 573 | struct nv50_disp_core_channel_dma_v0 args = { |
| 574 | .pushbuf = 0xb0007d00, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 575 | }; |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 576 | static const s32 oclass[] = { |
Ben Skeggs | ed82866 | 2016-11-16 15:03:07 +1000 | [diff] [blame] | 577 | GP102_DISP_CORE_CHANNEL_DMA, |
Ben Skeggs | f9d5cbb | 2016-07-09 10:41:01 +1000 | [diff] [blame] | 578 | GP100_DISP_CORE_CHANNEL_DMA, |
Ben Skeggs | db1eb52 | 2016-02-11 08:35:32 +1000 | [diff] [blame] | 579 | GM200_DISP_CORE_CHANNEL_DMA, |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 580 | GM107_DISP_CORE_CHANNEL_DMA, |
| 581 | GK110_DISP_CORE_CHANNEL_DMA, |
| 582 | GK104_DISP_CORE_CHANNEL_DMA, |
| 583 | GF110_DISP_CORE_CHANNEL_DMA, |
| 584 | GT214_DISP_CORE_CHANNEL_DMA, |
| 585 | GT206_DISP_CORE_CHANNEL_DMA, |
| 586 | GT200_DISP_CORE_CHANNEL_DMA, |
| 587 | G82_DISP_CORE_CHANNEL_DMA, |
| 588 | NV50_DISP_CORE_CHANNEL_DMA, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 589 | 0 |
| 590 | }; |
| 591 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 592 | return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args), |
| 593 | syncbuf, &core->base); |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 594 | } |
| 595 | |
| 596 | /****************************************************************************** |
| 597 | * Base |
| 598 | *****************************************************************************/ |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 599 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 600 | struct nv50_sync { |
| 601 | struct nv50_dmac base; |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 602 | u32 addr; |
| 603 | u32 data; |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 604 | }; |
| 605 | |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 606 | static int |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 607 | nv50_base_create(struct nvif_device *device, struct nvif_object *disp, |
| 608 | int head, u64 syncbuf, struct nv50_sync *base) |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 609 | { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 610 | struct nv50_disp_base_channel_dma_v0 args = { |
| 611 | .pushbuf = 0xb0007c00 | head, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 612 | .head = head, |
| 613 | }; |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 614 | static const s32 oclass[] = { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 615 | GK110_DISP_BASE_CHANNEL_DMA, |
| 616 | GK104_DISP_BASE_CHANNEL_DMA, |
| 617 | GF110_DISP_BASE_CHANNEL_DMA, |
| 618 | GT214_DISP_BASE_CHANNEL_DMA, |
| 619 | GT200_DISP_BASE_CHANNEL_DMA, |
| 620 | G82_DISP_BASE_CHANNEL_DMA, |
| 621 | NV50_DISP_BASE_CHANNEL_DMA, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 622 | 0 |
| 623 | }; |
| 624 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 625 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 626 | syncbuf, &base->base); |
| 627 | } |
| 628 | |
| 629 | /****************************************************************************** |
| 630 | * Overlay |
| 631 | *****************************************************************************/ |
| 632 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 633 | struct nv50_ovly { |
| 634 | struct nv50_dmac base; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 635 | }; |
Ben Skeggs | f20ce96 | 2011-07-08 13:17:01 +1000 | [diff] [blame] | 636 | |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 637 | static int |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 638 | nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp, |
| 639 | int head, u64 syncbuf, struct nv50_ovly *ovly) |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 640 | { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 641 | struct nv50_disp_overlay_channel_dma_v0 args = { |
| 642 | .pushbuf = 0xb0007e00 | head, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 643 | .head = head, |
| 644 | }; |
Ben Skeggs | 315a8b2 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 645 | static const s32 oclass[] = { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 646 | GK104_DISP_OVERLAY_CONTROL_DMA, |
| 647 | GF110_DISP_OVERLAY_CONTROL_DMA, |
| 648 | GT214_DISP_OVERLAY_CHANNEL_DMA, |
| 649 | GT200_DISP_OVERLAY_CHANNEL_DMA, |
| 650 | G82_DISP_OVERLAY_CHANNEL_DMA, |
| 651 | NV50_DISP_OVERLAY_CHANNEL_DMA, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 652 | 0 |
| 653 | }; |
| 654 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 655 | return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args), |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 656 | syncbuf, &ovly->base); |
| 657 | } |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 658 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 659 | struct nv50_head { |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 660 | struct nouveau_crtc base; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 661 | struct nv50_ovly ovly; |
| 662 | struct nv50_oimm oimm; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 663 | }; |
| 664 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 665 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 666 | #define nv50_ovly(c) (&nv50_head(c)->ovly) |
| 667 | #define nv50_oimm(c) (&nv50_head(c)->oimm) |
| 668 | #define nv50_chan(c) (&(c)->base.base) |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 669 | #define nv50_vers(c) nv50_chan(c)->user.oclass |
| 670 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 671 | struct nv50_disp { |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 672 | struct nvif_object *disp; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 673 | struct nv50_mast mast; |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 674 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 675 | struct nouveau_bo *sync; |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 676 | |
| 677 | struct mutex mutex; |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 678 | }; |
| 679 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 680 | static struct nv50_disp * |
| 681 | nv50_disp(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 682 | { |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 683 | return nouveau_display(dev)->priv; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 684 | } |
| 685 | |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 686 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 687 | |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 688 | /****************************************************************************** |
| 689 | * EVO channel helpers |
| 690 | *****************************************************************************/ |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 691 | static u32 * |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 692 | evo_wait(void *evoc, int nr) |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 693 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 694 | struct nv50_dmac *dmac = evoc; |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 695 | struct nvif_device *device = dmac->base.device; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 696 | u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 697 | |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 698 | mutex_lock(&dmac->lock); |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 699 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 700 | dmac->ptr[put] = 0x20000000; |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 701 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 702 | nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); |
Ben Skeggs | 5444204 | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 703 | if (nvif_msec(device, 2000, |
| 704 | if (!nvif_rd32(&dmac->base.user, 0x0004)) |
| 705 | break; |
| 706 | ) < 0) { |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 707 | mutex_unlock(&dmac->lock); |
Joe Perches | 8dfe162 | 2017-02-28 04:55:54 -0800 | [diff] [blame] | 708 | pr_err("nouveau: evo channel stalled\n"); |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 709 | return NULL; |
| 710 | } |
| 711 | |
| 712 | put = 0; |
| 713 | } |
| 714 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 715 | return dmac->ptr + put; |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 716 | } |
| 717 | |
| 718 | static void |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 719 | evo_kick(u32 *push, void *evoc) |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 720 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 721 | struct nv50_dmac *dmac = evoc; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 722 | nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
Daniel Vetter | 59ad146 | 2012-12-02 14:49:44 +0100 | [diff] [blame] | 723 | mutex_unlock(&dmac->lock); |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 724 | } |
| 725 | |
Joe Perches | 8dfe162 | 2017-02-28 04:55:54 -0800 | [diff] [blame] | 726 | #define evo_mthd(p, m, s) do { \ |
| 727 | const u32 _m = (m), _s = (s); \ |
| 728 | if (drm_debug & DRM_UT_KMS) \ |
| 729 | pr_err("%04x %d %s\n", _m, _s, __func__); \ |
| 730 | *((p)++) = ((_s << 18) | _m); \ |
Ben Skeggs | 2b1930c | 2014-11-03 16:43:59 +1000 | [diff] [blame] | 731 | } while(0) |
Ben Skeggs | 7f55a07 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 732 | |
Joe Perches | 8dfe162 | 2017-02-28 04:55:54 -0800 | [diff] [blame] | 733 | #define evo_data(p, d) do { \ |
| 734 | const u32 _d = (d); \ |
| 735 | if (drm_debug & DRM_UT_KMS) \ |
| 736 | pr_err("\t%08x\n", _d); \ |
| 737 | *((p)++) = _d; \ |
Ben Skeggs | 2b1930c | 2014-11-03 16:43:59 +1000 | [diff] [blame] | 738 | } while(0) |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 739 | |
Ben Skeggs | 3376ee3 | 2011-11-12 14:28:12 +1000 | [diff] [blame] | 740 | /****************************************************************************** |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 741 | * Plane |
| 742 | *****************************************************************************/ |
| 743 | #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane) |
| 744 | |
| 745 | struct nv50_wndw { |
| 746 | const struct nv50_wndw_func *func; |
| 747 | struct nv50_dmac *dmac; |
| 748 | |
| 749 | struct drm_plane plane; |
| 750 | |
| 751 | struct nvif_notify notify; |
| 752 | u16 ntfy; |
| 753 | u16 sema; |
| 754 | u32 data; |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 755 | }; |
| 756 | |
| 757 | struct nv50_wndw_func { |
| 758 | void *(*dtor)(struct nv50_wndw *); |
| 759 | int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, |
| 760 | struct nv50_head_atom *asyh); |
| 761 | void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw, |
| 762 | struct nv50_head_atom *asyh); |
| 763 | void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh, |
| 764 | struct nv50_wndw_atom *asyw); |
| 765 | |
| 766 | void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *); |
| 767 | void (*sema_clr)(struct nv50_wndw *); |
| 768 | void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); |
| 769 | void (*ntfy_clr)(struct nv50_wndw *); |
| 770 | int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *); |
| 771 | void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); |
| 772 | void (*image_clr)(struct nv50_wndw *); |
| 773 | void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *); |
| 774 | void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); |
| 775 | |
| 776 | u32 (*update)(struct nv50_wndw *, u32 interlock); |
| 777 | }; |
| 778 | |
| 779 | static int |
| 780 | nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) |
| 781 | { |
| 782 | if (asyw->set.ntfy) |
| 783 | return wndw->func->ntfy_wait_begun(wndw, asyw); |
| 784 | return 0; |
| 785 | } |
| 786 | |
| 787 | static u32 |
| 788 | nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush, |
| 789 | struct nv50_wndw_atom *asyw) |
| 790 | { |
| 791 | if (asyw->clr.sema && (!asyw->set.sema || flush)) |
| 792 | wndw->func->sema_clr(wndw); |
| 793 | if (asyw->clr.ntfy && (!asyw->set.ntfy || flush)) |
| 794 | wndw->func->ntfy_clr(wndw); |
| 795 | if (asyw->clr.image && (!asyw->set.image || flush)) |
| 796 | wndw->func->image_clr(wndw); |
| 797 | |
| 798 | return flush ? wndw->func->update(wndw, interlock) : 0; |
| 799 | } |
| 800 | |
| 801 | static u32 |
| 802 | nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock, |
| 803 | struct nv50_wndw_atom *asyw) |
| 804 | { |
| 805 | if (interlock) { |
| 806 | asyw->image.mode = 0; |
| 807 | asyw->image.interval = 1; |
| 808 | } |
| 809 | |
| 810 | if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw); |
| 811 | if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw); |
| 812 | if (asyw->set.image) wndw->func->image_set(wndw, asyw); |
| 813 | if (asyw->set.lut ) wndw->func->lut (wndw, asyw); |
| 814 | if (asyw->set.point) wndw->func->point (wndw, asyw); |
| 815 | |
| 816 | return wndw->func->update(wndw, interlock); |
| 817 | } |
| 818 | |
| 819 | static void |
| 820 | nv50_wndw_atomic_check_release(struct nv50_wndw *wndw, |
| 821 | struct nv50_wndw_atom *asyw, |
| 822 | struct nv50_head_atom *asyh) |
| 823 | { |
| 824 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); |
| 825 | NV_ATOMIC(drm, "%s release\n", wndw->plane.name); |
| 826 | wndw->func->release(wndw, asyw, asyh); |
| 827 | asyw->ntfy.handle = 0; |
| 828 | asyw->sema.handle = 0; |
| 829 | } |
| 830 | |
| 831 | static int |
| 832 | nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, |
| 833 | struct nv50_wndw_atom *asyw, |
Ben Skeggs | f42c570 | 2017-05-01 16:59:29 +1000 | [diff] [blame^] | 834 | struct nv50_head_atom *asyh) |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 835 | { |
| 836 | struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb); |
| 837 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); |
| 838 | int ret; |
| 839 | |
| 840 | NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name); |
| 841 | asyw->clip.x1 = 0; |
| 842 | asyw->clip.y1 = 0; |
| 843 | asyw->clip.x2 = asyh->state.mode.hdisplay; |
| 844 | asyw->clip.y2 = asyh->state.mode.vdisplay; |
| 845 | |
| 846 | asyw->image.w = fb->base.width; |
| 847 | asyw->image.h = fb->base.height; |
| 848 | asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8; |
Andrey Grodzovsky | 612fb5d | 2017-02-02 16:56:30 -0500 | [diff] [blame] | 849 | |
Ben Skeggs | f42c570 | 2017-05-01 16:59:29 +1000 | [diff] [blame^] | 850 | if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) |
| 851 | asyw->interval = 0; |
| 852 | else |
| 853 | asyw->interval = 1; |
Andrey Grodzovsky | 612fb5d | 2017-02-02 16:56:30 -0500 | [diff] [blame] | 854 | |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 855 | if (asyw->image.kind) { |
| 856 | asyw->image.layout = 0; |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 857 | if (drm->client.device.info.chipset >= 0xc0) |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 858 | asyw->image.block = fb->nvbo->tile_mode >> 4; |
| 859 | else |
| 860 | asyw->image.block = fb->nvbo->tile_mode; |
| 861 | asyw->image.pitch = (fb->base.pitches[0] / 4) << 4; |
| 862 | } else { |
| 863 | asyw->image.layout = 1; |
| 864 | asyw->image.block = 0; |
| 865 | asyw->image.pitch = fb->base.pitches[0]; |
| 866 | } |
| 867 | |
| 868 | ret = wndw->func->acquire(wndw, asyw, asyh); |
| 869 | if (ret) |
| 870 | return ret; |
| 871 | |
| 872 | if (asyw->set.image) { |
| 873 | if (!(asyw->image.mode = asyw->interval ? 0 : 1)) |
| 874 | asyw->image.interval = asyw->interval; |
| 875 | else |
| 876 | asyw->image.interval = 0; |
| 877 | } |
| 878 | |
| 879 | return 0; |
| 880 | } |
| 881 | |
| 882 | static int |
| 883 | nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) |
| 884 | { |
| 885 | struct nouveau_drm *drm = nouveau_drm(plane->dev); |
| 886 | struct nv50_wndw *wndw = nv50_wndw(plane); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 887 | struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state); |
| 888 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 889 | struct nv50_head_atom *harm = NULL, *asyh = NULL; |
| 890 | bool varm = false, asyv = false, asym = false; |
| 891 | int ret; |
| 892 | |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 893 | NV_ATOMIC(drm, "%s atomic_check\n", plane->name); |
| 894 | if (asyw->state.crtc) { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 895 | asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 896 | if (IS_ERR(asyh)) |
| 897 | return PTR_ERR(asyh); |
| 898 | asym = drm_atomic_crtc_needs_modeset(&asyh->state); |
| 899 | asyv = asyh->state.active; |
| 900 | } |
| 901 | |
| 902 | if (armw->state.crtc) { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 903 | harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 904 | if (IS_ERR(harm)) |
| 905 | return PTR_ERR(harm); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 906 | varm = harm->state.crtc->state->active; |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 907 | } |
| 908 | |
| 909 | if (asyv) { |
| 910 | asyw->point.x = asyw->state.crtc_x; |
| 911 | asyw->point.y = asyw->state.crtc_y; |
| 912 | if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point))) |
| 913 | asyw->set.point = true; |
| 914 | |
| 915 | if (!varm || asym || armw->state.fb != asyw->state.fb) { |
Ben Skeggs | f42c570 | 2017-05-01 16:59:29 +1000 | [diff] [blame^] | 916 | ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 917 | if (ret) |
| 918 | return ret; |
| 919 | } |
| 920 | } else |
| 921 | if (varm) { |
| 922 | nv50_wndw_atomic_check_release(wndw, asyw, harm); |
| 923 | } else { |
| 924 | return 0; |
| 925 | } |
| 926 | |
| 927 | if (!asyv || asym) { |
| 928 | asyw->clr.ntfy = armw->ntfy.handle != 0; |
| 929 | asyw->clr.sema = armw->sema.handle != 0; |
| 930 | if (wndw->func->image_clr) |
| 931 | asyw->clr.image = armw->image.handle != 0; |
| 932 | asyw->set.lut = wndw->func->lut && asyv; |
| 933 | } |
| 934 | |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 935 | return 0; |
| 936 | } |
| 937 | |
| 938 | static void |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 939 | nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state) |
| 940 | { |
| 941 | struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb); |
| 942 | struct nouveau_drm *drm = nouveau_drm(plane->dev); |
| 943 | |
| 944 | NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb); |
| 945 | if (!old_state->fb) |
| 946 | return; |
| 947 | |
| 948 | nouveau_bo_unpin(fb->nvbo); |
| 949 | } |
| 950 | |
| 951 | static int |
| 952 | nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state) |
| 953 | { |
| 954 | struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb); |
| 955 | struct nouveau_drm *drm = nouveau_drm(plane->dev); |
| 956 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 957 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); |
| 958 | struct nv50_head_atom *asyh; |
| 959 | struct nv50_dmac_ctxdma *ctxdma; |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 960 | int ret; |
| 961 | |
| 962 | NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb); |
| 963 | if (!asyw->state.fb) |
| 964 | return 0; |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 965 | |
| 966 | ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true); |
| 967 | if (ret) |
| 968 | return ret; |
| 969 | |
Ben Skeggs | f00f0e2 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 970 | ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 971 | if (IS_ERR(ctxdma)) { |
| 972 | nouveau_bo_unpin(fb->nvbo); |
| 973 | return PTR_ERR(ctxdma); |
| 974 | } |
| 975 | |
| 976 | asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv); |
| 977 | asyw->image.handle = ctxdma->object.handle; |
| 978 | asyw->image.offset = fb->nvbo->bo.offset; |
| 979 | |
| 980 | if (wndw->func->prepare) { |
| 981 | asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc); |
| 982 | if (IS_ERR(asyh)) |
| 983 | return PTR_ERR(asyh); |
| 984 | |
| 985 | wndw->func->prepare(wndw, asyh, asyw); |
| 986 | } |
| 987 | |
| 988 | return 0; |
| 989 | } |
| 990 | |
| 991 | static const struct drm_plane_helper_funcs |
| 992 | nv50_wndw_helper = { |
| 993 | .prepare_fb = nv50_wndw_prepare_fb, |
| 994 | .cleanup_fb = nv50_wndw_cleanup_fb, |
| 995 | .atomic_check = nv50_wndw_atomic_check, |
| 996 | }; |
| 997 | |
| 998 | static void |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 999 | nv50_wndw_atomic_destroy_state(struct drm_plane *plane, |
| 1000 | struct drm_plane_state *state) |
| 1001 | { |
| 1002 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(state); |
| 1003 | __drm_atomic_helper_plane_destroy_state(&asyw->state); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1004 | kfree(asyw); |
| 1005 | } |
| 1006 | |
| 1007 | static struct drm_plane_state * |
| 1008 | nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) |
| 1009 | { |
| 1010 | struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state); |
| 1011 | struct nv50_wndw_atom *asyw; |
| 1012 | if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL))) |
| 1013 | return NULL; |
| 1014 | __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1015 | asyw->interval = 1; |
| 1016 | asyw->sema = armw->sema; |
| 1017 | asyw->ntfy = armw->ntfy; |
| 1018 | asyw->image = armw->image; |
| 1019 | asyw->point = armw->point; |
| 1020 | asyw->lut = armw->lut; |
| 1021 | asyw->clr.mask = 0; |
| 1022 | asyw->set.mask = 0; |
| 1023 | return &asyw->state; |
| 1024 | } |
| 1025 | |
| 1026 | static void |
| 1027 | nv50_wndw_reset(struct drm_plane *plane) |
| 1028 | { |
| 1029 | struct nv50_wndw_atom *asyw; |
| 1030 | |
| 1031 | if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL)))) |
| 1032 | return; |
| 1033 | |
| 1034 | if (plane->state) |
| 1035 | plane->funcs->atomic_destroy_state(plane, plane->state); |
| 1036 | plane->state = &asyw->state; |
| 1037 | plane->state->plane = plane; |
| 1038 | plane->state->rotation = DRM_ROTATE_0; |
| 1039 | } |
| 1040 | |
| 1041 | static void |
| 1042 | nv50_wndw_destroy(struct drm_plane *plane) |
| 1043 | { |
| 1044 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 1045 | void *data; |
| 1046 | nvif_notify_fini(&wndw->notify); |
| 1047 | data = wndw->func->dtor(wndw); |
| 1048 | drm_plane_cleanup(&wndw->plane); |
| 1049 | kfree(data); |
| 1050 | } |
| 1051 | |
| 1052 | static const struct drm_plane_funcs |
| 1053 | nv50_wndw = { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1054 | .update_plane = drm_atomic_helper_update_plane, |
| 1055 | .disable_plane = drm_atomic_helper_disable_plane, |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1056 | .destroy = nv50_wndw_destroy, |
| 1057 | .reset = nv50_wndw_reset, |
| 1058 | .set_property = drm_atomic_helper_plane_set_property, |
| 1059 | .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state, |
| 1060 | .atomic_destroy_state = nv50_wndw_atomic_destroy_state, |
| 1061 | }; |
| 1062 | |
| 1063 | static void |
| 1064 | nv50_wndw_fini(struct nv50_wndw *wndw) |
| 1065 | { |
| 1066 | nvif_notify_put(&wndw->notify); |
| 1067 | } |
| 1068 | |
| 1069 | static void |
| 1070 | nv50_wndw_init(struct nv50_wndw *wndw) |
| 1071 | { |
| 1072 | nvif_notify_get(&wndw->notify); |
| 1073 | } |
| 1074 | |
| 1075 | static int |
| 1076 | nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev, |
| 1077 | enum drm_plane_type type, const char *name, int index, |
| 1078 | struct nv50_dmac *dmac, const u32 *format, int nformat, |
| 1079 | struct nv50_wndw *wndw) |
| 1080 | { |
| 1081 | int ret; |
| 1082 | |
| 1083 | wndw->func = func; |
| 1084 | wndw->dmac = dmac; |
| 1085 | |
| 1086 | ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, format, |
| 1087 | nformat, type, "%s-%d", name, index); |
| 1088 | if (ret) |
| 1089 | return ret; |
| 1090 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1091 | drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1092 | return 0; |
| 1093 | } |
| 1094 | |
| 1095 | /****************************************************************************** |
Ben Skeggs | 22e927d | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1096 | * Cursor plane |
| 1097 | *****************************************************************************/ |
| 1098 | #define nv50_curs(p) container_of((p), struct nv50_curs, wndw) |
| 1099 | |
| 1100 | struct nv50_curs { |
| 1101 | struct nv50_wndw wndw; |
| 1102 | struct nvif_object chan; |
| 1103 | }; |
| 1104 | |
| 1105 | static u32 |
| 1106 | nv50_curs_update(struct nv50_wndw *wndw, u32 interlock) |
| 1107 | { |
| 1108 | struct nv50_curs *curs = nv50_curs(wndw); |
| 1109 | nvif_wr32(&curs->chan, 0x0080, 0x00000000); |
| 1110 | return 0; |
| 1111 | } |
| 1112 | |
| 1113 | static void |
| 1114 | nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) |
| 1115 | { |
| 1116 | struct nv50_curs *curs = nv50_curs(wndw); |
| 1117 | nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x); |
| 1118 | } |
| 1119 | |
| 1120 | static void |
| 1121 | nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh, |
| 1122 | struct nv50_wndw_atom *asyw) |
| 1123 | { |
| 1124 | asyh->curs.handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle; |
| 1125 | asyh->curs.offset = asyw->image.offset; |
| 1126 | asyh->set.curs = asyh->curs.visible; |
| 1127 | } |
| 1128 | |
| 1129 | static void |
| 1130 | nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, |
| 1131 | struct nv50_head_atom *asyh) |
| 1132 | { |
| 1133 | asyh->curs.visible = false; |
| 1134 | } |
| 1135 | |
| 1136 | static int |
| 1137 | nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, |
| 1138 | struct nv50_head_atom *asyh) |
| 1139 | { |
| 1140 | int ret; |
| 1141 | |
| 1142 | ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip, |
| 1143 | DRM_PLANE_HELPER_NO_SCALING, |
| 1144 | DRM_PLANE_HELPER_NO_SCALING, |
| 1145 | true, true); |
| 1146 | asyh->curs.visible = asyw->state.visible; |
| 1147 | if (ret || !asyh->curs.visible) |
| 1148 | return ret; |
| 1149 | |
| 1150 | switch (asyw->state.fb->width) { |
| 1151 | case 32: asyh->curs.layout = 0; break; |
| 1152 | case 64: asyh->curs.layout = 1; break; |
| 1153 | default: |
| 1154 | return -EINVAL; |
| 1155 | } |
| 1156 | |
| 1157 | if (asyw->state.fb->width != asyw->state.fb->height) |
| 1158 | return -EINVAL; |
| 1159 | |
Ville Syrjälä | 438b74a | 2016-12-14 23:32:55 +0200 | [diff] [blame] | 1160 | switch (asyw->state.fb->format->format) { |
Ben Skeggs | 22e927d | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1161 | case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break; |
| 1162 | default: |
| 1163 | WARN_ON(1); |
| 1164 | return -EINVAL; |
| 1165 | } |
| 1166 | |
| 1167 | return 0; |
| 1168 | } |
| 1169 | |
| 1170 | static void * |
| 1171 | nv50_curs_dtor(struct nv50_wndw *wndw) |
| 1172 | { |
| 1173 | struct nv50_curs *curs = nv50_curs(wndw); |
| 1174 | nvif_object_fini(&curs->chan); |
| 1175 | return curs; |
| 1176 | } |
| 1177 | |
| 1178 | static const u32 |
| 1179 | nv50_curs_format[] = { |
| 1180 | DRM_FORMAT_ARGB8888, |
| 1181 | }; |
| 1182 | |
| 1183 | static const struct nv50_wndw_func |
| 1184 | nv50_curs = { |
| 1185 | .dtor = nv50_curs_dtor, |
| 1186 | .acquire = nv50_curs_acquire, |
| 1187 | .release = nv50_curs_release, |
| 1188 | .prepare = nv50_curs_prepare, |
| 1189 | .point = nv50_curs_point, |
| 1190 | .update = nv50_curs_update, |
| 1191 | }; |
| 1192 | |
| 1193 | static int |
| 1194 | nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head, |
| 1195 | struct nv50_curs **pcurs) |
| 1196 | { |
| 1197 | static const struct nvif_mclass curses[] = { |
| 1198 | { GK104_DISP_CURSOR, 0 }, |
| 1199 | { GF110_DISP_CURSOR, 0 }, |
| 1200 | { GT214_DISP_CURSOR, 0 }, |
| 1201 | { G82_DISP_CURSOR, 0 }, |
| 1202 | { NV50_DISP_CURSOR, 0 }, |
| 1203 | {} |
| 1204 | }; |
| 1205 | struct nv50_disp_cursor_v0 args = { |
| 1206 | .head = head->base.index, |
| 1207 | }; |
| 1208 | struct nv50_disp *disp = nv50_disp(drm->dev); |
| 1209 | struct nv50_curs *curs; |
| 1210 | int cid, ret; |
| 1211 | |
| 1212 | cid = nvif_mclass(disp->disp, curses); |
| 1213 | if (cid < 0) { |
| 1214 | NV_ERROR(drm, "No supported cursor immediate class\n"); |
| 1215 | return cid; |
| 1216 | } |
| 1217 | |
| 1218 | if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL))) |
| 1219 | return -ENOMEM; |
| 1220 | |
| 1221 | ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR, |
| 1222 | "curs", head->base.index, &disp->mast.base, |
| 1223 | nv50_curs_format, ARRAY_SIZE(nv50_curs_format), |
| 1224 | &curs->wndw); |
| 1225 | if (ret) { |
| 1226 | kfree(curs); |
| 1227 | return ret; |
| 1228 | } |
| 1229 | |
| 1230 | ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args, |
| 1231 | sizeof(args), &curs->chan); |
| 1232 | if (ret) { |
| 1233 | NV_ERROR(drm, "curs%04x allocation failed: %d\n", |
| 1234 | curses[cid].oclass, ret); |
| 1235 | return ret; |
| 1236 | } |
| 1237 | |
| 1238 | return 0; |
| 1239 | } |
| 1240 | |
| 1241 | /****************************************************************************** |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1242 | * Primary plane |
| 1243 | *****************************************************************************/ |
| 1244 | #define nv50_base(p) container_of((p), struct nv50_base, wndw) |
| 1245 | |
| 1246 | struct nv50_base { |
| 1247 | struct nv50_wndw wndw; |
| 1248 | struct nv50_sync chan; |
| 1249 | int id; |
| 1250 | }; |
| 1251 | |
| 1252 | static int |
| 1253 | nv50_base_notify(struct nvif_notify *notify) |
| 1254 | { |
| 1255 | return NVIF_NOTIFY_KEEP; |
| 1256 | } |
| 1257 | |
| 1258 | static void |
| 1259 | nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) |
| 1260 | { |
| 1261 | struct nv50_base *base = nv50_base(wndw); |
| 1262 | u32 *push; |
| 1263 | if ((push = evo_wait(&base->chan, 2))) { |
| 1264 | evo_mthd(push, 0x00e0, 1); |
| 1265 | evo_data(push, asyw->lut.enable << 30); |
| 1266 | evo_kick(push, &base->chan); |
| 1267 | } |
| 1268 | } |
| 1269 | |
| 1270 | static void |
| 1271 | nv50_base_image_clr(struct nv50_wndw *wndw) |
| 1272 | { |
| 1273 | struct nv50_base *base = nv50_base(wndw); |
| 1274 | u32 *push; |
| 1275 | if ((push = evo_wait(&base->chan, 4))) { |
| 1276 | evo_mthd(push, 0x0084, 1); |
| 1277 | evo_data(push, 0x00000000); |
| 1278 | evo_mthd(push, 0x00c0, 1); |
| 1279 | evo_data(push, 0x00000000); |
| 1280 | evo_kick(push, &base->chan); |
| 1281 | } |
| 1282 | } |
| 1283 | |
| 1284 | static void |
| 1285 | nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) |
| 1286 | { |
| 1287 | struct nv50_base *base = nv50_base(wndw); |
| 1288 | const s32 oclass = base->chan.base.base.user.oclass; |
| 1289 | u32 *push; |
| 1290 | if ((push = evo_wait(&base->chan, 10))) { |
| 1291 | evo_mthd(push, 0x0084, 1); |
| 1292 | evo_data(push, (asyw->image.mode << 8) | |
| 1293 | (asyw->image.interval << 4)); |
| 1294 | evo_mthd(push, 0x00c0, 1); |
| 1295 | evo_data(push, asyw->image.handle); |
| 1296 | if (oclass < G82_DISP_BASE_CHANNEL_DMA) { |
| 1297 | evo_mthd(push, 0x0800, 5); |
| 1298 | evo_data(push, asyw->image.offset >> 8); |
| 1299 | evo_data(push, 0x00000000); |
| 1300 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); |
| 1301 | evo_data(push, (asyw->image.layout << 20) | |
| 1302 | asyw->image.pitch | |
| 1303 | asyw->image.block); |
| 1304 | evo_data(push, (asyw->image.kind << 16) | |
| 1305 | (asyw->image.format << 8)); |
| 1306 | } else |
| 1307 | if (oclass < GF110_DISP_BASE_CHANNEL_DMA) { |
| 1308 | evo_mthd(push, 0x0800, 5); |
| 1309 | evo_data(push, asyw->image.offset >> 8); |
| 1310 | evo_data(push, 0x00000000); |
| 1311 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); |
| 1312 | evo_data(push, (asyw->image.layout << 20) | |
| 1313 | asyw->image.pitch | |
| 1314 | asyw->image.block); |
| 1315 | evo_data(push, asyw->image.format << 8); |
| 1316 | } else { |
| 1317 | evo_mthd(push, 0x0400, 5); |
| 1318 | evo_data(push, asyw->image.offset >> 8); |
| 1319 | evo_data(push, 0x00000000); |
| 1320 | evo_data(push, (asyw->image.h << 16) | asyw->image.w); |
| 1321 | evo_data(push, (asyw->image.layout << 24) | |
| 1322 | asyw->image.pitch | |
| 1323 | asyw->image.block); |
| 1324 | evo_data(push, asyw->image.format << 8); |
| 1325 | } |
| 1326 | evo_kick(push, &base->chan); |
| 1327 | } |
| 1328 | } |
| 1329 | |
| 1330 | static void |
| 1331 | nv50_base_ntfy_clr(struct nv50_wndw *wndw) |
| 1332 | { |
| 1333 | struct nv50_base *base = nv50_base(wndw); |
| 1334 | u32 *push; |
| 1335 | if ((push = evo_wait(&base->chan, 2))) { |
| 1336 | evo_mthd(push, 0x00a4, 1); |
| 1337 | evo_data(push, 0x00000000); |
| 1338 | evo_kick(push, &base->chan); |
| 1339 | } |
| 1340 | } |
| 1341 | |
| 1342 | static void |
| 1343 | nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) |
| 1344 | { |
| 1345 | struct nv50_base *base = nv50_base(wndw); |
| 1346 | u32 *push; |
| 1347 | if ((push = evo_wait(&base->chan, 3))) { |
| 1348 | evo_mthd(push, 0x00a0, 2); |
| 1349 | evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset); |
| 1350 | evo_data(push, asyw->ntfy.handle); |
| 1351 | evo_kick(push, &base->chan); |
| 1352 | } |
| 1353 | } |
| 1354 | |
| 1355 | static void |
| 1356 | nv50_base_sema_clr(struct nv50_wndw *wndw) |
| 1357 | { |
| 1358 | struct nv50_base *base = nv50_base(wndw); |
| 1359 | u32 *push; |
| 1360 | if ((push = evo_wait(&base->chan, 2))) { |
| 1361 | evo_mthd(push, 0x0094, 1); |
| 1362 | evo_data(push, 0x00000000); |
| 1363 | evo_kick(push, &base->chan); |
| 1364 | } |
| 1365 | } |
| 1366 | |
| 1367 | static void |
| 1368 | nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) |
| 1369 | { |
| 1370 | struct nv50_base *base = nv50_base(wndw); |
| 1371 | u32 *push; |
| 1372 | if ((push = evo_wait(&base->chan, 5))) { |
| 1373 | evo_mthd(push, 0x0088, 4); |
| 1374 | evo_data(push, asyw->sema.offset); |
| 1375 | evo_data(push, asyw->sema.acquire); |
| 1376 | evo_data(push, asyw->sema.release); |
| 1377 | evo_data(push, asyw->sema.handle); |
| 1378 | evo_kick(push, &base->chan); |
| 1379 | } |
| 1380 | } |
| 1381 | |
| 1382 | static u32 |
| 1383 | nv50_base_update(struct nv50_wndw *wndw, u32 interlock) |
| 1384 | { |
| 1385 | struct nv50_base *base = nv50_base(wndw); |
| 1386 | u32 *push; |
| 1387 | |
| 1388 | if (!(push = evo_wait(&base->chan, 2))) |
| 1389 | return 0; |
| 1390 | evo_mthd(push, 0x0080, 1); |
| 1391 | evo_data(push, interlock); |
| 1392 | evo_kick(push, &base->chan); |
| 1393 | |
| 1394 | if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) |
| 1395 | return interlock ? 2 << (base->id * 8) : 0; |
| 1396 | return interlock ? 2 << (base->id * 4) : 0; |
| 1397 | } |
| 1398 | |
| 1399 | static int |
| 1400 | nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) |
| 1401 | { |
| 1402 | struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev); |
| 1403 | struct nv50_disp *disp = nv50_disp(wndw->plane.dev); |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 1404 | if (nvif_msec(&drm->client.device, 2000ULL, |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1405 | u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4); |
| 1406 | if ((data & 0xc0000000) == 0x40000000) |
| 1407 | break; |
| 1408 | usleep_range(1, 2); |
| 1409 | ) < 0) |
| 1410 | return -ETIMEDOUT; |
| 1411 | return 0; |
| 1412 | } |
| 1413 | |
| 1414 | static void |
| 1415 | nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, |
| 1416 | struct nv50_head_atom *asyh) |
| 1417 | { |
| 1418 | asyh->base.cpp = 0; |
| 1419 | } |
| 1420 | |
| 1421 | static int |
| 1422 | nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, |
| 1423 | struct nv50_head_atom *asyh) |
| 1424 | { |
Ville Syrjälä | 9857ecb | 2016-11-18 21:53:03 +0200 | [diff] [blame] | 1425 | const struct drm_framebuffer *fb = asyw->state.fb; |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1426 | int ret; |
| 1427 | |
Ville Syrjälä | 9857ecb | 2016-11-18 21:53:03 +0200 | [diff] [blame] | 1428 | if (!fb->format->depth) |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1429 | return -EINVAL; |
| 1430 | |
| 1431 | ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip, |
| 1432 | DRM_PLANE_HELPER_NO_SCALING, |
| 1433 | DRM_PLANE_HELPER_NO_SCALING, |
| 1434 | false, true); |
| 1435 | if (ret) |
| 1436 | return ret; |
| 1437 | |
Ville Syrjälä | 9857ecb | 2016-11-18 21:53:03 +0200 | [diff] [blame] | 1438 | asyh->base.depth = fb->format->depth; |
| 1439 | asyh->base.cpp = fb->format->cpp[0]; |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1440 | asyh->base.x = asyw->state.src.x1 >> 16; |
| 1441 | asyh->base.y = asyw->state.src.y1 >> 16; |
| 1442 | asyh->base.w = asyw->state.fb->width; |
| 1443 | asyh->base.h = asyw->state.fb->height; |
| 1444 | |
Ville Syrjälä | 438b74a | 2016-12-14 23:32:55 +0200 | [diff] [blame] | 1445 | switch (fb->format->format) { |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1446 | case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; |
| 1447 | case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; |
| 1448 | case DRM_FORMAT_XRGB1555 : |
| 1449 | case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; |
| 1450 | case DRM_FORMAT_XRGB8888 : |
| 1451 | case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; |
| 1452 | case DRM_FORMAT_XBGR2101010: |
| 1453 | case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break; |
| 1454 | case DRM_FORMAT_XBGR8888 : |
| 1455 | case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; |
| 1456 | default: |
| 1457 | WARN_ON(1); |
| 1458 | return -EINVAL; |
| 1459 | } |
| 1460 | |
| 1461 | asyw->lut.enable = 1; |
| 1462 | asyw->set.image = true; |
| 1463 | return 0; |
| 1464 | } |
| 1465 | |
| 1466 | static void * |
| 1467 | nv50_base_dtor(struct nv50_wndw *wndw) |
| 1468 | { |
| 1469 | struct nv50_disp *disp = nv50_disp(wndw->plane.dev); |
| 1470 | struct nv50_base *base = nv50_base(wndw); |
| 1471 | nv50_dmac_destroy(&base->chan.base, disp->disp); |
| 1472 | return base; |
| 1473 | } |
| 1474 | |
| 1475 | static const u32 |
| 1476 | nv50_base_format[] = { |
| 1477 | DRM_FORMAT_C8, |
| 1478 | DRM_FORMAT_RGB565, |
| 1479 | DRM_FORMAT_XRGB1555, |
| 1480 | DRM_FORMAT_ARGB1555, |
| 1481 | DRM_FORMAT_XRGB8888, |
| 1482 | DRM_FORMAT_ARGB8888, |
| 1483 | DRM_FORMAT_XBGR2101010, |
| 1484 | DRM_FORMAT_ABGR2101010, |
| 1485 | DRM_FORMAT_XBGR8888, |
| 1486 | DRM_FORMAT_ABGR8888, |
| 1487 | }; |
| 1488 | |
| 1489 | static const struct nv50_wndw_func |
| 1490 | nv50_base = { |
| 1491 | .dtor = nv50_base_dtor, |
| 1492 | .acquire = nv50_base_acquire, |
| 1493 | .release = nv50_base_release, |
| 1494 | .sema_set = nv50_base_sema_set, |
| 1495 | .sema_clr = nv50_base_sema_clr, |
| 1496 | .ntfy_set = nv50_base_ntfy_set, |
| 1497 | .ntfy_clr = nv50_base_ntfy_clr, |
| 1498 | .ntfy_wait_begun = nv50_base_ntfy_wait_begun, |
| 1499 | .image_set = nv50_base_image_set, |
| 1500 | .image_clr = nv50_base_image_clr, |
| 1501 | .lut = nv50_base_lut, |
| 1502 | .update = nv50_base_update, |
| 1503 | }; |
| 1504 | |
| 1505 | static int |
| 1506 | nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head, |
| 1507 | struct nv50_base **pbase) |
| 1508 | { |
| 1509 | struct nv50_disp *disp = nv50_disp(drm->dev); |
| 1510 | struct nv50_base *base; |
| 1511 | int ret; |
| 1512 | |
| 1513 | if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL))) |
| 1514 | return -ENOMEM; |
| 1515 | base->id = head->base.index; |
| 1516 | base->wndw.ntfy = EVO_FLIP_NTFY0(base->id); |
| 1517 | base->wndw.sema = EVO_FLIP_SEM0(base->id); |
| 1518 | base->wndw.data = 0x00000000; |
| 1519 | |
| 1520 | ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY, |
| 1521 | "base", base->id, &base->chan.base, |
| 1522 | nv50_base_format, ARRAY_SIZE(nv50_base_format), |
| 1523 | &base->wndw); |
| 1524 | if (ret) { |
| 1525 | kfree(base); |
| 1526 | return ret; |
| 1527 | } |
| 1528 | |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 1529 | ret = nv50_base_create(&drm->client.device, disp->disp, base->id, |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1530 | disp->sync->bo.offset, &base->chan); |
| 1531 | if (ret) |
| 1532 | return ret; |
| 1533 | |
| 1534 | return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify, |
| 1535 | false, |
| 1536 | NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT, |
| 1537 | &(struct nvif_notify_uevent_req) {}, |
| 1538 | sizeof(struct nvif_notify_uevent_req), |
| 1539 | sizeof(struct nvif_notify_uevent_rep), |
| 1540 | &base->wndw.notify); |
| 1541 | } |
| 1542 | |
| 1543 | /****************************************************************************** |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1544 | * Head |
| 1545 | *****************************************************************************/ |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1546 | static void |
Ben Skeggs | 7e08d67 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1547 | nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1548 | { |
| 1549 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1550 | u32 *push; |
| 1551 | if ((push = evo_wait(core, 2))) { |
| 1552 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) |
| 1553 | evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1); |
| 1554 | else |
| 1555 | evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1); |
| 1556 | evo_data(push, (asyh->procamp.sat.sin << 20) | |
| 1557 | (asyh->procamp.sat.cos << 8)); |
| 1558 | evo_kick(push, core); |
| 1559 | } |
| 1560 | } |
| 1561 | |
| 1562 | static void |
Ben Skeggs | 7e91833 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1563 | nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1564 | { |
| 1565 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1566 | u32 *push; |
| 1567 | if ((push = evo_wait(core, 2))) { |
| 1568 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) |
| 1569 | evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1); |
| 1570 | else |
| 1571 | if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA) |
| 1572 | evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1); |
| 1573 | else |
| 1574 | evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1); |
| 1575 | evo_data(push, (asyh->dither.mode << 3) | |
| 1576 | (asyh->dither.bits << 1) | |
| 1577 | asyh->dither.enable); |
| 1578 | evo_kick(push, core); |
| 1579 | } |
| 1580 | } |
| 1581 | |
| 1582 | static void |
Ben Skeggs | 6bbab3b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1583 | nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1584 | { |
| 1585 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1586 | u32 bounds = 0; |
| 1587 | u32 *push; |
| 1588 | |
| 1589 | if (asyh->base.cpp) { |
| 1590 | switch (asyh->base.cpp) { |
| 1591 | case 8: bounds |= 0x00000500; break; |
| 1592 | case 4: bounds |= 0x00000300; break; |
| 1593 | case 2: bounds |= 0x00000100; break; |
| 1594 | default: |
| 1595 | WARN_ON(1); |
| 1596 | break; |
| 1597 | } |
| 1598 | bounds |= 0x00000001; |
| 1599 | } |
| 1600 | |
| 1601 | if ((push = evo_wait(core, 2))) { |
| 1602 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) |
| 1603 | evo_mthd(push, 0x0904 + head->base.index * 0x400, 1); |
| 1604 | else |
| 1605 | evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1); |
| 1606 | evo_data(push, bounds); |
| 1607 | evo_kick(push, core); |
| 1608 | } |
| 1609 | } |
| 1610 | |
| 1611 | static void |
| 1612 | nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1613 | { |
| 1614 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1615 | u32 bounds = 0; |
| 1616 | u32 *push; |
| 1617 | |
| 1618 | if (asyh->base.cpp) { |
| 1619 | switch (asyh->base.cpp) { |
| 1620 | case 8: bounds |= 0x00000500; break; |
| 1621 | case 4: bounds |= 0x00000300; break; |
| 1622 | case 2: bounds |= 0x00000100; break; |
| 1623 | case 1: bounds |= 0x00000000; break; |
| 1624 | default: |
| 1625 | WARN_ON(1); |
| 1626 | break; |
| 1627 | } |
| 1628 | bounds |= 0x00000001; |
| 1629 | } |
| 1630 | |
| 1631 | if ((push = evo_wait(core, 2))) { |
| 1632 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) |
| 1633 | evo_mthd(push, 0x0900 + head->base.index * 0x400, 1); |
| 1634 | else |
| 1635 | evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1); |
| 1636 | evo_data(push, bounds); |
| 1637 | evo_kick(push, core); |
| 1638 | } |
| 1639 | } |
| 1640 | |
| 1641 | static void |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1642 | nv50_head_curs_clr(struct nv50_head *head) |
| 1643 | { |
| 1644 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1645 | u32 *push; |
| 1646 | if ((push = evo_wait(core, 4))) { |
| 1647 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { |
| 1648 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); |
| 1649 | evo_data(push, 0x05000000); |
| 1650 | } else |
| 1651 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { |
| 1652 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); |
| 1653 | evo_data(push, 0x05000000); |
| 1654 | evo_mthd(push, 0x089c + head->base.index * 0x400, 1); |
| 1655 | evo_data(push, 0x00000000); |
| 1656 | } else { |
| 1657 | evo_mthd(push, 0x0480 + head->base.index * 0x300, 1); |
| 1658 | evo_data(push, 0x05000000); |
| 1659 | evo_mthd(push, 0x048c + head->base.index * 0x300, 1); |
| 1660 | evo_data(push, 0x00000000); |
| 1661 | } |
| 1662 | evo_kick(push, core); |
| 1663 | } |
| 1664 | } |
| 1665 | |
| 1666 | static void |
| 1667 | nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1668 | { |
| 1669 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1670 | u32 *push; |
| 1671 | if ((push = evo_wait(core, 5))) { |
| 1672 | if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) { |
| 1673 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); |
| 1674 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | |
| 1675 | (asyh->curs.format << 24)); |
| 1676 | evo_data(push, asyh->curs.offset >> 8); |
| 1677 | } else |
| 1678 | if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) { |
| 1679 | evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); |
| 1680 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | |
| 1681 | (asyh->curs.format << 24)); |
| 1682 | evo_data(push, asyh->curs.offset >> 8); |
| 1683 | evo_mthd(push, 0x089c + head->base.index * 0x400, 1); |
| 1684 | evo_data(push, asyh->curs.handle); |
| 1685 | } else { |
| 1686 | evo_mthd(push, 0x0480 + head->base.index * 0x300, 2); |
| 1687 | evo_data(push, 0x80000000 | (asyh->curs.layout << 26) | |
| 1688 | (asyh->curs.format << 24)); |
| 1689 | evo_data(push, asyh->curs.offset >> 8); |
| 1690 | evo_mthd(push, 0x048c + head->base.index * 0x300, 1); |
| 1691 | evo_data(push, asyh->curs.handle); |
| 1692 | } |
| 1693 | evo_kick(push, core); |
| 1694 | } |
| 1695 | } |
| 1696 | |
| 1697 | static void |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1698 | nv50_head_core_clr(struct nv50_head *head) |
| 1699 | { |
| 1700 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1701 | u32 *push; |
| 1702 | if ((push = evo_wait(core, 2))) { |
| 1703 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) |
| 1704 | evo_mthd(push, 0x0874 + head->base.index * 0x400, 1); |
| 1705 | else |
| 1706 | evo_mthd(push, 0x0474 + head->base.index * 0x300, 1); |
| 1707 | evo_data(push, 0x00000000); |
| 1708 | evo_kick(push, core); |
| 1709 | } |
| 1710 | } |
| 1711 | |
| 1712 | static void |
| 1713 | nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1714 | { |
| 1715 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1716 | u32 *push; |
| 1717 | if ((push = evo_wait(core, 9))) { |
| 1718 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { |
| 1719 | evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); |
| 1720 | evo_data(push, asyh->core.offset >> 8); |
| 1721 | evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); |
| 1722 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); |
| 1723 | evo_data(push, asyh->core.layout << 20 | |
| 1724 | (asyh->core.pitch >> 8) << 8 | |
| 1725 | asyh->core.block); |
| 1726 | evo_data(push, asyh->core.kind << 16 | |
| 1727 | asyh->core.format << 8); |
| 1728 | evo_data(push, asyh->core.handle); |
| 1729 | evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); |
| 1730 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); |
Ben Skeggs | 19d53d0 | 2016-12-13 11:18:46 +1000 | [diff] [blame] | 1731 | /* EVO will complain with INVALID_STATE if we have an |
| 1732 | * active cursor and (re)specify HeadSetContextDmaIso |
| 1733 | * without also updating HeadSetOffsetCursor. |
| 1734 | */ |
| 1735 | asyh->set.curs = asyh->curs.visible; |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1736 | } else |
| 1737 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { |
| 1738 | evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); |
| 1739 | evo_data(push, asyh->core.offset >> 8); |
| 1740 | evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); |
| 1741 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); |
| 1742 | evo_data(push, asyh->core.layout << 20 | |
| 1743 | (asyh->core.pitch >> 8) << 8 | |
| 1744 | asyh->core.block); |
| 1745 | evo_data(push, asyh->core.format << 8); |
| 1746 | evo_data(push, asyh->core.handle); |
| 1747 | evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); |
| 1748 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); |
| 1749 | } else { |
| 1750 | evo_mthd(push, 0x0460 + head->base.index * 0x300, 1); |
| 1751 | evo_data(push, asyh->core.offset >> 8); |
| 1752 | evo_mthd(push, 0x0468 + head->base.index * 0x300, 4); |
| 1753 | evo_data(push, (asyh->core.h << 16) | asyh->core.w); |
| 1754 | evo_data(push, asyh->core.layout << 24 | |
| 1755 | (asyh->core.pitch >> 8) << 8 | |
| 1756 | asyh->core.block); |
| 1757 | evo_data(push, asyh->core.format << 8); |
| 1758 | evo_data(push, asyh->core.handle); |
| 1759 | evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1); |
| 1760 | evo_data(push, (asyh->core.y << 16) | asyh->core.x); |
| 1761 | } |
| 1762 | evo_kick(push, core); |
| 1763 | } |
| 1764 | } |
| 1765 | |
| 1766 | static void |
Ben Skeggs | a7ae156 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1767 | nv50_head_lut_clr(struct nv50_head *head) |
| 1768 | { |
| 1769 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1770 | u32 *push; |
| 1771 | if ((push = evo_wait(core, 4))) { |
| 1772 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { |
| 1773 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); |
| 1774 | evo_data(push, 0x40000000); |
| 1775 | } else |
| 1776 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { |
| 1777 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); |
| 1778 | evo_data(push, 0x40000000); |
| 1779 | evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); |
| 1780 | evo_data(push, 0x00000000); |
| 1781 | } else { |
| 1782 | evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1); |
| 1783 | evo_data(push, 0x03000000); |
| 1784 | evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); |
| 1785 | evo_data(push, 0x00000000); |
| 1786 | } |
| 1787 | evo_kick(push, core); |
| 1788 | } |
| 1789 | } |
| 1790 | |
| 1791 | static void |
| 1792 | nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1793 | { |
| 1794 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1795 | u32 *push; |
| 1796 | if ((push = evo_wait(core, 7))) { |
| 1797 | if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) { |
| 1798 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); |
| 1799 | evo_data(push, 0xc0000000); |
| 1800 | evo_data(push, asyh->lut.offset >> 8); |
| 1801 | } else |
| 1802 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { |
| 1803 | evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); |
| 1804 | evo_data(push, 0xc0000000); |
| 1805 | evo_data(push, asyh->lut.offset >> 8); |
| 1806 | evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); |
| 1807 | evo_data(push, asyh->lut.handle); |
| 1808 | } else { |
| 1809 | evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4); |
| 1810 | evo_data(push, 0x83000000); |
| 1811 | evo_data(push, asyh->lut.offset >> 8); |
| 1812 | evo_data(push, 0x00000000); |
| 1813 | evo_data(push, 0x00000000); |
| 1814 | evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); |
| 1815 | evo_data(push, asyh->lut.handle); |
| 1816 | } |
| 1817 | evo_kick(push, core); |
| 1818 | } |
| 1819 | } |
| 1820 | |
| 1821 | static void |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1822 | nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1823 | { |
| 1824 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1825 | struct nv50_head_mode *m = &asyh->mode; |
| 1826 | u32 *push; |
| 1827 | if ((push = evo_wait(core, 14))) { |
| 1828 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { |
| 1829 | evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2); |
| 1830 | evo_data(push, 0x00800000 | m->clock); |
| 1831 | evo_data(push, m->interlace ? 0x00000002 : 0x00000000); |
Ben Skeggs | 06ab282 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1832 | evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7); |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1833 | evo_data(push, 0x00000000); |
| 1834 | evo_data(push, (m->v.active << 16) | m->h.active ); |
| 1835 | evo_data(push, (m->v.synce << 16) | m->h.synce ); |
| 1836 | evo_data(push, (m->v.blanke << 16) | m->h.blanke ); |
| 1837 | evo_data(push, (m->v.blanks << 16) | m->h.blanks ); |
| 1838 | evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); |
Ben Skeggs | 06ab282 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1839 | evo_data(push, asyh->mode.v.blankus); |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1840 | evo_mthd(push, 0x082c + (head->base.index * 0x400), 1); |
| 1841 | evo_data(push, 0x00000000); |
| 1842 | } else { |
| 1843 | evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6); |
| 1844 | evo_data(push, 0x00000000); |
| 1845 | evo_data(push, (m->v.active << 16) | m->h.active ); |
| 1846 | evo_data(push, (m->v.synce << 16) | m->h.synce ); |
| 1847 | evo_data(push, (m->v.blanke << 16) | m->h.blanke ); |
| 1848 | evo_data(push, (m->v.blanks << 16) | m->h.blanks ); |
| 1849 | evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); |
| 1850 | evo_mthd(push, 0x042c + (head->base.index * 0x300), 2); |
| 1851 | evo_data(push, 0x00000000); /* ??? */ |
| 1852 | evo_data(push, 0xffffff00); |
| 1853 | evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3); |
| 1854 | evo_data(push, m->clock * 1000); |
| 1855 | evo_data(push, 0x00200000); /* ??? */ |
| 1856 | evo_data(push, m->clock * 1000); |
| 1857 | } |
| 1858 | evo_kick(push, core); |
| 1859 | } |
| 1860 | } |
| 1861 | |
| 1862 | static void |
Ben Skeggs | c4e6812 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1863 | nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1864 | { |
| 1865 | struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base; |
| 1866 | u32 *push; |
| 1867 | if ((push = evo_wait(core, 10))) { |
| 1868 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { |
| 1869 | evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1); |
| 1870 | evo_data(push, 0x00000000); |
| 1871 | evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1); |
| 1872 | evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); |
| 1873 | evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2); |
| 1874 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); |
| 1875 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); |
| 1876 | } else { |
| 1877 | evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1); |
| 1878 | evo_data(push, 0x00000000); |
| 1879 | evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1); |
| 1880 | evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); |
| 1881 | evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3); |
| 1882 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); |
| 1883 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); |
| 1884 | evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); |
| 1885 | } |
| 1886 | evo_kick(push, core); |
| 1887 | } |
| 1888 | } |
| 1889 | |
| 1890 | static void |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1891 | nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y) |
| 1892 | { |
| 1893 | if (asyh->clr.core && (!asyh->set.core || y)) |
Ben Skeggs | a7ae156 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1894 | nv50_head_lut_clr(head); |
| 1895 | if (asyh->clr.core && (!asyh->set.core || y)) |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1896 | nv50_head_core_clr(head); |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1897 | if (asyh->clr.curs && (!asyh->set.curs || y)) |
| 1898 | nv50_head_curs_clr(head); |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1899 | } |
| 1900 | |
| 1901 | static void |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1902 | nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 1903 | { |
Ben Skeggs | c4e6812 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1904 | if (asyh->set.view ) nv50_head_view (head, asyh); |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1905 | if (asyh->set.mode ) nv50_head_mode (head, asyh); |
Ben Skeggs | a7ae156 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1906 | if (asyh->set.core ) nv50_head_lut_set (head, asyh); |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1907 | if (asyh->set.core ) nv50_head_core_set(head, asyh); |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1908 | if (asyh->set.curs ) nv50_head_curs_set(head, asyh); |
Ben Skeggs | 6bbab3b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1909 | if (asyh->set.base ) nv50_head_base (head, asyh); |
| 1910 | if (asyh->set.ovly ) nv50_head_ovly (head, asyh); |
Ben Skeggs | 7e91833 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1911 | if (asyh->set.dither ) nv50_head_dither (head, asyh); |
Ben Skeggs | 7e08d67 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1912 | if (asyh->set.procamp) nv50_head_procamp (head, asyh); |
| 1913 | } |
| 1914 | |
| 1915 | static void |
| 1916 | nv50_head_atomic_check_procamp(struct nv50_head_atom *armh, |
| 1917 | struct nv50_head_atom *asyh, |
| 1918 | struct nouveau_conn_atom *asyc) |
| 1919 | { |
| 1920 | const int vib = asyc->procamp.color_vibrance - 100; |
| 1921 | const int hue = asyc->procamp.vibrant_hue - 90; |
| 1922 | const int adj = (vib > 0) ? 50 : 0; |
| 1923 | asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff; |
| 1924 | asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff; |
| 1925 | asyh->set.procamp = true; |
Ben Skeggs | 7e91833 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1926 | } |
| 1927 | |
| 1928 | static void |
| 1929 | nv50_head_atomic_check_dither(struct nv50_head_atom *armh, |
| 1930 | struct nv50_head_atom *asyh, |
| 1931 | struct nouveau_conn_atom *asyc) |
| 1932 | { |
| 1933 | struct drm_connector *connector = asyc->state.connector; |
| 1934 | u32 mode = 0x00; |
| 1935 | |
| 1936 | if (asyc->dither.mode == DITHERING_MODE_AUTO) { |
| 1937 | if (asyh->base.depth > connector->display_info.bpc * 3) |
| 1938 | mode = DITHERING_MODE_DYNAMIC2X2; |
| 1939 | } else { |
| 1940 | mode = asyc->dither.mode; |
| 1941 | } |
| 1942 | |
| 1943 | if (asyc->dither.depth == DITHERING_DEPTH_AUTO) { |
| 1944 | if (connector->display_info.bpc >= 8) |
| 1945 | mode |= DITHERING_DEPTH_8BPC; |
| 1946 | } else { |
| 1947 | mode |= asyc->dither.depth; |
| 1948 | } |
| 1949 | |
| 1950 | asyh->dither.enable = mode; |
| 1951 | asyh->dither.bits = mode >> 1; |
| 1952 | asyh->dither.mode = mode >> 3; |
| 1953 | asyh->set.dither = true; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1954 | } |
| 1955 | |
| 1956 | static void |
Ben Skeggs | c4e6812 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 1957 | nv50_head_atomic_check_view(struct nv50_head_atom *armh, |
| 1958 | struct nv50_head_atom *asyh, |
| 1959 | struct nouveau_conn_atom *asyc) |
| 1960 | { |
| 1961 | struct drm_connector *connector = asyc->state.connector; |
| 1962 | struct drm_display_mode *omode = &asyh->state.adjusted_mode; |
| 1963 | struct drm_display_mode *umode = &asyh->state.mode; |
| 1964 | int mode = asyc->scaler.mode; |
| 1965 | struct edid *edid; |
| 1966 | |
| 1967 | if (connector->edid_blob_ptr) |
| 1968 | edid = (struct edid *)connector->edid_blob_ptr->data; |
| 1969 | else |
| 1970 | edid = NULL; |
| 1971 | |
| 1972 | if (!asyc->scaler.full) { |
| 1973 | if (mode == DRM_MODE_SCALE_NONE) |
| 1974 | omode = umode; |
| 1975 | } else { |
| 1976 | /* Non-EDID LVDS/eDP mode. */ |
| 1977 | mode = DRM_MODE_SCALE_FULLSCREEN; |
| 1978 | } |
| 1979 | |
| 1980 | asyh->view.iW = umode->hdisplay; |
| 1981 | asyh->view.iH = umode->vdisplay; |
| 1982 | asyh->view.oW = omode->hdisplay; |
| 1983 | asyh->view.oH = omode->vdisplay; |
| 1984 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1985 | asyh->view.oH *= 2; |
| 1986 | |
| 1987 | /* Add overscan compensation if necessary, will keep the aspect |
| 1988 | * ratio the same as the backend mode unless overridden by the |
| 1989 | * user setting both hborder and vborder properties. |
| 1990 | */ |
| 1991 | if ((asyc->scaler.underscan.mode == UNDERSCAN_ON || |
| 1992 | (asyc->scaler.underscan.mode == UNDERSCAN_AUTO && |
| 1993 | drm_detect_hdmi_monitor(edid)))) { |
| 1994 | u32 bX = asyc->scaler.underscan.hborder; |
| 1995 | u32 bY = asyc->scaler.underscan.vborder; |
| 1996 | u32 r = (asyh->view.oH << 19) / asyh->view.oW; |
| 1997 | |
| 1998 | if (bX) { |
| 1999 | asyh->view.oW -= (bX * 2); |
| 2000 | if (bY) asyh->view.oH -= (bY * 2); |
| 2001 | else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; |
| 2002 | } else { |
| 2003 | asyh->view.oW -= (asyh->view.oW >> 4) + 32; |
| 2004 | if (bY) asyh->view.oH -= (bY * 2); |
| 2005 | else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; |
| 2006 | } |
| 2007 | } |
| 2008 | |
| 2009 | /* Handle CENTER/ASPECT scaling, taking into account the areas |
| 2010 | * removed already for overscan compensation. |
| 2011 | */ |
| 2012 | switch (mode) { |
| 2013 | case DRM_MODE_SCALE_CENTER: |
| 2014 | asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW); |
| 2015 | asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH); |
| 2016 | /* fall-through */ |
| 2017 | case DRM_MODE_SCALE_ASPECT: |
| 2018 | if (asyh->view.oH < asyh->view.oW) { |
| 2019 | u32 r = (asyh->view.iW << 19) / asyh->view.iH; |
| 2020 | asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; |
| 2021 | } else { |
| 2022 | u32 r = (asyh->view.iH << 19) / asyh->view.iW; |
| 2023 | asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; |
| 2024 | } |
| 2025 | break; |
| 2026 | default: |
| 2027 | break; |
| 2028 | } |
| 2029 | |
| 2030 | asyh->set.view = true; |
| 2031 | } |
| 2032 | |
| 2033 | static void |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2034 | nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) |
| 2035 | { |
| 2036 | struct drm_display_mode *mode = &asyh->state.adjusted_mode; |
| 2037 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
| 2038 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; |
| 2039 | u32 hbackp = mode->htotal - mode->hsync_end; |
| 2040 | u32 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; |
| 2041 | u32 hfrontp = mode->hsync_start - mode->hdisplay; |
| 2042 | u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; |
Ben Skeggs | aeecfcd | 2017-04-05 09:12:54 +1000 | [diff] [blame] | 2043 | u32 blankus; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2044 | struct nv50_head_mode *m = &asyh->mode; |
| 2045 | |
| 2046 | m->h.active = mode->htotal; |
| 2047 | m->h.synce = mode->hsync_end - mode->hsync_start - 1; |
| 2048 | m->h.blanke = m->h.synce + hbackp; |
| 2049 | m->h.blanks = mode->htotal - hfrontp - 1; |
| 2050 | |
| 2051 | m->v.active = mode->vtotal * vscan / ilace; |
| 2052 | m->v.synce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; |
| 2053 | m->v.blanke = m->v.synce + vbackp; |
| 2054 | m->v.blanks = m->v.active - vfrontp - 1; |
| 2055 | |
| 2056 | /*XXX: Safe underestimate, even "0" works */ |
Ben Skeggs | aeecfcd | 2017-04-05 09:12:54 +1000 | [diff] [blame] | 2057 | blankus = (m->v.active - mode->vdisplay - 2) * m->h.active; |
| 2058 | blankus *= 1000; |
| 2059 | blankus /= mode->clock; |
| 2060 | m->v.blankus = blankus; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2061 | |
| 2062 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
| 2063 | m->v.blank2e = m->v.active + m->v.synce + vbackp; |
| 2064 | m->v.blank2s = m->v.blank2e + (mode->vdisplay * vscan / ilace); |
| 2065 | m->v.active = (m->v.active * 2) + 1; |
| 2066 | m->interlace = true; |
| 2067 | } else { |
| 2068 | m->v.blank2e = 0; |
| 2069 | m->v.blank2s = 1; |
| 2070 | m->interlace = false; |
| 2071 | } |
| 2072 | m->clock = mode->clock; |
| 2073 | |
| 2074 | drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); |
| 2075 | asyh->set.mode = true; |
| 2076 | } |
| 2077 | |
| 2078 | static int |
| 2079 | nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) |
| 2080 | { |
| 2081 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2082 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2083 | struct nv50_head *head = nv50_head(crtc); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2084 | struct nv50_head_atom *armh = nv50_head_atom(crtc->state); |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2085 | struct nv50_head_atom *asyh = nv50_head_atom(state); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2086 | struct nouveau_conn_atom *asyc = NULL; |
| 2087 | struct drm_connector_state *conns; |
| 2088 | struct drm_connector *conn; |
| 2089 | int i; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2090 | |
| 2091 | NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active); |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2092 | if (asyh->state.active) { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2093 | for_each_connector_in_state(asyh->state.state, conn, conns, i) { |
| 2094 | if (conns->crtc == crtc) { |
| 2095 | asyc = nouveau_conn_atom(conns); |
| 2096 | break; |
| 2097 | } |
| 2098 | } |
| 2099 | |
| 2100 | if (armh->state.active) { |
| 2101 | if (asyc) { |
| 2102 | if (asyh->state.mode_changed) |
| 2103 | asyc->set.scaler = true; |
| 2104 | if (armh->base.depth != asyh->base.depth) |
| 2105 | asyc->set.dither = true; |
| 2106 | } |
| 2107 | } else { |
| 2108 | asyc->set.mask = ~0; |
| 2109 | asyh->set.mask = ~0; |
| 2110 | } |
| 2111 | |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2112 | if (asyh->state.mode_changed) |
| 2113 | nv50_head_atomic_check_mode(head, asyh); |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2114 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2115 | if (asyc) { |
| 2116 | if (asyc->set.scaler) |
| 2117 | nv50_head_atomic_check_view(armh, asyh, asyc); |
| 2118 | if (asyc->set.dither) |
| 2119 | nv50_head_atomic_check_dither(armh, asyh, asyc); |
| 2120 | if (asyc->set.procamp) |
| 2121 | nv50_head_atomic_check_procamp(armh, asyh, asyc); |
| 2122 | } |
| 2123 | |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2124 | if ((asyh->core.visible = (asyh->base.cpp != 0))) { |
| 2125 | asyh->core.x = asyh->base.x; |
| 2126 | asyh->core.y = asyh->base.y; |
| 2127 | asyh->core.w = asyh->base.w; |
| 2128 | asyh->core.h = asyh->base.h; |
| 2129 | } else |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2130 | if ((asyh->core.visible = asyh->curs.visible)) { |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2131 | /*XXX: We need to either find some way of having the |
| 2132 | * primary base layer appear black, while still |
| 2133 | * being able to display the other layers, or we |
| 2134 | * need to allocate a dummy black surface here. |
| 2135 | */ |
| 2136 | asyh->core.x = 0; |
| 2137 | asyh->core.y = 0; |
| 2138 | asyh->core.w = asyh->state.mode.hdisplay; |
| 2139 | asyh->core.h = asyh->state.mode.vdisplay; |
| 2140 | } |
| 2141 | asyh->core.handle = disp->mast.base.vram.handle; |
| 2142 | asyh->core.offset = 0; |
| 2143 | asyh->core.format = 0xcf; |
| 2144 | asyh->core.kind = 0; |
| 2145 | asyh->core.layout = 1; |
| 2146 | asyh->core.block = 0; |
| 2147 | asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4; |
Ben Skeggs | a7ae156 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2148 | asyh->lut.handle = disp->mast.base.vram.handle; |
| 2149 | asyh->lut.offset = head->base.lut.nvbo->bo.offset; |
Ben Skeggs | 6bbab3b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2150 | asyh->set.base = armh->base.cpp != asyh->base.cpp; |
| 2151 | asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp; |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2152 | } else { |
| 2153 | asyh->core.visible = false; |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2154 | asyh->curs.visible = false; |
Ben Skeggs | 6bbab3b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2155 | asyh->base.cpp = 0; |
| 2156 | asyh->ovly.cpp = 0; |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2157 | } |
| 2158 | |
| 2159 | if (!drm_atomic_crtc_needs_modeset(&asyh->state)) { |
| 2160 | if (asyh->core.visible) { |
| 2161 | if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core))) |
| 2162 | asyh->set.core = true; |
| 2163 | } else |
| 2164 | if (armh->core.visible) { |
| 2165 | asyh->clr.core = true; |
| 2166 | } |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2167 | |
| 2168 | if (asyh->curs.visible) { |
| 2169 | if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs))) |
| 2170 | asyh->set.curs = true; |
| 2171 | } else |
| 2172 | if (armh->curs.visible) { |
| 2173 | asyh->clr.curs = true; |
| 2174 | } |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2175 | } else { |
| 2176 | asyh->clr.core = armh->core.visible; |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2177 | asyh->clr.curs = armh->curs.visible; |
Ben Skeggs | ad63361 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2178 | asyh->set.core = asyh->core.visible; |
Ben Skeggs | ea8ee39 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2179 | asyh->set.curs = asyh->curs.visible; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2180 | } |
| 2181 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2182 | if (asyh->clr.mask || asyh->set.mask) |
| 2183 | nv50_atom(asyh->state.state)->lock_core = true; |
Ben Skeggs | 3dbd036 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2184 | return 0; |
| 2185 | } |
| 2186 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2187 | static void |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2188 | nv50_head_lut_load(struct drm_crtc *crtc) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2189 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2190 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2191 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 2192 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); |
| 2193 | int i; |
| 2194 | |
| 2195 | for (i = 0; i < 256; i++) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 2196 | u16 r = nv_crtc->lut.r[i] >> 2; |
| 2197 | u16 g = nv_crtc->lut.g[i] >> 2; |
| 2198 | u16 b = nv_crtc->lut.b[i] >> 2; |
| 2199 | |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 2200 | if (disp->disp->oclass < GF110_DISP) { |
Ben Skeggs | de8268c | 2012-11-16 10:24:31 +1000 | [diff] [blame] | 2201 | writew(r + 0x0000, lut + (i * 0x08) + 0); |
| 2202 | writew(g + 0x0000, lut + (i * 0x08) + 2); |
| 2203 | writew(b + 0x0000, lut + (i * 0x08) + 4); |
| 2204 | } else { |
| 2205 | writew(r + 0x6000, lut + (i * 0x20) + 0); |
| 2206 | writew(g + 0x6000, lut + (i * 0x20) + 2); |
| 2207 | writew(b + 0x6000, lut + (i * 0x20) + 4); |
| 2208 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2209 | } |
| 2210 | } |
| 2211 | |
Maarten Lankhorst | 7ea7728 | 2016-06-07 12:49:30 +0200 | [diff] [blame] | 2212 | static int |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2213 | nv50_head_mode_set_base_atomic(struct drm_crtc *crtc, |
| 2214 | struct drm_framebuffer *fb, int x, int y, |
| 2215 | enum mode_set_atomic state) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2216 | { |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2217 | WARN_ON(1); |
Maarten Lankhorst | 7ea7728 | 2016-06-07 12:49:30 +0200 | [diff] [blame] | 2218 | return 0; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2219 | } |
| 2220 | |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2221 | static const struct drm_crtc_helper_funcs |
| 2222 | nv50_head_help = { |
| 2223 | .mode_set_base_atomic = nv50_head_mode_set_base_atomic, |
| 2224 | .load_lut = nv50_head_lut_load, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2225 | .atomic_check = nv50_head_atomic_check, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2226 | }; |
| 2227 | |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2228 | static int |
| 2229 | nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
| 2230 | uint32_t size) |
| 2231 | { |
| 2232 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 2233 | u32 i; |
| 2234 | |
| 2235 | for (i = 0; i < size; i++) { |
| 2236 | nv_crtc->lut.r[i] = r[i]; |
| 2237 | nv_crtc->lut.g[i] = g[i]; |
| 2238 | nv_crtc->lut.b[i] = b[i]; |
| 2239 | } |
| 2240 | |
| 2241 | nv50_head_lut_load(crtc); |
| 2242 | return 0; |
| 2243 | } |
| 2244 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2245 | static void |
| 2246 | nv50_head_atomic_destroy_state(struct drm_crtc *crtc, |
| 2247 | struct drm_crtc_state *state) |
| 2248 | { |
| 2249 | struct nv50_head_atom *asyh = nv50_head_atom(state); |
| 2250 | __drm_atomic_helper_crtc_destroy_state(&asyh->state); |
| 2251 | kfree(asyh); |
| 2252 | } |
| 2253 | |
| 2254 | static struct drm_crtc_state * |
| 2255 | nv50_head_atomic_duplicate_state(struct drm_crtc *crtc) |
| 2256 | { |
| 2257 | struct nv50_head_atom *armh = nv50_head_atom(crtc->state); |
| 2258 | struct nv50_head_atom *asyh; |
| 2259 | if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL))) |
| 2260 | return NULL; |
| 2261 | __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state); |
| 2262 | asyh->view = armh->view; |
| 2263 | asyh->mode = armh->mode; |
| 2264 | asyh->lut = armh->lut; |
| 2265 | asyh->core = armh->core; |
| 2266 | asyh->curs = armh->curs; |
| 2267 | asyh->base = armh->base; |
| 2268 | asyh->ovly = armh->ovly; |
| 2269 | asyh->dither = armh->dither; |
| 2270 | asyh->procamp = armh->procamp; |
| 2271 | asyh->clr.mask = 0; |
| 2272 | asyh->set.mask = 0; |
| 2273 | return &asyh->state; |
| 2274 | } |
| 2275 | |
| 2276 | static void |
| 2277 | __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, |
| 2278 | struct drm_crtc_state *state) |
| 2279 | { |
| 2280 | if (crtc->state) |
| 2281 | crtc->funcs->atomic_destroy_state(crtc, crtc->state); |
| 2282 | crtc->state = state; |
| 2283 | crtc->state->crtc = crtc; |
| 2284 | } |
| 2285 | |
| 2286 | static void |
| 2287 | nv50_head_reset(struct drm_crtc *crtc) |
| 2288 | { |
| 2289 | struct nv50_head_atom *asyh; |
| 2290 | |
| 2291 | if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL)))) |
| 2292 | return; |
| 2293 | |
| 2294 | __drm_atomic_helper_crtc_reset(crtc, &asyh->state); |
| 2295 | } |
| 2296 | |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2297 | static void |
| 2298 | nv50_head_destroy(struct drm_crtc *crtc) |
| 2299 | { |
| 2300 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
| 2301 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
| 2302 | struct nv50_head *head = nv50_head(crtc); |
| 2303 | |
| 2304 | nv50_dmac_destroy(&head->ovly.base, disp->disp); |
| 2305 | nv50_pioc_destroy(&head->oimm.base); |
| 2306 | |
| 2307 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
| 2308 | if (nv_crtc->lut.nvbo) |
| 2309 | nouveau_bo_unpin(nv_crtc->lut.nvbo); |
| 2310 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
| 2311 | |
| 2312 | drm_crtc_cleanup(crtc); |
| 2313 | kfree(crtc); |
| 2314 | } |
| 2315 | |
| 2316 | static const struct drm_crtc_funcs |
| 2317 | nv50_head_func = { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2318 | .reset = nv50_head_reset, |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2319 | .gamma_set = nv50_head_gamma_set, |
| 2320 | .destroy = nv50_head_destroy, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2321 | .set_config = drm_atomic_helper_set_config, |
Andrey Grodzovsky | 612fb5d | 2017-02-02 16:56:30 -0500 | [diff] [blame] | 2322 | .page_flip = drm_atomic_helper_page_flip, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2323 | .set_property = drm_atomic_helper_crtc_set_property, |
| 2324 | .atomic_duplicate_state = nv50_head_atomic_duplicate_state, |
| 2325 | .atomic_destroy_state = nv50_head_atomic_destroy_state, |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2326 | }; |
| 2327 | |
| 2328 | static int |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2329 | nv50_head_create(struct drm_device *dev, int index) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2330 | { |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2331 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 2332 | struct nvif_device *device = &drm->client.device; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2333 | struct nv50_disp *disp = nv50_disp(dev); |
| 2334 | struct nv50_head *head; |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2335 | struct nv50_base *base; |
Ben Skeggs | 22e927d | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2336 | struct nv50_curs *curs; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2337 | struct drm_crtc *crtc; |
| 2338 | int ret, i; |
| 2339 | |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 2340 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
| 2341 | if (!head) |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2342 | return -ENOMEM; |
| 2343 | |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 2344 | head->base.index = index; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2345 | for (i = 0; i < 256; i++) { |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 2346 | head->base.lut.r[i] = i << 8; |
| 2347 | head->base.lut.g[i] = i << 8; |
| 2348 | head->base.lut.b[i] = i << 8; |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2349 | } |
| 2350 | |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2351 | ret = nv50_base_new(drm, head, &base); |
Ben Skeggs | 22e927d | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2352 | if (ret == 0) |
| 2353 | ret = nv50_curs_new(drm, head, &curs); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2354 | if (ret) { |
| 2355 | kfree(head); |
| 2356 | return ret; |
| 2357 | } |
| 2358 | |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 2359 | crtc = &head->base.base; |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2360 | drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane, |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2361 | &curs->wndw.plane, &nv50_head_func, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2362 | "head-%d", head->base.index); |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2363 | drm_crtc_helper_add(crtc, &nv50_head_help); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2364 | drm_mode_crtc_set_gamma_size(crtc, 256); |
| 2365 | |
Ben Skeggs | bab7cc1 | 2016-05-24 17:26:48 +1000 | [diff] [blame] | 2366 | ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM, |
Maarten Lankhorst | bb6178b | 2014-01-09 11:03:15 +0100 | [diff] [blame] | 2367 | 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2368 | if (!ret) { |
Ben Skeggs | 547ad07 | 2014-11-10 12:35:06 +1000 | [diff] [blame] | 2369 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 2370 | if (!ret) { |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 2371 | ret = nouveau_bo_map(head->base.lut.nvbo); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 2372 | if (ret) |
| 2373 | nouveau_bo_unpin(head->base.lut.nvbo); |
| 2374 | } |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2375 | if (ret) |
Ben Skeggs | dd0e3d5 | 2012-10-16 14:00:31 +1000 | [diff] [blame] | 2376 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2377 | } |
| 2378 | |
| 2379 | if (ret) |
| 2380 | goto out; |
| 2381 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2382 | /* allocate overlay resources */ |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2383 | ret = nv50_oimm_create(device, disp->disp, index, &head->oimm); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2384 | if (ret) |
| 2385 | goto out; |
| 2386 | |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2387 | ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset, |
| 2388 | &head->ovly); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 2389 | if (ret) |
| 2390 | goto out; |
| 2391 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2392 | out: |
| 2393 | if (ret) |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2394 | nv50_head_destroy(crtc); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 2395 | return ret; |
| 2396 | } |
| 2397 | |
| 2398 | /****************************************************************************** |
Ben Skeggs | d92c8ad | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2399 | * Output path helpers |
Ben Skeggs | a91d322 | 2014-12-22 16:30:13 +1000 | [diff] [blame] | 2400 | *****************************************************************************/ |
Ben Skeggs | d92c8ad | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2401 | static int |
| 2402 | nv50_outp_atomic_check_view(struct drm_encoder *encoder, |
| 2403 | struct drm_crtc_state *crtc_state, |
| 2404 | struct drm_connector_state *conn_state, |
| 2405 | struct drm_display_mode *native_mode) |
| 2406 | { |
| 2407 | struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; |
| 2408 | struct drm_display_mode *mode = &crtc_state->mode; |
| 2409 | struct drm_connector *connector = conn_state->connector; |
| 2410 | struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state); |
| 2411 | struct nouveau_drm *drm = nouveau_drm(encoder->dev); |
| 2412 | |
| 2413 | NV_ATOMIC(drm, "%s atomic_check\n", encoder->name); |
| 2414 | asyc->scaler.full = false; |
| 2415 | if (!native_mode) |
| 2416 | return 0; |
| 2417 | |
| 2418 | if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) { |
| 2419 | switch (connector->connector_type) { |
| 2420 | case DRM_MODE_CONNECTOR_LVDS: |
| 2421 | case DRM_MODE_CONNECTOR_eDP: |
| 2422 | /* Force use of scaler for non-EDID modes. */ |
| 2423 | if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER) |
| 2424 | break; |
| 2425 | mode = native_mode; |
| 2426 | asyc->scaler.full = true; |
| 2427 | break; |
| 2428 | default: |
| 2429 | break; |
| 2430 | } |
| 2431 | } else { |
| 2432 | mode = native_mode; |
| 2433 | } |
| 2434 | |
| 2435 | if (!drm_mode_equal(adjusted_mode, mode)) { |
| 2436 | drm_mode_copy(adjusted_mode, mode); |
| 2437 | crtc_state->mode_changed = true; |
| 2438 | } |
| 2439 | |
| 2440 | return 0; |
| 2441 | } |
| 2442 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2443 | static int |
| 2444 | nv50_outp_atomic_check(struct drm_encoder *encoder, |
| 2445 | struct drm_crtc_state *crtc_state, |
| 2446 | struct drm_connector_state *conn_state) |
Ben Skeggs | a91d322 | 2014-12-22 16:30:13 +1000 | [diff] [blame] | 2447 | { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2448 | struct nouveau_connector *nv_connector = |
| 2449 | nouveau_connector(conn_state->connector); |
| 2450 | return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, |
| 2451 | nv_connector->native_mode); |
Ben Skeggs | a91d322 | 2014-12-22 16:30:13 +1000 | [diff] [blame] | 2452 | } |
| 2453 | |
| 2454 | /****************************************************************************** |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2455 | * DAC |
| 2456 | *****************************************************************************/ |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2457 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2458 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2459 | { |
| 2460 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2461 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | bf0eb89 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2462 | struct { |
| 2463 | struct nv50_disp_mthd_v1 base; |
| 2464 | struct nv50_disp_dac_pwr_v0 pwr; |
| 2465 | } args = { |
| 2466 | .base.version = 1, |
| 2467 | .base.method = NV50_DISP_MTHD_V1_DAC_PWR, |
| 2468 | .base.hasht = nv_encoder->dcb->hasht, |
| 2469 | .base.hashm = nv_encoder->dcb->hashm, |
| 2470 | .pwr.state = 1, |
| 2471 | .pwr.data = 1, |
| 2472 | .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND && |
| 2473 | mode != DRM_MODE_DPMS_OFF), |
| 2474 | .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY && |
| 2475 | mode != DRM_MODE_DPMS_OFF), |
| 2476 | }; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2477 | |
Ben Skeggs | bf0eb89 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2478 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2479 | } |
| 2480 | |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2481 | static void |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2482 | nv50_dac_disable(struct drm_encoder *encoder) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2483 | { |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2484 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 2485 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
| 2486 | const int or = nv_encoder->or; |
| 2487 | u32 *push; |
| 2488 | |
| 2489 | if (nv_encoder->crtc) { |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2490 | push = evo_wait(mast, 4); |
| 2491 | if (push) { |
| 2492 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
| 2493 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
| 2494 | evo_data(push, 0x00000000); |
| 2495 | } else { |
| 2496 | evo_mthd(push, 0x0180 + (or * 0x020), 1); |
| 2497 | evo_data(push, 0x00000000); |
| 2498 | } |
| 2499 | evo_kick(push, mast); |
| 2500 | } |
| 2501 | } |
| 2502 | |
| 2503 | nv_encoder->crtc = NULL; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2504 | } |
| 2505 | |
| 2506 | static void |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2507 | nv50_dac_enable(struct drm_encoder *encoder) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2508 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2509 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2510 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 2511 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2512 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 2513 | u32 *push; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2514 | |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 2515 | push = evo_wait(mast, 8); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2516 | if (push) { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 2517 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
Ben Skeggs | 97b19b5 | 2012-11-16 11:21:37 +1000 | [diff] [blame] | 2518 | u32 syncs = 0x00000000; |
| 2519 | |
| 2520 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 2521 | syncs |= 0x00000001; |
| 2522 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 2523 | syncs |= 0x00000002; |
| 2524 | |
| 2525 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); |
| 2526 | evo_data(push, 1 << nv_crtc->index); |
| 2527 | evo_data(push, syncs); |
| 2528 | } else { |
| 2529 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); |
| 2530 | u32 syncs = 0x00000001; |
| 2531 | |
| 2532 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 2533 | syncs |= 0x00000008; |
| 2534 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 2535 | syncs |= 0x00000010; |
| 2536 | |
| 2537 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 2538 | magic |= 0x00000001; |
| 2539 | |
| 2540 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); |
| 2541 | evo_data(push, syncs); |
| 2542 | evo_data(push, magic); |
| 2543 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); |
| 2544 | evo_data(push, 1 << nv_crtc->index); |
| 2545 | } |
| 2546 | |
| 2547 | evo_kick(push, mast); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2548 | } |
| 2549 | |
| 2550 | nv_encoder->crtc = encoder->crtc; |
| 2551 | } |
| 2552 | |
Ben Skeggs | b6d8e7e | 2011-07-07 09:51:29 +1000 | [diff] [blame] | 2553 | static enum drm_connector_status |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2554 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
Ben Skeggs | b6d8e7e | 2011-07-07 09:51:29 +1000 | [diff] [blame] | 2555 | { |
Ben Skeggs | c4abd31 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2556 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2557 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | c4abd31 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2558 | struct { |
| 2559 | struct nv50_disp_mthd_v1 base; |
| 2560 | struct nv50_disp_dac_load_v0 load; |
| 2561 | } args = { |
| 2562 | .base.version = 1, |
| 2563 | .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, |
| 2564 | .base.hasht = nv_encoder->dcb->hasht, |
| 2565 | .base.hashm = nv_encoder->dcb->hashm, |
| 2566 | }; |
| 2567 | int ret; |
Ben Skeggs | b681993 | 2011-07-08 11:14:50 +1000 | [diff] [blame] | 2568 | |
Ben Skeggs | c4abd31 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2569 | args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; |
| 2570 | if (args.load.data == 0) |
| 2571 | args.load.data = 340; |
| 2572 | |
| 2573 | ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
| 2574 | if (ret || !args.load.load) |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 2575 | return connector_status_disconnected; |
Ben Skeggs | b681993 | 2011-07-08 11:14:50 +1000 | [diff] [blame] | 2576 | |
Ben Skeggs | 35b21d3 | 2012-11-08 12:08:55 +1000 | [diff] [blame] | 2577 | return connector_status_connected; |
Ben Skeggs | b6d8e7e | 2011-07-07 09:51:29 +1000 | [diff] [blame] | 2578 | } |
| 2579 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2580 | static const struct drm_encoder_helper_funcs |
| 2581 | nv50_dac_help = { |
| 2582 | .dpms = nv50_dac_dpms, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2583 | .atomic_check = nv50_outp_atomic_check, |
| 2584 | .enable = nv50_dac_enable, |
| 2585 | .disable = nv50_dac_disable, |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2586 | .detect = nv50_dac_detect |
| 2587 | }; |
| 2588 | |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2589 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2590 | nv50_dac_destroy(struct drm_encoder *encoder) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2591 | { |
| 2592 | drm_encoder_cleanup(encoder); |
| 2593 | kfree(encoder); |
| 2594 | } |
| 2595 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2596 | static const struct drm_encoder_funcs |
| 2597 | nv50_dac_func = { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2598 | .destroy = nv50_dac_destroy, |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2599 | }; |
| 2600 | |
| 2601 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2602 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2603 | { |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 2604 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 2605 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2606 | struct nvkm_i2c_bus *bus; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2607 | struct nouveau_encoder *nv_encoder; |
| 2608 | struct drm_encoder *encoder; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 2609 | int type = DRM_MODE_ENCODER_DAC; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2610 | |
| 2611 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
| 2612 | if (!nv_encoder) |
| 2613 | return -ENOMEM; |
| 2614 | nv_encoder->dcb = dcbe; |
| 2615 | nv_encoder->or = ffs(dcbe->or) - 1; |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 2616 | |
| 2617 | bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index); |
| 2618 | if (bus) |
| 2619 | nv_encoder->i2c = &bus->i2c; |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2620 | |
| 2621 | encoder = to_drm_encoder(nv_encoder); |
| 2622 | encoder->possible_crtcs = dcbe->heads; |
| 2623 | encoder->possible_clones = 0; |
Ben Skeggs | 5a223da | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2624 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, |
| 2625 | "dac-%04x-%04x", dcbe->hasht, dcbe->hashm); |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2626 | drm_encoder_helper_add(encoder, &nv50_dac_help); |
Ben Skeggs | 8eaa966 | 2011-07-06 15:25:47 +1000 | [diff] [blame] | 2627 | |
| 2628 | drm_mode_connector_attach_encoder(connector, encoder); |
| 2629 | return 0; |
| 2630 | } |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 2631 | |
| 2632 | /****************************************************************************** |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2633 | * Audio |
| 2634 | *****************************************************************************/ |
| 2635 | static void |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2636 | nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
| 2637 | { |
| 2638 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 2639 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
| 2640 | struct { |
| 2641 | struct nv50_disp_mthd_v1 base; |
| 2642 | struct nv50_disp_sor_hda_eld_v0 eld; |
| 2643 | } args = { |
| 2644 | .base.version = 1, |
| 2645 | .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, |
| 2646 | .base.hasht = nv_encoder->dcb->hasht, |
| 2647 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
| 2648 | (0x0100 << nv_crtc->index), |
| 2649 | }; |
| 2650 | |
| 2651 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
| 2652 | } |
| 2653 | |
| 2654 | static void |
| 2655 | nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2656 | { |
| 2657 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | cc2a907 | 2014-09-15 21:29:05 +1000 | [diff] [blame] | 2658 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2659 | struct nouveau_connector *nv_connector; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2660 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | d889c52 | 2014-09-15 21:11:51 +1000 | [diff] [blame] | 2661 | struct __packed { |
| 2662 | struct { |
| 2663 | struct nv50_disp_mthd_v1 mthd; |
| 2664 | struct nv50_disp_sor_hda_eld_v0 eld; |
| 2665 | } base; |
Ben Skeggs | 120b0c3 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2666 | u8 data[sizeof(nv_connector->base.eld)]; |
| 2667 | } args = { |
Ben Skeggs | d889c52 | 2014-09-15 21:11:51 +1000 | [diff] [blame] | 2668 | .base.mthd.version = 1, |
| 2669 | .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, |
| 2670 | .base.mthd.hasht = nv_encoder->dcb->hasht, |
Ben Skeggs | cc2a907 | 2014-09-15 21:29:05 +1000 | [diff] [blame] | 2671 | .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
| 2672 | (0x0100 << nv_crtc->index), |
Ben Skeggs | 120b0c3 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2673 | }; |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2674 | |
| 2675 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 2676 | if (!drm_detect_monitor_audio(nv_connector->edid)) |
| 2677 | return; |
| 2678 | |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2679 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
Ben Skeggs | 120b0c3 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2680 | memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2681 | |
Jani Nikula | 938fd8a | 2014-10-28 16:20:48 +0200 | [diff] [blame] | 2682 | nvif_mthd(disp->disp, 0, &args, |
| 2683 | sizeof(args.base) + drm_eld_size(args.data)); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2684 | } |
| 2685 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2686 | /****************************************************************************** |
| 2687 | * HDMI |
| 2688 | *****************************************************************************/ |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2689 | static void |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2690 | nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2691 | { |
| 2692 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2693 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 120b0c3 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2694 | struct { |
| 2695 | struct nv50_disp_mthd_v1 base; |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2696 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; |
Ben Skeggs | 120b0c3 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2697 | } args = { |
| 2698 | .base.version = 1, |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2699 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, |
| 2700 | .base.hasht = nv_encoder->dcb->hasht, |
| 2701 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
| 2702 | (0x0100 << nv_crtc->index), |
Ben Skeggs | 120b0c3 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2703 | }; |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2704 | |
Ben Skeggs | 120b0c3 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2705 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2706 | } |
| 2707 | |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2708 | static void |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2709 | nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode) |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2710 | { |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 2711 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 2712 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 2713 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | e00f223 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2714 | struct { |
| 2715 | struct nv50_disp_mthd_v1 base; |
| 2716 | struct nv50_disp_sor_hdmi_pwr_v0 pwr; |
| 2717 | } args = { |
| 2718 | .base.version = 1, |
| 2719 | .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, |
| 2720 | .base.hasht = nv_encoder->dcb->hasht, |
| 2721 | .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | |
| 2722 | (0x0100 << nv_crtc->index), |
| 2723 | .pwr.state = 1, |
| 2724 | .pwr.rekey = 56, /* binary driver, and tegra, constant */ |
| 2725 | }; |
| 2726 | struct nouveau_connector *nv_connector; |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 2727 | u32 max_ac_packet; |
| 2728 | |
| 2729 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 2730 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) |
| 2731 | return; |
| 2732 | |
| 2733 | max_ac_packet = mode->htotal - mode->hdisplay; |
Ben Skeggs | e00f223 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2734 | max_ac_packet -= args.pwr.rekey; |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 2735 | max_ac_packet -= 18; /* constant from tegra */ |
Ben Skeggs | e00f223 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2736 | args.pwr.max_ac_packet = max_ac_packet / 32; |
Ben Skeggs | 64d9cc0 | 2011-11-11 19:51:20 +1000 | [diff] [blame] | 2737 | |
Ben Skeggs | e00f223 | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 2738 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2739 | nv50_audio_enable(encoder, mode); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 2740 | } |
| 2741 | |
| 2742 | /****************************************************************************** |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2743 | * MST |
| 2744 | *****************************************************************************/ |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2745 | #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr) |
| 2746 | #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector) |
| 2747 | #define nv50_msto(p) container_of((p), struct nv50_msto, encoder) |
| 2748 | |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2749 | struct nv50_mstm { |
| 2750 | struct nouveau_encoder *outp; |
| 2751 | |
| 2752 | struct drm_dp_mst_topology_mgr mgr; |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2753 | struct nv50_msto *msto[4]; |
| 2754 | |
| 2755 | bool modified; |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2756 | }; |
| 2757 | |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2758 | struct nv50_mstc { |
| 2759 | struct nv50_mstm *mstm; |
| 2760 | struct drm_dp_mst_port *port; |
| 2761 | struct drm_connector connector; |
| 2762 | |
| 2763 | struct drm_display_mode *native; |
| 2764 | struct edid *edid; |
| 2765 | |
| 2766 | int pbn; |
| 2767 | }; |
| 2768 | |
| 2769 | struct nv50_msto { |
| 2770 | struct drm_encoder encoder; |
| 2771 | |
| 2772 | struct nv50_head *head; |
| 2773 | struct nv50_mstc *mstc; |
| 2774 | bool disabled; |
| 2775 | }; |
| 2776 | |
| 2777 | static struct drm_dp_payload * |
| 2778 | nv50_msto_payload(struct nv50_msto *msto) |
| 2779 | { |
| 2780 | struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); |
| 2781 | struct nv50_mstc *mstc = msto->mstc; |
| 2782 | struct nv50_mstm *mstm = mstc->mstm; |
| 2783 | int vcpi = mstc->port->vcpi.vcpi, i; |
| 2784 | |
| 2785 | NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi); |
| 2786 | for (i = 0; i < mstm->mgr.max_payloads; i++) { |
| 2787 | struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; |
| 2788 | NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n", |
| 2789 | mstm->outp->base.base.name, i, payload->vcpi, |
| 2790 | payload->start_slot, payload->num_slots); |
| 2791 | } |
| 2792 | |
| 2793 | for (i = 0; i < mstm->mgr.max_payloads; i++) { |
| 2794 | struct drm_dp_payload *payload = &mstm->mgr.payloads[i]; |
| 2795 | if (payload->vcpi == vcpi) |
| 2796 | return payload; |
| 2797 | } |
| 2798 | |
| 2799 | return NULL; |
| 2800 | } |
| 2801 | |
| 2802 | static void |
| 2803 | nv50_msto_cleanup(struct nv50_msto *msto) |
| 2804 | { |
| 2805 | struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); |
| 2806 | struct nv50_mstc *mstc = msto->mstc; |
| 2807 | struct nv50_mstm *mstm = mstc->mstm; |
| 2808 | |
| 2809 | NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name); |
| 2810 | if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto)) |
| 2811 | drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port); |
| 2812 | if (msto->disabled) { |
| 2813 | msto->mstc = NULL; |
| 2814 | msto->head = NULL; |
| 2815 | msto->disabled = false; |
| 2816 | } |
| 2817 | } |
| 2818 | |
| 2819 | static void |
| 2820 | nv50_msto_prepare(struct nv50_msto *msto) |
| 2821 | { |
| 2822 | struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev); |
| 2823 | struct nv50_mstc *mstc = msto->mstc; |
| 2824 | struct nv50_mstm *mstm = mstc->mstm; |
| 2825 | struct { |
| 2826 | struct nv50_disp_mthd_v1 base; |
| 2827 | struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi; |
| 2828 | } args = { |
| 2829 | .base.version = 1, |
| 2830 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI, |
| 2831 | .base.hasht = mstm->outp->dcb->hasht, |
| 2832 | .base.hashm = (0xf0ff & mstm->outp->dcb->hashm) | |
| 2833 | (0x0100 << msto->head->base.index), |
| 2834 | }; |
| 2835 | |
| 2836 | NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name); |
| 2837 | if (mstc->port && mstc->port->vcpi.vcpi > 0) { |
| 2838 | struct drm_dp_payload *payload = nv50_msto_payload(msto); |
| 2839 | if (payload) { |
| 2840 | args.vcpi.start_slot = payload->start_slot; |
| 2841 | args.vcpi.num_slots = payload->num_slots; |
| 2842 | args.vcpi.pbn = mstc->port->vcpi.pbn; |
| 2843 | args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn; |
| 2844 | } |
| 2845 | } |
| 2846 | |
| 2847 | NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n", |
| 2848 | msto->encoder.name, msto->head->base.base.name, |
| 2849 | args.vcpi.start_slot, args.vcpi.num_slots, |
| 2850 | args.vcpi.pbn, args.vcpi.aligned_pbn); |
| 2851 | nvif_mthd(&drm->display->disp, 0, &args, sizeof(args)); |
| 2852 | } |
| 2853 | |
| 2854 | static int |
| 2855 | nv50_msto_atomic_check(struct drm_encoder *encoder, |
| 2856 | struct drm_crtc_state *crtc_state, |
| 2857 | struct drm_connector_state *conn_state) |
| 2858 | { |
| 2859 | struct nv50_mstc *mstc = nv50_mstc(conn_state->connector); |
| 2860 | struct nv50_mstm *mstm = mstc->mstm; |
| 2861 | int bpp = conn_state->connector->display_info.bpc * 3; |
| 2862 | int slots; |
| 2863 | |
| 2864 | mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp); |
| 2865 | |
| 2866 | slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); |
| 2867 | if (slots < 0) |
| 2868 | return slots; |
| 2869 | |
| 2870 | return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state, |
| 2871 | mstc->native); |
| 2872 | } |
| 2873 | |
| 2874 | static void |
| 2875 | nv50_msto_enable(struct drm_encoder *encoder) |
| 2876 | { |
| 2877 | struct nv50_head *head = nv50_head(encoder->crtc); |
| 2878 | struct nv50_msto *msto = nv50_msto(encoder); |
| 2879 | struct nv50_mstc *mstc = NULL; |
| 2880 | struct nv50_mstm *mstm = NULL; |
| 2881 | struct drm_connector *connector; |
| 2882 | u8 proto, depth; |
| 2883 | int slots; |
| 2884 | bool r; |
| 2885 | |
| 2886 | drm_for_each_connector(connector, encoder->dev) { |
| 2887 | if (connector->state->best_encoder == &msto->encoder) { |
| 2888 | mstc = nv50_mstc(connector); |
| 2889 | mstm = mstc->mstm; |
| 2890 | break; |
| 2891 | } |
| 2892 | } |
| 2893 | |
| 2894 | if (WARN_ON(!mstc)) |
| 2895 | return; |
| 2896 | |
Pandiyan, Dhinakaran | 1e797f5 | 2017-03-16 00:10:26 -0700 | [diff] [blame] | 2897 | slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn); |
| 2898 | r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots); |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 2899 | WARN_ON(!r); |
| 2900 | |
| 2901 | if (mstm->outp->dcb->sorconf.link & 1) |
| 2902 | proto = 0x8; |
| 2903 | else |
| 2904 | proto = 0x9; |
| 2905 | |
| 2906 | switch (mstc->connector.display_info.bpc) { |
| 2907 | case 6: depth = 0x2; break; |
| 2908 | case 8: depth = 0x5; break; |
| 2909 | case 10: |
| 2910 | default: depth = 0x6; break; |
| 2911 | } |
| 2912 | |
| 2913 | mstm->outp->update(mstm->outp, head->base.index, |
| 2914 | &head->base.base.state->adjusted_mode, proto, depth); |
| 2915 | |
| 2916 | msto->head = head; |
| 2917 | msto->mstc = mstc; |
| 2918 | mstm->modified = true; |
| 2919 | } |
| 2920 | |
| 2921 | static void |
| 2922 | nv50_msto_disable(struct drm_encoder *encoder) |
| 2923 | { |
| 2924 | struct nv50_msto *msto = nv50_msto(encoder); |
| 2925 | struct nv50_mstc *mstc = msto->mstc; |
| 2926 | struct nv50_mstm *mstm = mstc->mstm; |
| 2927 | |
| 2928 | if (mstc->port) |
| 2929 | drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port); |
| 2930 | |
| 2931 | mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0); |
| 2932 | mstm->modified = true; |
| 2933 | msto->disabled = true; |
| 2934 | } |
| 2935 | |
| 2936 | static const struct drm_encoder_helper_funcs |
| 2937 | nv50_msto_help = { |
| 2938 | .disable = nv50_msto_disable, |
| 2939 | .enable = nv50_msto_enable, |
| 2940 | .atomic_check = nv50_msto_atomic_check, |
| 2941 | }; |
| 2942 | |
| 2943 | static void |
| 2944 | nv50_msto_destroy(struct drm_encoder *encoder) |
| 2945 | { |
| 2946 | struct nv50_msto *msto = nv50_msto(encoder); |
| 2947 | drm_encoder_cleanup(&msto->encoder); |
| 2948 | kfree(msto); |
| 2949 | } |
| 2950 | |
| 2951 | static const struct drm_encoder_funcs |
| 2952 | nv50_msto = { |
| 2953 | .destroy = nv50_msto_destroy, |
| 2954 | }; |
| 2955 | |
| 2956 | static int |
| 2957 | nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id, |
| 2958 | struct nv50_msto **pmsto) |
| 2959 | { |
| 2960 | struct nv50_msto *msto; |
| 2961 | int ret; |
| 2962 | |
| 2963 | if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL))) |
| 2964 | return -ENOMEM; |
| 2965 | |
| 2966 | ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto, |
| 2967 | DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id); |
| 2968 | if (ret) { |
| 2969 | kfree(*pmsto); |
| 2970 | *pmsto = NULL; |
| 2971 | return ret; |
| 2972 | } |
| 2973 | |
| 2974 | drm_encoder_helper_add(&msto->encoder, &nv50_msto_help); |
| 2975 | msto->encoder.possible_crtcs = heads; |
| 2976 | return 0; |
| 2977 | } |
| 2978 | |
| 2979 | static struct drm_encoder * |
| 2980 | nv50_mstc_atomic_best_encoder(struct drm_connector *connector, |
| 2981 | struct drm_connector_state *connector_state) |
| 2982 | { |
| 2983 | struct nv50_head *head = nv50_head(connector_state->crtc); |
| 2984 | struct nv50_mstc *mstc = nv50_mstc(connector); |
| 2985 | if (mstc->port) { |
| 2986 | struct nv50_mstm *mstm = mstc->mstm; |
| 2987 | return &mstm->msto[head->base.index]->encoder; |
| 2988 | } |
| 2989 | return NULL; |
| 2990 | } |
| 2991 | |
| 2992 | static struct drm_encoder * |
| 2993 | nv50_mstc_best_encoder(struct drm_connector *connector) |
| 2994 | { |
| 2995 | struct nv50_mstc *mstc = nv50_mstc(connector); |
| 2996 | if (mstc->port) { |
| 2997 | struct nv50_mstm *mstm = mstc->mstm; |
| 2998 | return &mstm->msto[0]->encoder; |
| 2999 | } |
| 3000 | return NULL; |
| 3001 | } |
| 3002 | |
| 3003 | static enum drm_mode_status |
| 3004 | nv50_mstc_mode_valid(struct drm_connector *connector, |
| 3005 | struct drm_display_mode *mode) |
| 3006 | { |
| 3007 | return MODE_OK; |
| 3008 | } |
| 3009 | |
| 3010 | static int |
| 3011 | nv50_mstc_get_modes(struct drm_connector *connector) |
| 3012 | { |
| 3013 | struct nv50_mstc *mstc = nv50_mstc(connector); |
| 3014 | int ret = 0; |
| 3015 | |
| 3016 | mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port); |
| 3017 | drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid); |
| 3018 | if (mstc->edid) { |
| 3019 | ret = drm_add_edid_modes(&mstc->connector, mstc->edid); |
| 3020 | drm_edid_to_eld(&mstc->connector, mstc->edid); |
| 3021 | } |
| 3022 | |
| 3023 | if (!mstc->connector.display_info.bpc) |
| 3024 | mstc->connector.display_info.bpc = 8; |
| 3025 | |
| 3026 | if (mstc->native) |
| 3027 | drm_mode_destroy(mstc->connector.dev, mstc->native); |
| 3028 | mstc->native = nouveau_conn_native_mode(&mstc->connector); |
| 3029 | return ret; |
| 3030 | } |
| 3031 | |
| 3032 | static const struct drm_connector_helper_funcs |
| 3033 | nv50_mstc_help = { |
| 3034 | .get_modes = nv50_mstc_get_modes, |
| 3035 | .mode_valid = nv50_mstc_mode_valid, |
| 3036 | .best_encoder = nv50_mstc_best_encoder, |
| 3037 | .atomic_best_encoder = nv50_mstc_atomic_best_encoder, |
| 3038 | }; |
| 3039 | |
| 3040 | static enum drm_connector_status |
| 3041 | nv50_mstc_detect(struct drm_connector *connector, bool force) |
| 3042 | { |
| 3043 | struct nv50_mstc *mstc = nv50_mstc(connector); |
| 3044 | if (!mstc->port) |
| 3045 | return connector_status_disconnected; |
| 3046 | return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port); |
| 3047 | } |
| 3048 | |
| 3049 | static void |
| 3050 | nv50_mstc_destroy(struct drm_connector *connector) |
| 3051 | { |
| 3052 | struct nv50_mstc *mstc = nv50_mstc(connector); |
| 3053 | drm_connector_cleanup(&mstc->connector); |
| 3054 | kfree(mstc); |
| 3055 | } |
| 3056 | |
| 3057 | static const struct drm_connector_funcs |
| 3058 | nv50_mstc = { |
| 3059 | .dpms = drm_atomic_helper_connector_dpms, |
| 3060 | .reset = nouveau_conn_reset, |
| 3061 | .detect = nv50_mstc_detect, |
| 3062 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 3063 | .set_property = drm_atomic_helper_connector_set_property, |
| 3064 | .destroy = nv50_mstc_destroy, |
| 3065 | .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state, |
| 3066 | .atomic_destroy_state = nouveau_conn_atomic_destroy_state, |
| 3067 | .atomic_set_property = nouveau_conn_atomic_set_property, |
| 3068 | .atomic_get_property = nouveau_conn_atomic_get_property, |
| 3069 | }; |
| 3070 | |
| 3071 | static int |
| 3072 | nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port, |
| 3073 | const char *path, struct nv50_mstc **pmstc) |
| 3074 | { |
| 3075 | struct drm_device *dev = mstm->outp->base.base.dev; |
| 3076 | struct nv50_mstc *mstc; |
| 3077 | int ret, i; |
| 3078 | |
| 3079 | if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL))) |
| 3080 | return -ENOMEM; |
| 3081 | mstc->mstm = mstm; |
| 3082 | mstc->port = port; |
| 3083 | |
| 3084 | ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc, |
| 3085 | DRM_MODE_CONNECTOR_DisplayPort); |
| 3086 | if (ret) { |
| 3087 | kfree(*pmstc); |
| 3088 | *pmstc = NULL; |
| 3089 | return ret; |
| 3090 | } |
| 3091 | |
| 3092 | drm_connector_helper_add(&mstc->connector, &nv50_mstc_help); |
| 3093 | |
| 3094 | mstc->connector.funcs->reset(&mstc->connector); |
| 3095 | nouveau_conn_attach_properties(&mstc->connector); |
| 3096 | |
| 3097 | for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++) |
| 3098 | drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder); |
| 3099 | |
| 3100 | drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0); |
| 3101 | drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0); |
| 3102 | drm_mode_connector_set_path_property(&mstc->connector, path); |
| 3103 | return 0; |
| 3104 | } |
| 3105 | |
| 3106 | static void |
| 3107 | nv50_mstm_cleanup(struct nv50_mstm *mstm) |
| 3108 | { |
| 3109 | struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); |
| 3110 | struct drm_encoder *encoder; |
| 3111 | int ret; |
| 3112 | |
| 3113 | NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name); |
| 3114 | ret = drm_dp_check_act_status(&mstm->mgr); |
| 3115 | |
| 3116 | ret = drm_dp_update_payload_part2(&mstm->mgr); |
| 3117 | |
| 3118 | drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { |
| 3119 | if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { |
| 3120 | struct nv50_msto *msto = nv50_msto(encoder); |
| 3121 | struct nv50_mstc *mstc = msto->mstc; |
| 3122 | if (mstc && mstc->mstm == mstm) |
| 3123 | nv50_msto_cleanup(msto); |
| 3124 | } |
| 3125 | } |
| 3126 | |
| 3127 | mstm->modified = false; |
| 3128 | } |
| 3129 | |
| 3130 | static void |
| 3131 | nv50_mstm_prepare(struct nv50_mstm *mstm) |
| 3132 | { |
| 3133 | struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev); |
| 3134 | struct drm_encoder *encoder; |
| 3135 | int ret; |
| 3136 | |
| 3137 | NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name); |
| 3138 | ret = drm_dp_update_payload_part1(&mstm->mgr); |
| 3139 | |
| 3140 | drm_for_each_encoder(encoder, mstm->outp->base.base.dev) { |
| 3141 | if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { |
| 3142 | struct nv50_msto *msto = nv50_msto(encoder); |
| 3143 | struct nv50_mstc *mstc = msto->mstc; |
| 3144 | if (mstc && mstc->mstm == mstm) |
| 3145 | nv50_msto_prepare(msto); |
| 3146 | } |
| 3147 | } |
| 3148 | } |
| 3149 | |
| 3150 | static void |
| 3151 | nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr) |
| 3152 | { |
| 3153 | struct nv50_mstm *mstm = nv50_mstm(mgr); |
| 3154 | drm_kms_helper_hotplug_event(mstm->outp->base.base.dev); |
| 3155 | } |
| 3156 | |
| 3157 | static void |
| 3158 | nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr, |
| 3159 | struct drm_connector *connector) |
| 3160 | { |
| 3161 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
| 3162 | struct nv50_mstc *mstc = nv50_mstc(connector); |
| 3163 | |
| 3164 | drm_connector_unregister(&mstc->connector); |
| 3165 | |
| 3166 | drm_modeset_lock_all(drm->dev); |
| 3167 | drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector); |
| 3168 | mstc->port = NULL; |
| 3169 | drm_modeset_unlock_all(drm->dev); |
| 3170 | |
| 3171 | drm_connector_unreference(&mstc->connector); |
| 3172 | } |
| 3173 | |
| 3174 | static void |
| 3175 | nv50_mstm_register_connector(struct drm_connector *connector) |
| 3176 | { |
| 3177 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
| 3178 | |
| 3179 | drm_modeset_lock_all(drm->dev); |
| 3180 | drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector); |
| 3181 | drm_modeset_unlock_all(drm->dev); |
| 3182 | |
| 3183 | drm_connector_register(connector); |
| 3184 | } |
| 3185 | |
| 3186 | static struct drm_connector * |
| 3187 | nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr, |
| 3188 | struct drm_dp_mst_port *port, const char *path) |
| 3189 | { |
| 3190 | struct nv50_mstm *mstm = nv50_mstm(mgr); |
| 3191 | struct nv50_mstc *mstc; |
| 3192 | int ret; |
| 3193 | |
| 3194 | ret = nv50_mstc_new(mstm, port, path, &mstc); |
| 3195 | if (ret) { |
| 3196 | if (mstc) |
| 3197 | mstc->connector.funcs->destroy(&mstc->connector); |
| 3198 | return NULL; |
| 3199 | } |
| 3200 | |
| 3201 | return &mstc->connector; |
| 3202 | } |
| 3203 | |
| 3204 | static const struct drm_dp_mst_topology_cbs |
| 3205 | nv50_mstm = { |
| 3206 | .add_connector = nv50_mstm_add_connector, |
| 3207 | .register_connector = nv50_mstm_register_connector, |
| 3208 | .destroy_connector = nv50_mstm_destroy_connector, |
| 3209 | .hotplug = nv50_mstm_hotplug, |
| 3210 | }; |
| 3211 | |
| 3212 | void |
| 3213 | nv50_mstm_service(struct nv50_mstm *mstm) |
| 3214 | { |
| 3215 | struct drm_dp_aux *aux = mstm->mgr.aux; |
| 3216 | bool handled = true; |
| 3217 | int ret; |
| 3218 | u8 esi[8] = {}; |
| 3219 | |
| 3220 | while (handled) { |
| 3221 | ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8); |
| 3222 | if (ret != 8) { |
| 3223 | drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); |
| 3224 | return; |
| 3225 | } |
| 3226 | |
| 3227 | drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled); |
| 3228 | if (!handled) |
| 3229 | break; |
| 3230 | |
| 3231 | drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3); |
| 3232 | } |
| 3233 | } |
| 3234 | |
| 3235 | void |
| 3236 | nv50_mstm_remove(struct nv50_mstm *mstm) |
| 3237 | { |
| 3238 | if (mstm) |
| 3239 | drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false); |
| 3240 | } |
| 3241 | |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3242 | static int |
| 3243 | nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) |
| 3244 | { |
| 3245 | struct nouveau_encoder *outp = mstm->outp; |
| 3246 | struct { |
| 3247 | struct nv50_disp_mthd_v1 base; |
| 3248 | struct nv50_disp_sor_dp_mst_link_v0 mst; |
| 3249 | } args = { |
| 3250 | .base.version = 1, |
| 3251 | .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK, |
| 3252 | .base.hasht = outp->dcb->hasht, |
| 3253 | .base.hashm = outp->dcb->hashm, |
| 3254 | .mst.state = state, |
| 3255 | }; |
| 3256 | struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev); |
| 3257 | struct nvif_object *disp = &drm->display->disp; |
| 3258 | int ret; |
| 3259 | |
| 3260 | if (dpcd >= 0x12) { |
| 3261 | ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd); |
| 3262 | if (ret < 0) |
| 3263 | return ret; |
| 3264 | |
| 3265 | dpcd &= ~DP_MST_EN; |
| 3266 | if (state) |
| 3267 | dpcd |= DP_MST_EN; |
| 3268 | |
| 3269 | ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd); |
| 3270 | if (ret < 0) |
| 3271 | return ret; |
| 3272 | } |
| 3273 | |
| 3274 | return nvif_mthd(disp, 0, &args, sizeof(args)); |
| 3275 | } |
| 3276 | |
| 3277 | int |
| 3278 | nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) |
| 3279 | { |
| 3280 | int ret, state = 0; |
| 3281 | |
| 3282 | if (!mstm) |
| 3283 | return 0; |
| 3284 | |
Ben Skeggs | 3ca03ca | 2016-11-07 14:51:53 +1000 | [diff] [blame] | 3285 | if (dpcd[0] >= 0x12) { |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3286 | ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]); |
| 3287 | if (ret < 0) |
| 3288 | return ret; |
| 3289 | |
Ben Skeggs | 3ca03ca | 2016-11-07 14:51:53 +1000 | [diff] [blame] | 3290 | if (!(dpcd[1] & DP_MST_CAP)) |
| 3291 | dpcd[0] = 0x11; |
| 3292 | else |
| 3293 | state = allow; |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3294 | } |
| 3295 | |
| 3296 | ret = nv50_mstm_enable(mstm, dpcd[0], state); |
| 3297 | if (ret) |
| 3298 | return ret; |
| 3299 | |
| 3300 | ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state); |
| 3301 | if (ret) |
| 3302 | return nv50_mstm_enable(mstm, dpcd[0], 0); |
| 3303 | |
| 3304 | return mstm->mgr.mst_state; |
| 3305 | } |
| 3306 | |
| 3307 | static void |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3308 | nv50_mstm_fini(struct nv50_mstm *mstm) |
| 3309 | { |
| 3310 | if (mstm && mstm->mgr.mst_state) |
| 3311 | drm_dp_mst_topology_mgr_suspend(&mstm->mgr); |
| 3312 | } |
| 3313 | |
| 3314 | static void |
| 3315 | nv50_mstm_init(struct nv50_mstm *mstm) |
| 3316 | { |
| 3317 | if (mstm && mstm->mgr.mst_state) |
| 3318 | drm_dp_mst_topology_mgr_resume(&mstm->mgr); |
| 3319 | } |
| 3320 | |
| 3321 | static void |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3322 | nv50_mstm_del(struct nv50_mstm **pmstm) |
| 3323 | { |
| 3324 | struct nv50_mstm *mstm = *pmstm; |
| 3325 | if (mstm) { |
| 3326 | kfree(*pmstm); |
| 3327 | *pmstm = NULL; |
| 3328 | } |
| 3329 | } |
| 3330 | |
| 3331 | static int |
| 3332 | nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max, |
| 3333 | int conn_base_id, struct nv50_mstm **pmstm) |
| 3334 | { |
| 3335 | const int max_payloads = hweight8(outp->dcb->heads); |
| 3336 | struct drm_device *dev = outp->base.base.dev; |
| 3337 | struct nv50_mstm *mstm; |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3338 | int ret, i; |
| 3339 | u8 dpcd; |
| 3340 | |
| 3341 | /* This is a workaround for some monitors not functioning |
| 3342 | * correctly in MST mode on initial module load. I think |
| 3343 | * some bad interaction with the VBIOS may be responsible. |
| 3344 | * |
| 3345 | * A good ol' off and on again seems to work here ;) |
| 3346 | */ |
| 3347 | ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd); |
| 3348 | if (ret >= 0 && dpcd >= 0x12) |
| 3349 | drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0); |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3350 | |
| 3351 | if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL))) |
| 3352 | return -ENOMEM; |
| 3353 | mstm->outp = outp; |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3354 | mstm->mgr.cbs = &nv50_mstm; |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3355 | |
Dhinakaran Pandiyan | 7b0a89a | 2017-01-24 15:49:29 -0800 | [diff] [blame] | 3356 | ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max, |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3357 | max_payloads, conn_base_id); |
| 3358 | if (ret) |
| 3359 | return ret; |
| 3360 | |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3361 | for (i = 0; i < max_payloads; i++) { |
| 3362 | ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name, |
| 3363 | i, &mstm->msto[i]); |
| 3364 | if (ret) |
| 3365 | return ret; |
| 3366 | } |
| 3367 | |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3368 | return 0; |
| 3369 | } |
| 3370 | |
| 3371 | /****************************************************************************** |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 3372 | * SOR |
| 3373 | *****************************************************************************/ |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 3374 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 3375 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3376 | { |
| 3377 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | d55b4af | 2014-08-10 04:10:26 +1000 | [diff] [blame] | 3378 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
| 3379 | struct { |
| 3380 | struct nv50_disp_mthd_v1 base; |
| 3381 | struct nv50_disp_sor_pwr_v0 pwr; |
| 3382 | } args = { |
| 3383 | .base.version = 1, |
| 3384 | .base.method = NV50_DISP_MTHD_V1_SOR_PWR, |
| 3385 | .base.hasht = nv_encoder->dcb->hasht, |
| 3386 | .base.hashm = nv_encoder->dcb->hashm, |
| 3387 | .pwr.state = mode == DRM_MODE_DPMS_ON, |
| 3388 | }; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3389 | |
Ben Skeggs | 8896cee | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3390 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3391 | } |
| 3392 | |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3393 | static void |
Ben Skeggs | d665c7e | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3394 | nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, |
| 3395 | struct drm_display_mode *mode, u8 proto, u8 depth) |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3396 | { |
Ben Skeggs | d665c7e | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3397 | struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base; |
| 3398 | u32 *push; |
| 3399 | |
| 3400 | if (!mode) { |
| 3401 | nv_encoder->ctrl &= ~BIT(head); |
| 3402 | if (!(nv_encoder->ctrl & 0x0000000f)) |
| 3403 | nv_encoder->ctrl = 0; |
| 3404 | } else { |
| 3405 | nv_encoder->ctrl |= proto << 8; |
| 3406 | nv_encoder->ctrl |= BIT(head); |
| 3407 | } |
| 3408 | |
| 3409 | if ((push = evo_wait(core, 6))) { |
| 3410 | if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) { |
| 3411 | if (mode) { |
| 3412 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 3413 | nv_encoder->ctrl |= 0x00001000; |
| 3414 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 3415 | nv_encoder->ctrl |= 0x00002000; |
| 3416 | nv_encoder->ctrl |= depth << 16; |
| 3417 | } |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3418 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3419 | } else { |
Ben Skeggs | d665c7e | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3420 | if (mode) { |
| 3421 | u32 magic = 0x31ec6000 | (head << 25); |
| 3422 | u32 syncs = 0x00000001; |
| 3423 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 3424 | syncs |= 0x00000008; |
| 3425 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 3426 | syncs |= 0x00000010; |
| 3427 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 3428 | magic |= 0x00000001; |
| 3429 | |
| 3430 | evo_mthd(push, 0x0404 + (head * 0x300), 2); |
| 3431 | evo_data(push, syncs | (depth << 6)); |
| 3432 | evo_data(push, magic); |
| 3433 | } |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3434 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3435 | } |
Ben Skeggs | d665c7e | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3436 | evo_data(push, nv_encoder->ctrl); |
| 3437 | evo_kick(push, core); |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3438 | } |
| 3439 | } |
| 3440 | |
| 3441 | static void |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3442 | nv50_sor_disable(struct drm_encoder *encoder) |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 3443 | { |
| 3444 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3445 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3446 | |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3447 | nv_encoder->crtc = NULL; |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3448 | |
| 3449 | if (nv_crtc) { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3450 | struct nvkm_i2c_aux *aux = nv_encoder->aux; |
| 3451 | u8 pwr; |
| 3452 | |
| 3453 | if (aux) { |
| 3454 | int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1); |
| 3455 | if (ret == 0) { |
| 3456 | pwr &= ~DP_SET_POWER_MASK; |
| 3457 | pwr |= DP_SET_POWER_D3; |
| 3458 | nvkm_wraux(aux, DP_SET_POWER, &pwr, 1); |
| 3459 | } |
| 3460 | } |
| 3461 | |
Ben Skeggs | d665c7e | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3462 | nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0); |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3463 | nv50_audio_disable(encoder, nv_crtc); |
| 3464 | nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc); |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3465 | } |
Ben Skeggs | 4cbb0f8 | 2012-03-12 15:23:44 +1000 | [diff] [blame] | 3466 | } |
| 3467 | |
| 3468 | static void |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3469 | nv50_sor_enable(struct drm_encoder *encoder) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3470 | { |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3471 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 3472 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3473 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3474 | struct { |
| 3475 | struct nv50_disp_mthd_v1 base; |
| 3476 | struct nv50_disp_sor_lvds_script_v0 lvds; |
| 3477 | } lvds = { |
| 3478 | .base.version = 1, |
| 3479 | .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, |
| 3480 | .base.hasht = nv_encoder->dcb->hasht, |
| 3481 | .base.hashm = nv_encoder->dcb->hashm, |
| 3482 | }; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 3483 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 78951d2 | 2011-11-11 18:13:13 +1000 | [diff] [blame] | 3484 | struct drm_device *dev = encoder->dev; |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 3485 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3486 | struct nouveau_connector *nv_connector; |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 3487 | struct nvbios *bios = &drm->vbios; |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3488 | u8 proto = 0xf; |
| 3489 | u8 depth = 0x0; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3490 | |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3491 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
Ben Skeggs | e84a35a | 2014-06-05 10:59:55 +1000 | [diff] [blame] | 3492 | nv_encoder->crtc = encoder->crtc; |
| 3493 | |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3494 | switch (nv_encoder->dcb->type) { |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 3495 | case DCB_OUTPUT_TMDS: |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3496 | if (nv_encoder->dcb->sorconf.link & 1) { |
Hauke Mehrtens | 16ef53a9 | 2015-11-03 21:00:10 -0500 | [diff] [blame] | 3497 | proto = 0x1; |
| 3498 | /* Only enable dual-link if: |
| 3499 | * - Need to (i.e. rate > 165MHz) |
| 3500 | * - DCB says we can |
| 3501 | * - Not an HDMI monitor, since there's no dual-link |
| 3502 | * on HDMI. |
| 3503 | */ |
| 3504 | if (mode->clock >= 165000 && |
| 3505 | nv_encoder->dcb->duallink_possible && |
| 3506 | !drm_detect_hdmi_monitor(nv_connector->edid)) |
| 3507 | proto |= 0x4; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3508 | } else { |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3509 | proto = 0x2; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3510 | } |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3511 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3512 | nv50_hdmi_enable(&nv_encoder->base.base, mode); |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3513 | break; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 3514 | case DCB_OUTPUT_LVDS: |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3515 | proto = 0x0; |
| 3516 | |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3517 | if (bios->fp_no_ddc) { |
| 3518 | if (bios->fp.dual_link) |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3519 | lvds.lvds.script |= 0x0100; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3520 | if (bios->fp.if_is_24bit) |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3521 | lvds.lvds.script |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3522 | } else { |
Ben Skeggs | befb51e | 2011-11-18 10:23:59 +1000 | [diff] [blame] | 3523 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3524 | if (((u8 *)nv_connector->edid)[121] == 2) |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3525 | lvds.lvds.script |= 0x0100; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3526 | } else |
| 3527 | if (mode->clock >= bios->fp.duallink_transition_clk) { |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3528 | lvds.lvds.script |= 0x0100; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3529 | } |
| 3530 | |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3531 | if (lvds.lvds.script & 0x0100) { |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3532 | if (bios->fp.strapless_is_24bit & 2) |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3533 | lvds.lvds.script |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3534 | } else { |
| 3535 | if (bios->fp.strapless_is_24bit & 1) |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3536 | lvds.lvds.script |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3537 | } |
| 3538 | |
| 3539 | if (nv_connector->base.display_info.bpc == 8) |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3540 | lvds.lvds.script |= 0x0200; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3541 | } |
Ben Skeggs | 4a230fa | 2012-11-09 11:25:37 +1000 | [diff] [blame] | 3542 | |
Ben Skeggs | a3761fa | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3543 | nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3544 | break; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 3545 | case DCB_OUTPUT_DP: |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3546 | if (nv_connector->base.display_info.bpc == 6) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3547 | depth = 0x2; |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3548 | else |
| 3549 | if (nv_connector->base.display_info.bpc == 8) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3550 | depth = 0x5; |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3551 | else |
Ben Skeggs | bf2c886 | 2012-11-21 14:49:54 +1000 | [diff] [blame] | 3552 | depth = 0x6; |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 3553 | |
| 3554 | if (nv_encoder->dcb->sorconf.link & 1) |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3555 | proto = 0x8; |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 3556 | else |
Ben Skeggs | 419e8dc | 2012-11-16 11:40:34 +1000 | [diff] [blame] | 3557 | proto = 0x9; |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3558 | |
| 3559 | nv50_audio_enable(encoder, mode); |
Ben Skeggs | 6e83fda | 2012-03-11 01:28:48 +1000 | [diff] [blame] | 3560 | break; |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3561 | default: |
Ben Skeggs | af7db03 | 2016-03-03 12:56:33 +1000 | [diff] [blame] | 3562 | BUG(); |
Ben Skeggs | 3b6d83d1 | 2011-07-08 12:52:14 +1000 | [diff] [blame] | 3563 | break; |
| 3564 | } |
Ben Skeggs | ff8ff50 | 2011-07-08 11:53:37 +1000 | [diff] [blame] | 3565 | |
Ben Skeggs | d665c7e | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3566 | nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3567 | } |
| 3568 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3569 | static const struct drm_encoder_helper_funcs |
| 3570 | nv50_sor_help = { |
| 3571 | .dpms = nv50_sor_dpms, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3572 | .atomic_check = nv50_outp_atomic_check, |
| 3573 | .enable = nv50_sor_enable, |
| 3574 | .disable = nv50_sor_disable, |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3575 | }; |
| 3576 | |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3577 | static void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 3578 | nv50_sor_destroy(struct drm_encoder *encoder) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3579 | { |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3580 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 3581 | nv50_mstm_del(&nv_encoder->dp.mstm); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3582 | drm_encoder_cleanup(encoder); |
| 3583 | kfree(encoder); |
| 3584 | } |
| 3585 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3586 | static const struct drm_encoder_funcs |
| 3587 | nv50_sor_func = { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 3588 | .destroy = nv50_sor_destroy, |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3589 | }; |
| 3590 | |
| 3591 | static int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 3592 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3593 | { |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3594 | struct nouveau_connector *nv_connector = nouveau_connector(connector); |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 3595 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 3596 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3597 | struct nouveau_encoder *nv_encoder; |
| 3598 | struct drm_encoder *encoder; |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3599 | int type, ret; |
Ben Skeggs | 5ed5020 | 2013-02-11 20:15:03 +1000 | [diff] [blame] | 3600 | |
| 3601 | switch (dcbe->type) { |
| 3602 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; |
| 3603 | case DCB_OUTPUT_TMDS: |
| 3604 | case DCB_OUTPUT_DP: |
| 3605 | default: |
| 3606 | type = DRM_MODE_ENCODER_TMDS; |
| 3607 | break; |
| 3608 | } |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3609 | |
| 3610 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
| 3611 | if (!nv_encoder) |
| 3612 | return -ENOMEM; |
| 3613 | nv_encoder->dcb = dcbe; |
| 3614 | nv_encoder->or = ffs(dcbe->or) - 1; |
Ben Skeggs | d665c7e | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3615 | nv_encoder->update = nv50_sor_update; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3616 | |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3617 | encoder = to_drm_encoder(nv_encoder); |
| 3618 | encoder->possible_crtcs = dcbe->heads; |
| 3619 | encoder->possible_clones = 0; |
Ben Skeggs | 5a223da | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3620 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, |
| 3621 | "sor-%04x-%04x", dcbe->hasht, dcbe->hashm); |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3622 | drm_encoder_helper_add(encoder, &nv50_sor_help); |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3623 | |
| 3624 | drm_mode_connector_attach_encoder(connector, encoder); |
| 3625 | |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 3626 | if (dcbe->type == DCB_OUTPUT_DP) { |
| 3627 | struct nvkm_i2c_aux *aux = |
| 3628 | nvkm_i2c_aux_find(i2c, dcbe->i2c_index); |
| 3629 | if (aux) { |
Ben Skeggs | df8dc97 | 2017-03-01 09:42:04 +1000 | [diff] [blame] | 3630 | nv_encoder->i2c = &nv_connector->aux.ddc; |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 3631 | nv_encoder->aux = aux; |
| 3632 | } |
Ben Skeggs | 52aa30f | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3633 | |
| 3634 | /*TODO: Use DP Info Table to check for support. */ |
| 3635 | if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) { |
| 3636 | ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16, |
| 3637 | nv_connector->base.base.id, |
| 3638 | &nv_encoder->dp.mstm); |
| 3639 | if (ret) |
| 3640 | return ret; |
| 3641 | } |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 3642 | } else { |
| 3643 | struct nvkm_i2c_bus *bus = |
| 3644 | nvkm_i2c_bus_find(i2c, dcbe->i2c_index); |
| 3645 | if (bus) |
| 3646 | nv_encoder->i2c = &bus->i2c; |
| 3647 | } |
| 3648 | |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 3649 | return 0; |
| 3650 | } |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 3651 | |
| 3652 | /****************************************************************************** |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3653 | * PIOR |
| 3654 | *****************************************************************************/ |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3655 | static void |
| 3656 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) |
| 3657 | { |
| 3658 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 3659 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
Ben Skeggs | 67cb49c | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3660 | struct { |
| 3661 | struct nv50_disp_mthd_v1 base; |
| 3662 | struct nv50_disp_pior_pwr_v0 pwr; |
| 3663 | } args = { |
| 3664 | .base.version = 1, |
| 3665 | .base.method = NV50_DISP_MTHD_V1_PIOR_PWR, |
| 3666 | .base.hasht = nv_encoder->dcb->hasht, |
| 3667 | .base.hashm = nv_encoder->dcb->hashm, |
| 3668 | .pwr.state = mode == DRM_MODE_DPMS_ON, |
| 3669 | .pwr.type = nv_encoder->dcb->type, |
| 3670 | }; |
| 3671 | |
| 3672 | nvif_mthd(disp->disp, 0, &args, sizeof(args)); |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3673 | } |
| 3674 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3675 | static int |
| 3676 | nv50_pior_atomic_check(struct drm_encoder *encoder, |
| 3677 | struct drm_crtc_state *crtc_state, |
| 3678 | struct drm_connector_state *conn_state) |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3679 | { |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3680 | int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state); |
| 3681 | if (ret) |
| 3682 | return ret; |
| 3683 | crtc_state->adjusted_mode.clock *= 2; |
| 3684 | return 0; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3685 | } |
| 3686 | |
| 3687 | static void |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3688 | nv50_pior_disable(struct drm_encoder *encoder) |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3689 | { |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3690 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 3691 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
| 3692 | const int or = nv_encoder->or; |
| 3693 | u32 *push; |
| 3694 | |
| 3695 | if (nv_encoder->crtc) { |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3696 | push = evo_wait(mast, 4); |
| 3697 | if (push) { |
| 3698 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
| 3699 | evo_mthd(push, 0x0700 + (or * 0x040), 1); |
| 3700 | evo_data(push, 0x00000000); |
| 3701 | } |
| 3702 | evo_kick(push, mast); |
| 3703 | } |
| 3704 | } |
| 3705 | |
| 3706 | nv_encoder->crtc = NULL; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3707 | } |
| 3708 | |
| 3709 | static void |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3710 | nv50_pior_enable(struct drm_encoder *encoder) |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3711 | { |
| 3712 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
| 3713 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
| 3714 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); |
| 3715 | struct nouveau_connector *nv_connector; |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3716 | struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3717 | u8 owner = 1 << nv_crtc->index; |
| 3718 | u8 proto, depth; |
| 3719 | u32 *push; |
| 3720 | |
| 3721 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
| 3722 | switch (nv_connector->base.display_info.bpc) { |
| 3723 | case 10: depth = 0x6; break; |
| 3724 | case 8: depth = 0x5; break; |
| 3725 | case 6: depth = 0x2; break; |
| 3726 | default: depth = 0x0; break; |
| 3727 | } |
| 3728 | |
| 3729 | switch (nv_encoder->dcb->type) { |
| 3730 | case DCB_OUTPUT_TMDS: |
| 3731 | case DCB_OUTPUT_DP: |
| 3732 | proto = 0x0; |
| 3733 | break; |
| 3734 | default: |
Ben Skeggs | af7db03 | 2016-03-03 12:56:33 +1000 | [diff] [blame] | 3735 | BUG(); |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3736 | break; |
| 3737 | } |
| 3738 | |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3739 | push = evo_wait(mast, 8); |
| 3740 | if (push) { |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 3741 | if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3742 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
| 3743 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 3744 | ctrl |= 0x00001000; |
| 3745 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 3746 | ctrl |= 0x00002000; |
| 3747 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); |
| 3748 | evo_data(push, ctrl); |
| 3749 | } |
| 3750 | |
| 3751 | evo_kick(push, mast); |
| 3752 | } |
| 3753 | |
| 3754 | nv_encoder->crtc = encoder->crtc; |
| 3755 | } |
| 3756 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3757 | static const struct drm_encoder_helper_funcs |
| 3758 | nv50_pior_help = { |
| 3759 | .dpms = nv50_pior_dpms, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3760 | .atomic_check = nv50_pior_atomic_check, |
| 3761 | .enable = nv50_pior_enable, |
| 3762 | .disable = nv50_pior_disable, |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3763 | }; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3764 | |
| 3765 | static void |
| 3766 | nv50_pior_destroy(struct drm_encoder *encoder) |
| 3767 | { |
| 3768 | drm_encoder_cleanup(encoder); |
| 3769 | kfree(encoder); |
| 3770 | } |
| 3771 | |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3772 | static const struct drm_encoder_funcs |
| 3773 | nv50_pior_func = { |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3774 | .destroy = nv50_pior_destroy, |
| 3775 | }; |
| 3776 | |
| 3777 | static int |
| 3778 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) |
| 3779 | { |
Ben Skeggs | df8dc97 | 2017-03-01 09:42:04 +1000 | [diff] [blame] | 3780 | struct nouveau_connector *nv_connector = nouveau_connector(connector); |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3781 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 3782 | struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device); |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 3783 | struct nvkm_i2c_bus *bus = NULL; |
| 3784 | struct nvkm_i2c_aux *aux = NULL; |
| 3785 | struct i2c_adapter *ddc; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3786 | struct nouveau_encoder *nv_encoder; |
| 3787 | struct drm_encoder *encoder; |
| 3788 | int type; |
| 3789 | |
| 3790 | switch (dcbe->type) { |
| 3791 | case DCB_OUTPUT_TMDS: |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 3792 | bus = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev)); |
| 3793 | ddc = bus ? &bus->i2c : NULL; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3794 | type = DRM_MODE_ENCODER_TMDS; |
| 3795 | break; |
| 3796 | case DCB_OUTPUT_DP: |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 3797 | aux = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev)); |
Ben Skeggs | df8dc97 | 2017-03-01 09:42:04 +1000 | [diff] [blame] | 3798 | ddc = aux ? &nv_connector->aux.ddc : NULL; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3799 | type = DRM_MODE_ENCODER_TMDS; |
| 3800 | break; |
| 3801 | default: |
| 3802 | return -ENODEV; |
| 3803 | } |
| 3804 | |
| 3805 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); |
| 3806 | if (!nv_encoder) |
| 3807 | return -ENOMEM; |
| 3808 | nv_encoder->dcb = dcbe; |
| 3809 | nv_encoder->or = ffs(dcbe->or) - 1; |
| 3810 | nv_encoder->i2c = ddc; |
Ben Skeggs | 2aa5eac | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 3811 | nv_encoder->aux = aux; |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3812 | |
| 3813 | encoder = to_drm_encoder(nv_encoder); |
| 3814 | encoder->possible_crtcs = dcbe->heads; |
| 3815 | encoder->possible_clones = 0; |
Ben Skeggs | 5a223da | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3816 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, |
| 3817 | "pior-%04x-%04x", dcbe->hasht, dcbe->hashm); |
Ben Skeggs | f20c665 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3818 | drm_encoder_helper_add(encoder, &nv50_pior_help); |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 3819 | |
| 3820 | drm_mode_connector_attach_encoder(connector, encoder); |
| 3821 | return 0; |
| 3822 | } |
| 3823 | |
| 3824 | /****************************************************************************** |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3825 | * Atomic |
| 3826 | *****************************************************************************/ |
| 3827 | |
| 3828 | static void |
| 3829 | nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock) |
| 3830 | { |
| 3831 | struct nv50_disp *disp = nv50_disp(drm->dev); |
| 3832 | struct nv50_dmac *core = &disp->mast.base; |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3833 | struct nv50_mstm *mstm; |
| 3834 | struct drm_encoder *encoder; |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3835 | u32 *push; |
| 3836 | |
| 3837 | NV_ATOMIC(drm, "commit core %08x\n", interlock); |
| 3838 | |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3839 | drm_for_each_encoder(encoder, drm->dev) { |
| 3840 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { |
| 3841 | mstm = nouveau_encoder(encoder)->dp.mstm; |
| 3842 | if (mstm && mstm->modified) |
| 3843 | nv50_mstm_prepare(mstm); |
| 3844 | } |
| 3845 | } |
| 3846 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3847 | if ((push = evo_wait(core, 5))) { |
| 3848 | evo_mthd(push, 0x0084, 1); |
| 3849 | evo_data(push, 0x80000000); |
| 3850 | evo_mthd(push, 0x0080, 2); |
| 3851 | evo_data(push, interlock); |
| 3852 | evo_data(push, 0x00000000); |
| 3853 | nouveau_bo_wr32(disp->sync, 0, 0x00000000); |
| 3854 | evo_kick(push, core); |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 3855 | if (nvif_msec(&drm->client.device, 2000ULL, |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3856 | if (nouveau_bo_rd32(disp->sync, 0)) |
| 3857 | break; |
| 3858 | usleep_range(1, 2); |
| 3859 | ) < 0) |
| 3860 | NV_ERROR(drm, "EVO timeout\n"); |
| 3861 | } |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3862 | |
| 3863 | drm_for_each_encoder(encoder, drm->dev) { |
| 3864 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { |
| 3865 | mstm = nouveau_encoder(encoder)->dp.mstm; |
| 3866 | if (mstm && mstm->modified) |
| 3867 | nv50_mstm_cleanup(mstm); |
| 3868 | } |
| 3869 | } |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3870 | } |
| 3871 | |
| 3872 | static void |
| 3873 | nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) |
| 3874 | { |
| 3875 | struct drm_device *dev = state->dev; |
| 3876 | struct drm_crtc_state *crtc_state; |
| 3877 | struct drm_crtc *crtc; |
| 3878 | struct drm_plane_state *plane_state; |
| 3879 | struct drm_plane *plane; |
| 3880 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 3881 | struct nv50_disp *disp = nv50_disp(dev); |
| 3882 | struct nv50_atom *atom = nv50_atom(state); |
| 3883 | struct nv50_outp_atom *outp, *outt; |
| 3884 | u32 interlock_core = 0; |
| 3885 | u32 interlock_chan = 0; |
| 3886 | int i; |
| 3887 | |
| 3888 | NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable); |
| 3889 | drm_atomic_helper_wait_for_fences(dev, state, false); |
| 3890 | drm_atomic_helper_wait_for_dependencies(state); |
| 3891 | drm_atomic_helper_update_legacy_modeset_state(dev, state); |
| 3892 | |
| 3893 | if (atom->lock_core) |
| 3894 | mutex_lock(&disp->mutex); |
| 3895 | |
| 3896 | /* Disable head(s). */ |
| 3897 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 3898 | struct nv50_head_atom *asyh = nv50_head_atom(crtc->state); |
| 3899 | struct nv50_head *head = nv50_head(crtc); |
| 3900 | |
| 3901 | NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, |
| 3902 | asyh->clr.mask, asyh->set.mask); |
| 3903 | |
| 3904 | if (asyh->clr.mask) { |
| 3905 | nv50_head_flush_clr(head, asyh, atom->flush_disable); |
| 3906 | interlock_core |= 1; |
| 3907 | } |
| 3908 | } |
| 3909 | |
| 3910 | /* Disable plane(s). */ |
| 3911 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 3912 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state); |
| 3913 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 3914 | |
| 3915 | NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name, |
| 3916 | asyw->clr.mask, asyw->set.mask); |
| 3917 | if (!asyw->clr.mask) |
| 3918 | continue; |
| 3919 | |
| 3920 | interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core, |
| 3921 | atom->flush_disable, |
| 3922 | asyw); |
| 3923 | } |
| 3924 | |
| 3925 | /* Disable output path(s). */ |
| 3926 | list_for_each_entry(outp, &atom->outp, head) { |
| 3927 | const struct drm_encoder_helper_funcs *help; |
| 3928 | struct drm_encoder *encoder; |
| 3929 | |
| 3930 | encoder = outp->encoder; |
| 3931 | help = encoder->helper_private; |
| 3932 | |
| 3933 | NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name, |
| 3934 | outp->clr.mask, outp->set.mask); |
| 3935 | |
| 3936 | if (outp->clr.mask) { |
| 3937 | help->disable(encoder); |
| 3938 | interlock_core |= 1; |
| 3939 | if (outp->flush_disable) { |
| 3940 | nv50_disp_atomic_commit_core(drm, interlock_chan); |
| 3941 | interlock_core = 0; |
| 3942 | interlock_chan = 0; |
| 3943 | } |
| 3944 | } |
| 3945 | } |
| 3946 | |
| 3947 | /* Flush disable. */ |
| 3948 | if (interlock_core) { |
| 3949 | if (atom->flush_disable) { |
| 3950 | nv50_disp_atomic_commit_core(drm, interlock_chan); |
| 3951 | interlock_core = 0; |
| 3952 | interlock_chan = 0; |
| 3953 | } |
| 3954 | } |
| 3955 | |
| 3956 | /* Update output path(s). */ |
| 3957 | list_for_each_entry_safe(outp, outt, &atom->outp, head) { |
| 3958 | const struct drm_encoder_helper_funcs *help; |
| 3959 | struct drm_encoder *encoder; |
| 3960 | |
| 3961 | encoder = outp->encoder; |
| 3962 | help = encoder->helper_private; |
| 3963 | |
| 3964 | NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name, |
| 3965 | outp->set.mask, outp->clr.mask); |
| 3966 | |
| 3967 | if (outp->set.mask) { |
| 3968 | help->enable(encoder); |
| 3969 | interlock_core = 1; |
| 3970 | } |
| 3971 | |
| 3972 | list_del(&outp->head); |
| 3973 | kfree(outp); |
| 3974 | } |
| 3975 | |
| 3976 | /* Update head(s). */ |
| 3977 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 3978 | struct nv50_head_atom *asyh = nv50_head_atom(crtc->state); |
| 3979 | struct nv50_head *head = nv50_head(crtc); |
| 3980 | |
| 3981 | NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name, |
| 3982 | asyh->set.mask, asyh->clr.mask); |
| 3983 | |
| 3984 | if (asyh->set.mask) { |
| 3985 | nv50_head_flush_set(head, asyh); |
| 3986 | interlock_core = 1; |
| 3987 | } |
| 3988 | } |
| 3989 | |
Ben Skeggs | 2b50789 | 2017-01-24 09:32:26 +1000 | [diff] [blame] | 3990 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 3991 | if (crtc->state->event) |
| 3992 | drm_crtc_vblank_get(crtc); |
| 3993 | } |
| 3994 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 3995 | /* Update plane(s). */ |
| 3996 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 3997 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state); |
| 3998 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 3999 | |
| 4000 | NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name, |
| 4001 | asyw->set.mask, asyw->clr.mask); |
| 4002 | if ( !asyw->set.mask && |
| 4003 | (!asyw->clr.mask || atom->flush_disable)) |
| 4004 | continue; |
| 4005 | |
| 4006 | interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw); |
| 4007 | } |
| 4008 | |
| 4009 | /* Flush update. */ |
| 4010 | if (interlock_core) { |
| 4011 | if (!interlock_chan && atom->state.legacy_cursor_update) { |
| 4012 | u32 *push = evo_wait(&disp->mast, 2); |
| 4013 | if (push) { |
| 4014 | evo_mthd(push, 0x0080, 1); |
| 4015 | evo_data(push, 0x00000000); |
| 4016 | evo_kick(push, &disp->mast); |
| 4017 | } |
| 4018 | } else { |
| 4019 | nv50_disp_atomic_commit_core(drm, interlock_chan); |
| 4020 | } |
| 4021 | } |
| 4022 | |
| 4023 | if (atom->lock_core) |
| 4024 | mutex_unlock(&disp->mutex); |
| 4025 | |
| 4026 | /* Wait for HW to signal completion. */ |
| 4027 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 4028 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state); |
| 4029 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 4030 | int ret = nv50_wndw_wait_armed(wndw, asyw); |
| 4031 | if (ret) |
| 4032 | NV_ERROR(drm, "%s: timeout\n", plane->name); |
| 4033 | } |
| 4034 | |
| 4035 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
| 4036 | if (crtc->state->event) { |
| 4037 | unsigned long flags; |
Mario Kleiner | bd9f660 | 2016-11-23 07:58:54 +0100 | [diff] [blame] | 4038 | /* Get correct count/ts if racing with vblank irq */ |
| 4039 | drm_accurate_vblank_count(crtc); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4040 | spin_lock_irqsave(&crtc->dev->event_lock, flags); |
| 4041 | drm_crtc_send_vblank_event(crtc, crtc->state->event); |
| 4042 | spin_unlock_irqrestore(&crtc->dev->event_lock, flags); |
| 4043 | crtc->state->event = NULL; |
Ben Skeggs | 2b50789 | 2017-01-24 09:32:26 +1000 | [diff] [blame] | 4044 | drm_crtc_vblank_put(crtc); |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4045 | } |
| 4046 | } |
| 4047 | |
| 4048 | drm_atomic_helper_commit_hw_done(state); |
| 4049 | drm_atomic_helper_cleanup_planes(dev, state); |
| 4050 | drm_atomic_helper_commit_cleanup_done(state); |
| 4051 | drm_atomic_state_put(state); |
| 4052 | } |
| 4053 | |
| 4054 | static void |
| 4055 | nv50_disp_atomic_commit_work(struct work_struct *work) |
| 4056 | { |
| 4057 | struct drm_atomic_state *state = |
| 4058 | container_of(work, typeof(*state), commit_work); |
| 4059 | nv50_disp_atomic_commit_tail(state); |
| 4060 | } |
| 4061 | |
| 4062 | static int |
| 4063 | nv50_disp_atomic_commit(struct drm_device *dev, |
| 4064 | struct drm_atomic_state *state, bool nonblock) |
| 4065 | { |
| 4066 | struct nouveau_drm *drm = nouveau_drm(dev); |
| 4067 | struct nv50_disp *disp = nv50_disp(dev); |
| 4068 | struct drm_plane_state *plane_state; |
| 4069 | struct drm_plane *plane; |
| 4070 | struct drm_crtc *crtc; |
| 4071 | bool active = false; |
| 4072 | int ret, i; |
| 4073 | |
| 4074 | ret = pm_runtime_get_sync(dev->dev); |
| 4075 | if (ret < 0 && ret != -EACCES) |
| 4076 | return ret; |
| 4077 | |
| 4078 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
| 4079 | if (ret) |
| 4080 | goto done; |
| 4081 | |
| 4082 | INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work); |
| 4083 | |
| 4084 | ret = drm_atomic_helper_prepare_planes(dev, state); |
| 4085 | if (ret) |
| 4086 | goto done; |
| 4087 | |
| 4088 | if (!nonblock) { |
| 4089 | ret = drm_atomic_helper_wait_for_fences(dev, state, true); |
| 4090 | if (ret) |
| 4091 | goto done; |
| 4092 | } |
| 4093 | |
| 4094 | for_each_plane_in_state(state, plane, plane_state, i) { |
| 4095 | struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane_state); |
| 4096 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 4097 | if (asyw->set.image) { |
| 4098 | asyw->ntfy.handle = wndw->dmac->sync.handle; |
| 4099 | asyw->ntfy.offset = wndw->ntfy; |
| 4100 | asyw->ntfy.awaken = false; |
| 4101 | asyw->set.ntfy = true; |
| 4102 | nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000); |
| 4103 | wndw->ntfy ^= 0x10; |
| 4104 | } |
| 4105 | } |
| 4106 | |
| 4107 | drm_atomic_helper_swap_state(state, true); |
| 4108 | drm_atomic_state_get(state); |
| 4109 | |
| 4110 | if (nonblock) |
| 4111 | queue_work(system_unbound_wq, &state->commit_work); |
| 4112 | else |
| 4113 | nv50_disp_atomic_commit_tail(state); |
| 4114 | |
| 4115 | drm_for_each_crtc(crtc, dev) { |
| 4116 | if (crtc->state->enable) { |
| 4117 | if (!drm->have_disp_power_ref) { |
| 4118 | drm->have_disp_power_ref = true; |
| 4119 | return ret; |
| 4120 | } |
| 4121 | active = true; |
| 4122 | break; |
| 4123 | } |
| 4124 | } |
| 4125 | |
| 4126 | if (!active && drm->have_disp_power_ref) { |
| 4127 | pm_runtime_put_autosuspend(dev->dev); |
| 4128 | drm->have_disp_power_ref = false; |
| 4129 | } |
| 4130 | |
| 4131 | done: |
| 4132 | pm_runtime_put_autosuspend(dev->dev); |
| 4133 | return ret; |
| 4134 | } |
| 4135 | |
| 4136 | static struct nv50_outp_atom * |
| 4137 | nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder) |
| 4138 | { |
| 4139 | struct nv50_outp_atom *outp; |
| 4140 | |
| 4141 | list_for_each_entry(outp, &atom->outp, head) { |
| 4142 | if (outp->encoder == encoder) |
| 4143 | return outp; |
| 4144 | } |
| 4145 | |
| 4146 | outp = kzalloc(sizeof(*outp), GFP_KERNEL); |
| 4147 | if (!outp) |
| 4148 | return ERR_PTR(-ENOMEM); |
| 4149 | |
| 4150 | list_add(&outp->head, &atom->outp); |
| 4151 | outp->encoder = encoder; |
| 4152 | return outp; |
| 4153 | } |
| 4154 | |
| 4155 | static int |
| 4156 | nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom, |
| 4157 | struct drm_connector *connector) |
| 4158 | { |
| 4159 | struct drm_encoder *encoder = connector->state->best_encoder; |
| 4160 | struct drm_crtc_state *crtc_state; |
| 4161 | struct drm_crtc *crtc; |
| 4162 | struct nv50_outp_atom *outp; |
| 4163 | |
| 4164 | if (!(crtc = connector->state->crtc)) |
| 4165 | return 0; |
| 4166 | |
| 4167 | crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc); |
| 4168 | if (crtc->state->active && drm_atomic_crtc_needs_modeset(crtc_state)) { |
| 4169 | outp = nv50_disp_outp_atomic_add(atom, encoder); |
| 4170 | if (IS_ERR(outp)) |
| 4171 | return PTR_ERR(outp); |
| 4172 | |
| 4173 | if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) { |
| 4174 | outp->flush_disable = true; |
| 4175 | atom->flush_disable = true; |
| 4176 | } |
| 4177 | outp->clr.ctrl = true; |
| 4178 | atom->lock_core = true; |
| 4179 | } |
| 4180 | |
| 4181 | return 0; |
| 4182 | } |
| 4183 | |
| 4184 | static int |
| 4185 | nv50_disp_outp_atomic_check_set(struct nv50_atom *atom, |
| 4186 | struct drm_connector_state *connector_state) |
| 4187 | { |
| 4188 | struct drm_encoder *encoder = connector_state->best_encoder; |
| 4189 | struct drm_crtc_state *crtc_state; |
| 4190 | struct drm_crtc *crtc; |
| 4191 | struct nv50_outp_atom *outp; |
| 4192 | |
| 4193 | if (!(crtc = connector_state->crtc)) |
| 4194 | return 0; |
| 4195 | |
| 4196 | crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc); |
| 4197 | if (crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state)) { |
| 4198 | outp = nv50_disp_outp_atomic_add(atom, encoder); |
| 4199 | if (IS_ERR(outp)) |
| 4200 | return PTR_ERR(outp); |
| 4201 | |
| 4202 | outp->set.ctrl = true; |
| 4203 | atom->lock_core = true; |
| 4204 | } |
| 4205 | |
| 4206 | return 0; |
| 4207 | } |
| 4208 | |
| 4209 | static int |
| 4210 | nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) |
| 4211 | { |
| 4212 | struct nv50_atom *atom = nv50_atom(state); |
| 4213 | struct drm_connector_state *connector_state; |
| 4214 | struct drm_connector *connector; |
| 4215 | int ret, i; |
| 4216 | |
| 4217 | ret = drm_atomic_helper_check(dev, state); |
| 4218 | if (ret) |
| 4219 | return ret; |
| 4220 | |
| 4221 | for_each_connector_in_state(state, connector, connector_state, i) { |
| 4222 | ret = nv50_disp_outp_atomic_check_clr(atom, connector); |
| 4223 | if (ret) |
| 4224 | return ret; |
| 4225 | |
| 4226 | ret = nv50_disp_outp_atomic_check_set(atom, connector_state); |
| 4227 | if (ret) |
| 4228 | return ret; |
| 4229 | } |
| 4230 | |
| 4231 | return 0; |
| 4232 | } |
| 4233 | |
| 4234 | static void |
| 4235 | nv50_disp_atomic_state_clear(struct drm_atomic_state *state) |
| 4236 | { |
| 4237 | struct nv50_atom *atom = nv50_atom(state); |
| 4238 | struct nv50_outp_atom *outp, *outt; |
| 4239 | |
| 4240 | list_for_each_entry_safe(outp, outt, &atom->outp, head) { |
| 4241 | list_del(&outp->head); |
| 4242 | kfree(outp); |
| 4243 | } |
| 4244 | |
| 4245 | drm_atomic_state_default_clear(state); |
| 4246 | } |
| 4247 | |
| 4248 | static void |
| 4249 | nv50_disp_atomic_state_free(struct drm_atomic_state *state) |
| 4250 | { |
| 4251 | struct nv50_atom *atom = nv50_atom(state); |
| 4252 | drm_atomic_state_default_release(&atom->state); |
| 4253 | kfree(atom); |
| 4254 | } |
| 4255 | |
| 4256 | static struct drm_atomic_state * |
| 4257 | nv50_disp_atomic_state_alloc(struct drm_device *dev) |
| 4258 | { |
| 4259 | struct nv50_atom *atom; |
| 4260 | if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) || |
| 4261 | drm_atomic_state_init(dev, &atom->state) < 0) { |
| 4262 | kfree(atom); |
| 4263 | return NULL; |
| 4264 | } |
| 4265 | INIT_LIST_HEAD(&atom->outp); |
| 4266 | return &atom->state; |
| 4267 | } |
| 4268 | |
| 4269 | static const struct drm_mode_config_funcs |
| 4270 | nv50_disp_func = { |
| 4271 | .fb_create = nouveau_user_framebuffer_create, |
| 4272 | .output_poll_changed = nouveau_fbcon_output_poll_changed, |
| 4273 | .atomic_check = nv50_disp_atomic_check, |
| 4274 | .atomic_commit = nv50_disp_atomic_commit, |
| 4275 | .atomic_state_alloc = nv50_disp_atomic_state_alloc, |
| 4276 | .atomic_state_clear = nv50_disp_atomic_state_clear, |
| 4277 | .atomic_state_free = nv50_disp_atomic_state_free, |
| 4278 | }; |
| 4279 | |
| 4280 | /****************************************************************************** |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4281 | * Init |
| 4282 | *****************************************************************************/ |
Ben Skeggs | ab0af55 | 2014-08-10 04:10:19 +1000 | [diff] [blame] | 4283 | |
Ben Skeggs | 2a44e49 | 2011-11-09 11:36:33 +1000 | [diff] [blame] | 4284 | void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4285 | nv50_display_fini(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4286 | { |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4287 | struct nouveau_encoder *nv_encoder; |
| 4288 | struct drm_encoder *encoder; |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4289 | struct drm_plane *plane; |
| 4290 | |
| 4291 | drm_for_each_plane(plane, dev) { |
| 4292 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 4293 | if (plane->funcs != &nv50_wndw) |
| 4294 | continue; |
| 4295 | nv50_wndw_fini(wndw); |
| 4296 | } |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4297 | |
| 4298 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 4299 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { |
| 4300 | nv_encoder = nouveau_encoder(encoder); |
| 4301 | nv50_mstm_fini(nv_encoder->dp.mstm); |
| 4302 | } |
| 4303 | } |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4304 | } |
| 4305 | |
| 4306 | int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4307 | nv50_display_init(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4308 | { |
Ben Skeggs | 354d350 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4309 | struct drm_encoder *encoder; |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4310 | struct drm_plane *plane; |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 4311 | struct drm_crtc *crtc; |
| 4312 | u32 *push; |
| 4313 | |
| 4314 | push = evo_wait(nv50_mast(dev), 32); |
| 4315 | if (!push) |
| 4316 | return -EBUSY; |
| 4317 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 4318 | evo_mthd(push, 0x0088, 1); |
Ben Skeggs | f45f55c | 2014-08-10 04:10:23 +1000 | [diff] [blame] | 4319 | evo_data(push, nv50_mast(dev)->base.sync.handle); |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 4320 | evo_kick(push, nv50_mast(dev)); |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4321 | |
Ben Skeggs | 354d350 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4322 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 4323 | if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) { |
| 4324 | const struct drm_encoder_helper_funcs *help; |
| 4325 | struct nouveau_encoder *nv_encoder; |
| 4326 | |
| 4327 | nv_encoder = nouveau_encoder(encoder); |
Ben Skeggs | 354d350 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4328 | help = encoder->helper_private; |
| 4329 | if (help && help->dpms) |
| 4330 | help->dpms(encoder, DRM_MODE_DPMS_ON); |
Ben Skeggs | f479c0b | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4331 | |
| 4332 | nv50_mstm_init(nv_encoder->dp.mstm); |
Ben Skeggs | 354d350 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4333 | } |
| 4334 | } |
| 4335 | |
Ben Skeggs | e1ef6b4 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4336 | drm_for_each_crtc(crtc, dev) { |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4337 | nv50_head_lut_load(crtc); |
Ben Skeggs | e1ef6b4 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4338 | } |
| 4339 | |
Ben Skeggs | 973f10c | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4340 | drm_for_each_plane(plane, dev) { |
| 4341 | struct nv50_wndw *wndw = nv50_wndw(plane); |
| 4342 | if (plane->funcs != &nv50_wndw) |
| 4343 | continue; |
| 4344 | nv50_wndw_init(wndw); |
| 4345 | } |
| 4346 | |
Ben Skeggs | 9f9bdaa | 2013-03-02 13:21:31 +1000 | [diff] [blame] | 4347 | return 0; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4348 | } |
| 4349 | |
| 4350 | void |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4351 | nv50_display_destroy(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4352 | { |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4353 | struct nv50_disp *disp = nv50_disp(dev); |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4354 | |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 4355 | nv50_dmac_destroy(&disp->mast.base, disp->disp); |
Ben Skeggs | bdb8c21 | 2011-11-12 01:30:24 +1000 | [diff] [blame] | 4356 | |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 4357 | nouveau_bo_unmap(disp->sync); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 4358 | if (disp->sync) |
| 4359 | nouveau_bo_unpin(disp->sync); |
Ben Skeggs | 816af2f | 2011-11-16 15:48:48 +1000 | [diff] [blame] | 4360 | nouveau_bo_ref(NULL, &disp->sync); |
Ben Skeggs | 51beb42 | 2011-07-05 10:33:08 +1000 | [diff] [blame] | 4361 | |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 4362 | nouveau_display(dev)->priv = NULL; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4363 | kfree(disp); |
| 4364 | } |
| 4365 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4366 | MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)"); |
| 4367 | static int nouveau_atomic = 0; |
| 4368 | module_param_named(atomic, nouveau_atomic, int, 0400); |
| 4369 | |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4370 | int |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4371 | nv50_display_create(struct drm_device *dev) |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4372 | { |
Ben Skeggs | 1167c6b | 2016-05-18 13:57:42 +1000 | [diff] [blame] | 4373 | struct nvif_device *device = &nouveau_drm(dev)->client.device; |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 4374 | struct nouveau_drm *drm = nouveau_drm(dev); |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 4375 | struct dcb_table *dcb = &drm->vbios.dcb; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 4376 | struct drm_connector *connector, *tmp; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4377 | struct nv50_disp *disp; |
Ben Skeggs | cb75d97 | 2012-07-11 10:44:20 +1000 | [diff] [blame] | 4378 | struct dcb_output *dcbe; |
Ben Skeggs | 7c5f6a8 | 2012-03-04 16:25:59 +1000 | [diff] [blame] | 4379 | int crtcs, ret, i; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4380 | |
| 4381 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); |
| 4382 | if (!disp) |
| 4383 | return -ENOMEM; |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 4384 | |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4385 | mutex_init(&disp->mutex); |
| 4386 | |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 4387 | nouveau_display(dev)->priv = disp; |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4388 | nouveau_display(dev)->dtor = nv50_display_destroy; |
| 4389 | nouveau_display(dev)->init = nv50_display_init; |
| 4390 | nouveau_display(dev)->fini = nv50_display_fini; |
Ben Skeggs | 0ad7286 | 2014-08-10 04:10:22 +1000 | [diff] [blame] | 4391 | disp->disp = &nouveau_display(dev)->disp; |
Ben Skeggs | 839ca90 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4392 | dev->mode_config.funcs = &nv50_disp_func; |
| 4393 | if (nouveau_atomic) |
| 4394 | dev->driver->driver_features |= DRIVER_ATOMIC; |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4395 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 4396 | /* small shared memory area we use for notifiers and semaphores */ |
Ben Skeggs | bab7cc1 | 2016-05-24 17:26:48 +1000 | [diff] [blame] | 4397 | ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
Maarten Lankhorst | bb6178b | 2014-01-09 11:03:15 +0100 | [diff] [blame] | 4398 | 0, 0x0000, NULL, NULL, &disp->sync); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 4399 | if (!ret) { |
Ben Skeggs | 547ad07 | 2014-11-10 12:35:06 +1000 | [diff] [blame] | 4400 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 4401 | if (!ret) { |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 4402 | ret = nouveau_bo_map(disp->sync); |
Marcin Slusarz | 04c8c21 | 2012-11-25 23:04:23 +0100 | [diff] [blame] | 4403 | if (ret) |
| 4404 | nouveau_bo_unpin(disp->sync); |
| 4405 | } |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 4406 | if (ret) |
| 4407 | nouveau_bo_ref(NULL, &disp->sync); |
| 4408 | } |
| 4409 | |
| 4410 | if (ret) |
| 4411 | goto out; |
| 4412 | |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 4413 | /* allocate master evo channel */ |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 4414 | ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset, |
Ben Skeggs | 410f3ec | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 4415 | &disp->mast); |
Ben Skeggs | b5a794b | 2012-10-16 14:18:32 +1000 | [diff] [blame] | 4416 | if (ret) |
| 4417 | goto out; |
| 4418 | |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 4419 | /* create crtc objects to represent the hw heads */ |
Ben Skeggs | 648d4df | 2014-08-10 04:10:27 +1000 | [diff] [blame] | 4420 | if (disp->disp->oclass >= GF110_DISP) |
Ben Skeggs | a01ca78 | 2015-08-20 14:54:15 +1000 | [diff] [blame] | 4421 | crtcs = nvif_rd32(&device->object, 0x022448); |
Ben Skeggs | 63718a0 | 2012-11-16 11:44:14 +1000 | [diff] [blame] | 4422 | else |
| 4423 | crtcs = 2; |
| 4424 | |
Ben Skeggs | 7c5f6a8 | 2012-03-04 16:25:59 +1000 | [diff] [blame] | 4425 | for (i = 0; i < crtcs; i++) { |
Ben Skeggs | 9bfdee9 | 2016-11-04 17:20:36 +1000 | [diff] [blame] | 4426 | ret = nv50_head_create(dev, i); |
Ben Skeggs | 438d99e | 2011-07-05 16:48:06 +1000 | [diff] [blame] | 4427 | if (ret) |
| 4428 | goto out; |
| 4429 | } |
| 4430 | |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 4431 | /* create encoder/connector objects based on VBIOS DCB table */ |
| 4432 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { |
| 4433 | connector = nouveau_connector_create(dev, dcbe->connector); |
| 4434 | if (IS_ERR(connector)) |
| 4435 | continue; |
| 4436 | |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 4437 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
| 4438 | switch (dcbe->type) { |
| 4439 | case DCB_OUTPUT_TMDS: |
| 4440 | case DCB_OUTPUT_LVDS: |
| 4441 | case DCB_OUTPUT_DP: |
| 4442 | ret = nv50_sor_create(connector, dcbe); |
| 4443 | break; |
| 4444 | case DCB_OUTPUT_ANALOG: |
| 4445 | ret = nv50_dac_create(connector, dcbe); |
| 4446 | break; |
| 4447 | default: |
| 4448 | ret = -ENODEV; |
| 4449 | break; |
| 4450 | } |
| 4451 | } else { |
| 4452 | ret = nv50_pior_create(connector, dcbe); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 4453 | } |
| 4454 | |
Ben Skeggs | eb6313a | 2013-02-11 09:52:58 +1000 | [diff] [blame] | 4455 | if (ret) { |
| 4456 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", |
| 4457 | dcbe->location, dcbe->type, |
| 4458 | ffs(dcbe->or) - 1, ret); |
Ben Skeggs | 94f54f5 | 2013-03-05 22:26:06 +1000 | [diff] [blame] | 4459 | ret = 0; |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 4460 | } |
| 4461 | } |
| 4462 | |
| 4463 | /* cull any connectors we created that don't have an encoder */ |
| 4464 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { |
| 4465 | if (connector->encoder_ids[0]) |
| 4466 | continue; |
| 4467 | |
Ben Skeggs | 77145f1 | 2012-07-31 16:16:21 +1000 | [diff] [blame] | 4468 | NV_WARN(drm, "%s has no encoders, removing\n", |
Jani Nikula | 8c6c361 | 2014-06-03 14:56:18 +0300 | [diff] [blame] | 4469 | connector->name); |
Ben Skeggs | 83fc083 | 2011-07-05 13:08:40 +1000 | [diff] [blame] | 4470 | connector->funcs->destroy(connector); |
| 4471 | } |
| 4472 | |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4473 | out: |
| 4474 | if (ret) |
Ben Skeggs | e225f44 | 2012-11-21 14:40:21 +1000 | [diff] [blame] | 4475 | nv50_display_destroy(dev); |
Ben Skeggs | 26f6d88 | 2011-07-04 16:25:18 +1000 | [diff] [blame] | 4476 | return ret; |
| 4477 | } |