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Ben Dooks51022cf2010-01-06 11:18:44 +09001/* arch/arm/plat-samsung/irq-uart.c
2 * originally part of arch/arm/plat-s3c64xx/irq.c
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * Samsung- UART Interrupt handling
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/serial_core.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21
22#include <mach/map.h>
23#include <plat/irq-uart.h>
24#include <plat/regs-serial.h>
25#include <plat/cpu.h>
26
27/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
28 * are consecutive when looking up the interrupt in the demux routines.
29 */
Ben Dooks51022cf2010-01-06 11:18:44 +090030static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
31{
Lennert Buytenhek04ea1cc2010-12-14 22:55:57 +010032 struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
Ben Dooks51022cf2010-01-06 11:18:44 +090033 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
34 int base = uirq->base_irq;
35
36 if (pend & (1 << 0))
37 generic_handle_irq(base);
38 if (pend & (1 << 1))
39 generic_handle_irq(base + 1);
40 if (pend & (1 << 2))
41 generic_handle_irq(base + 2);
42 if (pend & (1 << 3))
43 generic_handle_irq(base + 3);
44}
45
Ben Dooks51022cf2010-01-06 11:18:44 +090046static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
47{
Ben Dooks51022cf2010-01-06 11:18:44 +090048 void __iomem *reg_base = uirq->regs;
Thomas Gleixnerbd7e3882011-05-09 10:10:22 +020049 struct irq_chip_generic *gc;
50 struct irq_chip_type *ct;
Ben Dooks51022cf2010-01-06 11:18:44 +090051
52 /* mask all interrupts at the start. */
53 __raw_writel(0xf, reg_base + S3C64XX_UINTM);
54
Thomas Gleixnerbd7e3882011-05-09 10:10:22 +020055 gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
56 handle_level_irq);
57 ct = gc->chip_types;
58 ct->chip.irq_ack = irq_gc_ack;
59 ct->chip.irq_mask = irq_gc_mask_set_bit;
60 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
61 ct->regs.ack = S3C64XX_UINTP;
62 ct->regs.mask = S3C64XX_UINTM;
63 irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
64 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
Ben Dooks51022cf2010-01-06 11:18:44 +090065
Thomas Gleixner7222f392011-03-24 12:36:46 +010066 irq_set_handler_data(uirq->parent_irq, uirq);
67 irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
Ben Dooks51022cf2010-01-06 11:18:44 +090068}
69
70/**
71 * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing
72 * @irq: The interrupt data for registering
73 * @nr_irqs: The number of interrupt descriptions in @irq.
74 *
75 * Register the UART interrupts specified by @irq including the demuxing
76 * routines. This supports the S3C6400 and newer style of devices.
77 */
78void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs)
79{
80 for (; nr_irqs > 0; nr_irqs--, irq++)
81 s3c_init_uart_irq(irq);
82}