Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Author: Jani Nikula <jani.nikula@intel.com> |
| 24 | */ |
| 25 | |
| 26 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 27 | #include <drm/drm_atomic_helper.h> |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 28 | #include <drm/drm_crtc.h> |
| 29 | #include <drm/drm_edid.h> |
| 30 | #include <drm/i915_drm.h> |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 31 | #include <drm/drm_panel.h> |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 32 | #include <drm/drm_mipi_dsi.h> |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 33 | #include <linux/slab.h> |
| 34 | #include "i915_drv.h" |
| 35 | #include "intel_drv.h" |
| 36 | #include "intel_dsi.h" |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 37 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 38 | static const struct { |
| 39 | u16 panel_id; |
| 40 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); |
| 41 | } intel_dsi_drivers[] = { |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 42 | { |
| 43 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 44 | .init = vbt_panel_init, |
Shobhit Kumar | 2ab8b45 | 2014-05-23 21:35:27 +0530 | [diff] [blame] | 45 | }, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 46 | }; |
| 47 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 48 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
Jani Nikula | 3b1808b | 2015-01-16 14:27:18 +0200 | [diff] [blame] | 49 | { |
| 50 | struct drm_encoder *encoder = &intel_dsi->base.base; |
| 51 | struct drm_device *dev = encoder->dev; |
| 52 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 3b1808b | 2015-01-16 14:27:18 +0200 | [diff] [blame] | 53 | u32 mask; |
| 54 | |
| 55 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | |
| 56 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; |
| 57 | |
| 58 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) |
| 59 | DRM_ERROR("DPI FIFOs are not empty\n"); |
| 60 | } |
| 61 | |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 62 | static void write_data(struct drm_i915_private *dev_priv, u32 reg, |
| 63 | const u8 *data, u32 len) |
| 64 | { |
| 65 | u32 i, j; |
| 66 | |
| 67 | for (i = 0; i < len; i += 4) { |
| 68 | u32 val = 0; |
| 69 | |
| 70 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
| 71 | val |= *data++ << 8 * j; |
| 72 | |
| 73 | I915_WRITE(reg, val); |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | static void read_data(struct drm_i915_private *dev_priv, u32 reg, |
| 78 | u8 *data, u32 len) |
| 79 | { |
| 80 | u32 i, j; |
| 81 | |
| 82 | for (i = 0; i < len; i += 4) { |
| 83 | u32 val = I915_READ(reg); |
| 84 | |
| 85 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
| 86 | *data++ = val >> 8 * j; |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, |
| 91 | const struct mipi_dsi_msg *msg) |
| 92 | { |
| 93 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); |
| 94 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; |
| 95 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 96 | enum port port = intel_dsi_host->port; |
| 97 | struct mipi_dsi_packet packet; |
| 98 | ssize_t ret; |
| 99 | const u8 *header, *data; |
| 100 | u32 data_reg, data_mask, ctrl_reg, ctrl_mask; |
| 101 | |
| 102 | ret = mipi_dsi_create_packet(&packet, msg); |
| 103 | if (ret < 0) |
| 104 | return ret; |
| 105 | |
| 106 | header = packet.header; |
| 107 | data = packet.payload; |
| 108 | |
| 109 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { |
| 110 | data_reg = MIPI_LP_GEN_DATA(port); |
| 111 | data_mask = LP_DATA_FIFO_FULL; |
| 112 | ctrl_reg = MIPI_LP_GEN_CTRL(port); |
| 113 | ctrl_mask = LP_CTRL_FIFO_FULL; |
| 114 | } else { |
| 115 | data_reg = MIPI_HS_GEN_DATA(port); |
| 116 | data_mask = HS_DATA_FIFO_FULL; |
| 117 | ctrl_reg = MIPI_HS_GEN_CTRL(port); |
| 118 | ctrl_mask = HS_CTRL_FIFO_FULL; |
| 119 | } |
| 120 | |
| 121 | /* note: this is never true for reads */ |
| 122 | if (packet.payload_length) { |
| 123 | |
| 124 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) |
| 125 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
| 126 | |
| 127 | write_data(dev_priv, data_reg, packet.payload, |
| 128 | packet.payload_length); |
| 129 | } |
| 130 | |
| 131 | if (msg->rx_len) { |
| 132 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); |
| 133 | } |
| 134 | |
| 135 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { |
| 136 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
| 137 | } |
| 138 | |
| 139 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); |
| 140 | |
| 141 | /* ->rx_len is set only for reads */ |
| 142 | if (msg->rx_len) { |
| 143 | data_mask = GEN_READ_DATA_AVAIL; |
| 144 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) |
| 145 | DRM_ERROR("Timeout waiting for read data.\n"); |
| 146 | |
| 147 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); |
| 148 | } |
| 149 | |
| 150 | /* XXX: fix for reads and writes */ |
| 151 | return 4 + packet.payload_length; |
| 152 | } |
| 153 | |
| 154 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, |
| 155 | struct mipi_dsi_device *dsi) |
| 156 | { |
| 157 | return 0; |
| 158 | } |
| 159 | |
| 160 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, |
| 161 | struct mipi_dsi_device *dsi) |
| 162 | { |
| 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { |
| 167 | .attach = intel_dsi_host_attach, |
| 168 | .detach = intel_dsi_host_detach, |
| 169 | .transfer = intel_dsi_host_transfer, |
| 170 | }; |
| 171 | |
| 172 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, |
| 173 | enum port port) |
| 174 | { |
| 175 | struct intel_dsi_host *host; |
| 176 | struct mipi_dsi_device *device; |
| 177 | |
| 178 | host = kzalloc(sizeof(*host), GFP_KERNEL); |
| 179 | if (!host) |
| 180 | return NULL; |
| 181 | |
| 182 | host->base.ops = &intel_dsi_host_ops; |
| 183 | host->intel_dsi = intel_dsi; |
| 184 | host->port = port; |
| 185 | |
| 186 | /* |
| 187 | * We should call mipi_dsi_host_register(&host->base) here, but we don't |
| 188 | * have a host->dev, and we don't have OF stuff either. So just use the |
| 189 | * dsi framework as a library and hope for the best. Create the dsi |
| 190 | * devices by ourselves here too. Need to be careful though, because we |
| 191 | * don't initialize any of the driver model devices here. |
| 192 | */ |
| 193 | device = kzalloc(sizeof(*device), GFP_KERNEL); |
| 194 | if (!device) { |
| 195 | kfree(host); |
| 196 | return NULL; |
| 197 | } |
| 198 | |
| 199 | device->host = &host->base; |
| 200 | host->device = device; |
| 201 | |
| 202 | return host; |
| 203 | } |
| 204 | |
Jani Nikula | a2581a9 | 2015-01-16 14:27:26 +0200 | [diff] [blame] | 205 | /* |
| 206 | * send a video mode command |
| 207 | * |
| 208 | * XXX: commands with data in MIPI_DPI_DATA? |
| 209 | */ |
| 210 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, |
| 211 | enum port port) |
| 212 | { |
| 213 | struct drm_encoder *encoder = &intel_dsi->base.base; |
| 214 | struct drm_device *dev = encoder->dev; |
| 215 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 216 | u32 mask; |
| 217 | |
| 218 | /* XXX: pipe, hs */ |
| 219 | if (hs) |
| 220 | cmd &= ~DPI_LP_MODE; |
| 221 | else |
| 222 | cmd |= DPI_LP_MODE; |
| 223 | |
| 224 | /* clear bit */ |
| 225 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); |
| 226 | |
| 227 | /* XXX: old code skips write if control unchanged */ |
| 228 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) |
| 229 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); |
| 230 | |
| 231 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); |
| 232 | |
| 233 | mask = SPL_PKT_SENT_INTERRUPT; |
| 234 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) |
| 235 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
| 236 | |
| 237 | return 0; |
| 238 | } |
| 239 | |
Shobhit Kumar | e9fe51c | 2013-12-10 12:14:55 +0530 | [diff] [blame] | 240 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
Shobhit Kumar | 4ce8c9a | 2013-08-27 15:12:24 +0300 | [diff] [blame] | 241 | { |
| 242 | mutex_lock(&dev_priv->dpio_lock); |
| 243 | |
Shobhit Kumar | e9fe51c | 2013-12-10 12:14:55 +0530 | [diff] [blame] | 244 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
| 245 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
| 246 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
| 247 | udelay(150); |
| 248 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
| 249 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
Shobhit Kumar | 4ce8c9a | 2013-08-27 15:12:24 +0300 | [diff] [blame] | 250 | |
| 251 | mutex_unlock(&dev_priv->dpio_lock); |
Shobhit Kumar | 4ce8c9a | 2013-08-27 15:12:24 +0300 | [diff] [blame] | 252 | } |
| 253 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 254 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
| 255 | { |
Shobhit Kumar | dfba2e2 | 2014-04-14 11:18:24 +0530 | [diff] [blame] | 256 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
| 260 | { |
Shobhit Kumar | dfba2e2 | 2014-04-14 11:18:24 +0530 | [diff] [blame] | 261 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) |
| 265 | { |
| 266 | DRM_DEBUG_KMS("\n"); |
| 267 | } |
| 268 | |
| 269 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 270 | struct intel_crtc_state *config) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 271 | { |
| 272 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
| 273 | base); |
| 274 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
| 275 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 276 | struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 277 | |
| 278 | DRM_DEBUG_KMS("\n"); |
| 279 | |
| 280 | if (fixed_mode) |
| 281 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
| 282 | |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 283 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
| 284 | adjusted_mode->flags = 0; |
| 285 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 286 | return true; |
| 287 | } |
| 288 | |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 289 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
| 290 | { |
| 291 | struct drm_device *dev = encoder->base.dev; |
| 292 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 293 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 294 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 295 | enum port port; |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 296 | u32 temp; |
| 297 | |
Gaurav K Singh | a9da9bc | 2014-12-05 14:13:41 +0530 | [diff] [blame] | 298 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
| 299 | temp = I915_READ(VLV_CHICKEN_3); |
| 300 | temp &= ~PIXEL_OVERLAP_CNT_MASK | |
| 301 | intel_dsi->pixel_overlap << |
| 302 | PIXEL_OVERLAP_CNT_SHIFT; |
| 303 | I915_WRITE(VLV_CHICKEN_3, temp); |
| 304 | } |
| 305 | |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 306 | for_each_dsi_port(port, intel_dsi->ports) { |
| 307 | temp = I915_READ(MIPI_PORT_CTRL(port)); |
| 308 | temp &= ~LANE_CONFIGURATION_MASK; |
| 309 | temp &= ~DUAL_LINK_MODE_MASK; |
| 310 | |
| 311 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { |
| 312 | temp |= (intel_dsi->dual_link - 1) |
| 313 | << DUAL_LINK_MODE_SHIFT; |
| 314 | temp |= intel_crtc->pipe ? |
| 315 | LANE_CONFIGURATION_DUAL_LINK_B : |
| 316 | LANE_CONFIGURATION_DUAL_LINK_A; |
| 317 | } |
| 318 | /* assert ip_tg_enable signal */ |
| 319 | I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); |
| 320 | POSTING_READ(MIPI_PORT_CTRL(port)); |
| 321 | } |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 322 | } |
| 323 | |
| 324 | static void intel_dsi_port_disable(struct intel_encoder *encoder) |
| 325 | { |
| 326 | struct drm_device *dev = encoder->base.dev; |
| 327 | struct drm_i915_private *dev_priv = dev->dev_private; |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 328 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 329 | enum port port; |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 330 | u32 temp; |
| 331 | |
Gaurav K Singh | 369602d | 2014-12-05 14:09:28 +0530 | [diff] [blame] | 332 | for_each_dsi_port(port, intel_dsi->ports) { |
| 333 | /* de-assert ip_tg_enable signal */ |
| 334 | temp = I915_READ(MIPI_PORT_CTRL(port)); |
| 335 | I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); |
| 336 | POSTING_READ(MIPI_PORT_CTRL(port)); |
| 337 | } |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 338 | } |
| 339 | |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 340 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
| 341 | { |
| 342 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 343 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 344 | enum port port; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 345 | u32 val; |
| 346 | |
| 347 | DRM_DEBUG_KMS("\n"); |
| 348 | |
Shobhit Kumar | 2095f9f | 2014-04-09 13:59:30 +0530 | [diff] [blame] | 349 | mutex_lock(&dev_priv->dpio_lock); |
| 350 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
| 351 | * needed everytime after power gate */ |
| 352 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
| 353 | mutex_unlock(&dev_priv->dpio_lock); |
| 354 | |
| 355 | /* bandgap reset is needed after everytime we do power gate */ |
| 356 | band_gap_reset(dev_priv); |
| 357 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 358 | for_each_dsi_port(port, intel_dsi->ports) { |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 359 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 360 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
| 361 | usleep_range(2500, 3000); |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 362 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 363 | val = I915_READ(MIPI_PORT_CTRL(port)); |
Gaurav K Singh | bf344e8 | 2014-12-07 16:13:54 +0530 | [diff] [blame] | 364 | |
| 365 | /* Enable MIPI PHY transparent latch |
| 366 | * Common bit for both MIPI Port A & MIPI Port C |
| 367 | * No similar bit in MIPI Port C reg |
| 368 | */ |
| 369 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 370 | usleep_range(1000, 1500); |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 371 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 372 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
| 373 | usleep_range(2500, 3000); |
| 374 | |
| 375 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); |
| 376 | usleep_range(2500, 3000); |
| 377 | } |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 378 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 379 | |
| 380 | static void intel_dsi_enable(struct intel_encoder *encoder) |
| 381 | { |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 382 | struct drm_device *dev = encoder->base.dev; |
| 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 384 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Jani Nikula | 4934b65 | 2015-01-22 15:01:35 +0200 | [diff] [blame] | 385 | enum port port; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 386 | |
| 387 | DRM_DEBUG_KMS("\n"); |
| 388 | |
Jani Nikula | 4934b65 | 2015-01-22 15:01:35 +0200 | [diff] [blame] | 389 | if (is_cmd_mode(intel_dsi)) { |
| 390 | for_each_dsi_port(port, intel_dsi->ports) |
| 391 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); |
| 392 | } else { |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 393 | msleep(20); /* XXX */ |
Jani Nikula | f03e417 | 2015-01-16 14:27:16 +0200 | [diff] [blame] | 394 | for_each_dsi_port(port, intel_dsi->ports) |
Jani Nikula | a2581a9 | 2015-01-16 14:27:26 +0200 | [diff] [blame] | 395 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 396 | msleep(100); |
| 397 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 398 | drm_panel_enable(intel_dsi->panel); |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 399 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 400 | for_each_dsi_port(port, intel_dsi->ports) |
| 401 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 402 | |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 403 | intel_dsi_port_enable(encoder); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 404 | } |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 405 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 406 | |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 407 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
| 408 | { |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 409 | struct drm_device *dev = encoder->base.dev; |
| 410 | struct drm_i915_private *dev_priv = dev->dev_private; |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 411 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 412 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 413 | enum pipe pipe = intel_crtc->pipe; |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 414 | enum port port; |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 415 | u32 tmp; |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 416 | |
| 417 | DRM_DEBUG_KMS("\n"); |
| 418 | |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 419 | /* Disable DPOunit clock gating, can stall pipe |
| 420 | * and we need DPLL REFA always enabled */ |
| 421 | tmp = I915_READ(DPLL(pipe)); |
| 422 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; |
| 423 | I915_WRITE(DPLL(pipe), tmp); |
| 424 | |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 425 | /* update the hw state for DPLL */ |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 426 | intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | |
Daniel Vetter | 7f3de83 | 2014-07-30 22:34:27 +0200 | [diff] [blame] | 427 | DPLL_REFA_CLK_ENABLE_VLV; |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 428 | |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 429 | tmp = I915_READ(DSPCLK_GATE_D); |
| 430 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; |
| 431 | I915_WRITE(DSPCLK_GATE_D, tmp); |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 432 | |
| 433 | /* put device in ready state */ |
| 434 | intel_dsi_device_ready(encoder); |
| 435 | |
Shobhit Kumar | df38e65 | 2014-04-14 11:18:26 +0530 | [diff] [blame] | 436 | msleep(intel_dsi->panel_on_delay); |
| 437 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 438 | drm_panel_prepare(intel_dsi->panel); |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 439 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 440 | for_each_dsi_port(port, intel_dsi->ports) |
| 441 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 442 | |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 443 | /* Enable port in pre-enable phase itself because as per hw team |
| 444 | * recommendation, port should be enabled befor plane & pipe */ |
| 445 | intel_dsi_enable(encoder); |
| 446 | } |
| 447 | |
| 448 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) |
| 449 | { |
| 450 | DRM_DEBUG_KMS("\n"); |
| 451 | |
| 452 | /* for DSI port enable has to be done before pipe |
| 453 | * and plane enable, so port enable is done in |
| 454 | * pre_enable phase itself unlike other encoders |
| 455 | */ |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 456 | } |
| 457 | |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 458 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
| 459 | { |
| 460 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Jani Nikula | f03e417 | 2015-01-16 14:27:16 +0200 | [diff] [blame] | 461 | enum port port; |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 462 | |
| 463 | DRM_DEBUG_KMS("\n"); |
| 464 | |
| 465 | if (is_vid_mode(intel_dsi)) { |
| 466 | /* Send Shutdown command to the panel in LP mode */ |
Jani Nikula | f03e417 | 2015-01-16 14:27:16 +0200 | [diff] [blame] | 467 | for_each_dsi_port(port, intel_dsi->ports) |
Jani Nikula | a2581a9 | 2015-01-16 14:27:26 +0200 | [diff] [blame] | 468 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 469 | msleep(10); |
| 470 | } |
| 471 | } |
| 472 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 473 | static void intel_dsi_disable(struct intel_encoder *encoder) |
| 474 | { |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 475 | struct drm_device *dev = encoder->base.dev; |
| 476 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 477 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 478 | enum port port; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 479 | u32 temp; |
| 480 | |
| 481 | DRM_DEBUG_KMS("\n"); |
| 482 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 483 | if (is_vid_mode(intel_dsi)) { |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 484 | for_each_dsi_port(port, intel_dsi->ports) |
| 485 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 486 | |
Gaurav K Singh | 5505a24 | 2014-12-04 10:58:47 +0530 | [diff] [blame] | 487 | intel_dsi_port_disable(encoder); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 488 | msleep(2); |
| 489 | } |
| 490 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 491 | for_each_dsi_port(port, intel_dsi->ports) { |
| 492 | /* Panel commands can be sent when clock is in LP11 */ |
| 493 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); |
Shobhit Kumar | 339023e | 2014-04-09 13:59:34 +0530 | [diff] [blame] | 494 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 495 | temp = I915_READ(MIPI_CTRL(port)); |
| 496 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
| 497 | I915_WRITE(MIPI_CTRL(port), temp | |
| 498 | intel_dsi->escape_clk_div << |
| 499 | ESCAPE_CLOCK_DIVIDER_SHIFT); |
Shobhit Kumar | 339023e | 2014-04-09 13:59:34 +0530 | [diff] [blame] | 500 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 501 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
Shobhit Kumar | 339023e | 2014-04-09 13:59:34 +0530 | [diff] [blame] | 502 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 503 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
| 504 | temp &= ~VID_MODE_FORMAT_MASK; |
| 505 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); |
Shobhit Kumar | 339023e | 2014-04-09 13:59:34 +0530 | [diff] [blame] | 506 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 507 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
| 508 | } |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 509 | /* if disable packets are sent before sending shutdown packet then in |
| 510 | * some next enable sequence send turn on packet error is observed */ |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 511 | drm_panel_disable(intel_dsi->panel); |
Shobhit Kumar | 1381308 | 2014-07-12 17:17:22 +0530 | [diff] [blame] | 512 | |
Jani Nikula | 7f6a6a4 | 2015-01-16 14:27:19 +0200 | [diff] [blame] | 513 | for_each_dsi_port(port, intel_dsi->ports) |
| 514 | wait_for_dsi_fifo_empty(intel_dsi, port); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 515 | } |
| 516 | |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 517 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 518 | { |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 519 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 520 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 521 | enum port port; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 522 | u32 val; |
| 523 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 524 | DRM_DEBUG_KMS("\n"); |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 525 | for_each_dsi_port(port, intel_dsi->ports) { |
ymohanma | be4fc04 | 2013-08-27 23:40:56 +0300 | [diff] [blame] | 526 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 527 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
| 528 | ULPS_STATE_ENTER); |
| 529 | usleep_range(2000, 2500); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 530 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 531 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
| 532 | ULPS_STATE_EXIT); |
| 533 | usleep_range(2000, 2500); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 534 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 535 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
| 536 | ULPS_STATE_ENTER); |
| 537 | usleep_range(2000, 2500); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 538 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 539 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A |
| 540 | * only. MIPI Port C has no similar bit for checking |
| 541 | */ |
| 542 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT) |
| 543 | == 0x00000), 30)) |
| 544 | DRM_ERROR("DSI LP not going Low\n"); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 545 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 546 | val = I915_READ(MIPI_PORT_CTRL(port)); |
| 547 | /* Disable MIPI PHY transparent latch |
| 548 | * Common bit for both MIPI Port A & MIPI Port C |
| 549 | */ |
| 550 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); |
| 551 | usleep_range(1000, 1500); |
Shobhit Kumar | aceb365 | 2014-07-03 16:35:41 +0530 | [diff] [blame] | 552 | |
Gaurav K Singh | 384f02a | 2014-12-05 14:22:44 +0530 | [diff] [blame] | 553 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); |
| 554 | usleep_range(2000, 2500); |
| 555 | } |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 556 | |
ymohanma | be4fc04 | 2013-08-27 23:40:56 +0300 | [diff] [blame] | 557 | vlv_disable_dsi_pll(encoder); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 558 | } |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 559 | |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 560 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
| 561 | { |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 562 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 563 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 564 | u32 val; |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 565 | |
| 566 | DRM_DEBUG_KMS("\n"); |
| 567 | |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 568 | intel_dsi_disable(encoder); |
| 569 | |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 570 | intel_dsi_clear_device_ready(encoder); |
| 571 | |
Shobhit Kumar | 20e5bf6 | 2014-04-09 13:59:32 +0530 | [diff] [blame] | 572 | val = I915_READ(DSPCLK_GATE_D); |
| 573 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
| 574 | I915_WRITE(DSPCLK_GATE_D, val); |
| 575 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 576 | drm_panel_unprepare(intel_dsi->panel); |
Shobhit Kumar | df38e65 | 2014-04-14 11:18:26 +0530 | [diff] [blame] | 577 | |
| 578 | msleep(intel_dsi->panel_off_delay); |
| 579 | msleep(intel_dsi->panel_pwr_cycle_delay); |
Shobhit Kumar | 1dbd7cb | 2013-12-11 17:52:05 +0530 | [diff] [blame] | 580 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 581 | |
| 582 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
| 583 | enum pipe *pipe) |
| 584 | { |
| 585 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 586 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
| 587 | struct drm_device *dev = encoder->base.dev; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 588 | enum intel_display_power_domain power_domain; |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 589 | u32 dpi_enabled, func; |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 590 | enum port port; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 591 | |
| 592 | DRM_DEBUG_KMS("\n"); |
| 593 | |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 594 | power_domain = intel_display_port_power_domain(encoder); |
Daniel Vetter | f458ebb | 2014-09-30 10:56:39 +0200 | [diff] [blame] | 595 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 596 | return false; |
| 597 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 598 | /* XXX: this only works for one DSI output */ |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 599 | for_each_dsi_port(port, intel_dsi->ports) { |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 600 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 601 | dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) & |
| 602 | DPI_ENABLE; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 603 | |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 604 | /* Due to some hardware limitations on BYT, MIPI Port C DPI |
| 605 | * Enable bit does not get set. To check whether DSI Port C |
| 606 | * was enabled in BIOS, check the Pipe B enable bit |
| 607 | */ |
| 608 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 609 | (port == PORT_C)) |
| 610 | dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & |
| 611 | PIPECONF_ENABLE; |
| 612 | |
| 613 | if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 614 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { |
Gaurav K Singh | c0beefd | 2014-12-09 10:59:20 +0530 | [diff] [blame] | 615 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 616 | return true; |
| 617 | } |
| 618 | } |
| 619 | } |
| 620 | |
| 621 | return false; |
| 622 | } |
| 623 | |
| 624 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 625 | struct intel_crtc_state *pipe_config) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 626 | { |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 627 | u32 pclk; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 628 | DRM_DEBUG_KMS("\n"); |
| 629 | |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 630 | /* |
| 631 | * DPLL_MD is not used in case of DSI, reading will get some default value |
| 632 | * set dpll_md = 0 |
| 633 | */ |
| 634 | pipe_config->dpll_hw_state.dpll_md = 0; |
| 635 | |
| 636 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
| 637 | if (!pclk) |
| 638 | return; |
| 639 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 640 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
Shobhit Kumar | f573de5 | 2014-07-30 20:32:37 +0530 | [diff] [blame] | 641 | pipe_config->port_clock = pclk; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 642 | } |
| 643 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 644 | static enum drm_mode_status |
| 645 | intel_dsi_mode_valid(struct drm_connector *connector, |
| 646 | struct drm_display_mode *mode) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 647 | { |
| 648 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 649 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 650 | |
| 651 | DRM_DEBUG_KMS("\n"); |
| 652 | |
| 653 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
| 654 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); |
| 655 | return MODE_NO_DBLESCAN; |
| 656 | } |
| 657 | |
| 658 | if (fixed_mode) { |
| 659 | if (mode->hdisplay > fixed_mode->hdisplay) |
| 660 | return MODE_PANEL; |
| 661 | if (mode->vdisplay > fixed_mode->vdisplay) |
| 662 | return MODE_PANEL; |
| 663 | } |
| 664 | |
Jani Nikula | 36d21f4 | 2015-01-16 14:27:20 +0200 | [diff] [blame] | 665 | return MODE_OK; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 666 | } |
| 667 | |
| 668 | /* return txclkesc cycles in terms of divider and duration in us */ |
| 669 | static u16 txclkesc(u32 divider, unsigned int us) |
| 670 | { |
| 671 | switch (divider) { |
| 672 | case ESCAPE_CLOCK_DIVIDER_1: |
| 673 | default: |
| 674 | return 20 * us; |
| 675 | case ESCAPE_CLOCK_DIVIDER_2: |
| 676 | return 10 * us; |
| 677 | case ESCAPE_CLOCK_DIVIDER_4: |
| 678 | return 5 * us; |
| 679 | } |
| 680 | } |
| 681 | |
| 682 | /* return pixels in terms of txbyteclkhs */ |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 683 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
| 684 | u16 burst_mode_ratio) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 685 | { |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 686 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
Daniel Vetter | 7f3de83 | 2014-07-30 22:34:27 +0200 | [diff] [blame] | 687 | 8 * 100), lane_count); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 688 | } |
| 689 | |
| 690 | static void set_dsi_timings(struct drm_encoder *encoder, |
| 691 | const struct drm_display_mode *mode) |
| 692 | { |
| 693 | struct drm_device *dev = encoder->dev; |
| 694 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 695 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 696 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 697 | enum port port; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 698 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 699 | unsigned int lane_count = intel_dsi->lane_count; |
| 700 | |
| 701 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
| 702 | |
| 703 | hactive = mode->hdisplay; |
| 704 | hfp = mode->hsync_start - mode->hdisplay; |
| 705 | hsync = mode->hsync_end - mode->hsync_start; |
| 706 | hbp = mode->htotal - mode->hsync_end; |
| 707 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 708 | if (intel_dsi->dual_link) { |
| 709 | hactive /= 2; |
| 710 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
| 711 | hactive += intel_dsi->pixel_overlap; |
| 712 | hfp /= 2; |
| 713 | hsync /= 2; |
| 714 | hbp /= 2; |
| 715 | } |
| 716 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 717 | vfp = mode->vsync_start - mode->vdisplay; |
| 718 | vsync = mode->vsync_end - mode->vsync_start; |
| 719 | vbp = mode->vtotal - mode->vsync_end; |
| 720 | |
| 721 | /* horizontal values are in terms of high speed byte clock */ |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 722 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
Daniel Vetter | 7f3de83 | 2014-07-30 22:34:27 +0200 | [diff] [blame] | 723 | intel_dsi->burst_mode_ratio); |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 724 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
| 725 | hsync = txbyteclkhs(hsync, bpp, lane_count, |
Daniel Vetter | 7f3de83 | 2014-07-30 22:34:27 +0200 | [diff] [blame] | 726 | intel_dsi->burst_mode_ratio); |
Shobhit Kumar | 7f0c860 | 2014-07-30 20:34:57 +0530 | [diff] [blame] | 727 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 728 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 729 | for_each_dsi_port(port, intel_dsi->ports) { |
| 730 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
| 731 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 732 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 733 | /* meaningful for video mode non-burst sync pulse mode only, |
| 734 | * can be zero for non-burst sync events and burst modes */ |
| 735 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); |
| 736 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 737 | |
Gaurav K Singh | aa102d2 | 2014-12-04 10:58:54 +0530 | [diff] [blame] | 738 | /* vertical values are in terms of lines */ |
| 739 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); |
| 740 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); |
| 741 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); |
| 742 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 743 | } |
| 744 | |
Daniel Vetter | 07e4fb9 | 2014-04-24 23:54:59 +0200 | [diff] [blame] | 745 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 746 | { |
| 747 | struct drm_encoder *encoder = &intel_encoder->base; |
| 748 | struct drm_device *dev = encoder->dev; |
| 749 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 750 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
| 751 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
| 752 | struct drm_display_mode *adjusted_mode = |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 753 | &intel_crtc->config->base.adjusted_mode; |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 754 | enum port port; |
Ander Conselvan de Oliveira | 6e3c971 | 2015-01-15 14:55:25 +0200 | [diff] [blame] | 755 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 756 | u32 val, tmp; |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 757 | u16 mode_hdisplay; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 758 | |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 759 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 760 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 761 | mode_hdisplay = adjusted_mode->hdisplay; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 762 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 763 | if (intel_dsi->dual_link) { |
| 764 | mode_hdisplay /= 2; |
| 765 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
| 766 | mode_hdisplay += intel_dsi->pixel_overlap; |
| 767 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 768 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 769 | for_each_dsi_port(port, intel_dsi->ports) { |
| 770 | /* escape clock divider, 20MHz, shared for A and C. |
| 771 | * device ready must be off when doing this! txclkesc? */ |
| 772 | tmp = I915_READ(MIPI_CTRL(PORT_A)); |
| 773 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
| 774 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 775 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 776 | /* read request priority is per pipe */ |
| 777 | tmp = I915_READ(MIPI_CTRL(port)); |
| 778 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
| 779 | I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 780 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 781 | /* XXX: why here, why like this? handling in irq handler?! */ |
| 782 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); |
| 783 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); |
| 784 | |
| 785 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); |
| 786 | |
| 787 | I915_WRITE(MIPI_DPI_RESOLUTION(port), |
| 788 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | |
| 789 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
| 790 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 791 | |
| 792 | set_dsi_timings(encoder, adjusted_mode); |
| 793 | |
| 794 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; |
| 795 | if (is_cmd_mode(intel_dsi)) { |
| 796 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; |
| 797 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ |
| 798 | } else { |
| 799 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
| 800 | |
| 801 | /* XXX: cross-check bpp vs. pixel format? */ |
| 802 | val |= intel_dsi->pixel_format; |
| 803 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 804 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 805 | tmp = 0; |
Shobhit Kumar | f1c79f1 | 2014-04-09 13:59:33 +0530 | [diff] [blame] | 806 | if (intel_dsi->eotp_pkt == 0) |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 807 | tmp |= EOT_DISABLE; |
Shobhit Kumar | f1c79f1 | 2014-04-09 13:59:33 +0530 | [diff] [blame] | 808 | if (intel_dsi->clock_stop) |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 809 | tmp |= CLOCKSTOP; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 810 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 811 | for_each_dsi_port(port, intel_dsi->ports) { |
| 812 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 813 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 814 | /* timeouts for recovery. one frame IIUC. if counter expires, |
| 815 | * EOT and stop state. */ |
Shobhit Kumar | cf4dbd2 | 2014-04-14 11:18:25 +0530 | [diff] [blame] | 816 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 817 | /* |
| 818 | * In burst mode, value greater than one DPI line Time in byte |
| 819 | * clock (txbyteclkhs) To timeout this timer 1+ of the above |
| 820 | * said value is recommended. |
| 821 | * |
| 822 | * In non-burst mode, Value greater than one DPI frame time in |
| 823 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
| 824 | * said value is recommended. |
| 825 | * |
| 826 | * In DBI only mode, value greater than one DBI frame time in |
| 827 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
| 828 | * said value is recommended. |
| 829 | */ |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 830 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 831 | if (is_vid_mode(intel_dsi) && |
| 832 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
| 833 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
| 834 | txbyteclkhs(adjusted_mode->htotal, bpp, |
| 835 | intel_dsi->lane_count, |
| 836 | intel_dsi->burst_mode_ratio) + 1); |
| 837 | } else { |
| 838 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
| 839 | txbyteclkhs(adjusted_mode->vtotal * |
| 840 | adjusted_mode->htotal, |
| 841 | bpp, intel_dsi->lane_count, |
| 842 | intel_dsi->burst_mode_ratio) + 1); |
| 843 | } |
| 844 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); |
| 845 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), |
| 846 | intel_dsi->turn_arnd_val); |
| 847 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), |
| 848 | intel_dsi->rst_timer_val); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 849 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 850 | /* dphy stuff */ |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 851 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 852 | /* in terms of low power clock */ |
| 853 | I915_WRITE(MIPI_INIT_COUNT(port), |
| 854 | txclkesc(intel_dsi->escape_clk_div, 100)); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 855 | |
Gaurav K Singh | 24ee0e6 | 2014-12-05 14:24:21 +0530 | [diff] [blame] | 856 | |
| 857 | /* recovery disables */ |
| 858 | I915_WRITE(MIPI_EOT_DISABLE(port), val); |
| 859 | |
| 860 | /* in terms of low power clock */ |
| 861 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); |
| 862 | |
| 863 | /* in terms of txbyteclkhs. actual high to low switch + |
| 864 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
| 865 | * |
| 866 | * XXX: write MIPI_STOP_STATE_STALL? |
| 867 | */ |
| 868 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), |
| 869 | intel_dsi->hs_to_lp_count); |
| 870 | |
| 871 | /* XXX: low power clock equivalence in terms of byte clock. |
| 872 | * the number of byte clocks occupied in one low power clock. |
| 873 | * based on txbyteclkhs and txclkesc. |
| 874 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL |
| 875 | * ) / 105.??? |
| 876 | */ |
| 877 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); |
| 878 | |
| 879 | /* the bw essential for transmitting 16 long packets containing |
| 880 | * 252 bytes meant for dcs write memory command is programmed in |
| 881 | * this register in terms of byte clocks. based on dsi transfer |
| 882 | * rate and the number of lanes configured the time taken to |
| 883 | * transmit 16 long packets in a dsi stream varies. */ |
| 884 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); |
| 885 | |
| 886 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), |
| 887 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
| 888 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
| 889 | |
| 890 | if (is_vid_mode(intel_dsi)) |
| 891 | /* Some panels might have resolution which is not a |
| 892 | * multiple of 64 like 1366 x 768. Enable RANDOM |
| 893 | * resolution support for such panels by default */ |
| 894 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), |
| 895 | intel_dsi->video_frmt_cfg_bits | |
| 896 | intel_dsi->video_mode_format | |
| 897 | IP_TG_CONFIG | |
| 898 | RANDOM_DPI_DISPLAY_RESOLUTION); |
| 899 | } |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 900 | } |
| 901 | |
Daniel Vetter | 07e4fb9 | 2014-04-24 23:54:59 +0200 | [diff] [blame] | 902 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
| 903 | { |
| 904 | DRM_DEBUG_KMS("\n"); |
| 905 | |
| 906 | intel_dsi_prepare(encoder); |
| 907 | |
| 908 | vlv_enable_dsi_pll(encoder); |
| 909 | } |
| 910 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 911 | static enum drm_connector_status |
| 912 | intel_dsi_detect(struct drm_connector *connector, bool force) |
| 913 | { |
Jani Nikula | 36d21f4 | 2015-01-16 14:27:20 +0200 | [diff] [blame] | 914 | return connector_status_connected; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 915 | } |
| 916 | |
| 917 | static int intel_dsi_get_modes(struct drm_connector *connector) |
| 918 | { |
| 919 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 920 | struct drm_display_mode *mode; |
| 921 | |
| 922 | DRM_DEBUG_KMS("\n"); |
| 923 | |
| 924 | if (!intel_connector->panel.fixed_mode) { |
| 925 | DRM_DEBUG_KMS("no fixed mode\n"); |
| 926 | return 0; |
| 927 | } |
| 928 | |
| 929 | mode = drm_mode_duplicate(connector->dev, |
| 930 | intel_connector->panel.fixed_mode); |
| 931 | if (!mode) { |
| 932 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); |
| 933 | return 0; |
| 934 | } |
| 935 | |
| 936 | drm_mode_probed_add(connector, mode); |
| 937 | return 1; |
| 938 | } |
| 939 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 940 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 941 | { |
| 942 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 943 | |
| 944 | DRM_DEBUG_KMS("\n"); |
| 945 | intel_panel_fini(&intel_connector->panel); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 946 | drm_connector_cleanup(connector); |
| 947 | kfree(connector); |
| 948 | } |
| 949 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 950 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
| 951 | { |
| 952 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
| 953 | |
| 954 | if (intel_dsi->panel) { |
| 955 | drm_panel_detach(intel_dsi->panel); |
| 956 | /* XXX: Logically this call belongs in the panel driver. */ |
| 957 | drm_panel_remove(intel_dsi->panel); |
| 958 | } |
| 959 | intel_encoder_destroy(encoder); |
| 960 | } |
| 961 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 962 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 963 | .destroy = intel_dsi_encoder_destroy, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 964 | }; |
| 965 | |
| 966 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
| 967 | .get_modes = intel_dsi_get_modes, |
| 968 | .mode_valid = intel_dsi_mode_valid, |
| 969 | .best_encoder = intel_best_encoder, |
| 970 | }; |
| 971 | |
| 972 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
| 973 | .dpms = intel_connector_dpms, |
| 974 | .detect = intel_dsi_detect, |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 975 | .destroy = intel_dsi_connector_destroy, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 976 | .fill_modes = drm_helper_probe_single_connector_modes, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 977 | .atomic_get_property = intel_connector_atomic_get_property, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 978 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 979 | }; |
| 980 | |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 981 | void intel_dsi_init(struct drm_device *dev) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 982 | { |
| 983 | struct intel_dsi *intel_dsi; |
| 984 | struct intel_encoder *intel_encoder; |
| 985 | struct drm_encoder *encoder; |
| 986 | struct intel_connector *intel_connector; |
| 987 | struct drm_connector *connector; |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 988 | struct drm_display_mode *scan, *fixed_mode = NULL; |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 989 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 990 | enum port port; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 991 | unsigned int i; |
| 992 | |
| 993 | DRM_DEBUG_KMS("\n"); |
| 994 | |
Shobhit Kumar | 3e6bd01 | 2014-05-27 19:33:59 +0530 | [diff] [blame] | 995 | /* There is no detection method for MIPI so rely on VBT */ |
| 996 | if (!dev_priv->vbt.has_mipi) |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 997 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 998 | |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 999 | if (IS_VALLEYVIEW(dev)) { |
| 1000 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
| 1001 | } else { |
| 1002 | DRM_ERROR("Unsupported Mipi device to reg base"); |
Christoph Jaeger | 868d665 | 2014-06-13 21:51:22 +0200 | [diff] [blame] | 1003 | return; |
Shashank Sharma | b6fdd0f | 2014-05-19 20:54:03 +0530 | [diff] [blame] | 1004 | } |
| 1005 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1006 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
| 1007 | if (!intel_dsi) |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1008 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1009 | |
| 1010 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
| 1011 | if (!intel_connector) { |
| 1012 | kfree(intel_dsi); |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1013 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1014 | } |
| 1015 | |
| 1016 | intel_encoder = &intel_dsi->base; |
| 1017 | encoder = &intel_encoder->base; |
| 1018 | intel_dsi->attached_connector = intel_connector; |
| 1019 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1020 | connector = &intel_connector->base; |
| 1021 | |
| 1022 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); |
| 1023 | |
| 1024 | /* XXX: very likely not all of these are needed */ |
| 1025 | intel_encoder->hot_plug = intel_dsi_hot_plug; |
| 1026 | intel_encoder->compute_config = intel_dsi_compute_config; |
| 1027 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; |
| 1028 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
Shobhit Kumar | 2634fd7 | 2014-04-09 13:59:31 +0530 | [diff] [blame] | 1029 | intel_encoder->enable = intel_dsi_enable_nop; |
Imre Deak | c315faf | 2014-05-27 19:00:09 +0300 | [diff] [blame] | 1030 | intel_encoder->disable = intel_dsi_pre_disable; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1031 | intel_encoder->post_disable = intel_dsi_post_disable; |
| 1032 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; |
| 1033 | intel_encoder->get_config = intel_dsi_get_config; |
| 1034 | |
| 1035 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 1036 | intel_connector->unregister = intel_connector_unregister; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1037 | |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 1038 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 1039 | if (dev_priv->vbt.dsi.config->dual_link) { |
| 1040 | /* XXX: does dual link work on either pipe? */ |
| 1041 | intel_encoder->crtc_mask = (1 << PIPE_A); |
| 1042 | intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); |
| 1043 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 1044 | intel_encoder->crtc_mask = (1 << PIPE_A); |
Jani Nikula | 17af40a | 2014-11-14 16:54:22 +0200 | [diff] [blame] | 1045 | intel_dsi->ports = (1 << PORT_A); |
| 1046 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 1047 | intel_encoder->crtc_mask = (1 << PIPE_B); |
Jani Nikula | 17af40a | 2014-11-14 16:54:22 +0200 | [diff] [blame] | 1048 | intel_dsi->ports = (1 << PORT_C); |
| 1049 | } |
Jani Nikula | e7d7cad | 2014-11-14 16:54:21 +0200 | [diff] [blame] | 1050 | |
Jani Nikula | 7e9804f | 2015-01-16 14:27:23 +0200 | [diff] [blame] | 1051 | /* Create a DSI host (and a device) for each port. */ |
| 1052 | for_each_dsi_port(port, intel_dsi->ports) { |
| 1053 | struct intel_dsi_host *host; |
| 1054 | |
| 1055 | host = intel_dsi_host_init(intel_dsi, port); |
| 1056 | if (!host) |
| 1057 | goto err; |
| 1058 | |
| 1059 | intel_dsi->dsi_hosts[port] = host; |
| 1060 | } |
| 1061 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1062 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
| 1063 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, |
| 1064 | intel_dsi_drivers[i].panel_id); |
| 1065 | if (intel_dsi->panel) |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1066 | break; |
| 1067 | } |
| 1068 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1069 | if (!intel_dsi->panel) { |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1070 | DRM_DEBUG_KMS("no device found\n"); |
| 1071 | goto err; |
| 1072 | } |
| 1073 | |
| 1074 | intel_encoder->type = INTEL_OUTPUT_DSI; |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 1075 | intel_encoder->cloneable = 0; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1076 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
| 1077 | DRM_MODE_CONNECTOR_DSI); |
| 1078 | |
| 1079 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); |
| 1080 | |
| 1081 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ |
| 1082 | connector->interlace_allowed = false; |
| 1083 | connector->doublescan_allowed = false; |
| 1084 | |
| 1085 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
| 1086 | |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 1087 | drm_connector_register(connector); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1088 | |
Jani Nikula | 593e062 | 2015-01-23 15:30:56 +0200 | [diff] [blame] | 1089 | drm_panel_attach(intel_dsi->panel, connector); |
| 1090 | |
| 1091 | mutex_lock(&dev->mode_config.mutex); |
| 1092 | drm_panel_get_modes(intel_dsi->panel); |
| 1093 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 1094 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 1095 | fixed_mode = drm_mode_duplicate(dev, scan); |
| 1096 | break; |
| 1097 | } |
| 1098 | } |
| 1099 | mutex_unlock(&dev->mode_config.mutex); |
| 1100 | |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1101 | if (!fixed_mode) { |
| 1102 | DRM_DEBUG_KMS("no fixed mode\n"); |
| 1103 | goto err; |
| 1104 | } |
| 1105 | |
Vandana Kannan | 4b6ed68 | 2014-02-11 14:26:36 +0530 | [diff] [blame] | 1106 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1107 | |
Damien Lespiau | 4328633d | 2014-05-28 12:30:56 +0100 | [diff] [blame] | 1108 | return; |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1109 | |
| 1110 | err: |
| 1111 | drm_encoder_cleanup(&intel_encoder->base); |
| 1112 | kfree(intel_dsi); |
| 1113 | kfree(intel_connector); |
Jani Nikula | 4e64649 | 2013-08-27 15:12:20 +0300 | [diff] [blame] | 1114 | } |