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review.shift-gmbh.com / SHIFTPHONES / kernel / common / ef2053afd71e5b1f3a94e81293f8f67bb3c7807b / . / arch / arm / lib / csumpartialcopyuser.S
blob: 6928781e6beebcf3aab564ef0a52461e3ad43e92 [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2/*
3 * linux/arch/arm/lib/csumpartialcopyuser.S
4 *
5 * Copyright (C) 1995-1998 Russell King
6 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]7 * 27/03/03 Ian Molton Clean up CONFIG_CPU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]8 */
9#include <linux/linkage.h>
10#include <asm/assembler.h>
11#include <asm/errno.h>
Sam Ravnborge6ae7442005-09-09 21:08:59 +0200[diff] [blame]12#include <asm/asm-offsets.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]13
14 .text
15
Russell Kinga5e090a2015-08-19 20:40:41 +0100[diff] [blame]16#ifdef CONFIG_CPU_SW_DOMAIN_PAN
17 .macro save_regs
18 mrc p15, 0, ip, c3, c0, 0
19 stmfd sp!, {r1, r2, r4 - r8, ip, lr}
20 uaccess_enable ip
21 .endm
22
23 .macro load_regs
24 ldmfd sp!, {r1, r2, r4 - r8, ip, lr}
25 mcr p15, 0, ip, c3, c0, 0
26 ret lr
27 .endm
28#else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]29 .macro save_regs
Catalin Marinas22acc4e2008-08-29 18:31:27 +0100[diff] [blame]30 stmfd sp!, {r1, r2, r4 - r8, lr}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]31 .endm
32
Catalin Marinas90303b12006-01-12 16:53:51 +0000[diff] [blame]33 .macro load_regs
Catalin Marinas22acc4e2008-08-29 18:31:27 +0100[diff] [blame]34 ldmfd sp!, {r1, r2, r4 - r8, pc}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]35 .endm
Russell Kinga5e090a2015-08-19 20:40:41 +0100[diff] [blame]36#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]37
38 .macro load1b, reg1
Catalin Marinas8b592782009-07-24 12:32:57 +0100[diff] [blame]39 ldrusr \reg1, r0, 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]40 .endm
41
42 .macro load2b, reg1, reg2
Catalin Marinas8b592782009-07-24 12:32:57 +0100[diff] [blame]43 ldrusr \reg1, r0, 1
44 ldrusr \reg2, r0, 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]45 .endm
46
47 .macro load1l, reg1
Catalin Marinas8b592782009-07-24 12:32:57 +0100[diff] [blame]48 ldrusr \reg1, r0, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]49 .endm
50
51 .macro load2l, reg1, reg2
Catalin Marinas8b592782009-07-24 12:32:57 +0100[diff] [blame]52 ldrusr \reg1, r0, 4
53 ldrusr \reg2, r0, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]54 .endm
55
56 .macro load4l, reg1, reg2, reg3, reg4
Catalin Marinas8b592782009-07-24 12:32:57 +0100[diff] [blame]57 ldrusr \reg1, r0, 4
58 ldrusr \reg2, r0, 4
59 ldrusr \reg3, r0, 4
60 ldrusr \reg4, r0, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]61 .endm
62
63/*
64 * unsigned int
Al Viro1d60be32020-07-12 22:56:34 -0400[diff] [blame]65 * csum_partial_copy_from_user(const char *src, char *dst, int len)
66 * r0 = src, r1 = dst, r2 = len
67 * Returns : r0 = checksum or 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]68 */
69
70#define FN_ENTRY ENTRY(csum_partial_copy_from_user)
Catalin Marinas93ed3972008-08-28 11:22:32 +0100[diff] [blame]71#define FN_EXIT ENDPROC(csum_partial_copy_from_user)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]72
73#include "csumpartialcopygeneric.S"
74
75/*
Al Viro1d60be32020-07-12 22:56:34 -0400[diff] [blame]76 * We report fault by returning 0 csum - impossible in normal case, since
77 * we start with 0xffffffff for initial sum.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]78 */
Ard Biesheuvelc4a84ae2015-03-24 10:41:09 +0100[diff] [blame]79 .pushsection .text.fixup,"ax"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]80 .align 4
Al Viro1d60be32020-07-12 22:56:34 -0400[diff] [blame]819001: mov r0, #0
Catalin Marinas90303b12006-01-12 16:53:51 +0000[diff] [blame]82 load_regs
Russell King42604152010-04-19 10:15:03 +0100[diff] [blame]83 .popsection