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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_PROCESSOR_H
2#define _ASM_X86_PROCESSOR_H
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +01003
Glauber de Oliveira Costa053de042008-01-30 13:31:27 +01004#include <asm/processor-flags.h>
5
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +01006/* Forward declaration, a strange C thing */
7struct task_struct;
8struct mm_struct;
Brian Gerst9fda6a02015-07-29 01:41:16 -04009struct vm86;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +010010
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010011#include <asm/math_emu.h>
12#include <asm/segment.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010013#include <asm/types.h>
Ingo Molnardecb4c42015-09-05 09:32:43 +020014#include <uapi/asm/sigcontext.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010015#include <asm/current.h>
Borislav Petkovcd4d09e2016-01-26 22:12:04 +010016#include <asm/cpufeatures.h>
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +010017#include <asm/page.h>
Jeremy Fitzhardinge54321d92009-02-11 10:20:05 -080018#include <asm/pgtable_types.h>
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +010019#include <asm/percpu.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010020#include <asm/msr.h>
21#include <asm/desc_defs.h>
Andi Kleenbd616432008-01-30 13:32:38 +010022#include <asm/nops.h>
David Howellsf05e7982012-03-28 18:11:12 +010023#include <asm/special_insns.h>
Ingo Molnar14b96752015-04-22 09:57:24 +020024#include <asm/fpu/types.h>
Ingo Molnar4d46a892008-02-21 04:24:40 +010025
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010026#include <linux/personality.h>
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +010027#include <linux/cache.h>
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +010028#include <linux/threads.h>
Peter Zijlstra5cbc19a2009-09-02 11:49:52 +020029#include <linux/math64.h>
Peter Zijlstrafaa46022010-03-25 14:51:50 +010030#include <linux/err.h>
David Howellsf05e7982012-03-28 18:11:12 +010031#include <linux/irqflags.h>
Tom Lendacky21729f82017-07-17 16:10:07 -050032#include <linux/mem_encrypt.h>
David Howellsf05e7982012-03-28 18:11:12 +010033
34/*
35 * We handle most unaligned accesses in hardware. On the other hand
36 * unaligned DMA can be quite expensive on some Nehalem processors.
37 *
38 * Based on this we disable the IP header alignment in network drivers.
39 */
40#define NET_IP_ALIGN 0
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +010041
K.Prasadb332828c2009-06-01 23:43:10 +053042#define HBP_NUM 4
Glauber de Oliveira Costa0ccb8ac2008-01-30 13:31:27 +010043/*
44 * Default implementation of macro that returns current
45 * instruction pointer ("program counter").
46 */
47static inline void *current_text_addr(void)
48{
49 void *pc;
Ingo Molnar4d46a892008-02-21 04:24:40 +010050
51 asm volatile("mov $1f, %0; 1:":"=r" (pc));
52
Glauber de Oliveira Costa0ccb8ac2008-01-30 13:31:27 +010053 return pc;
54}
55
Ingo Molnarb8c1b8ea2015-05-24 09:58:12 +020056/*
57 * These alignment constraints are for performance in the vSMP case,
58 * but in the task_struct case we must also meet hardware imposed
59 * alignment requirements of the FPU state:
60 */
Glauber de Oliveira Costadbcb4662008-01-30 13:31:31 +010061#ifdef CONFIG_X86_VSMP
Ingo Molnar4d46a892008-02-21 04:24:40 +010062# define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
63# define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
Glauber de Oliveira Costadbcb4662008-01-30 13:31:31 +010064#else
Ingo Molnarb8c1b8ea2015-05-24 09:58:12 +020065# define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
Ingo Molnar4d46a892008-02-21 04:24:40 +010066# define ARCH_MIN_MMSTRUCT_ALIGN 0
Glauber de Oliveira Costadbcb4662008-01-30 13:31:31 +010067#endif
68
Alex Shie0ba94f2012-06-28 09:02:16 +080069enum tlb_infos {
70 ENTRIES,
71 NR_INFO
72};
73
74extern u16 __read_mostly tlb_lli_4k[NR_INFO];
75extern u16 __read_mostly tlb_lli_2m[NR_INFO];
76extern u16 __read_mostly tlb_lli_4m[NR_INFO];
77extern u16 __read_mostly tlb_lld_4k[NR_INFO];
78extern u16 __read_mostly tlb_lld_2m[NR_INFO];
79extern u16 __read_mostly tlb_lld_4m[NR_INFO];
Kirill A. Shutemovdd360392013-12-23 14:16:58 +020080extern u16 __read_mostly tlb_lld_1g[NR_INFO];
Alex Shic4211f42012-06-28 09:02:19 +080081
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +010082/*
83 * CPU type and hardware bug flags. Kept separately for each CPU.
Mathias Krause04402112017-02-12 22:12:07 +010084 * Members of this structure are referenced in head_32.S, so think twice
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +010085 * before touching them. [mj]
86 */
87
88struct cpuinfo_x86 {
Ingo Molnar4d46a892008-02-21 04:24:40 +010089 __u8 x86; /* CPU family */
90 __u8 x86_vendor; /* CPU vendor */
91 __u8 x86_model;
92 __u8 x86_mask;
Mathias Krause64158132017-02-12 22:12:08 +010093#ifdef CONFIG_X86_64
Ingo Molnar4d46a892008-02-21 04:24:40 +010094 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
H. Peter Anvinb1882e62009-01-23 17:18:52 -080095 int x86_tlbsize;
Jan Beulich13c6c532009-03-12 12:37:34 +000096#endif
Ingo Molnar4d46a892008-02-21 04:24:40 +010097 __u8 x86_virt_bits;
98 __u8 x86_phys_bits;
99 /* CPUID returned core id bits: */
100 __u8 x86_coreid_bits;
Borislav Petkov79a8b9a2017-02-05 11:50:21 +0100101 __u8 cu_id;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100102 /* Max extended CPUID function supported: */
103 __u32 extended_cpuid_level;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100104 /* Maximum supported CPUID level, -1=no CPUID: */
105 int cpuid_level;
Borislav Petkov65fc9852013-03-20 15:07:23 +0100106 __u32 x86_capability[NCAPINTS + NBUGINTS];
Ingo Molnar4d46a892008-02-21 04:24:40 +0100107 char x86_vendor_id[16];
108 char x86_model_id[64];
109 /* in KB - valid for CPUS which support this call: */
110 int x86_cache_size;
111 int x86_cache_alignment; /* In bytes */
Peter P Waskiewicz Jrcbc82b12015-01-23 18:45:43 +0000112 /* Cache QoS architectural values: */
113 int x86_cache_max_rmid; /* max index */
114 int x86_cache_occ_scale; /* scale to bytes */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100115 int x86_power;
116 unsigned long loops_per_jiffy;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100117 /* cpuid returned max cores value: */
118 u16 x86_max_cores;
119 u16 apicid;
Yinghai Lu01aaea12008-03-06 13:46:39 -0800120 u16 initial_apicid;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100121 u16 x86_clflush_size;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100122 /* number of cores as seen by the OS: */
123 u16 booted_cores;
124 /* Physical processor id: */
125 u16 phys_proc_id;
Thomas Gleixner1f12e322016-02-22 22:19:15 +0000126 /* Logical processor id: */
127 u16 logical_proc_id;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100128 /* Core id: */
129 u16 cpu_core_id;
130 /* Index into per_cpu list: */
131 u16 cpu_index;
Andi Kleen506ed6b2011-10-12 17:46:33 -0700132 u32 microcode;
Jan Beulich2c773dd2014-11-04 08:26:42 +0000133};
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100134
He Chen47f10a32016-11-11 17:25:34 +0800135struct cpuid_regs {
136 u32 eax, ebx, ecx, edx;
137};
138
139enum cpuid_regs_idx {
140 CPUID_EAX = 0,
141 CPUID_EBX,
142 CPUID_ECX,
143 CPUID_EDX,
144};
145
Ingo Molnar4d46a892008-02-21 04:24:40 +0100146#define X86_VENDOR_INTEL 0
147#define X86_VENDOR_CYRIX 1
148#define X86_VENDOR_AMD 2
149#define X86_VENDOR_UMC 3
Ingo Molnar4d46a892008-02-21 04:24:40 +0100150#define X86_VENDOR_CENTAUR 5
151#define X86_VENDOR_TRANSMETA 7
152#define X86_VENDOR_NSC 8
153#define X86_VENDOR_NUM 9
154
155#define X86_VENDOR_UNKNOWN 0xff
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100156
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100157/*
158 * capabilities of CPUs
159 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100160extern struct cpuinfo_x86 boot_cpu_data;
161extern struct cpuinfo_x86 new_cpu_data;
162
163extern struct tss_struct doublefault_tss;
Yinghai Lu3e0c3732009-05-09 23:47:42 -0700164extern __u32 cpu_caps_cleared[NCAPINTS];
165extern __u32 cpu_caps_set[NCAPINTS];
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100166
167#ifdef CONFIG_SMP
Jan Beulich2c773dd2014-11-04 08:26:42 +0000168DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100169#define cpu_data(cpu) per_cpu(cpu_info, cpu)
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100170#else
Tejun Heo7b543a52010-12-18 16:30:05 +0100171#define cpu_info boot_cpu_data
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100172#define cpu_data(cpu) boot_cpu_data
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100173#endif
174
Jaswinder Singh1c6c7272008-07-21 22:40:37 +0530175extern const struct seq_operations cpuinfo_op;
176
Ingo Molnar4d46a892008-02-21 04:24:40 +0100177#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
178
179extern void cpu_detect(struct cpuinfo_x86 *c);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100180
Yinghai Luf5803662008-06-21 03:24:19 -0700181extern void early_cpu_init(void);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100182extern void identify_boot_cpu(void);
183extern void identify_secondary_cpu(struct cpuinfo_x86 *);
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100184extern void print_cpu_info(struct cpuinfo_x86 *);
Yinghai Lu21c3fcf2012-02-12 09:53:57 -0800185void print_cpu_msr(struct cpuinfo_x86 *);
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100186extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
He Chen47bdf332016-11-11 17:25:35 +0800187extern u32 get_scattered_cpuid_leaf(unsigned int level,
188 unsigned int sub_leaf,
189 enum cpuid_regs_idx reg);
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100190extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
Andreas Herrmann04a15412012-10-19 10:59:33 +0200191extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
Glauber de Oliveira Costa5300db82008-01-30 13:31:33 +0100192
Suresh Siddhabbb65d22008-08-23 17:47:10 +0200193extern void detect_extended_topology(struct cpuinfo_x86 *c);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100194extern void detect_ht(struct cpuinfo_x86 *c);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100195
Fenghua Yud288e1c2012-12-20 23:44:23 -0800196#ifdef CONFIG_X86_32
197extern int have_cpuid_p(void);
198#else
199static inline int have_cpuid_p(void)
200{
201 return 1;
202}
203#endif
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100204static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
Ingo Molnar4d46a892008-02-21 04:24:40 +0100205 unsigned int *ecx, unsigned int *edx)
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100206{
207 /* ecx is often an input as well as an output. */
Suresh Siddha45a94d72009-12-16 16:25:42 -0800208 asm volatile("cpuid"
Joe Perchescca2e6f2008-03-23 01:03:15 -0700209 : "=a" (*eax),
210 "=b" (*ebx),
211 "=c" (*ecx),
212 "=d" (*edx)
Andi Kleen506ed6b2011-10-12 17:46:33 -0700213 : "0" (*eax), "2" (*ecx)
214 : "memory");
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100215}
216
Borislav Petkov5dedade2017-01-09 12:41:43 +0100217#define native_cpuid_reg(reg) \
218static inline unsigned int native_cpuid_##reg(unsigned int op) \
219{ \
220 unsigned int eax = op, ebx, ecx = 0, edx; \
221 \
222 native_cpuid(&eax, &ebx, &ecx, &edx); \
223 \
224 return reg; \
225}
226
227/*
228 * Native CPUID functions returning a single datum.
229 */
230native_cpuid_reg(eax)
231native_cpuid_reg(ebx)
232native_cpuid_reg(ecx)
233native_cpuid_reg(edx)
234
Andy Lutomirski6c690ee2017-06-12 10:26:14 -0700235/*
236 * Friendlier CR3 helpers.
237 */
238static inline unsigned long read_cr3_pa(void)
239{
240 return __read_cr3() & CR3_ADDR_MASK;
241}
242
Tom Lendackyeef9c4a2017-07-17 16:10:08 -0500243static inline unsigned long native_read_cr3_pa(void)
244{
245 return __native_read_cr3() & CR3_ADDR_MASK;
246}
247
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +0100248static inline void load_cr3(pgd_t *pgdir)
249{
Tom Lendacky21729f82017-07-17 16:10:07 -0500250 write_cr3(__sme_pa(pgdir));
Glauber de Oliveira Costac72dcf82008-01-30 13:31:27 +0100251}
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100252
Thomas Gleixner96a388d2007-10-11 11:20:03 +0200253#ifdef CONFIG_X86_32
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100254/* This is the TSS defined by the hardware. */
255struct x86_hw_tss {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100256 unsigned short back_link, __blh;
257 unsigned long sp0;
258 unsigned short ss0, __ss0h;
Andy Lutomirskicf9328c2015-04-02 12:41:45 -0700259 unsigned long sp1;
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700260
261 /*
Andy Lutomirskicf9328c2015-04-02 12:41:45 -0700262 * We don't use ring 1, so ss1 is a convenient scratch space in
263 * the same cacheline as sp0. We use ss1 to cache the value in
264 * MSR_IA32_SYSENTER_CS. When we context switch
265 * MSR_IA32_SYSENTER_CS, we first check if the new value being
266 * written matches ss1, and, if it's not, then we wrmsr the new
267 * value and update ss1.
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700268 *
Andy Lutomirskicf9328c2015-04-02 12:41:45 -0700269 * The only reason we context switch MSR_IA32_SYSENTER_CS is
270 * that we set it to zero in vm86 tasks to avoid corrupting the
271 * stack if we were to go through the sysenter path from vm86
272 * mode.
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700273 */
Andy Lutomirski76e4c492015-03-10 11:06:00 -0700274 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
275
276 unsigned short __ss1h;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100277 unsigned long sp2;
278 unsigned short ss2, __ss2h;
279 unsigned long __cr3;
280 unsigned long ip;
281 unsigned long flags;
282 unsigned long ax;
283 unsigned long cx;
284 unsigned long dx;
285 unsigned long bx;
286 unsigned long sp;
287 unsigned long bp;
288 unsigned long si;
289 unsigned long di;
290 unsigned short es, __esh;
291 unsigned short cs, __csh;
292 unsigned short ss, __ssh;
293 unsigned short ds, __dsh;
294 unsigned short fs, __fsh;
295 unsigned short gs, __gsh;
296 unsigned short ldt, __ldth;
297 unsigned short trace;
298 unsigned short io_bitmap_base;
299
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100300} __attribute__((packed));
301#else
302struct x86_hw_tss {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100303 u32 reserved1;
304 u64 sp0;
305 u64 sp1;
306 u64 sp2;
307 u64 reserved2;
308 u64 ist[7];
309 u32 reserved3;
310 u32 reserved4;
311 u16 reserved5;
312 u16 io_bitmap_base;
313
Andy Lutomirskid3273de2017-02-20 08:56:13 -0800314} __attribute__((packed));
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100315#endif
316
317/*
Ingo Molnar4d46a892008-02-21 04:24:40 +0100318 * IO-bitmap sizes:
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100319 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100320#define IO_BITMAP_BITS 65536
321#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
322#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
323#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
324#define INVALID_IO_BITMAP_OFFSET 0x8000
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100325
326struct tss_struct {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100327 /*
328 * The hardware state:
329 */
330 struct x86_hw_tss x86_tss;
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100331
332 /*
333 * The extra 1 is there because the CPU will access an
334 * additional byte beyond the end of the IO permission
335 * bitmap. The extra byte must be all 1 bits, and must
336 * be within the limit.
337 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100338 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
Ingo Molnar4d46a892008-02-21 04:24:40 +0100339
Andy Lutomirski6dcc9412016-03-09 19:00:31 -0800340#ifdef CONFIG_X86_32
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100341 /*
Andy Lutomirski2a41aa42016-03-09 19:00:33 -0800342 * Space for the temporary SYSENTER stack.
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100343 */
Andy Lutomirski2a41aa42016-03-09 19:00:33 -0800344 unsigned long SYSENTER_stack_canary;
Denys Vlasenkod828c712015-03-09 15:52:18 +0100345 unsigned long SYSENTER_stack[64];
Andy Lutomirski6dcc9412016-03-09 19:00:31 -0800346#endif
Ingo Molnar4d46a892008-02-21 04:24:40 +0100347
Richard Kennedy84e65b02008-07-04 13:56:16 +0100348} ____cacheline_aligned;
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100349
Andy Lutomirski24933b82015-03-05 19:19:05 -0800350DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
Glauber de Oliveira Costaca241c72008-01-30 13:31:31 +0100351
Andy Lutomirski4f53ab12017-02-20 08:56:09 -0800352/*
353 * sizeof(unsigned long) coming from an extra "long" at the end
354 * of the iobitmap.
355 *
356 * -1? seg base+limit should be pointing to the address of the
357 * last valid byte
358 */
359#define __KERNEL_TSS_LIMIT \
360 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
361
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800362#ifdef CONFIG_X86_32
363DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
364#endif
365
Ingo Molnar4d46a892008-02-21 04:24:40 +0100366/*
367 * Save the original ist values for checking stack pointers during debugging
368 */
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100369struct orig_ist {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100370 unsigned long ist[7];
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100371};
372
Glauber Costafe676202008-03-03 14:12:56 -0300373#ifdef CONFIG_X86_64
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100374DECLARE_PER_CPU(struct orig_ist, orig_ist);
Brian Gerst26f80bd2009-01-19 00:38:58 +0900375
Brian Gerst947e76c2009-01-19 12:21:28 +0900376union irq_stack_union {
377 char irq_stack[IRQ_STACK_SIZE];
378 /*
379 * GCC hardcodes the stack canary as %gs:40. Since the
380 * irq_stack is the object at %gs:0, we reserve the bottom
381 * 48 bytes of the irq stack for the canary.
382 */
383 struct {
384 char gs_base[40];
385 unsigned long stack_canary;
386 };
387};
388
Andi Kleen277d5b42013-08-05 15:02:43 -0700389DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
Brian Gerst2add8e22009-02-08 09:58:39 -0500390DECLARE_INIT_PER_CPU(irq_stack_union);
391
Brian Gerst26f80bd2009-01-19 00:38:58 +0900392DECLARE_PER_CPU(char *, irq_stack_ptr);
Jaswinder Singh Rajput9766cdb2009-03-14 11:19:49 +0530393DECLARE_PER_CPU(unsigned int, irq_count);
Jaswinder Singh Rajput9766cdb2009-03-14 11:19:49 +0530394extern asmlinkage void ignore_sysret(void);
Tejun Heo60a53172009-02-09 22:17:40 +0900395#else /* X86_64 */
396#ifdef CONFIG_CC_STACKPROTECTOR
Jeremy Fitzhardinge1ea0d142009-09-03 12:27:15 -0700397/*
398 * Make sure stack canary segment base is cached-aligned:
399 * "For Intel Atom processors, avoid non zero segment base address
400 * that is not aligned to cache line boundary at all cost."
401 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
402 */
403struct stack_canary {
404 char __pad[20]; /* canary at %gs:20 */
405 unsigned long canary;
406};
Jeremy Fitzhardinge53f82452009-09-03 14:31:44 -0700407DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
Thomas Gleixner96a388d2007-10-11 11:20:03 +0200408#endif
Steven Rostedt198d2082014-02-06 09:41:31 -0500409/*
410 * per-CPU IRQ handling stacks
411 */
412struct irq_stack {
413 u32 stack[THREAD_SIZE/sizeof(u32)];
414} __aligned(THREAD_SIZE);
415
416DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
417DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
Tejun Heo60a53172009-02-09 22:17:40 +0900418#endif /* X86_64 */
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100419
Fenghua Yubf15a8c2016-05-20 10:47:06 -0700420extern unsigned int fpu_kernel_xstate_size;
Fenghua Yua1141e02016-05-20 10:47:05 -0700421extern unsigned int fpu_user_xstate_size;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100422
Frederic Weisbecker24f1e32c2009-09-09 19:22:48 +0200423struct perf_event;
424
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700425typedef struct {
426 unsigned long seg;
427} mm_segment_t;
428
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100429struct thread_struct {
Ingo Molnar4d46a892008-02-21 04:24:40 +0100430 /* Cached TLS descriptors: */
431 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
432 unsigned long sp0;
433 unsigned long sp;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100434#ifdef CONFIG_X86_32
Ingo Molnar4d46a892008-02-21 04:24:40 +0100435 unsigned long sysenter_cs;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100436#else
Ingo Molnar4d46a892008-02-21 04:24:40 +0100437 unsigned short es;
438 unsigned short ds;
439 unsigned short fsindex;
440 unsigned short gsindex;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100441#endif
Andy Lutomirskib9d989c2016-09-13 14:29:21 -0700442
443 u32 status; /* thread synchronous flags */
444
Alexey Dobriyand756f4ad2009-05-04 03:29:52 +0400445#ifdef CONFIG_X86_64
Andy Lutomirski296f7812016-04-26 12:23:29 -0700446 unsigned long fsbase;
447 unsigned long gsbase;
448#else
449 /*
450 * XXX: this could presumably be unsigned short. Alternatively,
451 * 32-bit kernels could be taught to use fsindex instead.
452 */
453 unsigned long fs;
454 unsigned long gs;
Alexey Dobriyand756f4ad2009-05-04 03:29:52 +0400455#endif
Ingo Molnarc5bedc62015-04-23 12:49:20 +0200456
Frederic Weisbecker24f1e32c2009-09-09 19:22:48 +0200457 /* Save middle states of ptrace breakpoints */
458 struct perf_event *ptrace_bps[HBP_NUM];
459 /* Debug status used for traps, single steps, etc... */
460 unsigned long debugreg6;
Frederic Weisbecker326264a2010-02-18 18:24:18 +0100461 /* Keep track of the exact dr7 value set by the user */
462 unsigned long ptrace_dr7;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100463 /* Fault info: */
464 unsigned long cr2;
Srikar Dronamraju51e7dc72012-03-12 14:55:55 +0530465 unsigned long trap_nr;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100466 unsigned long error_code;
Brian Gerst9fda6a02015-07-29 01:41:16 -0400467#ifdef CONFIG_VM86
Ingo Molnar4d46a892008-02-21 04:24:40 +0100468 /* Virtual 86 mode info */
Brian Gerst9fda6a02015-07-29 01:41:16 -0400469 struct vm86 *vm86;
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100470#endif
Ingo Molnar4d46a892008-02-21 04:24:40 +0100471 /* IO permissions: */
472 unsigned long *io_bitmap_ptr;
473 unsigned long iopl;
474 /* Max allowed port in the bitmap, in bytes: */
475 unsigned io_bitmap_max;
Dave Hansen0c8c0f02015-07-17 12:28:11 +0200476
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700477 mm_segment_t addr_limit;
478
Ingo Molnar2a53ccb2016-07-15 10:21:11 +0200479 unsigned int sig_on_uaccess_err:1;
Andy Lutomirskidfa9a942016-07-14 13:22:56 -0700480 unsigned int uaccess_err:1; /* uaccess failed */
481
Dave Hansen0c8c0f02015-07-17 12:28:11 +0200482 /* Floating point and extended processor state */
483 struct fpu fpu;
484 /*
485 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
486 * the end.
487 */
Glauber de Oliveira Costacb38d372008-01-30 13:31:31 +0100488};
489
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100490/*
Andy Lutomirskib9d989c2016-09-13 14:29:21 -0700491 * Thread-synchronous status.
492 *
493 * This is different from the flags in that nobody else
494 * ever touches our thread-synchronous status, so we don't
495 * have to worry about atomic accesses.
496 */
497#define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
498
499/*
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100500 * Set IOPL bits in EFLAGS from given mask
501 */
502static inline void native_set_iopl_mask(unsigned mask)
503{
504#ifdef CONFIG_X86_32
505 unsigned int reg;
Ingo Molnar4d46a892008-02-21 04:24:40 +0100506
Joe Perchescca2e6f2008-03-23 01:03:15 -0700507 asm volatile ("pushfl;"
508 "popl %0;"
509 "andl %1, %0;"
510 "orl %2, %0;"
511 "pushl %0;"
512 "popfl"
513 : "=&r" (reg)
514 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100515#endif
516}
517
Ingo Molnar4d46a892008-02-21 04:24:40 +0100518static inline void
519native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100520{
521 tss->x86_tss.sp0 = thread->sp0;
522#ifdef CONFIG_X86_32
Ingo Molnar4d46a892008-02-21 04:24:40 +0100523 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100524 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
525 tss->x86_tss.ss1 = thread->sysenter_cs;
526 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
527 }
528#endif
529}
Glauber de Oliveira Costa1b46cbe2008-01-30 13:31:27 +0100530
Glauber de Oliveira Costae801f862008-01-30 13:32:08 +0100531static inline void native_swapgs(void)
532{
533#ifdef CONFIG_X86_64
534 asm volatile("swapgs" ::: "memory");
535#endif
536}
537
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800538static inline unsigned long current_top_of_stack(void)
Andy Lutomirski8ef46a62015-03-05 19:19:02 -0800539{
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800540#ifdef CONFIG_X86_64
Andy Lutomirski24933b82015-03-05 19:19:05 -0800541 return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
Andy Lutomirskia7fcf282015-03-06 17:50:19 -0800542#else
543 /* sp0 on x86_32 is special in and around vm86 mode. */
544 return this_cpu_read_stable(cpu_current_top_of_stack);
545#endif
Andy Lutomirski8ef46a62015-03-05 19:19:02 -0800546}
547
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100548#ifdef CONFIG_PARAVIRT
549#include <asm/paravirt.h>
550#else
Ingo Molnar4d46a892008-02-21 04:24:40 +0100551#define __cpuid native_cpuid
Glauber de Oliveira Costa1b46cbe2008-01-30 13:31:27 +0100552
Joe Perchescca2e6f2008-03-23 01:03:15 -0700553static inline void load_sp0(struct tss_struct *tss,
554 struct thread_struct *thread)
Glauber de Oliveira Costa7818a1e2008-01-30 13:31:31 +0100555{
556 native_load_sp0(tss, thread);
557}
558
Glauber de Oliveira Costa62d7d7e2008-01-30 13:31:27 +0100559#define set_iopl_mask native_set_iopl_mask
Glauber de Oliveira Costa1b46cbe2008-01-30 13:31:27 +0100560#endif /* CONFIG_PARAVIRT */
561
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100562/* Free all resources held by a thread. */
563extern void release_thread(struct task_struct *);
564
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100565unsigned long get_wchan(struct task_struct *p);
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100566
567/*
568 * Generic CPUID function
569 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
570 * resulting in stale register contents being returned.
571 */
572static inline void cpuid(unsigned int op,
573 unsigned int *eax, unsigned int *ebx,
574 unsigned int *ecx, unsigned int *edx)
575{
576 *eax = op;
577 *ecx = 0;
578 __cpuid(eax, ebx, ecx, edx);
579}
580
581/* Some CPUID calls want 'count' to be placed in ecx */
582static inline void cpuid_count(unsigned int op, int count,
583 unsigned int *eax, unsigned int *ebx,
584 unsigned int *ecx, unsigned int *edx)
585{
586 *eax = op;
587 *ecx = count;
588 __cpuid(eax, ebx, ecx, edx);
589}
590
591/*
592 * CPUID functions returning a single datum
593 */
594static inline unsigned int cpuid_eax(unsigned int op)
595{
596 unsigned int eax, ebx, ecx, edx;
597
598 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100599
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100600 return eax;
601}
Ingo Molnar4d46a892008-02-21 04:24:40 +0100602
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100603static inline unsigned int cpuid_ebx(unsigned int op)
604{
605 unsigned int eax, ebx, ecx, edx;
606
607 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100608
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100609 return ebx;
610}
Ingo Molnar4d46a892008-02-21 04:24:40 +0100611
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100612static inline unsigned int cpuid_ecx(unsigned int op)
613{
614 unsigned int eax, ebx, ecx, edx;
615
616 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100617
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100618 return ecx;
619}
Ingo Molnar4d46a892008-02-21 04:24:40 +0100620
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100621static inline unsigned int cpuid_edx(unsigned int op)
622{
623 unsigned int eax, ebx, ecx, edx;
624
625 cpuid(op, &eax, &ebx, &ecx, &edx);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100626
Glauber de Oliveira Costac758ecf2008-01-30 13:31:03 +0100627 return edx;
628}
629
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100630/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
Denys Vlasenko0b101e62015-09-24 14:02:29 +0200631static __always_inline void rep_nop(void)
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100632{
Joe Perchescca2e6f2008-03-23 01:03:15 -0700633 asm volatile("rep; nop" ::: "memory");
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100634}
635
Denys Vlasenko0b101e62015-09-24 14:02:29 +0200636static __always_inline void cpu_relax(void)
Ingo Molnar4d46a892008-02-21 04:24:40 +0100637{
638 rep_nop();
639}
640
Andy Lutomirskic198b122016-12-09 10:24:08 -0800641/*
642 * This function forces the icache and prefetched instruction stream to
643 * catch up with reality in two very specific cases:
644 *
645 * a) Text was modified using one virtual address and is about to be executed
646 * from the same physical page at a different virtual address.
647 *
648 * b) Text was modified on a different CPU, may subsequently be
649 * executed on this CPU, and you want to make sure the new version
650 * gets executed. This generally means you're calling this in a IPI.
651 *
652 * If you're calling this for a different reason, you're probably doing
653 * it wrong.
654 */
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100655static inline void sync_core(void)
656{
Andy Lutomirskic198b122016-12-09 10:24:08 -0800657 /*
658 * There are quite a few ways to do this. IRET-to-self is nice
659 * because it works on every CPU, at any CPL (so it's compatible
660 * with paravirtualization), and it never exits to a hypervisor.
661 * The only down sides are that it's a bit slow (it seems to be
662 * a bit more than 2x slower than the fastest options) and that
663 * it unmasks NMIs. The "push %cs" is needed because, in
664 * paravirtual environments, __KERNEL_CS may not be a valid CS
665 * value when we do IRET directly.
666 *
667 * In case NMI unmasking or performance ever becomes a problem,
668 * the next best option appears to be MOV-to-CR2 and an
669 * unconditional jump. That sequence also works on all CPUs,
670 * but it will fault at CPL3 (i.e. Xen PV and lguest).
671 *
672 * CPUID is the conventional way, but it's nasty: it doesn't
673 * exist on some 486-like CPUs, and it usually exits to a
674 * hypervisor.
675 *
676 * Like all of Linux's memory ordering operations, this is a
677 * compiler barrier as well.
678 */
679 register void *__sp asm(_ASM_SP);
Ingo Molnar4d46a892008-02-21 04:24:40 +0100680
Andy Lutomirski1c52d852016-12-09 10:24:05 -0800681#ifdef CONFIG_X86_32
Andy Lutomirskic198b122016-12-09 10:24:08 -0800682 asm volatile (
683 "pushfl\n\t"
684 "pushl %%cs\n\t"
685 "pushl $1f\n\t"
686 "iret\n\t"
687 "1:"
688 : "+r" (__sp) : : "memory");
H. Peter Anvin45c39fb2012-11-28 11:50:30 -0800689#else
Andy Lutomirskic198b122016-12-09 10:24:08 -0800690 unsigned int tmp;
691
692 asm volatile (
693 "mov %%ss, %0\n\t"
694 "pushq %q0\n\t"
695 "pushq %%rsp\n\t"
696 "addq $8, (%%rsp)\n\t"
697 "pushfq\n\t"
698 "mov %%cs, %0\n\t"
699 "pushq %q0\n\t"
700 "pushq $1f\n\t"
701 "iretq\n\t"
702 "1:"
703 : "=&r" (tmp), "+r" (__sp) : : "cc", "memory");
Ben Hutchings5367b682009-09-10 02:53:50 +0100704#endif
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100705}
706
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100707extern void select_idle_routine(const struct cpuinfo_x86 *c);
Borislav Petkov07c94a32016-12-09 19:29:11 +0100708extern void amd_e400_c1e_apic_setup(void);
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100709
Ingo Molnar4d46a892008-02-21 04:24:40 +0100710extern unsigned long boot_option_idle_override;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100711
Thomas Renningerd1896042010-11-03 17:06:14 +0100712enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
Len Brown69fb3672013-02-10 01:38:39 -0500713 IDLE_POLL};
Thomas Renningerd1896042010-11-03 17:06:14 +0100714
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100715extern void enable_sep_cpu(void);
716extern int sysenter_setup(void);
717
Jan Kiszka29c84392010-05-20 21:04:29 -0500718extern void early_trap_init(void);
H. Peter Anvin8170e6b2013-01-24 12:19:52 -0800719void early_trap_pf_init(void);
Jan Kiszka29c84392010-05-20 21:04:29 -0500720
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100721/* Defined in head.S */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100722extern struct desc_ptr early_gdt_descr;
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100723
724extern void cpu_set_gdt(int);
Brian Gerst552be872009-01-30 17:47:53 +0900725extern void switch_to_new_gdt(int);
Thomas Garnier45fc8752017-03-14 10:05:08 -0700726extern void load_direct_gdt(int);
Thomas Garnier69218e42017-03-14 10:05:07 -0700727extern void load_fixmap_gdt(int);
Jeremy Fitzhardinge11e3a842009-01-30 17:47:54 +0900728extern void load_percpu_segment(int);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100729extern void cpu_init(void);
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100730
Markus Metzgerc2724772008-12-11 13:49:59 +0100731static inline unsigned long get_debugctlmsr(void)
732{
Peter Zijlstraea8e61b2010-03-25 14:51:51 +0100733 unsigned long debugctlmsr = 0;
Markus Metzgerc2724772008-12-11 13:49:59 +0100734
735#ifndef CONFIG_X86_DEBUGCTLMSR
736 if (boot_cpu_data.x86 < 6)
737 return 0;
738#endif
739 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
740
Peter Zijlstraea8e61b2010-03-25 14:51:51 +0100741 return debugctlmsr;
Markus Metzgerc2724772008-12-11 13:49:59 +0100742}
743
Jan Beulich5b0e5082008-03-10 13:11:17 +0000744static inline void update_debugctlmsr(unsigned long debugctlmsr)
745{
746#ifndef CONFIG_X86_DEBUGCTLMSR
747 if (boot_cpu_data.x86 < 6)
748 return;
749#endif
750 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
751}
752
Oleg Nesterov9bd11902012-09-03 15:24:17 +0200753extern void set_task_blockstep(struct task_struct *task, bool on);
754
Ingo Molnar4d46a892008-02-21 04:24:40 +0100755/* Boot loader type from the setup header: */
756extern int bootloader_type;
H. Peter Anvin50312962009-05-07 16:54:11 -0700757extern int bootloader_version;
Glauber de Oliveira Costa1a539052008-01-30 13:31:39 +0100758
Ingo Molnar4d46a892008-02-21 04:24:40 +0100759extern char ignore_fpu_irq;
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100760
761#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
762#define ARCH_HAS_PREFETCHW
763#define ARCH_HAS_SPINLOCK_PREFETCH
764
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100765#ifdef CONFIG_X86_32
Borislav Petkova930dc42015-01-18 17:48:18 +0100766# define BASE_PREFETCH ""
Ingo Molnar4d46a892008-02-21 04:24:40 +0100767# define ARCH_HAS_PREFETCH
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100768#else
Borislav Petkova930dc42015-01-18 17:48:18 +0100769# define BASE_PREFETCH "prefetcht0 %P1"
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100770#endif
771
Ingo Molnar4d46a892008-02-21 04:24:40 +0100772/*
773 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
774 *
775 * It's not worth to care about 3dnow prefetches for the K6
776 * because they are microcoded there and very slow.
777 */
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100778static inline void prefetch(const void *x)
779{
Borislav Petkova930dc42015-01-18 17:48:18 +0100780 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100781 X86_FEATURE_XMM,
Borislav Petkova930dc42015-01-18 17:48:18 +0100782 "m" (*(const char *)x));
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100783}
784
Ingo Molnar4d46a892008-02-21 04:24:40 +0100785/*
786 * 3dnow prefetch to get an exclusive cache line.
787 * Useful for spinlocks to avoid one state transition in the
788 * cache coherency protocol:
789 */
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100790static inline void prefetchw(const void *x)
791{
Borislav Petkova930dc42015-01-18 17:48:18 +0100792 alternative_input(BASE_PREFETCH, "prefetchw %P1",
793 X86_FEATURE_3DNOWPREFETCH,
794 "m" (*(const char *)x));
Glauber de Oliveira Costaae2e15e2008-01-30 13:31:40 +0100795}
796
Ingo Molnar4d46a892008-02-21 04:24:40 +0100797static inline void spin_lock_prefetch(const void *x)
798{
799 prefetchw(x);
800}
801
Andy Lutomirskid9e05cc2015-03-10 11:05:59 -0700802#define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
803 TOP_OF_KERNEL_STACK_PADDING)
804
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100805#ifdef CONFIG_X86_32
806/*
807 * User space process size: 3GB (default).
808 */
Dmitry Safonov8f3e4742017-03-06 17:17:18 +0300809#define IA32_PAGE_OFFSET PAGE_OFFSET
Ingo Molnar4d46a892008-02-21 04:24:40 +0100810#define TASK_SIZE PAGE_OFFSET
Ingo Molnard9517342009-02-20 23:32:28 +0100811#define TASK_SIZE_MAX TASK_SIZE
Ingo Molnar4d46a892008-02-21 04:24:40 +0100812#define STACK_TOP TASK_SIZE
813#define STACK_TOP_MAX STACK_TOP
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100814
Ingo Molnar4d46a892008-02-21 04:24:40 +0100815#define INIT_THREAD { \
Andy Lutomirskid9e05cc2015-03-10 11:05:59 -0700816 .sp0 = TOP_OF_INIT_STACK, \
Ingo Molnar4d46a892008-02-21 04:24:40 +0100817 .sysenter_cs = __KERNEL_CS, \
818 .io_bitmap_ptr = NULL, \
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700819 .addr_limit = KERNEL_DS, \
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100820}
821
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100822/*
Denys Vlasenko5c394032015-03-13 15:09:03 +0100823 * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100824 * This is necessary to guarantee that the entire "struct pt_regs"
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400825 * is accessible even if the CPU haven't stored the SS/ESP registers
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100826 * on the stack (interrupt gate does not save these registers
827 * when switching to the same priv ring).
828 * Therefore beware: accessing the ss/esp fields of the
829 * "struct pt_regs" is possible, but they may contain the
830 * completely wrong values.
831 */
Denys Vlasenko5c394032015-03-13 15:09:03 +0100832#define task_pt_regs(task) \
833({ \
834 unsigned long __ptr = (unsigned long)task_stack_page(task); \
835 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
836 ((struct pt_regs *)__ptr) - 1; \
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100837})
838
Ingo Molnar4d46a892008-02-21 04:24:40 +0100839#define KSTK_ESP(task) (task_pt_regs(task)->sp)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100840
841#else
842/*
Andy Lutomirski07114f02014-11-04 15:46:21 -0800843 * User space process size. 47bits minus one guard page. The guard
844 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
845 * the highest possible canonical userspace address, then that
846 * syscall will enter the kernel with a non-canonical return
847 * address, and SYSRET will explode dangerously. We avoid this
848 * particular problem by preventing anything from being mapped
849 * at the maximum canonical address.
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100850 */
Ingo Molnard9517342009-02-20 23:32:28 +0100851#define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100852
853/* This decides where the kernel will search for a free chunk of vm
854 * space during mmap's.
855 */
Ingo Molnar4d46a892008-02-21 04:24:40 +0100856#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
857 0xc0000000 : 0xFFFFe000)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100858
H. Peter Anvin6bd33002012-02-06 13:03:09 -0800859#define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
Ingo Molnard9517342009-02-20 23:32:28 +0100860 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
H. Peter Anvin6bd33002012-02-06 13:03:09 -0800861#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
Ingo Molnard9517342009-02-20 23:32:28 +0100862 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100863
David Howells922a70d2008-02-08 04:19:26 -0800864#define STACK_TOP TASK_SIZE
Ingo Molnard9517342009-02-20 23:32:28 +0100865#define STACK_TOP_MAX TASK_SIZE_MAX
David Howells922a70d2008-02-08 04:19:26 -0800866
Andy Lutomirski13d4ea02016-07-14 13:22:57 -0700867#define INIT_THREAD { \
868 .sp0 = TOP_OF_INIT_STACK, \
869 .addr_limit = KERNEL_DS, \
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100870}
871
Ingo Molnar4d46a892008-02-21 04:24:40 +0100872#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
Stefani Seibold89240ba2009-11-03 10:22:40 +0100873extern unsigned long KSTK_ESP(struct task_struct *task);
H. J. Lud046ff82012-02-14 13:49:48 -0800874
Glauber de Oliveira Costa2f66dcc2008-01-30 13:31:57 +0100875#endif /* CONFIG_X86_64 */
876
Ingo Molnar513ad842008-02-21 05:18:40 +0100877extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
878 unsigned long new_sp);
879
Ingo Molnar4d46a892008-02-21 04:24:40 +0100880/*
881 * This decides where the kernel will search for a free chunk of vm
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100882 * space during mmap's.
883 */
Dmitry Safonov8f3e4742017-03-06 17:17:18 +0300884#define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
885#define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE)
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100886
Ingo Molnar4d46a892008-02-21 04:24:40 +0100887#define KSTK_EIP(task) (task_pt_regs(task)->ip)
Glauber de Oliveira Costa683e0252008-01-30 13:31:27 +0100888
Erik Bosman529e25f2008-04-14 00:24:18 +0200889/* Get/set a process' ability to use the timestamp counter instruction */
890#define GET_TSC_CTL(adr) get_tsc_mode((adr))
891#define SET_TSC_CTL(val) set_tsc_mode((val))
892
893extern int get_tsc_mode(unsigned long adr);
894extern int set_tsc_mode(unsigned int val);
895
Kyle Hueye9ea1e72017-03-20 01:16:26 -0700896DECLARE_PER_CPU(u64, msr_misc_features_shadow);
897
Dave Hansenfe3d1972014-11-14 07:18:29 -0800898/* Register/unregister a process' MPX related resource */
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700899#define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
900#define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
Dave Hansenfe3d1972014-11-14 07:18:29 -0800901
902#ifdef CONFIG_X86_INTEL_MPX
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700903extern int mpx_enable_management(void);
904extern int mpx_disable_management(void);
Dave Hansenfe3d1972014-11-14 07:18:29 -0800905#else
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700906static inline int mpx_enable_management(void)
Dave Hansenfe3d1972014-11-14 07:18:29 -0800907{
908 return -EINVAL;
909}
Dave Hansen46a6e0c2015-06-07 11:37:02 -0700910static inline int mpx_disable_management(void)
Dave Hansenfe3d1972014-11-14 07:18:29 -0800911{
912 return -EINVAL;
913}
914#endif /* CONFIG_X86_INTEL_MPX */
915
Borislav Petkovbc8e80d2017-06-13 18:28:30 +0200916#ifdef CONFIG_CPU_SUP_AMD
Daniel J Blueman8b84c8d2012-11-27 14:32:10 +0800917extern u16 amd_get_nb_id(int cpu);
Aravind Gopalakrishnancc2749e2015-06-15 10:28:15 +0200918extern u32 amd_get_nodes_per_socket(void);
Borislav Petkovbc8e80d2017-06-13 18:28:30 +0200919#else
920static inline u16 amd_get_nb_id(int cpu) { return 0; }
921static inline u32 amd_get_nodes_per_socket(void) { return 0; }
922#endif
Andreas Herrmann6a812692009-09-16 11:33:40 +0200923
Jason Wang96e39ac2013-07-25 16:54:32 +0800924static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
925{
926 uint32_t base, eax, signature[3];
927
928 for (base = 0x40000000; base < 0x40010000; base += 0x100) {
929 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
930
931 if (!memcmp(sig, signature, 12) &&
932 (leaves == 0 || ((eax - base) >= leaves)))
933 return base;
934 }
935
936 return 0;
937}
938
David Howellsf05e7982012-03-28 18:11:12 +0100939extern unsigned long arch_align_stack(unsigned long sp);
940extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
941
942void default_idle(void);
Len Brown6a377dd2013-02-09 23:08:07 -0500943#ifdef CONFIG_XEN
944bool xen_set_default_idle(void);
945#else
946#define xen_set_default_idle 0
947#endif
David Howellsf05e7982012-03-28 18:11:12 +0100948
949void stop_this_cpu(void *dummy);
Borislav Petkov4d067d82013-05-09 12:02:29 +0200950void df_debug(struct pt_regs *regs, long error_code);
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700951#endif /* _ASM_X86_PROCESSOR_H */