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Mathieu Poirier8a9fd832018-04-18 16:05:18 -06001/* SPDX-License-Identifier: GPL-2.0 */
Mathieu Poirier0bcbf2e2016-02-17 17:52:01 -07002/*
3 * Copyright(C) 2015 Linaro Limited. All rights reserved.
4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
Mathieu Poirier0bcbf2e2016-02-17 17:52:01 -07005 */
6
7#ifndef _LINUX_CORESIGHT_PMU_H
8#define _LINUX_CORESIGHT_PMU_H
9
10#define CORESIGHT_ETM_PMU_NAME "cs_etm"
Mathieu Poirier17534ce2016-02-17 17:52:02 -070011#define CORESIGHT_ETM_PMU_SEED 0x10
Mathieu Poirier0bcbf2e2016-02-17 17:52:01 -070012
13/* ETMv3.5/PTM's ETMCR config bit */
14#define ETM_OPT_CYCACC 12
15#define ETM_OPT_TS 28
Mike Leachb97971b2017-08-02 10:22:01 -060016#define ETM_OPT_RETSTK 29
Mathieu Poirier0bcbf2e2016-02-17 17:52:01 -070017
Mike Leachdf770ff2017-08-02 10:22:19 -060018/* ETMv4 CONFIGR programming bits for the ETM OPTs */
19#define ETM4_CFG_BIT_CYCACC 4
20#define ETM4_CFG_BIT_TS 11
21#define ETM4_CFG_BIT_RETSTK 12
22
Mathieu Poirier17534ce2016-02-17 17:52:02 -070023static inline int coresight_get_trace_id(int cpu)
24{
25 /*
26 * A trace ID of value 0 is invalid, so let's start at some
27 * random value that fits in 7 bits and go from there. Since
28 * the common convention is to have data trace IDs be I(N) + 1,
29 * set instruction trace IDs as a function of the CPU number.
30 */
31 return (CORESIGHT_ETM_PMU_SEED + (cpu * 2));
32}
33
Mathieu Poirier0bcbf2e2016-02-17 17:52:01 -070034#endif