Mathieu Poirier | 8a9fd83 | 2018-04-18 16:05:18 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright(C) 2015 Linaro Limited. All rights reserved. |
| 4 | * Author: Mathieu Poirier <mathieu.poirier@linaro.org> |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _LINUX_CORESIGHT_PMU_H |
| 8 | #define _LINUX_CORESIGHT_PMU_H |
| 9 | |
| 10 | #define CORESIGHT_ETM_PMU_NAME "cs_etm" |
Mathieu Poirier | 17534ce | 2016-02-17 17:52:02 -0700 | [diff] [blame] | 11 | #define CORESIGHT_ETM_PMU_SEED 0x10 |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 12 | |
| 13 | /* ETMv3.5/PTM's ETMCR config bit */ |
| 14 | #define ETM_OPT_CYCACC 12 |
| 15 | #define ETM_OPT_TS 28 |
Mike Leach | b97971b | 2017-08-02 10:22:01 -0600 | [diff] [blame] | 16 | #define ETM_OPT_RETSTK 29 |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 17 | |
Mike Leach | df770ff | 2017-08-02 10:22:19 -0600 | [diff] [blame] | 18 | /* ETMv4 CONFIGR programming bits for the ETM OPTs */ |
| 19 | #define ETM4_CFG_BIT_CYCACC 4 |
| 20 | #define ETM4_CFG_BIT_TS 11 |
| 21 | #define ETM4_CFG_BIT_RETSTK 12 |
| 22 | |
Mathieu Poirier | 17534ce | 2016-02-17 17:52:02 -0700 | [diff] [blame] | 23 | static inline int coresight_get_trace_id(int cpu) |
| 24 | { |
| 25 | /* |
| 26 | * A trace ID of value 0 is invalid, so let's start at some |
| 27 | * random value that fits in 7 bits and go from there. Since |
| 28 | * the common convention is to have data trace IDs be I(N) + 1, |
| 29 | * set instruction trace IDs as a function of the CPU number. |
| 30 | */ |
| 31 | return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); |
| 32 | } |
| 33 | |
Mathieu Poirier | 0bcbf2e | 2016-02-17 17:52:01 -0700 | [diff] [blame] | 34 | #endif |