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Thomas Gleixnerec8f24b2019-05-19 13:07:45 +01001# SPDX-License-Identifier: GPL-2.0-only
Rob Herring30058672013-01-28 16:13:14 +00002menuconfig MAILBOX
3 bool "Mailbox Hardware Support"
4 help
5 Mailbox is a framework to control hardware communication between
6 on-chip processors through queued messages and interrupt driven
7 signals. Say Y if your platform supports hardware mailboxes.
8
9if MAILBOX
Jassi Braree23d662014-06-26 19:09:42 +053010
11config ARM_MHU
12 tristate "ARM MHU Mailbox"
13 depends on ARM_AMBA
14 help
15 Say Y here if you want to build the ARM MHU controller driver.
16 The controller has 3 mailbox channels, the last of which can be
17 used in Secure mode only.
18
Oleksij Rempel2bb70052018-08-03 07:29:19 +020019config IMX_MBOX
20 tristate "i.MX Mailbox"
21 depends on ARCH_MXC || COMPILE_TEST
22 help
23 Mailbox implementation for i.MX Messaging Unit (MU).
24
Neil Armstrongad3a2122016-08-18 12:10:25 +020025config PLATFORM_MHU
26 tristate "Platform MHU Mailbox"
27 depends on OF
28 depends on HAS_IOMEM
29 help
30 Say Y here if you want to build a platform specific variant MHU
31 controller driver.
32 The controller has a maximum of 3 mailbox channels, the last of
33 which can be used in Secure mode only.
34
Rob Herring30058672013-01-28 16:13:14 +000035config PL320_MBOX
36 bool "ARM PL320 Mailbox"
37 depends on ARM_AMBA
38 help
39 An implementation of the ARM PL320 Interprocessor Communication
40 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
41 send short messages between Highbank's A9 cores and the EnergyCore
42 Management Engine, primarily for cpufreq. Say Y here if you want
43 to use the PL320 IPCM support.
44
Marek Behun8fbbfd92019-03-31 05:15:33 +020045config ARMADA_37XX_RWTM_MBOX
46 tristate "Armada 37xx rWTM BIU Mailbox"
47 depends on ARCH_MVEBU || COMPILE_TEST
48 depends on OF
49 help
50 Mailbox implementation for communication with the the firmware
51 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
52 SOC. Say Y here if you are building for such a device (for example
53 the Turris Mox router).
54
Suman Annac869c752013-03-12 17:55:29 -050055config OMAP2PLUS_MBOX
56 tristate "OMAP2+ Mailbox framework support"
57 depends on ARCH_OMAP2PLUS
Suman Annac869c752013-03-12 17:55:29 -050058 help
59 Mailbox implementation for OMAP family chips with hardware for
60 interprocessor communication involving DSP, IVA1.0 and IVA2 in
61 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
62 want to use OMAP2+ Mailbox framework support.
63
64config OMAP_MBOX_KFIFO_SIZE
65 int "Mailbox kfifo default buffer size (bytes)"
Suman Anna79859092014-06-24 19:43:38 -050066 depends on OMAP2PLUS_MBOX
Suman Annac869c752013-03-12 17:55:29 -050067 default 256
68 help
69 Specify the default size of mailbox's kfifo buffers (bytes).
70 This can also be changed at runtime (via the mbox_kfifo_size
71 module parameter).
Ashwin Chaugule86c22f82014-11-12 19:59:38 -050072
Caesar Wangf70ed3b2015-10-27 15:31:45 +080073config ROCKCHIP_MBOX
74 bool "Rockchip Soc Intergrated Mailbox Support"
75 depends on ARCH_ROCKCHIP || COMPILE_TEST
76 help
77 This driver provides support for inter-processor communication
78 between CPU cores and MCU processor on Some Rockchip SOCs.
79 Please check it that the Soc you use have Mailbox hardware.
80 Say Y here if you want to use the Rockchip Mailbox support.
81
Ashwin Chaugule86c22f82014-11-12 19:59:38 -050082config PCC
83 bool "Platform Communication Channel Driver"
84 depends on ACPI
Ashwin Chauguleb6fc6072015-08-05 09:40:31 -040085 default n
Ashwin Chaugule86c22f82014-11-12 19:59:38 -050086 help
87 ACPI 5.0+ spec defines a generic mode of communication
88 between the OS and a platform such as the BMC. This medium
89 (PCC) is typically used by CPPC (ACPI CPU Performance management),
90 RAS (ACPI reliability protocol) and MPST (ACPI Memory power
91 states). Select this driver if your platform implements the
92 PCC clients mentioned above.
93
Ley Foon Tanf62092f2015-02-04 16:32:18 +080094config ALTERA_MBOX
95 tristate "Altera Mailbox"
Richard Weinberger59dd3f02015-05-04 20:59:46 +020096 depends on HAS_IOMEM
Ley Foon Tanf62092f2015-02-04 16:32:18 +080097 help
98 An implementation of the Altera Mailbox soft core. It is used
99 to send message between processors. Say Y here if you want to use the
100 Altera mailbox support.
Lubomir Rintel0bae6af2015-05-05 13:27:45 -0700101
102config BCM2835_MBOX
103 tristate "BCM2835 Mailbox"
104 depends on ARCH_BCM2835
105 help
106 An implementation of the BCM2385 Mailbox. It is used to invoke
107 the services of the Videocore. Say Y here if you want to use the
108 BCM2835 Mailbox.
109
Lee Jones9ef45462015-10-16 08:21:28 +0100110config STI_MBOX
111 tristate "STI Mailbox framework support"
112 depends on ARCH_STI && OF
113 help
114 Mailbox implementation for STMicroelectonics family chips with
115 hardware for interprocessor communication.
116
Nishanth Menonaace66b2016-03-16 19:23:14 -0500117config TI_MESSAGE_MANAGER
118 tristate "Texas Instruments Message Manager Driver"
Nishanth Menoncfc0f7a2018-08-27 19:53:11 -0500119 depends on ARCH_KEYSTONE || ARCH_K3
Nishanth Menonaace66b2016-03-16 19:23:14 -0500120 help
121 An implementation of Message Manager slave driver for Keystone
Nishanth Menoncfc0f7a2018-08-27 19:53:11 -0500122 and K3 architecture SoCs from Texas Instruments. Message Manager
123 is a communication entity found on few of Texas Instrument's keystone
124 and K3 architecture SoCs. These may be used for communication between
Nishanth Menonaace66b2016-03-16 19:23:14 -0500125 multiple processors within the SoC. Select this driver if your
126 platform has support for the hardware block.
127
Kaihua Zhong41c0e932018-02-28 12:54:54 +0800128config HI3660_MBOX
Daniel Lezcanof83d1cf2018-05-22 22:54:49 +0200129 tristate "Hi3660 Mailbox" if EXPERT
130 depends on (ARCH_HISI || COMPILE_TEST)
131 depends on OF
132 default ARCH_HISI
Kaihua Zhong41c0e932018-02-28 12:54:54 +0800133 help
134 An implementation of the hi3660 mailbox. It is used to send message
135 between application processors and other processors/MCU/DSP. Select
136 Y here if you want to use Hi3660 mailbox controller.
137
Leo Yan9c384182016-02-15 21:50:24 +0800138config HI6220_MBOX
Daniel Lezcanof83d1cf2018-05-22 22:54:49 +0200139 tristate "Hi6220 Mailbox" if EXPERT
140 depends on (ARCH_HISI || COMPILE_TEST)
141 depends on OF
142 default ARCH_HISI
Leo Yan9c384182016-02-15 21:50:24 +0800143 help
144 An implementation of the hi6220 mailbox. It is used to send message
145 between application processors and MCU. Say Y here if you want to
146 build Hi6220 mailbox controller driver.
147
Lee Jones8ea44842015-10-16 08:21:30 +0100148config MAILBOX_TEST
149 tristate "Mailbox Test Client"
150 depends on OF
Richard Weinberger65d3b042016-01-25 23:24:09 +0100151 depends on HAS_IOMEM
Lee Jones8ea44842015-10-16 08:21:30 +0100152 help
153 Test client to help with testing new Controller driver
154 implementations.
155
Bjorn Andersson25bfee12017-05-27 16:14:04 -0700156config QCOM_APCS_IPC
157 tristate "Qualcomm APCS IPC driver"
158 depends on ARCH_QCOM || COMPILE_TEST
159 help
160 Say y here to enable support for the APCS IPC mailbox driver,
161 providing an interface for invoking the inter-process communication
162 signals from the application processor to other masters.
163
Thierry Reding0fe88462016-08-19 19:19:39 +0200164config TEGRA_HSP_MBOX
165 bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
Arnd Bergmann85bd2de2018-03-13 13:11:43 +0100166 depends on ARCH_TEGRA
Thierry Reding0fe88462016-08-19 19:19:39 +0200167 help
168 The Tegra HSP driver is used for the interprocessor communication
169 between different remote processors and host processors on Tegra186
170 and later SoCs. Say Y here if you want to have this support.
171 If unsure say N.
172
Duc Dangf700e842016-02-12 19:39:26 -0800173config XGENE_SLIMPRO_MBOX
174 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
175 depends on ARCH_XGENE
176 help
177 An implementation of the APM X-Gene Interprocessor Communication
178 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
179 It is used to send short messages between ARM64-bit cores and
180 the SLIMpro Management Engine, primarily for PM. Say Y here if you
181 want to use the APM X-Gene SLIMpro IPCM support.
Rob Ricea24532f2016-06-30 15:59:23 -0400182
183config BCM_PDC_MBOX
Steve Linfc2041c2017-02-23 09:49:50 -0500184 tristate "Broadcom FlexSparx DMA Mailbox"
185 depends on ARCH_BCM_IPROC || COMPILE_TEST
Rob Ricea24532f2016-06-30 15:59:23 -0400186 help
Steve Linfc2041c2017-02-23 09:49:50 -0500187 Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
Rob Ricea24532f2016-06-30 15:59:23 -0400188 which provides access to various offload engines on Broadcom
Steve Linfc2041c2017-02-23 09:49:50 -0500189 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
Anup Pateldbc049e2017-03-15 12:10:00 +0530190
191config BCM_FLEXRM_MBOX
192 tristate "Broadcom FlexRM Mailbox"
Anup Patel73874912017-03-29 11:00:55 +0530193 depends on ARM64
Scott Branden8f821212017-10-03 10:51:50 +0530194 depends on ARCH_BCM_IPROC || COMPILE_TEST
Anup Pateldbc049e2017-03-15 12:10:00 +0530195 select GENERIC_MSI_IRQ_DOMAIN
Anup Patel22d28b02017-10-03 10:51:52 +0530196 default m if ARCH_BCM_IPROC
Anup Pateldbc049e2017-03-15 12:10:00 +0530197 help
198 Mailbox implementation of the Broadcom FlexRM ring manager,
199 which provides access to various offload engines on Broadcom
200 SoCs. Say Y here if you want to use the Broadcom FlexRM.
Fabien Dessenneffbded72018-05-31 10:27:25 +0200201
202config STM32_IPCC
203 tristate "STM32 IPCC Mailbox"
204 depends on MACH_STM32MP157
205 help
206 Mailbox implementation for STMicroelectonics STM32 family chips
207 with hardware for Inter-Processor Communication Controller (IPCC)
208 between processors. Say Y here if you want to have this support.
Houlong Wei623a6142018-07-25 09:26:40 +0800209
210config MTK_CMDQ_MBOX
211 tristate "MediaTek CMDQ Mailbox Support"
212 depends on ARCH_MEDIATEK || COMPILE_TEST
213 select MTK_INFRACFG
214 help
215 Say yes here to add support for the MediaTek Command Queue (CMDQ)
216 mailbox driver. The CMDQ is used to help read/write registers with
217 critical time limitation, such as updating display configuration
218 during the vblank.
Wendy Liang4981b822019-02-21 16:36:33 -0800219
220config ZYNQMP_IPI_MBOX
221 bool "Xilinx ZynqMP IPI Mailbox"
222 depends on ARCH_ZYNQMP && OF
223 help
224 Say yes here to add support for Xilinx IPI mailbox driver.
225 This mailbox driver is used to send notification or short message
226 between processors with Xilinx ZynqMP IPI. It will place the
227 message to the IPI buffer and will access the IPI control
228 registers to kick the other processor or enquire status.
229
Rob Herring30058672013-01-28 16:13:14 +0000230endif