Alexey Brodkin | a518d63 | 2017-08-15 21:13:55 +0300 | [diff] [blame] | 1 | /* |
| 2 | * ARC HSDK Platform support code |
| 3 | * |
| 4 | * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com) |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/smp.h> |
| 13 | #include <asm/arcregs.h> |
| 14 | #include <asm/io.h> |
| 15 | #include <asm/mach_desc.h> |
| 16 | |
| 17 | #define ARC_CCM_UNUSED_ADDR 0x60000000 |
| 18 | |
| 19 | static void __init hsdk_init_per_cpu(unsigned int cpu) |
| 20 | { |
| 21 | /* |
| 22 | * By default ICCM is mapped to 0x7z while this area is used for |
| 23 | * kernel virtual mappings, so move it to currently unused area. |
| 24 | */ |
| 25 | if (cpuinfo_arc700[cpu].iccm.sz) |
| 26 | write_aux_reg(ARC_REG_AUX_ICCM, ARC_CCM_UNUSED_ADDR); |
| 27 | |
| 28 | /* |
| 29 | * By default DCCM is mapped to 0x8z while this area is used by kernel, |
| 30 | * so move it to currently unused area. |
| 31 | */ |
| 32 | if (cpuinfo_arc700[cpu].dccm.sz) |
| 33 | write_aux_reg(ARC_REG_AUX_DCCM, ARC_CCM_UNUSED_ADDR); |
| 34 | } |
| 35 | |
| 36 | #define ARC_PERIPHERAL_BASE 0xf0000000 |
| 37 | #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000) |
| 38 | #define CREG_PAE (CREG_BASE + 0x180) |
| 39 | #define CREG_PAE_UPDATE (CREG_BASE + 0x194) |
| 40 | |
Eugeniy Paltsev | 753affb | 2017-10-11 20:01:42 +0300 | [diff] [blame] | 41 | #define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000) |
| 42 | #define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108) |
| 43 | #define SDIO_UHS_REG_EXT_DIV_2 (2 << 30) |
| 44 | |
Gustavo Pimentel | ec58ba1 | 2018-07-06 11:32:37 +0100 | [diff] [blame^] | 45 | #define HSDK_GPIO_INTC (ARC_PERIPHERAL_BASE + 0x3000) |
| 46 | |
| 47 | static void __init hsdk_enable_gpio_intc_wire(void) |
| 48 | { |
| 49 | /* |
| 50 | * Peripherals on CPU Card are wired to cpu intc via intermediate |
| 51 | * DW APB GPIO blocks (mainly for debouncing) |
| 52 | * |
| 53 | * --------------------- |
| 54 | * | snps,archs-intc | |
| 55 | * --------------------- |
| 56 | * | |
| 57 | * ---------------------- |
| 58 | * | snps,archs-idu-intc | |
| 59 | * ---------------------- |
| 60 | * | | | | | |
| 61 | * | [eth] [USB] [... other peripherals] |
| 62 | * | |
| 63 | * ------------------- |
| 64 | * | snps,dw-apb-intc | |
| 65 | * ------------------- |
| 66 | * | | | | |
| 67 | * [Bt] [HAPS] [... other peripherals] |
| 68 | * |
| 69 | * Current implementation of "irq-dw-apb-ictl" driver doesn't work well |
| 70 | * with stacked INTCs. In particular problem happens if its master INTC |
| 71 | * not yet instantiated. See discussion here - |
| 72 | * https://lkml.org/lkml/2015/3/4/755 |
| 73 | * |
| 74 | * So setup the first gpio block as a passive pass thru and hide it from |
| 75 | * DT hardware topology - connect intc directly to cpu intc |
| 76 | * The GPIO "wire" needs to be init nevertheless (here) |
| 77 | * |
| 78 | * One side adv is that peripheral interrupt handling avoids one nested |
| 79 | * intc ISR hop |
| 80 | * |
| 81 | * According to HSDK User's Manual [1], "Table 2 Interrupt Mapping" |
| 82 | * we have the following GPIO input lines used as sources of interrupt: |
| 83 | * - GPIO[0] - Bluetooth interrupt of RS9113 module |
| 84 | * - GPIO[2] - HAPS interrupt (on HapsTrak 3 connector) |
| 85 | * - GPIO[3] - Audio codec (MAX9880A) interrupt |
| 86 | * - GPIO[8-23] - Available on Arduino and PMOD_x headers |
| 87 | * For now there's no use of Arduino and PMOD_x headers in Linux |
| 88 | * use-case so we only enable lines 0, 2 and 3. |
| 89 | * |
| 90 | * [1] https://github.com/foss-for-synopsys-dwc-arc-processors/ARC-Development-Systems-Forum/wiki/docs/ARC_HSDK_User_Guide.pdf |
| 91 | */ |
| 92 | #define GPIO_INTEN (HSDK_GPIO_INTC + 0x30) |
| 93 | #define GPIO_INTMASK (HSDK_GPIO_INTC + 0x34) |
| 94 | #define GPIO_INTTYPE_LEVEL (HSDK_GPIO_INTC + 0x38) |
| 95 | #define GPIO_INT_POLARITY (HSDK_GPIO_INTC + 0x3c) |
| 96 | #define GPIO_INT_CONNECTED_MASK 0x0d |
| 97 | |
| 98 | iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK); |
| 99 | iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK); |
| 100 | iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL); |
| 101 | iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY); |
| 102 | iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN); |
| 103 | } |
| 104 | |
Alexey Brodkin | a518d63 | 2017-08-15 21:13:55 +0300 | [diff] [blame] | 105 | static void __init hsdk_init_early(void) |
| 106 | { |
| 107 | /* |
| 108 | * PAE remapping for DMA clients does not work due to an RTL bug, so |
| 109 | * CREG_PAE register must be programmed to all zeroes, otherwise it |
| 110 | * will cause problems with DMA to/from peripherals even if PAE40 is |
| 111 | * not used. |
| 112 | */ |
| 113 | |
| 114 | /* Default is 1, which means "PAE offset = 4GByte" */ |
| 115 | writel_relaxed(0, (void __iomem *) CREG_PAE); |
| 116 | |
| 117 | /* Really apply settings made above */ |
| 118 | writel(1, (void __iomem *) CREG_PAE_UPDATE); |
Eugeniy Paltsev | edb40d7 | 2017-09-28 17:33:29 +0300 | [diff] [blame] | 119 | |
| 120 | /* |
Eugeniy Paltsev | 753affb | 2017-10-11 20:01:42 +0300 | [diff] [blame] | 121 | * Switch SDIO external ciu clock divider from default div-by-8 to |
| 122 | * minimum possible div-by-2. |
| 123 | */ |
| 124 | iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT); |
Gustavo Pimentel | ec58ba1 | 2018-07-06 11:32:37 +0100 | [diff] [blame^] | 125 | |
| 126 | hsdk_enable_gpio_intc_wire(); |
Alexey Brodkin | a518d63 | 2017-08-15 21:13:55 +0300 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | static const char *hsdk_compat[] __initconst = { |
| 130 | "snps,hsdk", |
| 131 | NULL, |
| 132 | }; |
| 133 | |
| 134 | MACHINE_START(SIMULATION, "hsdk") |
| 135 | .dt_compat = hsdk_compat, |
| 136 | .init_early = hsdk_init_early, |
| 137 | .init_per_cpu = hsdk_init_per_cpu, |
| 138 | MACHINE_END |