| Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 2 | #ifndef _ASM_X86_CACHEFLUSH_H |
| 3 | #define _ASM_X86_CACHEFLUSH_H |
| Thomas Gleixner | b2bba72 | 2007-10-15 23:28:20 +0200 | [diff] [blame] | 4 | |
| Thomas Gleixner | b2bba72 | 2007-10-15 23:28:20 +0200 | [diff] [blame] | 5 | /* Caches aren't brain-dead on the intel. */ |
| Akinobu Mita | cc67ba63 | 2011-01-20 20:32:14 +0900 | [diff] [blame] | 6 | #include <asm-generic/cacheflush.h> |
| David Howells | f05e798 | 2012-03-28 18:11:12 +0100 | [diff] [blame] | 7 | #include <asm/special_insns.h> |
| Arjan van de Ven | 7219beb | 2008-04-17 17:41:31 +0200 | [diff] [blame] | 8 | |
| Ingo Molnar | 4c61afc | 2008-01-30 13:34:09 +0100 | [diff] [blame] | 9 | void clflush_cache_range(void *addr, unsigned int size); |
| Thomas Gleixner | b2bba72 | 2007-10-15 23:28:20 +0200 | [diff] [blame] | 10 | |
| H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 11 | #endif /* _ASM_X86_CACHEFLUSH_H */ |