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review.shift-gmbh.com / SHIFTPHONES / kernel / common / e9d90d472da97e1b1560bffb89578ba082c88a69 / . / arch / x86 / kvm / lapic.h
blob: d7251c92ed426ef96cb48a74edc958cf45fe69ee [file] [log] [blame]
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]1#ifndef __KVM_X86_LAPIC_H
2#define __KVM_X86_LAPIC_H
3
4#include "iodev.h"
5
6#include <linux/kvm_host.h>
7
Avi Kivitye9d90d42012-07-26 18:01:50 +0300[diff] [blame^]8struct kvm_timer {
9 struct hrtimer timer;
10 s64 period; /* unit: ns */
11 u32 timer_mode_mask;
12 u64 tscdeadline;
13 atomic_t pending; /* accumulated triggered timers */
14 bool reinject;
15 struct kvm_timer_ops *t_ops;
16 struct kvm *kvm;
17 struct kvm_vcpu *vcpu;
18};
19
20struct kvm_timer_ops {
21 bool (*is_periodic)(struct kvm_timer *);
22};
23
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]24struct kvm_lapic {
25 unsigned long base_address;
26 struct kvm_io_device dev;
Marcelo Tosattid3c7b772009-02-23 10:57:41 -0300[diff] [blame]27 struct kvm_timer lapic_timer;
28 u32 divide_count;
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]29 struct kvm_vcpu *vcpu;
Gleb Natapov33e4c682009-06-11 11:06:51 +0300[diff] [blame]30 bool irr_pending;
Michael S. Tsirkin8680b942012-06-24 19:24:26 +0300[diff] [blame]31 /* Number of bits set in ISR. */
32 s16 isr_count;
33 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
34 int highest_isr_cache;
Michael S. Tsirkin5eadf912012-06-24 19:24:19 +0300[diff] [blame]35 /**
36 * APIC register page. The layout matches the register layout seen by
37 * the guest 1:1, because it is accessed by the vmx microcode.
38 * Note: Only one register, the TPR, is used by the microcode.
39 */
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]40 void *regs;
Avi Kivityb93463a2007-10-25 16:52:32 +0200[diff] [blame]41 gpa_t vapic_addr;
42 struct page *vapic_page;
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]43};
44int kvm_create_lapic(struct kvm_vcpu *vcpu);
45void kvm_free_lapic(struct kvm_vcpu *vcpu);
46
47int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
48int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
49int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
50void kvm_lapic_reset(struct kvm_vcpu *vcpu);
51u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
52void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
Kevin Tian58fbbf22011-08-30 13:56:17 +0300[diff] [blame]53void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]54void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
Harvey Harrison8b2cf732008-04-27 12:14:13 -0700[diff] [blame]55u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
Gleb Natapovfc61b802009-07-05 17:39:35 +0300[diff] [blame]56void kvm_apic_set_version(struct kvm_vcpu *vcpu);
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]57
58int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
59int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
Gleb Natapov58c2dde2009-03-05 16:35:04 +0200[diff] [blame]60int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
Avi Kivity89342082011-11-10 14:57:21 +0200[diff] [blame]61int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]62
63u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
64void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
65void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
66int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
Gleb Natapov343f94f2009-03-05 16:34:54 +0200[diff] [blame]67bool kvm_apic_present(struct kvm_vcpu *vcpu);
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]68int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]69
Liu, Jinsonga3e06bb2011-09-22 16:55:52 +0800[diff] [blame]70u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
71void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
72
Avi Kivityb93463a2007-10-25 16:52:32 +0200[diff] [blame]73void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
74void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
75void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
76
Gleb Natapov0105d1a2009-07-05 17:39:36 +0300[diff] [blame]77int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
78int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
Gleb Natapov10388a02010-01-17 15:51:23 +0200[diff] [blame]79
80int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
81int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
82
83static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
84{
85 return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
86}
Michael S. Tsirkinae7a2a32012-06-24 19:25:07 +0300[diff] [blame]87
88int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
Zhang Xiantao82470192007-12-17 13:59:56 +0800[diff] [blame]89#endif