blob: c938298cb103d49b6d296c7837223b8597a68ea2 [file] [log] [blame]
Ian Minett95c6e9c2011-06-15 15:35:17 -07001/*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/init.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
Ian Minett95c6e9c2011-06-15 15:35:17 -070027#include <linux/mutex.h>
Paul Gortmakerda155d52011-07-15 12:38:28 -040028#include <linux/module.h>
Ian Minett4aa3bb02012-09-20 20:29:15 -070029#include <linux/firmware.h>
Jérémy Lefaurea9291f42017-10-12 22:36:31 -040030#include <linux/kernel.h>
Connor McAdamsaa317042018-05-08 13:20:03 -040031#include <linux/types.h>
32#include <linux/io.h>
33#include <linux/pci.h>
Ian Minett95c6e9c2011-06-15 15:35:17 -070034#include <sound/core.h>
35#include "hda_codec.h"
36#include "hda_local.h"
Takashi Iwai128bc4b2012-05-07 17:42:31 +020037#include "hda_auto_parser.h"
Ian Minett5aaca442012-12-20 18:53:34 -080038#include "hda_jack.h"
Ian Minett95c6e9c2011-06-15 15:35:17 -070039
Ian Minettbcd109c2012-09-20 20:29:14 -070040#include "ca0132_regs.h"
41
Ian Minettef6b2ea2012-12-20 18:53:33 -080042/* Enable this to see controls for tuning purpose. */
43/*#define ENABLE_TUNING_CONTROLS*/
44
Takashi Sakamoto8e142e92018-05-02 22:48:16 +090045#ifdef ENABLE_TUNING_CONTROLS
46#include <sound/tlv.h>
47#endif
48
Ian Minettef6b2ea2012-12-20 18:53:33 -080049#define FLOAT_ZERO 0x00000000
50#define FLOAT_ONE 0x3f800000
51#define FLOAT_TWO 0x40000000
Connor McAdams38ba69f2018-05-08 13:20:07 -040052#define FLOAT_THREE 0x40400000
Connor McAdams7cb9d942018-05-08 13:20:10 -040053#define FLOAT_EIGHT 0x41000000
Ian Minettef6b2ea2012-12-20 18:53:33 -080054#define FLOAT_MINUS_5 0xc0a00000
55
Ian Minettef6b2ea2012-12-20 18:53:33 -080056#define UNSOL_TAG_DSP 0x16
57
Ian Minett4aa3bb02012-09-20 20:29:15 -070058#define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
59#define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
60
61#define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
62#define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
63#define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
64
65#define MASTERCONTROL 0x80
Ian Minettef6b2ea2012-12-20 18:53:33 -080066#define MASTERCONTROL_ALLOC_DMA_CHAN 10
67#define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
Ian Minett4aa3bb02012-09-20 20:29:15 -070068
Ian Minett95c6e9c2011-06-15 15:35:17 -070069#define WIDGET_CHIP_CTRL 0x15
70#define WIDGET_DSP_CTRL 0x16
71
Ian Minett4aa3bb02012-09-20 20:29:15 -070072#define MEM_CONNID_MICIN1 3
73#define MEM_CONNID_MICIN2 5
74#define MEM_CONNID_MICOUT1 12
75#define MEM_CONNID_MICOUT2 14
76#define MEM_CONNID_WUH 10
77#define MEM_CONNID_DSP 16
78#define MEM_CONNID_DMIC 100
79
80#define SCP_SET 0
81#define SCP_GET 1
82
Ian Minett01ef7db2012-09-20 20:29:16 -070083#define EFX_FILE "ctefx.bin"
Connor McAdams8a19bce2018-05-08 13:20:01 -040084#define SBZ_EFX_FILE "ctefx-sbz.bin"
85#define R3DI_EFX_FILE "ctefx-r3di.bin"
Ian Minett01ef7db2012-09-20 20:29:16 -070086
Takashi Iwai24f3ced2013-02-04 18:25:51 +010087#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
Ian Minett01ef7db2012-09-20 20:29:16 -070088MODULE_FIRMWARE(EFX_FILE);
Connor McAdams8a19bce2018-05-08 13:20:01 -040089MODULE_FIRMWARE(SBZ_EFX_FILE);
90MODULE_FIRMWARE(R3DI_EFX_FILE);
Takashi Iwai7a527ed2013-01-15 17:44:20 +010091#endif
Ian Minett01ef7db2012-09-20 20:29:16 -070092
Takashi Sakamoto3a03f832018-05-15 22:12:58 +090093static const char *const dirstr[2] = { "Playback", "Capture" };
Ian Minettef6b2ea2012-12-20 18:53:33 -080094
Connor McAdams7cb9d942018-05-08 13:20:10 -040095#define NUM_OF_OUTPUTS 3
Ian Minettef6b2ea2012-12-20 18:53:33 -080096enum {
97 SPEAKER_OUT,
Connor McAdams7cb9d942018-05-08 13:20:10 -040098 HEADPHONE_OUT,
99 SURROUND_OUT
Ian Minettef6b2ea2012-12-20 18:53:33 -0800100};
101
102enum {
103 DIGITAL_MIC,
104 LINE_MIC_IN
105};
106
Connor McAdams7cb9d942018-05-08 13:20:10 -0400107/* Strings for Input Source Enum Control */
Takashi Sakamoto3a03f832018-05-15 22:12:58 +0900108static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
Connor McAdams7cb9d942018-05-08 13:20:10 -0400109#define IN_SRC_NUM_OF_INPUTS 3
110enum {
111 REAR_MIC,
112 REAR_LINE_IN,
113 FRONT_MIC,
114};
115
Ian Minettef6b2ea2012-12-20 18:53:33 -0800116enum {
117#define VNODE_START_NID 0x80
118 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
119 VNID_MIC,
120 VNID_HP_SEL,
121 VNID_AMIC1_SEL,
122 VNID_HP_ASEL,
123 VNID_AMIC1_ASEL,
124 VNODE_END_NID,
125#define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
126
127#define EFFECT_START_NID 0x90
128#define OUT_EFFECT_START_NID EFFECT_START_NID
129 SURROUND = OUT_EFFECT_START_NID,
130 CRYSTALIZER,
131 DIALOG_PLUS,
132 SMART_VOLUME,
133 X_BASS,
134 EQUALIZER,
135 OUT_EFFECT_END_NID,
136#define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
137
138#define IN_EFFECT_START_NID OUT_EFFECT_END_NID
139 ECHO_CANCELLATION = IN_EFFECT_START_NID,
140 VOICE_FOCUS,
141 MIC_SVM,
142 NOISE_REDUCTION,
143 IN_EFFECT_END_NID,
144#define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
145
146 VOICEFX = IN_EFFECT_END_NID,
147 PLAY_ENHANCEMENT,
148 CRYSTAL_VOICE,
Connor McAdams7cb9d942018-05-08 13:20:10 -0400149 EFFECT_END_NID,
150 OUTPUT_SOURCE_ENUM,
Connor McAdams47cdf762018-05-08 13:20:13 -0400151 INPUT_SOURCE_ENUM,
152 XBASS_XOVER,
153 EQ_PRESET_ENUM,
154 SMART_VOLUME_ENUM,
155 MIC_BOOST_ENUM
Ian Minettef6b2ea2012-12-20 18:53:33 -0800156#define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
157};
158
159/* Effects values size*/
160#define EFFECT_VALS_MAX_COUNT 12
161
Connor McAdams47cdf762018-05-08 13:20:13 -0400162/*
163 * Default values for the effect slider controls, they are in order of their
164 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
165 * X-bass.
166 */
167static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
168/* Amount of effect level sliders for ca0132_alt controls. */
169#define EFFECT_LEVEL_SLIDERS 5
170
Dylan Reide8412ca2013-04-04 13:55:09 -0700171/* Latency introduced by DSP blocks in milliseconds. */
172#define DSP_CAPTURE_INIT_LATENCY 0
173#define DSP_CRYSTAL_VOICE_LATENCY 124
174#define DSP_PLAYBACK_INIT_LATENCY 13
175#define DSP_PLAY_ENHANCEMENT_LATENCY 30
176#define DSP_SPEAKER_OUT_LATENCY 7
177
Ian Minettef6b2ea2012-12-20 18:53:33 -0800178struct ct_effect {
Takashi Iwai975cc022013-06-28 11:56:49 +0200179 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
Ian Minettef6b2ea2012-12-20 18:53:33 -0800180 hda_nid_t nid;
181 int mid; /*effect module ID*/
182 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
183 int direct; /* 0:output; 1:input*/
184 int params; /* number of default non-on/off params */
185 /*effect default values, 1st is on/off. */
186 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
187};
188
189#define EFX_DIR_OUT 0
190#define EFX_DIR_IN 1
191
Takashi Sakamoto862154b2018-05-15 22:13:00 +0900192static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
Ian Minettef6b2ea2012-12-20 18:53:33 -0800193 { .name = "Surround",
194 .nid = SURROUND,
195 .mid = 0x96,
196 .reqs = {0, 1},
197 .direct = EFX_DIR_OUT,
198 .params = 1,
199 .def_vals = {0x3F800000, 0x3F2B851F}
200 },
201 { .name = "Crystalizer",
202 .nid = CRYSTALIZER,
203 .mid = 0x96,
204 .reqs = {7, 8},
205 .direct = EFX_DIR_OUT,
206 .params = 1,
207 .def_vals = {0x3F800000, 0x3F266666}
208 },
209 { .name = "Dialog Plus",
210 .nid = DIALOG_PLUS,
211 .mid = 0x96,
212 .reqs = {2, 3},
213 .direct = EFX_DIR_OUT,
214 .params = 1,
215 .def_vals = {0x00000000, 0x3F000000}
216 },
217 { .name = "Smart Volume",
218 .nid = SMART_VOLUME,
219 .mid = 0x96,
220 .reqs = {4, 5, 6},
221 .direct = EFX_DIR_OUT,
222 .params = 2,
223 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
224 },
225 { .name = "X-Bass",
226 .nid = X_BASS,
227 .mid = 0x96,
228 .reqs = {24, 23, 25},
229 .direct = EFX_DIR_OUT,
230 .params = 2,
231 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
232 },
233 { .name = "Equalizer",
234 .nid = EQUALIZER,
235 .mid = 0x96,
236 .reqs = {9, 10, 11, 12, 13, 14,
237 15, 16, 17, 18, 19, 20},
238 .direct = EFX_DIR_OUT,
239 .params = 11,
240 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
241 0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000}
243 },
244 { .name = "Echo Cancellation",
245 .nid = ECHO_CANCELLATION,
246 .mid = 0x95,
247 .reqs = {0, 1, 2, 3},
248 .direct = EFX_DIR_IN,
249 .params = 3,
250 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
251 },
252 { .name = "Voice Focus",
253 .nid = VOICE_FOCUS,
254 .mid = 0x95,
255 .reqs = {6, 7, 8, 9},
256 .direct = EFX_DIR_IN,
257 .params = 3,
258 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
259 },
260 { .name = "Mic SVM",
261 .nid = MIC_SVM,
262 .mid = 0x95,
263 .reqs = {44, 45},
264 .direct = EFX_DIR_IN,
265 .params = 1,
266 .def_vals = {0x00000000, 0x3F3D70A4}
267 },
268 { .name = "Noise Reduction",
269 .nid = NOISE_REDUCTION,
270 .mid = 0x95,
271 .reqs = {4, 5},
272 .direct = EFX_DIR_IN,
273 .params = 1,
274 .def_vals = {0x3F800000, 0x3F000000}
275 },
276 { .name = "VoiceFX",
277 .nid = VOICEFX,
278 .mid = 0x95,
279 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
280 .direct = EFX_DIR_IN,
281 .params = 8,
282 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
283 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
284 0x00000000}
285 }
286};
287
288/* Tuning controls */
289#ifdef ENABLE_TUNING_CONTROLS
290
291enum {
292#define TUNING_CTL_START_NID 0xC0
293 WEDGE_ANGLE = TUNING_CTL_START_NID,
294 SVM_LEVEL,
295 EQUALIZER_BAND_0,
296 EQUALIZER_BAND_1,
297 EQUALIZER_BAND_2,
298 EQUALIZER_BAND_3,
299 EQUALIZER_BAND_4,
300 EQUALIZER_BAND_5,
301 EQUALIZER_BAND_6,
302 EQUALIZER_BAND_7,
303 EQUALIZER_BAND_8,
304 EQUALIZER_BAND_9,
305 TUNING_CTL_END_NID
306#define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
307};
308
309struct ct_tuning_ctl {
Takashi Iwai975cc022013-06-28 11:56:49 +0200310 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
Ian Minettef6b2ea2012-12-20 18:53:33 -0800311 hda_nid_t parent_nid;
312 hda_nid_t nid;
313 int mid; /*effect module ID*/
314 int req; /*effect module request*/
315 int direct; /* 0:output; 1:input*/
316 unsigned int def_val;/*effect default values*/
317};
318
Takashi Sakamoto862154b2018-05-15 22:13:00 +0900319static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
Ian Minettef6b2ea2012-12-20 18:53:33 -0800320 { .name = "Wedge Angle",
321 .parent_nid = VOICE_FOCUS,
322 .nid = WEDGE_ANGLE,
323 .mid = 0x95,
324 .req = 8,
325 .direct = EFX_DIR_IN,
326 .def_val = 0x41F00000
327 },
328 { .name = "SVM Level",
329 .parent_nid = MIC_SVM,
330 .nid = SVM_LEVEL,
331 .mid = 0x95,
332 .req = 45,
333 .direct = EFX_DIR_IN,
334 .def_val = 0x3F3D70A4
335 },
336 { .name = "EQ Band0",
337 .parent_nid = EQUALIZER,
338 .nid = EQUALIZER_BAND_0,
339 .mid = 0x96,
340 .req = 11,
341 .direct = EFX_DIR_OUT,
342 .def_val = 0x00000000
343 },
344 { .name = "EQ Band1",
345 .parent_nid = EQUALIZER,
346 .nid = EQUALIZER_BAND_1,
347 .mid = 0x96,
348 .req = 12,
349 .direct = EFX_DIR_OUT,
350 .def_val = 0x00000000
351 },
352 { .name = "EQ Band2",
353 .parent_nid = EQUALIZER,
354 .nid = EQUALIZER_BAND_2,
355 .mid = 0x96,
356 .req = 13,
357 .direct = EFX_DIR_OUT,
358 .def_val = 0x00000000
359 },
360 { .name = "EQ Band3",
361 .parent_nid = EQUALIZER,
362 .nid = EQUALIZER_BAND_3,
363 .mid = 0x96,
364 .req = 14,
365 .direct = EFX_DIR_OUT,
366 .def_val = 0x00000000
367 },
368 { .name = "EQ Band4",
369 .parent_nid = EQUALIZER,
370 .nid = EQUALIZER_BAND_4,
371 .mid = 0x96,
372 .req = 15,
373 .direct = EFX_DIR_OUT,
374 .def_val = 0x00000000
375 },
376 { .name = "EQ Band5",
377 .parent_nid = EQUALIZER,
378 .nid = EQUALIZER_BAND_5,
379 .mid = 0x96,
380 .req = 16,
381 .direct = EFX_DIR_OUT,
382 .def_val = 0x00000000
383 },
384 { .name = "EQ Band6",
385 .parent_nid = EQUALIZER,
386 .nid = EQUALIZER_BAND_6,
387 .mid = 0x96,
388 .req = 17,
389 .direct = EFX_DIR_OUT,
390 .def_val = 0x00000000
391 },
392 { .name = "EQ Band7",
393 .parent_nid = EQUALIZER,
394 .nid = EQUALIZER_BAND_7,
395 .mid = 0x96,
396 .req = 18,
397 .direct = EFX_DIR_OUT,
398 .def_val = 0x00000000
399 },
400 { .name = "EQ Band8",
401 .parent_nid = EQUALIZER,
402 .nid = EQUALIZER_BAND_8,
403 .mid = 0x96,
404 .req = 19,
405 .direct = EFX_DIR_OUT,
406 .def_val = 0x00000000
407 },
408 { .name = "EQ Band9",
409 .parent_nid = EQUALIZER,
410 .nid = EQUALIZER_BAND_9,
411 .mid = 0x96,
412 .req = 20,
413 .direct = EFX_DIR_OUT,
414 .def_val = 0x00000000
415 }
416};
417#endif
418
419/* Voice FX Presets */
420#define VOICEFX_MAX_PARAM_COUNT 9
421
422struct ct_voicefx {
423 char *name;
424 hda_nid_t nid;
425 int mid;
426 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
427};
428
429struct ct_voicefx_preset {
430 char *name; /*preset name*/
431 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
432};
433
Takashi Sakamoto862154b2018-05-15 22:13:00 +0900434static const struct ct_voicefx ca0132_voicefx = {
Ian Minettef6b2ea2012-12-20 18:53:33 -0800435 .name = "VoiceFX Capture Switch",
436 .nid = VOICEFX,
437 .mid = 0x95,
438 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
439};
440
Takashi Sakamoto862154b2018-05-15 22:13:00 +0900441static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
Ian Minettef6b2ea2012-12-20 18:53:33 -0800442 { .name = "Neutral",
443 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
444 0x44FA0000, 0x3F800000, 0x3F800000,
445 0x3F800000, 0x00000000, 0x00000000 }
446 },
447 { .name = "Female2Male",
448 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
449 0x44FA0000, 0x3F19999A, 0x3F866666,
450 0x3F800000, 0x00000000, 0x00000000 }
451 },
452 { .name = "Male2Female",
453 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
454 0x450AC000, 0x4017AE14, 0x3F6B851F,
455 0x3F800000, 0x00000000, 0x00000000 }
456 },
457 { .name = "ScrappyKid",
458 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
459 0x44FA0000, 0x40400000, 0x3F28F5C3,
460 0x3F800000, 0x00000000, 0x00000000 }
461 },
462 { .name = "Elderly",
463 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
464 0x44E10000, 0x3FB33333, 0x3FB9999A,
465 0x3F800000, 0x3E3A2E43, 0x00000000 }
466 },
467 { .name = "Orc",
468 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
469 0x45098000, 0x3F266666, 0x3FC00000,
470 0x3F800000, 0x00000000, 0x00000000 }
471 },
472 { .name = "Elf",
473 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
474 0x45193000, 0x3F8E147B, 0x3F75C28F,
475 0x3F800000, 0x00000000, 0x00000000 }
476 },
477 { .name = "Dwarf",
478 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
479 0x45007000, 0x3F451EB8, 0x3F7851EC,
480 0x3F800000, 0x00000000, 0x00000000 }
481 },
482 { .name = "AlienBrute",
483 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
484 0x451F6000, 0x3F266666, 0x3FA7D945,
485 0x3F800000, 0x3CF5C28F, 0x00000000 }
486 },
487 { .name = "Robot",
488 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
489 0x44FA0000, 0x3FB2718B, 0x3F800000,
490 0xBC07010E, 0x00000000, 0x00000000 }
491 },
492 { .name = "Marine",
493 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
494 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
495 0x3F0A3D71, 0x00000000, 0x00000000 }
496 },
497 { .name = "Emo",
498 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
499 0x44FA0000, 0x3F800000, 0x3F800000,
500 0x3E4CCCCD, 0x00000000, 0x00000000 }
501 },
502 { .name = "DeepVoice",
503 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
504 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
505 0x3F800000, 0x00000000, 0x00000000 }
506 },
507 { .name = "Munchkin",
508 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
509 0x44FA0000, 0x3F800000, 0x3F1A043C,
510 0x3F800000, 0x00000000, 0x00000000 }
511 }
512};
513
Connor McAdams47cdf762018-05-08 13:20:13 -0400514/* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
515
516#define EQ_PRESET_MAX_PARAM_COUNT 11
517
518struct ct_eq {
519 char *name;
520 hda_nid_t nid;
521 int mid;
522 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
523};
524
525struct ct_eq_preset {
526 char *name; /*preset name*/
527 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
528};
529
Takashi Sakamoto862154b2018-05-15 22:13:00 +0900530static const struct ct_eq ca0132_alt_eq_enum = {
Connor McAdams47cdf762018-05-08 13:20:13 -0400531 .name = "FX: Equalizer Preset Switch",
532 .nid = EQ_PRESET_ENUM,
533 .mid = 0x96,
534 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
535};
536
537
Takashi Sakamoto862154b2018-05-15 22:13:00 +0900538static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
Connor McAdams47cdf762018-05-08 13:20:13 -0400539 { .name = "Flat",
540 .vals = { 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000 }
544 },
545 { .name = "Acoustic",
546 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
547 0x40000000, 0x00000000, 0x00000000,
548 0x00000000, 0x00000000, 0x40000000,
549 0x40000000, 0x40000000 }
550 },
551 { .name = "Classical",
552 .vals = { 0x00000000, 0x00000000, 0x40C00000,
553 0x40C00000, 0x40466666, 0x00000000,
554 0x00000000, 0x00000000, 0x00000000,
555 0x40466666, 0x40466666 }
556 },
557 { .name = "Country",
558 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
559 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
560 0x00000000, 0x00000000, 0x40000000,
561 0x40466666, 0x40800000 }
562 },
563 { .name = "Dance",
564 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
565 0x40466666, 0x40866666, 0xBF99999A,
566 0xBF99999A, 0x00000000, 0x00000000,
567 0x40800000, 0x40800000 }
568 },
569 { .name = "Jazz",
570 .vals = { 0x00000000, 0x00000000, 0x00000000,
571 0x3F8CCCCD, 0x40800000, 0x40800000,
572 0x40800000, 0x00000000, 0x3F8CCCCD,
573 0x40466666, 0x40466666 }
574 },
575 { .name = "New Age",
576 .vals = { 0x00000000, 0x00000000, 0x40000000,
577 0x40000000, 0x00000000, 0x00000000,
578 0x00000000, 0x3F8CCCCD, 0x40000000,
579 0x40000000, 0x40000000 }
580 },
581 { .name = "Pop",
582 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
583 0x40000000, 0x40000000, 0x00000000,
584 0xBF99999A, 0xBF99999A, 0x00000000,
585 0x40466666, 0x40C00000 }
586 },
587 { .name = "Rock",
588 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
589 0x3F8CCCCD, 0x40000000, 0xBF99999A,
590 0xBF99999A, 0x00000000, 0x00000000,
591 0x40800000, 0x40800000 }
592 },
593 { .name = "Vocal",
594 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
595 0xBF99999A, 0x00000000, 0x40466666,
596 0x40800000, 0x40466666, 0x00000000,
597 0x00000000, 0x3F8CCCCD }
598 }
599};
600
Connor McAdams7cb9d942018-05-08 13:20:10 -0400601/* DSP command sequences for ca0132_alt_select_out */
602#define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
603struct ca0132_alt_out_set {
604 char *name; /*preset name*/
605 unsigned char commands;
606 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
607 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
609};
610
611static const struct ca0132_alt_out_set alt_out_presets[] = {
612 { .name = "Line Out",
613 .commands = 7,
614 .mids = { 0x96, 0x96, 0x96, 0x8F,
615 0x96, 0x96, 0x96 },
616 .reqs = { 0x19, 0x17, 0x18, 0x01,
617 0x1F, 0x15, 0x3A },
618 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
619 0x00000000, 0x00000000, 0x00000000,
620 0x00000000 }
621 },
622 { .name = "Headphone",
623 .commands = 7,
624 .mids = { 0x96, 0x96, 0x96, 0x8F,
625 0x96, 0x96, 0x96 },
626 .reqs = { 0x19, 0x17, 0x18, 0x01,
627 0x1F, 0x15, 0x3A },
628 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
629 0x00000000, 0x00000000, 0x00000000,
630 0x00000000 }
631 },
632 { .name = "Surround",
633 .commands = 8,
634 .mids = { 0x96, 0x8F, 0x96, 0x96,
635 0x96, 0x96, 0x96, 0x96 },
636 .reqs = { 0x18, 0x01, 0x1F, 0x15,
637 0x3A, 0x1A, 0x1B, 0x1C },
638 .vals = { 0x00000000, 0x00000000, 0x00000000,
639 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000 }
641 }
642};
643
Connor McAdams017310f2018-05-08 13:20:11 -0400644/*
645 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
646 * and I don't know what the third req is, but it's always zero. I assume it's
647 * some sort of update or set command to tell the DSP there's new volume info.
648 */
649#define DSP_VOL_OUT 0
650#define DSP_VOL_IN 1
651
652struct ct_dsp_volume_ctl {
653 hda_nid_t vnid;
654 int mid; /* module ID*/
655 unsigned int reqs[3]; /* scp req ID */
656};
657
Takashi Sakamoto862154b2018-05-15 22:13:00 +0900658static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
Connor McAdams017310f2018-05-08 13:20:11 -0400659 { .vnid = VNID_SPK,
660 .mid = 0x32,
661 .reqs = {3, 4, 2}
662 },
663 { .vnid = VNID_MIC,
664 .mid = 0x37,
665 .reqs = {2, 3, 1}
666 }
667};
668
Ian Minett95c6e9c2011-06-15 15:35:17 -0700669enum hda_cmd_vendor_io {
670 /* for DspIO node */
671 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
672 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
673
674 VENDOR_DSPIO_STATUS = 0xF01,
675 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
676 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
677 VENDOR_DSPIO_DSP_INIT = 0x703,
678 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
679 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
680
681 /* for ChipIO node */
682 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
683 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
684 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
685 VENDOR_CHIPIO_DATA_LOW = 0x300,
686 VENDOR_CHIPIO_DATA_HIGH = 0x400,
687
688 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
689 VENDOR_CHIPIO_STATUS = 0xF01,
690 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
691 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
692
Ian Minett4aa3bb02012-09-20 20:29:15 -0700693 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
694 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
695
Ian Minett95c6e9c2011-06-15 15:35:17 -0700696 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
Ian Minett4aa3bb02012-09-20 20:29:15 -0700697 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
Ian Minett95c6e9c2011-06-15 15:35:17 -0700698
699 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
700 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
701 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
702 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
703 VENDOR_CHIPIO_FLAG_SET = 0x70F,
704 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
Ian Minett4aa3bb02012-09-20 20:29:15 -0700705 VENDOR_CHIPIO_PARAM_SET = 0x710,
706 VENDOR_CHIPIO_PARAM_GET = 0xF10,
Ian Minett95c6e9c2011-06-15 15:35:17 -0700707
708 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
709 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
710 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
711 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
712
Ian Minett4aa3bb02012-09-20 20:29:15 -0700713 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
714 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
715 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
716 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
717
718 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
719 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
720 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
721 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
722 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
723 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
724
725 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
Ian Minett95c6e9c2011-06-15 15:35:17 -0700726};
727
728/*
729 * Control flag IDs
730 */
731enum control_flag_id {
732 /* Connection manager stream setup is bypassed/enabled */
733 CONTROL_FLAG_C_MGR = 0,
734 /* DSP DMA is bypassed/enabled */
735 CONTROL_FLAG_DMA = 1,
736 /* 8051 'idle' mode is disabled/enabled */
737 CONTROL_FLAG_IDLE_ENABLE = 2,
738 /* Tracker for the SPDIF-in path is bypassed/enabled */
739 CONTROL_FLAG_TRACKER = 3,
740 /* DigitalOut to Spdif2Out connection is disabled/enabled */
741 CONTROL_FLAG_SPDIF2OUT = 4,
742 /* Digital Microphone is disabled/enabled */
743 CONTROL_FLAG_DMIC = 5,
744 /* ADC_B rate is 48 kHz/96 kHz */
745 CONTROL_FLAG_ADC_B_96KHZ = 6,
746 /* ADC_C rate is 48 kHz/96 kHz */
747 CONTROL_FLAG_ADC_C_96KHZ = 7,
748 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
749 CONTROL_FLAG_DAC_96KHZ = 8,
750 /* DSP rate is 48 kHz/96 kHz */
751 CONTROL_FLAG_DSP_96KHZ = 9,
752 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
753 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
754 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
755 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
756 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
757 CONTROL_FLAG_DECODE_LOOP = 12,
758 /* De-emphasis filter on DAC-1 disabled/enabled */
759 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
760 /* De-emphasis filter on DAC-2 disabled/enabled */
761 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
762 /* De-emphasis filter on DAC-3 disabled/enabled */
763 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
764 /* High-pass filter on ADC_B disabled/enabled */
765 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
766 /* High-pass filter on ADC_C disabled/enabled */
767 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
768 /* Common mode on Port_A disabled/enabled */
769 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
770 /* Common mode on Port_D disabled/enabled */
771 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
772 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
773 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
774 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
Ian Minett4aa3bb02012-09-20 20:29:15 -0700775 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
Ian Minett95c6e9c2011-06-15 15:35:17 -0700776 /* ASI rate is 48kHz/96kHz */
777 CONTROL_FLAG_ASI_96KHZ = 22,
778 /* DAC power settings able to control attached ports no/yes */
779 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
780 /* Clock Stop OK reporting is disabled/enabled */
781 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
782 /* Number of control flags */
783 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
784};
785
786/*
787 * Control parameter IDs
788 */
Ian Minett4aa3bb02012-09-20 20:29:15 -0700789enum control_param_id {
Ian Minettef6b2ea2012-12-20 18:53:33 -0800790 /* 0: None, 1: Mic1In*/
791 CONTROL_PARAM_VIP_SOURCE = 1,
Ian Minett95c6e9c2011-06-15 15:35:17 -0700792 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
793 CONTROL_PARAM_SPDIF1_SOURCE = 2,
Ian Minettef6b2ea2012-12-20 18:53:33 -0800794 /* Port A output stage gain setting to use when 16 Ohm output
795 * impedance is selected*/
796 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
797 /* Port D output stage gain setting to use when 16 Ohm output
798 * impedance is selected*/
799 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
Ian Minett95c6e9c2011-06-15 15:35:17 -0700800
801 /* Stream Control */
802
803 /* Select stream with the given ID */
804 CONTROL_PARAM_STREAM_ID = 24,
805 /* Source connection point for the selected stream */
806 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
807 /* Destination connection point for the selected stream */
808 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
809 /* Number of audio channels in the selected stream */
810 CONTROL_PARAM_STREAMS_CHANNELS = 27,
811 /*Enable control for the selected stream */
812 CONTROL_PARAM_STREAM_CONTROL = 28,
813
814 /* Connection Point Control */
815
816 /* Select connection point with the given ID */
817 CONTROL_PARAM_CONN_POINT_ID = 29,
818 /* Connection point sample rate */
819 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
820
821 /* Node Control */
822
823 /* Select HDA node with the given ID */
824 CONTROL_PARAM_NODE_ID = 31
825};
826
827/*
828 * Dsp Io Status codes
829 */
830enum hda_vendor_status_dspio {
831 /* Success */
832 VENDOR_STATUS_DSPIO_OK = 0x00,
833 /* Busy, unable to accept new command, the host must retry */
834 VENDOR_STATUS_DSPIO_BUSY = 0x01,
835 /* SCP command queue is full */
836 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
837 /* SCP response queue is empty */
838 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
839};
840
841/*
842 * Chip Io Status codes
843 */
844enum hda_vendor_status_chipio {
845 /* Success */
846 VENDOR_STATUS_CHIPIO_OK = 0x00,
847 /* Busy, unable to accept new command, the host must retry */
848 VENDOR_STATUS_CHIPIO_BUSY = 0x01
849};
850
851/*
852 * CA0132 sample rate
853 */
854enum ca0132_sample_rate {
855 SR_6_000 = 0x00,
856 SR_8_000 = 0x01,
857 SR_9_600 = 0x02,
858 SR_11_025 = 0x03,
859 SR_16_000 = 0x04,
860 SR_22_050 = 0x05,
861 SR_24_000 = 0x06,
862 SR_32_000 = 0x07,
863 SR_44_100 = 0x08,
864 SR_48_000 = 0x09,
865 SR_88_200 = 0x0A,
866 SR_96_000 = 0x0B,
867 SR_144_000 = 0x0C,
868 SR_176_400 = 0x0D,
869 SR_192_000 = 0x0E,
870 SR_384_000 = 0x0F,
871
872 SR_COUNT = 0x10,
873
874 SR_RATE_UNKNOWN = 0x1F
875};
876
Ian Minett01ef7db2012-09-20 20:29:16 -0700877enum dsp_download_state {
878 DSP_DOWNLOAD_FAILED = -1,
879 DSP_DOWNLOAD_INIT = 0,
880 DSP_DOWNLOADING = 1,
881 DSP_DOWNLOADED = 2
882};
883
Ian Minett01ef7db2012-09-20 20:29:16 -0700884/* retrieve parameters from hda format */
885#define get_hdafmt_chs(fmt) (fmt & 0xf)
886#define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
887#define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
888#define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
Ian Minett95c6e9c2011-06-15 15:35:17 -0700889
890/*
891 * CA0132 specific
892 */
893
894struct ca0132_spec {
Takashi Sakamotob0eaa072018-05-15 22:12:57 +0900895 const struct snd_kcontrol_new *mixers[5];
Ian Minetta7e76272012-12-20 18:53:35 -0800896 unsigned int num_mixers;
Ian Minett5aaca442012-12-20 18:53:34 -0800897 const struct hda_verb *base_init_verbs;
898 const struct hda_verb *base_exit_verbs;
Gabriele Martinod5c016b2015-05-18 21:15:13 +0200899 const struct hda_verb *chip_init_verbs;
Connor McAdamse42c7c72018-08-08 13:34:18 -0400900 const struct hda_verb *desktop_init_verbs;
Gabriele Martinod5c016b2015-05-18 21:15:13 +0200901 struct hda_verb *spec_init_verbs;
Ian Minett95c6e9c2011-06-15 15:35:17 -0700902 struct auto_pin_cfg autocfg;
Ian Minett5aaca442012-12-20 18:53:34 -0800903
904 /* Nodes configurations */
Ian Minett95c6e9c2011-06-15 15:35:17 -0700905 struct hda_multi_out multiout;
906 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
907 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
Ian Minett5aaca442012-12-20 18:53:34 -0800908 unsigned int num_outputs;
Ian Minett95c6e9c2011-06-15 15:35:17 -0700909 hda_nid_t input_pins[AUTO_PIN_LAST];
910 hda_nid_t adcs[AUTO_PIN_LAST];
911 hda_nid_t dig_out;
912 hda_nid_t dig_in;
913 unsigned int num_inputs;
Ian Minetta7e76272012-12-20 18:53:35 -0800914 hda_nid_t shared_mic_nid;
915 hda_nid_t shared_out_nid;
Gabriele Martinod5c016b2015-05-18 21:15:13 +0200916 hda_nid_t unsol_tag_hp;
Connor McAdams63177af2018-05-08 13:20:02 -0400917 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
Gabriele Martinod5c016b2015-05-18 21:15:13 +0200918 hda_nid_t unsol_tag_amic1;
Ian Minett01ef7db2012-09-20 20:29:16 -0700919
920 /* chip access */
921 struct mutex chipio_mutex; /* chip access mutex */
922 u32 curr_chip_addx;
923
924 /* DSP download related */
925 enum dsp_download_state dsp_state;
926 unsigned int dsp_stream_id;
927 unsigned int wait_scp;
928 unsigned int wait_scp_header;
929 unsigned int wait_num_data;
930 unsigned int scp_resp_header;
931 unsigned int scp_resp_data[4];
932 unsigned int scp_resp_count;
Connor McAdams8a19bce2018-05-08 13:20:01 -0400933 bool alt_firmware_present;
Connor McAdams38ba69f2018-05-08 13:20:07 -0400934 bool startup_check_entered;
Connor McAdamse93ac302018-05-08 13:20:05 -0400935 bool dsp_reload;
Ian Minett5aaca442012-12-20 18:53:34 -0800936
937 /* mixer and effects related */
938 unsigned char dmic_ctl;
939 int cur_out_type;
940 int cur_mic_type;
941 long vnode_lvol[VNODES_COUNT];
942 long vnode_rvol[VNODES_COUNT];
943 long vnode_lswitch[VNODES_COUNT];
944 long vnode_rswitch[VNODES_COUNT];
945 long effects_switch[EFFECTS_COUNT];
946 long voicefx_val;
947 long cur_mic_boost;
Connor McAdams7cb9d942018-05-08 13:20:10 -0400948 /* ca0132_alt control related values */
949 unsigned char in_enum_val;
950 unsigned char out_enum_val;
Connor McAdams47cdf762018-05-08 13:20:13 -0400951 unsigned char mic_boost_enum_val;
952 unsigned char smart_volume_setting;
953 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
954 long xbass_xover_freq;
955 long eq_preset_val;
956 unsigned int tlv[4];
957 struct hda_vmaster_mute_hook vmaster_mute;
958
Ian Minett44f0c972012-12-20 18:53:38 -0800959
Chih-Chung Chang993884f2013-03-25 10:39:23 -0700960 struct hda_codec *codec;
961 struct delayed_work unsol_hp_work;
Gabriele Martinod5c016b2015-05-18 21:15:13 +0200962 int quirk;
Chih-Chung Chang993884f2013-03-25 10:39:23 -0700963
Ian Minett44f0c972012-12-20 18:53:38 -0800964#ifdef ENABLE_TUNING_CONTROLS
965 long cur_ctl_vals[TUNING_CTLS_COUNT];
966#endif
Connor McAdamsaa317042018-05-08 13:20:03 -0400967 /*
Connor McAdams08eca6b2018-08-08 13:34:17 -0400968 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
969 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
970 * things.
Connor McAdamsaa317042018-05-08 13:20:03 -0400971 */
Connor McAdams08eca6b2018-08-08 13:34:17 -0400972 bool use_pci_mmio;
Connor McAdamsaa317042018-05-08 13:20:03 -0400973 void __iomem *mem_base;
Connor McAdams009b8f92018-05-08 13:20:06 -0400974
975 /*
976 * Whether or not to use the alt functions like alt_select_out,
977 * alt_select_in, etc. Only used on desktop codecs for now, because of
978 * surround sound support.
979 */
980 bool use_alt_functions;
Connor McAdams47cdf762018-05-08 13:20:13 -0400981
982 /*
983 * Whether or not to use alt controls: volume effect sliders, EQ
984 * presets, smart volume presets, and new control names with FX prefix.
985 * Renames PlayEnhancement and CrystalVoice too.
986 */
987 bool use_alt_controls;
Ian Minett95c6e9c2011-06-15 15:35:17 -0700988};
989
Ian Minett01ef7db2012-09-20 20:29:16 -0700990/*
Gabriele Martinod5c016b2015-05-18 21:15:13 +0200991 * CA0132 quirks table
992 */
993enum {
994 QUIRK_NONE,
995 QUIRK_ALIENWARE,
Alastair Bridgewatera57a46b2018-06-15 21:56:20 -0400996 QUIRK_ALIENWARE_M17XR4,
Connor McAdams8a19bce2018-05-08 13:20:01 -0400997 QUIRK_SBZ,
998 QUIRK_R3DI,
Connor McAdams8f8c5232018-08-08 13:34:15 -0400999 QUIRK_R3D,
Gabriele Martinod5c016b2015-05-18 21:15:13 +02001000};
1001
Takashi Iwaife14f392015-08-10 16:53:32 +02001002static const struct hda_pintbl alienware_pincfgs[] = {
1003 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1004 { 0x0c, 0x411111f0 }, /* N/A */
1005 { 0x0d, 0x411111f0 }, /* N/A */
1006 { 0x0e, 0x411111f0 }, /* N/A */
1007 { 0x0f, 0x0321101f }, /* HP */
1008 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1009 { 0x11, 0x03a11021 }, /* Mic */
1010 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1011 { 0x13, 0x411111f0 }, /* N/A */
1012 { 0x18, 0x411111f0 }, /* N/A */
1013 {}
1014};
1015
Connor McAdams63177af2018-05-08 13:20:02 -04001016/* Sound Blaster Z pin configs taken from Windows Driver */
1017static const struct hda_pintbl sbz_pincfgs[] = {
1018 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1019 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1020 { 0x0d, 0x014510f0 }, /* Digital Out */
1021 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1022 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1023 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1024 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1025 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1026 { 0x13, 0x908700f0 }, /* What U Hear In*/
1027 { 0x18, 0x50d000f0 }, /* N/A */
1028 {}
1029};
1030
Connor McAdams7f73df92018-08-08 13:34:16 -04001031/* Recon3D pin configs taken from Windows Driver */
1032static const struct hda_pintbl r3d_pincfgs[] = {
1033 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1034 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1035 { 0x0d, 0x014510f0 }, /* Digital Out */
1036 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1037 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1038 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1039 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1040 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1041 { 0x13, 0x908700f0 }, /* What U Hear In*/
1042 { 0x18, 0x50d000f0 }, /* N/A */
1043 {}
1044};
1045
Connor McAdams63177af2018-05-08 13:20:02 -04001046/* Recon3D integrated pin configs taken from Windows Driver */
1047static const struct hda_pintbl r3di_pincfgs[] = {
1048 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1049 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1050 { 0x0d, 0x014510f0 }, /* Digital Out */
1051 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1052 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1053 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1054 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1055 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1056 { 0x13, 0x908700f0 }, /* What U Hear In*/
1057 { 0x18, 0x500000f0 }, /* N/A */
1058 {}
1059};
1060
Gabriele Martinod5c016b2015-05-18 21:15:13 +02001061static const struct snd_pci_quirk ca0132_quirks[] = {
Alastair Bridgewatera57a46b2018-06-15 21:56:20 -04001062 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
Gabriele Martino5328e1e2015-12-09 17:05:58 +01001063 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1064 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
Sven Hahneb5337cf2016-11-25 14:16:43 +01001065 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
Connor McAdams8a19bce2018-05-08 13:20:01 -04001066 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1067 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1068 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
Alastair Bridgewaterdad59262018-07-11 18:09:45 -04001069 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
Alastair Bridgewaterc5a59d22018-07-11 18:09:46 -04001070 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
Connor McAdams8f8c5232018-08-08 13:34:15 -04001071 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
Gabriele Martinod5c016b2015-05-18 21:15:13 +02001072 {}
1073};
1074
1075/*
Ian Minett01ef7db2012-09-20 20:29:16 -07001076 * CA0132 codec access
1077 */
Sachin Kamat399ae722013-09-13 15:14:22 +05301078static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
Ian Minett01ef7db2012-09-20 20:29:16 -07001079 unsigned int verb, unsigned int parm, unsigned int *res)
1080{
1081 unsigned int response;
1082 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1083 *res = response;
1084
1085 return ((response == -1) ? -1 : 0);
1086}
1087
1088static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1089 unsigned short converter_format, unsigned int *res)
1090{
1091 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1092 converter_format & 0xffff, res);
1093}
1094
1095static int codec_set_converter_stream_channel(struct hda_codec *codec,
1096 hda_nid_t nid, unsigned char stream,
1097 unsigned char channel, unsigned int *res)
1098{
1099 unsigned char converter_stream_channel = 0;
1100
1101 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1102 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1103 converter_stream_channel, res);
1104}
1105
Ian Minett95c6e9c2011-06-15 15:35:17 -07001106/* Chip access helper function */
1107static int chipio_send(struct hda_codec *codec,
1108 unsigned int reg,
1109 unsigned int data)
1110{
1111 unsigned int res;
Ian Minett6d675302013-02-08 18:31:43 -08001112 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
Ian Minett95c6e9c2011-06-15 15:35:17 -07001113
1114 /* send bits of data specified by reg */
1115 do {
1116 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1117 reg, data);
1118 if (res == VENDOR_STATUS_CHIPIO_OK)
1119 return 0;
Ian Minett6d675302013-02-08 18:31:43 -08001120 msleep(20);
1121 } while (time_before(jiffies, timeout));
1122
Ian Minett95c6e9c2011-06-15 15:35:17 -07001123 return -EIO;
1124}
1125
1126/*
1127 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1128 */
1129static int chipio_write_address(struct hda_codec *codec,
1130 unsigned int chip_addx)
1131{
Ian Minett4861af82012-09-20 20:29:20 -07001132 struct ca0132_spec *spec = codec->spec;
Ian Minett95c6e9c2011-06-15 15:35:17 -07001133 int res;
1134
Ian Minett4861af82012-09-20 20:29:20 -07001135 if (spec->curr_chip_addx == chip_addx)
1136 return 0;
1137
Ian Minett95c6e9c2011-06-15 15:35:17 -07001138 /* send low 16 bits of the address */
1139 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1140 chip_addx & 0xffff);
1141
1142 if (res != -EIO) {
1143 /* send high 16 bits of the address */
1144 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1145 chip_addx >> 16);
1146 }
1147
Matthias Kaehlcked1600402017-03-31 18:00:04 -07001148 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
Ian Minett4861af82012-09-20 20:29:20 -07001149
Ian Minett95c6e9c2011-06-15 15:35:17 -07001150 return res;
1151}
1152
1153/*
1154 * Write data through the vendor widget -- NOT protected by the Mutex!
1155 */
Ian Minett95c6e9c2011-06-15 15:35:17 -07001156static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1157{
Ian Minett5aaca442012-12-20 18:53:34 -08001158 struct ca0132_spec *spec = codec->spec;
Ian Minett95c6e9c2011-06-15 15:35:17 -07001159 int res;
1160
1161 /* send low 16 bits of the data */
1162 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1163
1164 if (res != -EIO) {
1165 /* send high 16 bits of the data */
1166 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1167 data >> 16);
1168 }
1169
Ian Minett5aaca442012-12-20 18:53:34 -08001170 /*If no error encountered, automatically increment the address
1171 as per chip behaviour*/
1172 spec->curr_chip_addx = (res != -EIO) ?
Matthias Kaehlcked1600402017-03-31 18:00:04 -07001173 (spec->curr_chip_addx + 4) : ~0U;
Ian Minett95c6e9c2011-06-15 15:35:17 -07001174 return res;
1175}
1176
Ian Minettd5c21b82012-09-20 20:29:18 -07001177/*
1178 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1179 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001180static int chipio_write_data_multiple(struct hda_codec *codec,
1181 const u32 *data,
1182 unsigned int count)
1183{
1184 int status = 0;
1185
1186 if (data == NULL) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001187 codec_dbg(codec, "chipio_write_data null ptr\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001188 return -EINVAL;
1189 }
1190
1191 while ((count-- != 0) && (status == 0))
1192 status = chipio_write_data(codec, *data++);
1193
1194 return status;
1195}
1196
1197
Ian Minett95c6e9c2011-06-15 15:35:17 -07001198/*
1199 * Read data through the vendor widget -- NOT protected by the Mutex!
1200 */
1201static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1202{
Ian Minett5aaca442012-12-20 18:53:34 -08001203 struct ca0132_spec *spec = codec->spec;
Ian Minett95c6e9c2011-06-15 15:35:17 -07001204 int res;
1205
1206 /* post read */
1207 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1208
1209 if (res != -EIO) {
1210 /* read status */
1211 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1212 }
1213
1214 if (res != -EIO) {
1215 /* read data */
1216 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1217 VENDOR_CHIPIO_HIC_READ_DATA,
1218 0);
1219 }
1220
Ian Minett5aaca442012-12-20 18:53:34 -08001221 /*If no error encountered, automatically increment the address
1222 as per chip behaviour*/
1223 spec->curr_chip_addx = (res != -EIO) ?
Matthias Kaehlcked1600402017-03-31 18:00:04 -07001224 (spec->curr_chip_addx + 4) : ~0U;
Ian Minett95c6e9c2011-06-15 15:35:17 -07001225 return res;
1226}
1227
1228/*
1229 * Write given value to the given address through the chip I/O widget.
1230 * protected by the Mutex
1231 */
1232static int chipio_write(struct hda_codec *codec,
1233 unsigned int chip_addx, const unsigned int data)
1234{
1235 struct ca0132_spec *spec = codec->spec;
1236 int err;
1237
1238 mutex_lock(&spec->chipio_mutex);
1239
1240 /* write the address, and if successful proceed to write data */
1241 err = chipio_write_address(codec, chip_addx);
1242 if (err < 0)
1243 goto exit;
1244
1245 err = chipio_write_data(codec, data);
1246 if (err < 0)
1247 goto exit;
1248
1249exit:
1250 mutex_unlock(&spec->chipio_mutex);
1251 return err;
1252}
1253
Ian Minettd5c21b82012-09-20 20:29:18 -07001254/*
Connor McAdams38ba69f2018-05-08 13:20:07 -04001255 * Write given value to the given address through the chip I/O widget.
1256 * not protected by the Mutex
1257 */
1258static int chipio_write_no_mutex(struct hda_codec *codec,
1259 unsigned int chip_addx, const unsigned int data)
1260{
1261 int err;
1262
1263
1264 /* write the address, and if successful proceed to write data */
1265 err = chipio_write_address(codec, chip_addx);
1266 if (err < 0)
1267 goto exit;
1268
1269 err = chipio_write_data(codec, data);
1270 if (err < 0)
1271 goto exit;
1272
1273exit:
1274 return err;
1275}
1276
1277/*
Ian Minettd5c21b82012-09-20 20:29:18 -07001278 * Write multiple values to the given address through the chip I/O widget.
1279 * protected by the Mutex
1280 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001281static int chipio_write_multiple(struct hda_codec *codec,
1282 u32 chip_addx,
1283 const u32 *data,
1284 unsigned int count)
1285{
1286 struct ca0132_spec *spec = codec->spec;
1287 int status;
1288
1289 mutex_lock(&spec->chipio_mutex);
Ian Minett4861af82012-09-20 20:29:20 -07001290 status = chipio_write_address(codec, chip_addx);
Ian Minett01ef7db2012-09-20 20:29:16 -07001291 if (status < 0)
1292 goto error;
1293
1294 status = chipio_write_data_multiple(codec, data, count);
1295error:
1296 mutex_unlock(&spec->chipio_mutex);
1297
1298 return status;
1299}
1300
Ian Minett95c6e9c2011-06-15 15:35:17 -07001301/*
1302 * Read the given address through the chip I/O widget
1303 * protected by the Mutex
1304 */
1305static int chipio_read(struct hda_codec *codec,
1306 unsigned int chip_addx, unsigned int *data)
1307{
1308 struct ca0132_spec *spec = codec->spec;
1309 int err;
1310
1311 mutex_lock(&spec->chipio_mutex);
1312
1313 /* write the address, and if successful proceed to write data */
1314 err = chipio_write_address(codec, chip_addx);
1315 if (err < 0)
1316 goto exit;
1317
1318 err = chipio_read_data(codec, data);
1319 if (err < 0)
1320 goto exit;
1321
1322exit:
1323 mutex_unlock(&spec->chipio_mutex);
1324 return err;
1325}
1326
Ian Minettd5c21b82012-09-20 20:29:18 -07001327/*
1328 * Set chip control flags through the chip I/O widget.
1329 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001330static void chipio_set_control_flag(struct hda_codec *codec,
1331 enum control_flag_id flag_id,
1332 bool flag_state)
1333{
1334 unsigned int val;
1335 unsigned int flag_bit;
1336
1337 flag_bit = (flag_state ? 1 : 0);
1338 val = (flag_bit << 7) | (flag_id);
1339 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1340 VENDOR_CHIPIO_FLAG_SET, val);
1341}
1342
Ian Minettd5c21b82012-09-20 20:29:18 -07001343/*
1344 * Set chip parameters through the chip I/O widget.
1345 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001346static void chipio_set_control_param(struct hda_codec *codec,
1347 enum control_param_id param_id, int param_val)
1348{
1349 struct ca0132_spec *spec = codec->spec;
1350 int val;
1351
1352 if ((param_id < 32) && (param_val < 8)) {
1353 val = (param_val << 5) | (param_id);
1354 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1355 VENDOR_CHIPIO_PARAM_SET, val);
1356 } else {
1357 mutex_lock(&spec->chipio_mutex);
1358 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1359 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1360 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1361 param_id);
1362 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1363 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1364 param_val);
1365 }
1366 mutex_unlock(&spec->chipio_mutex);
1367 }
1368}
1369
Ian Minettd5c21b82012-09-20 20:29:18 -07001370/*
Connor McAdams009b8f92018-05-08 13:20:06 -04001371 * Set chip parameters through the chip I/O widget. NO MUTEX.
1372 */
1373static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1374 enum control_param_id param_id, int param_val)
1375{
1376 int val;
1377
1378 if ((param_id < 32) && (param_val < 8)) {
1379 val = (param_val << 5) | (param_id);
1380 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1381 VENDOR_CHIPIO_PARAM_SET, val);
1382 } else {
1383 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1384 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1385 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1386 param_id);
1387 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1388 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1389 param_val);
1390 }
1391 }
1392}
Connor McAdams38ba69f2018-05-08 13:20:07 -04001393/*
1394 * Connect stream to a source point, and then connect
1395 * that source point to a destination point.
1396 */
1397static void chipio_set_stream_source_dest(struct hda_codec *codec,
1398 int streamid, int source_point, int dest_point)
1399{
1400 chipio_set_control_param_no_mutex(codec,
1401 CONTROL_PARAM_STREAM_ID, streamid);
1402 chipio_set_control_param_no_mutex(codec,
1403 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1404 chipio_set_control_param_no_mutex(codec,
1405 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1406}
1407
1408/*
1409 * Set number of channels in the selected stream.
1410 */
1411static void chipio_set_stream_channels(struct hda_codec *codec,
1412 int streamid, unsigned int channels)
1413{
1414 chipio_set_control_param_no_mutex(codec,
1415 CONTROL_PARAM_STREAM_ID, streamid);
1416 chipio_set_control_param_no_mutex(codec,
1417 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1418}
Connor McAdams009b8f92018-05-08 13:20:06 -04001419
1420/*
1421 * Enable/Disable audio stream.
1422 */
1423static void chipio_set_stream_control(struct hda_codec *codec,
1424 int streamid, int enable)
1425{
1426 chipio_set_control_param_no_mutex(codec,
1427 CONTROL_PARAM_STREAM_ID, streamid);
1428 chipio_set_control_param_no_mutex(codec,
1429 CONTROL_PARAM_STREAM_CONTROL, enable);
1430}
1431
Connor McAdams38ba69f2018-05-08 13:20:07 -04001432
1433/*
1434 * Set sampling rate of the connection point. NO MUTEX.
1435 */
1436static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1437 int connid, enum ca0132_sample_rate rate)
1438{
1439 chipio_set_control_param_no_mutex(codec,
1440 CONTROL_PARAM_CONN_POINT_ID, connid);
1441 chipio_set_control_param_no_mutex(codec,
1442 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1443}
1444
Connor McAdams009b8f92018-05-08 13:20:06 -04001445/*
Ian Minettd5c21b82012-09-20 20:29:18 -07001446 * Set sampling rate of the connection point.
1447 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001448static void chipio_set_conn_rate(struct hda_codec *codec,
1449 int connid, enum ca0132_sample_rate rate)
1450{
1451 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1452 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1453 rate);
1454}
1455
Ian Minettd5c21b82012-09-20 20:29:18 -07001456/*
1457 * Enable clocks.
1458 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001459static void chipio_enable_clocks(struct hda_codec *codec)
1460{
1461 struct ca0132_spec *spec = codec->spec;
1462
1463 mutex_lock(&spec->chipio_mutex);
1464 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1465 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1466 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1467 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1468 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1469 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1470 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1471 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1472 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1474 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1475 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1476 mutex_unlock(&spec->chipio_mutex);
1477}
1478
1479/*
1480 * CA0132 DSP IO stuffs
1481 */
1482static int dspio_send(struct hda_codec *codec, unsigned int reg,
1483 unsigned int data)
1484{
Takashi Iwaib645d792013-01-15 17:39:29 +01001485 int res;
Ian Minett6d675302013-02-08 18:31:43 -08001486 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
Ian Minett01ef7db2012-09-20 20:29:16 -07001487
1488 /* send bits of data specified by reg to dsp */
1489 do {
1490 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1491 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1492 return res;
Ian Minett6d675302013-02-08 18:31:43 -08001493 msleep(20);
1494 } while (time_before(jiffies, timeout));
Ian Minett01ef7db2012-09-20 20:29:16 -07001495
1496 return -EIO;
1497}
1498
Ian Minettd5c21b82012-09-20 20:29:18 -07001499/*
1500 * Wait for DSP to be ready for commands
1501 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001502static void dspio_write_wait(struct hda_codec *codec)
1503{
Ian Minett4861af82012-09-20 20:29:20 -07001504 int status;
1505 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
Ian Minett01ef7db2012-09-20 20:29:16 -07001506
Ian Minett01ef7db2012-09-20 20:29:16 -07001507 do {
Ian Minett4861af82012-09-20 20:29:20 -07001508 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1509 VENDOR_DSPIO_STATUS, 0);
1510 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1511 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1512 break;
1513 msleep(1);
1514 } while (time_before(jiffies, timeout));
Ian Minett01ef7db2012-09-20 20:29:16 -07001515}
1516
Ian Minettd5c21b82012-09-20 20:29:18 -07001517/*
1518 * Write SCP data to DSP
1519 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001520static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1521{
1522 struct ca0132_spec *spec = codec->spec;
1523 int status;
1524
1525 dspio_write_wait(codec);
1526
1527 mutex_lock(&spec->chipio_mutex);
1528 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1529 scp_data & 0xffff);
1530 if (status < 0)
1531 goto error;
1532
1533 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1534 scp_data >> 16);
1535 if (status < 0)
1536 goto error;
1537
1538 /* OK, now check if the write itself has executed*/
1539 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1540 VENDOR_DSPIO_STATUS, 0);
1541error:
1542 mutex_unlock(&spec->chipio_mutex);
1543
1544 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1545 -EIO : 0;
1546}
1547
Ian Minettd5c21b82012-09-20 20:29:18 -07001548/*
1549 * Write multiple SCP data to DSP
1550 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001551static int dspio_write_multiple(struct hda_codec *codec,
1552 unsigned int *buffer, unsigned int size)
1553{
1554 int status = 0;
1555 unsigned int count;
1556
Matthias Kaehlckea16fbb82017-03-15 15:41:23 -07001557 if (buffer == NULL)
Ian Minett01ef7db2012-09-20 20:29:16 -07001558 return -EINVAL;
1559
1560 count = 0;
1561 while (count < size) {
1562 status = dspio_write(codec, *buffer++);
1563 if (status != 0)
1564 break;
1565 count++;
1566 }
1567
1568 return status;
1569}
1570
Ian Minetta73d5112012-12-20 18:53:37 -08001571static int dspio_read(struct hda_codec *codec, unsigned int *data)
1572{
1573 int status;
1574
1575 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1576 if (status == -EIO)
1577 return status;
1578
1579 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1580 if (status == -EIO ||
1581 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1582 return -EIO;
1583
1584 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1585 VENDOR_DSPIO_SCP_READ_DATA, 0);
1586
1587 return 0;
1588}
1589
1590static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1591 unsigned int *buf_size, unsigned int size_count)
1592{
1593 int status = 0;
1594 unsigned int size = *buf_size;
1595 unsigned int count;
1596 unsigned int skip_count;
1597 unsigned int dummy;
1598
Matthias Kaehlckea16fbb82017-03-15 15:41:23 -07001599 if (buffer == NULL)
Ian Minetta73d5112012-12-20 18:53:37 -08001600 return -1;
1601
1602 count = 0;
1603 while (count < size && count < size_count) {
1604 status = dspio_read(codec, buffer++);
1605 if (status != 0)
1606 break;
1607 count++;
1608 }
1609
1610 skip_count = count;
1611 if (status == 0) {
1612 while (skip_count < size) {
1613 status = dspio_read(codec, &dummy);
1614 if (status != 0)
1615 break;
1616 skip_count++;
1617 }
1618 }
1619 *buf_size = count;
1620
1621 return status;
1622}
1623
Ian Minettd5c21b82012-09-20 20:29:18 -07001624/*
1625 * Construct the SCP header using corresponding fields
1626 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001627static inline unsigned int
1628make_scp_header(unsigned int target_id, unsigned int source_id,
1629 unsigned int get_flag, unsigned int req,
1630 unsigned int device_flag, unsigned int resp_flag,
1631 unsigned int error_flag, unsigned int data_size)
1632{
1633 unsigned int header = 0;
1634
1635 header = (data_size & 0x1f) << 27;
1636 header |= (error_flag & 0x01) << 26;
1637 header |= (resp_flag & 0x01) << 25;
1638 header |= (device_flag & 0x01) << 24;
1639 header |= (req & 0x7f) << 17;
1640 header |= (get_flag & 0x01) << 16;
1641 header |= (source_id & 0xff) << 8;
1642 header |= target_id & 0xff;
1643
1644 return header;
1645}
1646
Ian Minettd5c21b82012-09-20 20:29:18 -07001647/*
1648 * Extract corresponding fields from SCP header
1649 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001650static inline void
1651extract_scp_header(unsigned int header,
1652 unsigned int *target_id, unsigned int *source_id,
1653 unsigned int *get_flag, unsigned int *req,
1654 unsigned int *device_flag, unsigned int *resp_flag,
1655 unsigned int *error_flag, unsigned int *data_size)
1656{
1657 if (data_size)
1658 *data_size = (header >> 27) & 0x1f;
1659 if (error_flag)
1660 *error_flag = (header >> 26) & 0x01;
1661 if (resp_flag)
1662 *resp_flag = (header >> 25) & 0x01;
1663 if (device_flag)
1664 *device_flag = (header >> 24) & 0x01;
1665 if (req)
1666 *req = (header >> 17) & 0x7f;
1667 if (get_flag)
1668 *get_flag = (header >> 16) & 0x01;
1669 if (source_id)
1670 *source_id = (header >> 8) & 0xff;
1671 if (target_id)
1672 *target_id = header & 0xff;
1673}
1674
1675#define SCP_MAX_DATA_WORDS (16)
1676
1677/* Structure to contain any SCP message */
1678struct scp_msg {
1679 unsigned int hdr;
1680 unsigned int data[SCP_MAX_DATA_WORDS];
1681};
1682
Ian Minetta73d5112012-12-20 18:53:37 -08001683static void dspio_clear_response_queue(struct hda_codec *codec)
1684{
1685 unsigned int dummy = 0;
1686 int status = -1;
1687
1688 /* clear all from the response queue */
1689 do {
1690 status = dspio_read(codec, &dummy);
1691 } while (status == 0);
1692}
1693
1694static int dspio_get_response_data(struct hda_codec *codec)
1695{
1696 struct ca0132_spec *spec = codec->spec;
1697 unsigned int data = 0;
1698 unsigned int count;
1699
1700 if (dspio_read(codec, &data) < 0)
1701 return -EIO;
1702
1703 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1704 spec->scp_resp_header = data;
1705 spec->scp_resp_count = data >> 27;
1706 count = spec->wait_num_data;
1707 dspio_read_multiple(codec, spec->scp_resp_data,
1708 &spec->scp_resp_count, count);
1709 return 0;
1710 }
1711
1712 return -EIO;
1713}
1714
Ian Minettd5c21b82012-09-20 20:29:18 -07001715/*
1716 * Send SCP message to DSP
1717 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001718static int dspio_send_scp_message(struct hda_codec *codec,
1719 unsigned char *send_buf,
1720 unsigned int send_buf_size,
1721 unsigned char *return_buf,
1722 unsigned int return_buf_size,
1723 unsigned int *bytes_returned)
1724{
1725 struct ca0132_spec *spec = codec->spec;
Ian Minett01ef7db2012-09-20 20:29:16 -07001726 int status = -1;
1727 unsigned int scp_send_size = 0;
1728 unsigned int total_size;
1729 bool waiting_for_resp = false;
1730 unsigned int header;
1731 struct scp_msg *ret_msg;
1732 unsigned int resp_src_id, resp_target_id;
1733 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1734
1735 if (bytes_returned)
1736 *bytes_returned = 0;
1737
1738 /* get scp header from buffer */
1739 header = *((unsigned int *)send_buf);
1740 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1741 &device_flag, NULL, NULL, &data_size);
1742 scp_send_size = data_size + 1;
1743 total_size = (scp_send_size * 4);
1744
1745 if (send_buf_size < total_size)
1746 return -EINVAL;
1747
1748 if (get_flag || device_flag) {
1749 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1750 return -EINVAL;
1751
1752 spec->wait_scp_header = *((unsigned int *)send_buf);
1753
1754 /* swap source id with target id */
1755 resp_target_id = src_id;
1756 resp_src_id = target_id;
1757 spec->wait_scp_header &= 0xffff0000;
1758 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1759 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1760 spec->wait_scp = 1;
1761 waiting_for_resp = true;
1762 }
1763
1764 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1765 scp_send_size);
1766 if (status < 0) {
1767 spec->wait_scp = 0;
1768 return status;
1769 }
1770
1771 if (waiting_for_resp) {
Ian Minett6d675302013-02-08 18:31:43 -08001772 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
Ian Minett01ef7db2012-09-20 20:29:16 -07001773 memset(return_buf, 0, return_buf_size);
Ian Minett01ef7db2012-09-20 20:29:16 -07001774 do {
1775 msleep(20);
Ian Minett6d675302013-02-08 18:31:43 -08001776 } while (spec->wait_scp && time_before(jiffies, timeout));
Ian Minett01ef7db2012-09-20 20:29:16 -07001777 waiting_for_resp = false;
Ian Minett6d675302013-02-08 18:31:43 -08001778 if (!spec->wait_scp) {
Ian Minett01ef7db2012-09-20 20:29:16 -07001779 ret_msg = (struct scp_msg *)return_buf;
1780 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1781 memcpy(&ret_msg->data, spec->scp_resp_data,
1782 spec->wait_num_data);
1783 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1784 status = 0;
1785 } else {
1786 status = -EIO;
1787 }
1788 spec->wait_scp = 0;
1789 }
1790
1791 return status;
1792}
1793
Ian Minettd5c21b82012-09-20 20:29:18 -07001794/**
1795 * Prepare and send the SCP message to DSP
1796 * @codec: the HDA codec
1797 * @mod_id: ID of the DSP module to send the command
1798 * @req: ID of request to send to the DSP module
1799 * @dir: SET or GET
1800 * @data: pointer to the data to send with the request, request specific
1801 * @len: length of the data, in bytes
1802 * @reply: point to the buffer to hold data returned for a reply
1803 * @reply_len: length of the reply buffer returned from GET
1804 *
1805 * Returns zero or a negative error code.
1806 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001807static int dspio_scp(struct hda_codec *codec,
Connor McAdams447fd8e2018-05-08 13:20:09 -04001808 int mod_id, int src_id, int req, int dir, const void *data,
1809 unsigned int len, void *reply, unsigned int *reply_len)
Ian Minett01ef7db2012-09-20 20:29:16 -07001810{
1811 int status = 0;
1812 struct scp_msg scp_send, scp_reply;
1813 unsigned int ret_bytes, send_size, ret_size;
1814 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1815 unsigned int reply_data_size;
1816
1817 memset(&scp_send, 0, sizeof(scp_send));
1818 memset(&scp_reply, 0, sizeof(scp_reply));
1819
1820 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1821 return -EINVAL;
1822
1823 if (dir == SCP_GET && reply == NULL) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001824 codec_dbg(codec, "dspio_scp get but has no buffer\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001825 return -EINVAL;
1826 }
1827
1828 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001829 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001830 return -EINVAL;
1831 }
1832
Connor McAdams447fd8e2018-05-08 13:20:09 -04001833 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
Ian Minett01ef7db2012-09-20 20:29:16 -07001834 0, 0, 0, len/sizeof(unsigned int));
1835 if (data != NULL && len > 0) {
1836 len = min((unsigned int)(sizeof(scp_send.data)), len);
1837 memcpy(scp_send.data, data, len);
1838 }
1839
1840 ret_bytes = 0;
1841 send_size = sizeof(unsigned int) + len;
1842 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1843 send_size, (unsigned char *)&scp_reply,
1844 sizeof(scp_reply), &ret_bytes);
1845
1846 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001847 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001848 return status;
1849 }
1850
1851 /* extract send and reply headers members */
1852 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1853 NULL, NULL, NULL, NULL, NULL);
1854 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1855 &reply_resp_flag, &reply_error_flag,
1856 &reply_data_size);
1857
1858 if (!send_get_flag)
1859 return 0;
1860
1861 if (reply_resp_flag && !reply_error_flag) {
1862 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1863 / sizeof(unsigned int);
1864
1865 if (*reply_len < ret_size*sizeof(unsigned int)) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001866 codec_dbg(codec, "reply too long for buf\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001867 return -EINVAL;
1868 } else if (ret_size != reply_data_size) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001869 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001870 return -EINVAL;
Arnd Bergmann46a049d2017-01-11 14:39:44 +01001871 } else if (!reply) {
1872 codec_dbg(codec, "NULL reply\n");
1873 return -EINVAL;
Ian Minett01ef7db2012-09-20 20:29:16 -07001874 } else {
1875 *reply_len = ret_size*sizeof(unsigned int);
1876 memcpy(reply, scp_reply.data, *reply_len);
1877 }
1878 } else {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001879 codec_dbg(codec, "reply ill-formed or errflag set\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001880 return -EIO;
1881 }
1882
1883 return status;
1884}
1885
Ian Minettd5c21b82012-09-20 20:29:18 -07001886/*
Ian Minett5aaca442012-12-20 18:53:34 -08001887 * Set DSP parameters
1888 */
1889static int dspio_set_param(struct hda_codec *codec, int mod_id,
Connor McAdams447fd8e2018-05-08 13:20:09 -04001890 int src_id, int req, const void *data, unsigned int len)
Ian Minett5aaca442012-12-20 18:53:34 -08001891{
Connor McAdams447fd8e2018-05-08 13:20:09 -04001892 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1893 NULL);
Ian Minett5aaca442012-12-20 18:53:34 -08001894}
1895
1896static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
Connor McAdams447fd8e2018-05-08 13:20:09 -04001897 int req, const unsigned int data)
Ian Minett5aaca442012-12-20 18:53:34 -08001898{
Connor McAdams447fd8e2018-05-08 13:20:09 -04001899 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1900 sizeof(unsigned int));
1901}
1902
1903static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1904 int req, const unsigned int data)
1905{
1906 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1907 sizeof(unsigned int));
Ian Minett5aaca442012-12-20 18:53:34 -08001908}
1909
1910/*
Ian Minettd5c21b82012-09-20 20:29:18 -07001911 * Allocate a DSP DMA channel via an SCP message
1912 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001913static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1914{
1915 int status = 0;
1916 unsigned int size = sizeof(dma_chan);
1917
Takashi Iwai4e76a882014-02-25 12:21:03 +01001918 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
Connor McAdams447fd8e2018-05-08 13:20:09 -04001919 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1920 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1921 dma_chan, &size);
Ian Minett01ef7db2012-09-20 20:29:16 -07001922
1923 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001924 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001925 return status;
1926 }
1927
1928 if ((*dma_chan + 1) == 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001929 codec_dbg(codec, "no free dma channels to allocate\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001930 return -EBUSY;
1931 }
1932
Takashi Iwai4e76a882014-02-25 12:21:03 +01001933 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1934 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001935
1936 return status;
1937}
1938
Ian Minettd5c21b82012-09-20 20:29:18 -07001939/*
1940 * Free a DSP DMA via an SCP message
1941 */
Ian Minett01ef7db2012-09-20 20:29:16 -07001942static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1943{
1944 int status = 0;
1945 unsigned int dummy = 0;
1946
Takashi Iwai4e76a882014-02-25 12:21:03 +01001947 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1948 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
Ian Minett01ef7db2012-09-20 20:29:16 -07001949
Connor McAdams447fd8e2018-05-08 13:20:09 -04001950 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1951 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1952 sizeof(dma_chan), NULL, &dummy);
Ian Minett01ef7db2012-09-20 20:29:16 -07001953
1954 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01001955 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001956 return status;
1957 }
1958
Takashi Iwai4e76a882014-02-25 12:21:03 +01001959 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07001960
1961 return status;
1962}
1963
1964/*
Ian Minettd5c21b82012-09-20 20:29:18 -07001965 * (Re)start the DSP
Ian Minett01ef7db2012-09-20 20:29:16 -07001966 */
1967static int dsp_set_run_state(struct hda_codec *codec)
1968{
1969 unsigned int dbg_ctrl_reg;
1970 unsigned int halt_state;
1971 int err;
1972
1973 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1974 if (err < 0)
1975 return err;
1976
1977 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1978 DSP_DBGCNTL_STATE_LOBIT;
1979
1980 if (halt_state != 0) {
1981 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1982 DSP_DBGCNTL_SS_MASK);
1983 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1984 dbg_ctrl_reg);
1985 if (err < 0)
1986 return err;
1987
1988 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1989 DSP_DBGCNTL_EXEC_MASK;
1990 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1991 dbg_ctrl_reg);
1992 if (err < 0)
1993 return err;
1994 }
1995
1996 return 0;
1997}
1998
Ian Minettd5c21b82012-09-20 20:29:18 -07001999/*
2000 * Reset the DSP
2001 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002002static int dsp_reset(struct hda_codec *codec)
2003{
2004 unsigned int res;
2005 int retry = 20;
2006
Takashi Iwai4e76a882014-02-25 12:21:03 +01002007 codec_dbg(codec, "dsp_reset\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002008 do {
2009 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2010 retry--;
2011 } while (res == -EIO && retry);
2012
2013 if (!retry) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002014 codec_dbg(codec, "dsp_reset timeout\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002015 return -EIO;
2016 }
2017
2018 return 0;
2019}
2020
Ian Minettd5c21b82012-09-20 20:29:18 -07002021/*
2022 * Convert chip address to DSP address
2023 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002024static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2025 bool *code, bool *yram)
2026{
2027 *code = *yram = false;
2028
2029 if (UC_RANGE(chip_addx, 1)) {
2030 *code = true;
2031 return UC_OFF(chip_addx);
2032 } else if (X_RANGE_ALL(chip_addx, 1)) {
2033 return X_OFF(chip_addx);
2034 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2035 *yram = true;
2036 return Y_OFF(chip_addx);
2037 }
2038
Takashi Iwai4a8b89f2013-02-12 10:15:15 +01002039 return INVALID_CHIP_ADDRESS;
Ian Minett01ef7db2012-09-20 20:29:16 -07002040}
2041
Ian Minettd5c21b82012-09-20 20:29:18 -07002042/*
2043 * Check if the DSP DMA is active
2044 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002045static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2046{
2047 unsigned int dma_chnlstart_reg;
2048
2049 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2050
2051 return ((dma_chnlstart_reg & (1 <<
2052 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2053}
2054
2055static int dsp_dma_setup_common(struct hda_codec *codec,
2056 unsigned int chip_addx,
2057 unsigned int dma_chan,
2058 unsigned int port_map_mask,
2059 bool ovly)
2060{
2061 int status = 0;
2062 unsigned int chnl_prop;
2063 unsigned int dsp_addx;
2064 unsigned int active;
2065 bool code, yram;
2066
Takashi Iwai4e76a882014-02-25 12:21:03 +01002067 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002068
2069 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002070 codec_dbg(codec, "dma chan num invalid\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002071 return -EINVAL;
2072 }
2073
2074 if (dsp_is_dma_active(codec, dma_chan)) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002075 codec_dbg(codec, "dma already active\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002076 return -EBUSY;
2077 }
2078
2079 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2080
2081 if (dsp_addx == INVALID_CHIP_ADDRESS) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002082 codec_dbg(codec, "invalid chip addr\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002083 return -ENXIO;
2084 }
2085
2086 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2087 active = 0;
2088
Takashi Iwai4e76a882014-02-25 12:21:03 +01002089 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002090
2091 if (ovly) {
2092 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2093 &chnl_prop);
2094
2095 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002096 codec_dbg(codec, "read CHNLPROP Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002097 return status;
2098 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002099 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002100 }
2101
2102 if (!code)
2103 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2104 else
2105 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2106
2107 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2108
2109 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2110 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002111 codec_dbg(codec, "write CHNLPROP Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002112 return status;
2113 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002114 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002115
2116 if (ovly) {
2117 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2118 &active);
2119
2120 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002121 codec_dbg(codec, "read ACTIVE Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002122 return status;
2123 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002124 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002125 }
2126
2127 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2128 DSPDMAC_ACTIVE_AAR_MASK;
2129
2130 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2131 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002132 codec_dbg(codec, "write ACTIVE Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002133 return status;
2134 }
2135
Takashi Iwai4e76a882014-02-25 12:21:03 +01002136 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002137
2138 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2139 port_map_mask);
2140 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002141 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002142 return status;
2143 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002144 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002145
2146 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2147 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2148 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002149 codec_dbg(codec, "write IRQCNT Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002150 return status;
2151 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002152 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002153
Takashi Iwai4e76a882014-02-25 12:21:03 +01002154 codec_dbg(codec,
Ian Minett01ef7db2012-09-20 20:29:16 -07002155 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2156 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2157 chip_addx, dsp_addx, dma_chan,
2158 port_map_mask, chnl_prop, active);
2159
Takashi Iwai4e76a882014-02-25 12:21:03 +01002160 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002161
2162 return 0;
2163}
2164
Ian Minettd5c21b82012-09-20 20:29:18 -07002165/*
2166 * Setup the DSP DMA per-transfer-specific registers
2167 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002168static int dsp_dma_setup(struct hda_codec *codec,
2169 unsigned int chip_addx,
2170 unsigned int count,
2171 unsigned int dma_chan)
2172{
2173 int status = 0;
2174 bool code, yram;
2175 unsigned int dsp_addx;
2176 unsigned int addr_field;
2177 unsigned int incr_field;
2178 unsigned int base_cnt;
2179 unsigned int cur_cnt;
2180 unsigned int dma_cfg = 0;
2181 unsigned int adr_ofs = 0;
2182 unsigned int xfr_cnt = 0;
2183 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2184 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2185
Takashi Iwai4e76a882014-02-25 12:21:03 +01002186 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002187
2188 if (count > max_dma_count) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002189 codec_dbg(codec, "count too big\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002190 return -EINVAL;
2191 }
2192
2193 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2194 if (dsp_addx == INVALID_CHIP_ADDRESS) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002195 codec_dbg(codec, "invalid chip addr\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002196 return -ENXIO;
2197 }
2198
Takashi Iwai4e76a882014-02-25 12:21:03 +01002199 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002200
2201 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2202 incr_field = 0;
2203
2204 if (!code) {
2205 addr_field <<= 1;
2206 if (yram)
2207 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2208
2209 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2210 }
2211
2212 dma_cfg = addr_field + incr_field;
2213 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2214 dma_cfg);
2215 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002216 codec_dbg(codec, "write DMACFG Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002217 return status;
2218 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002219 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002220
2221 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2222 (code ? 0 : 1));
2223
2224 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2225 adr_ofs);
2226 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002227 codec_dbg(codec, "write DSPADROFS Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002228 return status;
2229 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002230 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002231
2232 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2233
2234 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2235
2236 xfr_cnt = base_cnt | cur_cnt;
2237
2238 status = chipio_write(codec,
2239 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2240 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002241 codec_dbg(codec, "write XFRCNT Reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002242 return status;
2243 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002244 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002245
Takashi Iwai4e76a882014-02-25 12:21:03 +01002246 codec_dbg(codec,
Ian Minett01ef7db2012-09-20 20:29:16 -07002247 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2248 "ADROFS=0x%x, XFRCNT=0x%x\n",
2249 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2250
Takashi Iwai4e76a882014-02-25 12:21:03 +01002251 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002252
2253 return 0;
2254}
2255
Ian Minettd5c21b82012-09-20 20:29:18 -07002256/*
2257 * Start the DSP DMA
2258 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002259static int dsp_dma_start(struct hda_codec *codec,
2260 unsigned int dma_chan, bool ovly)
2261{
2262 unsigned int reg = 0;
2263 int status = 0;
2264
Takashi Iwai4e76a882014-02-25 12:21:03 +01002265 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002266
2267 if (ovly) {
2268 status = chipio_read(codec,
2269 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2270
2271 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002272 codec_dbg(codec, "read CHNLSTART reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002273 return status;
2274 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002275 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002276
2277 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2278 DSPDMAC_CHNLSTART_DIS_MASK);
2279 }
2280
2281 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2282 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2283 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002284 codec_dbg(codec, "write CHNLSTART reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002285 return status;
2286 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002287 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002288
2289 return status;
2290}
2291
Ian Minettd5c21b82012-09-20 20:29:18 -07002292/*
2293 * Stop the DSP DMA
2294 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002295static int dsp_dma_stop(struct hda_codec *codec,
2296 unsigned int dma_chan, bool ovly)
2297{
2298 unsigned int reg = 0;
2299 int status = 0;
2300
Takashi Iwai4e76a882014-02-25 12:21:03 +01002301 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002302
2303 if (ovly) {
2304 status = chipio_read(codec,
2305 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2306
2307 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002308 codec_dbg(codec, "read CHNLSTART reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002309 return status;
2310 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002311 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002312 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2313 DSPDMAC_CHNLSTART_DIS_MASK);
2314 }
2315
2316 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2317 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2318 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002319 codec_dbg(codec, "write CHNLSTART reg fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002320 return status;
2321 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002322 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002323
2324 return status;
2325}
2326
Ian Minettd5c21b82012-09-20 20:29:18 -07002327/**
2328 * Allocate router ports
2329 *
2330 * @codec: the HDA codec
2331 * @num_chans: number of channels in the stream
2332 * @ports_per_channel: number of ports per channel
2333 * @start_device: start device
2334 * @port_map: pointer to the port list to hold the allocated ports
2335 *
2336 * Returns zero or a negative error code.
2337 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002338static int dsp_allocate_router_ports(struct hda_codec *codec,
2339 unsigned int num_chans,
2340 unsigned int ports_per_channel,
2341 unsigned int start_device,
2342 unsigned int *port_map)
2343{
2344 int status = 0;
2345 int res;
2346 u8 val;
2347
2348 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2349 if (status < 0)
2350 return status;
2351
2352 val = start_device << 6;
2353 val |= (ports_per_channel - 1) << 4;
2354 val |= num_chans - 1;
2355
2356 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2357 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2358 val);
2359
2360 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2361 VENDOR_CHIPIO_PORT_ALLOC_SET,
2362 MEM_CONNID_DSP);
2363
2364 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2365 if (status < 0)
2366 return status;
2367
2368 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2369 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2370
2371 *port_map = res;
2372
2373 return (res < 0) ? res : 0;
2374}
2375
Ian Minettd5c21b82012-09-20 20:29:18 -07002376/*
2377 * Free router ports
2378 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002379static int dsp_free_router_ports(struct hda_codec *codec)
2380{
2381 int status = 0;
2382
2383 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2384 if (status < 0)
2385 return status;
2386
2387 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2388 VENDOR_CHIPIO_PORT_FREE_SET,
2389 MEM_CONNID_DSP);
2390
2391 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2392
2393 return status;
2394}
2395
Ian Minettd5c21b82012-09-20 20:29:18 -07002396/*
2397 * Allocate DSP ports for the download stream
2398 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002399static int dsp_allocate_ports(struct hda_codec *codec,
2400 unsigned int num_chans,
2401 unsigned int rate_multi, unsigned int *port_map)
2402{
2403 int status;
2404
Takashi Iwai4e76a882014-02-25 12:21:03 +01002405 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002406
2407 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002408 codec_dbg(codec, "bad rate multiple\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002409 return -EINVAL;
2410 }
2411
2412 status = dsp_allocate_router_ports(codec, num_chans,
2413 rate_multi, 0, port_map);
2414
Takashi Iwai4e76a882014-02-25 12:21:03 +01002415 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002416
2417 return status;
2418}
2419
Ian Minett01ef7db2012-09-20 20:29:16 -07002420static int dsp_allocate_ports_format(struct hda_codec *codec,
2421 const unsigned short fmt,
2422 unsigned int *port_map)
2423{
2424 int status;
2425 unsigned int num_chans;
2426
2427 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2428 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2429 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2430
2431 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002432 codec_dbg(codec, "bad rate multiple\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002433 return -EINVAL;
2434 }
2435
2436 num_chans = get_hdafmt_chs(fmt) + 1;
2437
2438 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2439
2440 return status;
2441}
2442
2443/*
Ian Minettd5c21b82012-09-20 20:29:18 -07002444 * free DSP ports
2445 */
2446static int dsp_free_ports(struct hda_codec *codec)
2447{
2448 int status;
2449
Takashi Iwai4e76a882014-02-25 12:21:03 +01002450 codec_dbg(codec, " dsp_free_ports() -- begin\n");
Ian Minettd5c21b82012-09-20 20:29:18 -07002451
2452 status = dsp_free_router_ports(codec);
2453 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002454 codec_dbg(codec, "free router ports fail\n");
Ian Minettd5c21b82012-09-20 20:29:18 -07002455 return status;
2456 }
Takashi Iwai4e76a882014-02-25 12:21:03 +01002457 codec_dbg(codec, " dsp_free_ports() -- complete\n");
Ian Minettd5c21b82012-09-20 20:29:18 -07002458
2459 return status;
2460}
2461
2462/*
Ian Minett01ef7db2012-09-20 20:29:16 -07002463 * HDA DMA engine stuffs for DSP code download
2464 */
2465struct dma_engine {
2466 struct hda_codec *codec;
2467 unsigned short m_converter_format;
2468 struct snd_dma_buffer *dmab;
2469 unsigned int buf_size;
2470};
2471
2472
2473enum dma_state {
2474 DMA_STATE_STOP = 0,
2475 DMA_STATE_RUN = 1
2476};
2477
Takashi Iwai6194b992014-06-06 18:12:16 +02002478static int dma_convert_to_hda_format(struct hda_codec *codec,
Ian Minette97249d2012-09-20 20:29:21 -07002479 unsigned int sample_rate,
2480 unsigned short channels,
Ian Minett01ef7db2012-09-20 20:29:16 -07002481 unsigned short *hda_format)
2482{
2483 unsigned int format_val;
2484
Takashi Iwaib7d023e2015-04-16 08:19:06 +02002485 format_val = snd_hdac_calc_stream_format(sample_rate,
2486 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
Ian Minett01ef7db2012-09-20 20:29:16 -07002487
2488 if (hda_format)
2489 *hda_format = (unsigned short)format_val;
2490
2491 return 0;
2492}
2493
Ian Minettd5c21b82012-09-20 20:29:18 -07002494/*
2495 * Reset DMA for DSP download
2496 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002497static int dma_reset(struct dma_engine *dma)
2498{
2499 struct hda_codec *codec = dma->codec;
2500 struct ca0132_spec *spec = codec->spec;
2501 int status;
2502
Takashi Iwaib3667bd2013-02-10 11:58:40 +01002503 if (dma->dmab->area)
Ian Minett01ef7db2012-09-20 20:29:16 -07002504 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2505
2506 status = snd_hda_codec_load_dsp_prepare(codec,
2507 dma->m_converter_format,
2508 dma->buf_size,
2509 dma->dmab);
2510 if (status < 0)
2511 return status;
2512 spec->dsp_stream_id = status;
2513 return 0;
2514}
2515
2516static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2517{
2518 bool cmd;
2519
Ian Minett01ef7db2012-09-20 20:29:16 -07002520 switch (state) {
2521 case DMA_STATE_STOP:
2522 cmd = false;
2523 break;
2524 case DMA_STATE_RUN:
2525 cmd = true;
2526 break;
2527 default:
2528 return 0;
2529 }
2530
2531 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2532 return 0;
2533}
2534
2535static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2536{
2537 return dma->dmab->bytes;
2538}
2539
2540static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2541{
2542 return dma->dmab->area;
2543}
2544
2545static int dma_xfer(struct dma_engine *dma,
2546 const unsigned int *data,
2547 unsigned int count)
2548{
2549 memcpy(dma->dmab->area, data, count);
2550 return 0;
2551}
2552
2553static void dma_get_converter_format(
2554 struct dma_engine *dma,
2555 unsigned short *format)
2556{
2557 if (format)
2558 *format = dma->m_converter_format;
2559}
2560
2561static unsigned int dma_get_stream_id(struct dma_engine *dma)
2562{
2563 struct ca0132_spec *spec = dma->codec->spec;
2564
2565 return spec->dsp_stream_id;
2566}
2567
2568struct dsp_image_seg {
2569 u32 magic;
2570 u32 chip_addr;
2571 u32 count;
2572 u32 data[0];
2573};
2574
2575static const u32 g_magic_value = 0x4c46584d;
2576static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2577
2578static bool is_valid(const struct dsp_image_seg *p)
2579{
2580 return p->magic == g_magic_value;
2581}
2582
2583static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2584{
2585 return g_chip_addr_magic_value == p->chip_addr;
2586}
2587
2588static bool is_last(const struct dsp_image_seg *p)
2589{
2590 return p->count == 0;
2591}
2592
2593static size_t dsp_sizeof(const struct dsp_image_seg *p)
2594{
2595 return sizeof(*p) + p->count*sizeof(u32);
2596}
2597
2598static const struct dsp_image_seg *get_next_seg_ptr(
2599 const struct dsp_image_seg *p)
2600{
2601 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2602}
2603
2604/*
2605 * CA0132 chip DSP transfer stuffs. For DSP download.
2606 */
Takashi Iwai8ae3124b2013-01-15 17:43:09 +01002607#define INVALID_DMA_CHANNEL (~0U)
Ian Minett01ef7db2012-09-20 20:29:16 -07002608
Ian Minettd5c21b82012-09-20 20:29:18 -07002609/*
2610 * Program a list of address/data pairs via the ChipIO widget.
2611 * The segment data is in the format of successive pairs of words.
2612 * These are repeated as indicated by the segment's count field.
2613 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002614static int dspxfr_hci_write(struct hda_codec *codec,
2615 const struct dsp_image_seg *fls)
2616{
2617 int status;
2618 const u32 *data;
2619 unsigned int count;
2620
2621 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002622 codec_dbg(codec, "hci_write invalid params\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002623 return -EINVAL;
2624 }
2625
2626 count = fls->count;
2627 data = (u32 *)(fls->data);
2628 while (count >= 2) {
2629 status = chipio_write(codec, data[0], data[1]);
2630 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002631 codec_dbg(codec, "hci_write chipio failed\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002632 return status;
2633 }
2634 count -= 2;
2635 data += 2;
2636 }
2637 return 0;
2638}
2639
Ian Minettd5c21b82012-09-20 20:29:18 -07002640/**
2641 * Write a block of data into DSP code or data RAM using pre-allocated
2642 * DMA engine.
2643 *
2644 * @codec: the HDA codec
2645 * @fls: pointer to a fast load image
2646 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2647 * no relocation
2648 * @dma_engine: pointer to DMA engine to be used for DSP download
2649 * @dma_chan: The number of DMA channels used for DSP download
2650 * @port_map_mask: port mapping
2651 * @ovly: TRUE if overlay format is required
2652 *
2653 * Returns zero or a negative error code.
2654 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002655static int dspxfr_one_seg(struct hda_codec *codec,
2656 const struct dsp_image_seg *fls,
2657 unsigned int reloc,
2658 struct dma_engine *dma_engine,
2659 unsigned int dma_chan,
2660 unsigned int port_map_mask,
2661 bool ovly)
2662{
Ian Minett406261c2012-12-20 18:53:41 -08002663 int status = 0;
Ian Minett01ef7db2012-09-20 20:29:16 -07002664 bool comm_dma_setup_done = false;
2665 const unsigned int *data;
2666 unsigned int chip_addx;
2667 unsigned int words_to_write;
2668 unsigned int buffer_size_words;
2669 unsigned char *buffer_addx;
2670 unsigned short hda_format;
2671 unsigned int sample_rate_div;
2672 unsigned int sample_rate_mul;
2673 unsigned int num_chans;
2674 unsigned int hda_frame_size_words;
2675 unsigned int remainder_words;
2676 const u32 *data_remainder;
2677 u32 chip_addx_remainder;
2678 unsigned int run_size_words;
2679 const struct dsp_image_seg *hci_write = NULL;
Ian Minett6d675302013-02-08 18:31:43 -08002680 unsigned long timeout;
2681 bool dma_active;
Ian Minett01ef7db2012-09-20 20:29:16 -07002682
2683 if (fls == NULL)
2684 return -EINVAL;
2685 if (is_hci_prog_list_seg(fls)) {
2686 hci_write = fls;
2687 fls = get_next_seg_ptr(fls);
2688 }
2689
2690 if (hci_write && (!fls || is_last(fls))) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002691 codec_dbg(codec, "hci_write\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002692 return dspxfr_hci_write(codec, hci_write);
2693 }
2694
2695 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002696 codec_dbg(codec, "Invalid Params\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002697 return -EINVAL;
2698 }
2699
2700 data = fls->data;
2701 chip_addx = fls->chip_addr,
2702 words_to_write = fls->count;
2703
2704 if (!words_to_write)
2705 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2706 if (reloc)
2707 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2708
2709 if (!UC_RANGE(chip_addx, words_to_write) &&
2710 !X_RANGE_ALL(chip_addx, words_to_write) &&
2711 !Y_RANGE_ALL(chip_addx, words_to_write)) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002712 codec_dbg(codec, "Invalid chip_addx Params\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002713 return -EINVAL;
2714 }
2715
2716 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2717 sizeof(u32);
2718
2719 buffer_addx = dma_get_buffer_addr(dma_engine);
2720
2721 if (buffer_addx == NULL) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002722 codec_dbg(codec, "dma_engine buffer NULL\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002723 return -EINVAL;
2724 }
2725
2726 dma_get_converter_format(dma_engine, &hda_format);
2727 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2728 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2729 num_chans = get_hdafmt_chs(hda_format) + 1;
2730
2731 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2732 (num_chans * sample_rate_mul / sample_rate_div));
2733
Xi Wang3bc085a2013-03-07 00:13:51 -05002734 if (hda_frame_size_words == 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002735 codec_dbg(codec, "frmsz zero\n");
Xi Wang3bc085a2013-03-07 00:13:51 -05002736 return -EINVAL;
2737 }
2738
Ian Minett01ef7db2012-09-20 20:29:16 -07002739 buffer_size_words = min(buffer_size_words,
2740 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2741 65536 : 32768));
2742 buffer_size_words -= buffer_size_words % hda_frame_size_words;
Takashi Iwai4e76a882014-02-25 12:21:03 +01002743 codec_dbg(codec,
Ian Minett01ef7db2012-09-20 20:29:16 -07002744 "chpadr=0x%08x frmsz=%u nchan=%u "
2745 "rate_mul=%u div=%u bufsz=%u\n",
2746 chip_addx, hda_frame_size_words, num_chans,
2747 sample_rate_mul, sample_rate_div, buffer_size_words);
2748
Xi Wang3bc085a2013-03-07 00:13:51 -05002749 if (buffer_size_words < hda_frame_size_words) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002750 codec_dbg(codec, "dspxfr_one_seg:failed\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002751 return -EINVAL;
2752 }
2753
2754 remainder_words = words_to_write % hda_frame_size_words;
2755 data_remainder = data;
2756 chip_addx_remainder = chip_addx;
2757
2758 data += remainder_words;
2759 chip_addx += remainder_words*sizeof(u32);
2760 words_to_write -= remainder_words;
2761
2762 while (words_to_write != 0) {
2763 run_size_words = min(buffer_size_words, words_to_write);
Takashi Iwai4e76a882014-02-25 12:21:03 +01002764 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
Ian Minett01ef7db2012-09-20 20:29:16 -07002765 words_to_write, run_size_words, remainder_words);
2766 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2767 if (!comm_dma_setup_done) {
2768 status = dsp_dma_stop(codec, dma_chan, ovly);
2769 if (status < 0)
Takashi Iwai425a7882013-01-15 17:41:21 +01002770 return status;
Ian Minett01ef7db2012-09-20 20:29:16 -07002771 status = dsp_dma_setup_common(codec, chip_addx,
2772 dma_chan, port_map_mask, ovly);
2773 if (status < 0)
2774 return status;
2775 comm_dma_setup_done = true;
2776 }
2777
2778 status = dsp_dma_setup(codec, chip_addx,
2779 run_size_words, dma_chan);
2780 if (status < 0)
2781 return status;
2782 status = dsp_dma_start(codec, dma_chan, ovly);
2783 if (status < 0)
2784 return status;
2785 if (!dsp_is_dma_active(codec, dma_chan)) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002786 codec_dbg(codec, "dspxfr:DMA did not start\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002787 return -EIO;
2788 }
2789 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2790 if (status < 0)
2791 return status;
2792 if (remainder_words != 0) {
2793 status = chipio_write_multiple(codec,
2794 chip_addx_remainder,
2795 data_remainder,
2796 remainder_words);
Takashi Iwaib3667bd2013-02-10 11:58:40 +01002797 if (status < 0)
2798 return status;
Ian Minett01ef7db2012-09-20 20:29:16 -07002799 remainder_words = 0;
2800 }
2801 if (hci_write) {
2802 status = dspxfr_hci_write(codec, hci_write);
Takashi Iwaib3667bd2013-02-10 11:58:40 +01002803 if (status < 0)
2804 return status;
Ian Minett01ef7db2012-09-20 20:29:16 -07002805 hci_write = NULL;
2806 }
Ian Minett6d675302013-02-08 18:31:43 -08002807
2808 timeout = jiffies + msecs_to_jiffies(2000);
2809 do {
2810 dma_active = dsp_is_dma_active(codec, dma_chan);
2811 if (!dma_active)
Ian Minett01ef7db2012-09-20 20:29:16 -07002812 break;
Ian Minett6d675302013-02-08 18:31:43 -08002813 msleep(20);
2814 } while (time_before(jiffies, timeout));
2815 if (dma_active)
2816 break;
2817
Takashi Iwai4e76a882014-02-25 12:21:03 +01002818 codec_dbg(codec, "+++++ DMA complete\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002819 dma_set_state(dma_engine, DMA_STATE_STOP);
Takashi Iwaib3667bd2013-02-10 11:58:40 +01002820 status = dma_reset(dma_engine);
Ian Minett01ef7db2012-09-20 20:29:16 -07002821
2822 if (status < 0)
2823 return status;
2824
2825 data += run_size_words;
2826 chip_addx += run_size_words*sizeof(u32);
2827 words_to_write -= run_size_words;
2828 }
2829
2830 if (remainder_words != 0) {
2831 status = chipio_write_multiple(codec, chip_addx_remainder,
2832 data_remainder, remainder_words);
2833 }
2834
2835 return status;
2836}
2837
Ian Minettd5c21b82012-09-20 20:29:18 -07002838/**
2839 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2840 *
2841 * @codec: the HDA codec
2842 * @fls_data: pointer to a fast load image
2843 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2844 * no relocation
Ian Minette97249d2012-09-20 20:29:21 -07002845 * @sample_rate: sampling rate of the stream used for DSP download
Takashi Iwaie60b2c72014-11-10 16:47:26 +01002846 * @channels: channels of the stream used for DSP download
Ian Minettd5c21b82012-09-20 20:29:18 -07002847 * @ovly: TRUE if overlay format is required
2848 *
2849 * Returns zero or a negative error code.
2850 */
Ian Minett01ef7db2012-09-20 20:29:16 -07002851static int dspxfr_image(struct hda_codec *codec,
2852 const struct dsp_image_seg *fls_data,
Ian Minette97249d2012-09-20 20:29:21 -07002853 unsigned int reloc,
2854 unsigned int sample_rate,
2855 unsigned short channels,
Ian Minett01ef7db2012-09-20 20:29:16 -07002856 bool ovly)
2857{
2858 struct ca0132_spec *spec = codec->spec;
2859 int status;
2860 unsigned short hda_format = 0;
2861 unsigned int response;
2862 unsigned char stream_id = 0;
2863 struct dma_engine *dma_engine;
2864 unsigned int dma_chan;
2865 unsigned int port_map_mask;
2866
2867 if (fls_data == NULL)
2868 return -EINVAL;
2869
2870 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
Takashi Iwai549e8292013-01-15 17:42:15 +01002871 if (!dma_engine)
2872 return -ENOMEM;
Ian Minett01ef7db2012-09-20 20:29:16 -07002873
2874 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2875 if (!dma_engine->dmab) {
Takashi Iwai549e8292013-01-15 17:42:15 +01002876 kfree(dma_engine);
2877 return -ENOMEM;
Ian Minett01ef7db2012-09-20 20:29:16 -07002878 }
2879
2880 dma_engine->codec = codec;
Takashi Iwai6194b992014-06-06 18:12:16 +02002881 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
Ian Minett01ef7db2012-09-20 20:29:16 -07002882 dma_engine->m_converter_format = hda_format;
2883 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2884 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2885
Takashi Iwai8ae3124b2013-01-15 17:43:09 +01002886 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
Ian Minett01ef7db2012-09-20 20:29:16 -07002887
2888 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2889 hda_format, &response);
2890
2891 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002892 codec_dbg(codec, "set converter format fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002893 goto exit;
2894 }
2895
2896 status = snd_hda_codec_load_dsp_prepare(codec,
2897 dma_engine->m_converter_format,
2898 dma_engine->buf_size,
2899 dma_engine->dmab);
2900 if (status < 0)
2901 goto exit;
2902 spec->dsp_stream_id = status;
2903
2904 if (ovly) {
2905 status = dspio_alloc_dma_chan(codec, &dma_chan);
2906 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002907 codec_dbg(codec, "alloc dmachan fail\n");
Takashi Iwai8ae3124b2013-01-15 17:43:09 +01002908 dma_chan = INVALID_DMA_CHANNEL;
Ian Minett01ef7db2012-09-20 20:29:16 -07002909 goto exit;
2910 }
2911 }
2912
2913 port_map_mask = 0;
2914 status = dsp_allocate_ports_format(codec, hda_format,
2915 &port_map_mask);
2916 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002917 codec_dbg(codec, "alloc ports fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002918 goto exit;
2919 }
2920
2921 stream_id = dma_get_stream_id(dma_engine);
2922 status = codec_set_converter_stream_channel(codec,
2923 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2924 if (status < 0) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002925 codec_dbg(codec, "set stream chan fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002926 goto exit;
2927 }
2928
2929 while ((fls_data != NULL) && !is_last(fls_data)) {
2930 if (!is_valid(fls_data)) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01002931 codec_dbg(codec, "FLS check fail\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07002932 status = -EINVAL;
2933 goto exit;
2934 }
2935 status = dspxfr_one_seg(codec, fls_data, reloc,
2936 dma_engine, dma_chan,
2937 port_map_mask, ovly);
2938 if (status < 0)
2939 break;
2940
2941 if (is_hci_prog_list_seg(fls_data))
2942 fls_data = get_next_seg_ptr(fls_data);
2943
2944 if ((fls_data != NULL) && !is_last(fls_data))
2945 fls_data = get_next_seg_ptr(fls_data);
2946 }
2947
2948 if (port_map_mask != 0)
2949 status = dsp_free_ports(codec);
2950
2951 if (status < 0)
2952 goto exit;
2953
2954 status = codec_set_converter_stream_channel(codec,
2955 WIDGET_CHIP_CTRL, 0, 0, &response);
2956
2957exit:
2958 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2959 dspio_free_dma_chan(codec, dma_chan);
2960
Takashi Iwaib3667bd2013-02-10 11:58:40 +01002961 if (dma_engine->dmab->area)
Ian Minett01ef7db2012-09-20 20:29:16 -07002962 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2963 kfree(dma_engine->dmab);
2964 kfree(dma_engine);
2965
2966 return status;
2967}
2968
2969/*
2970 * CA0132 DSP download stuffs.
2971 */
2972static void dspload_post_setup(struct hda_codec *codec)
2973{
Connor McAdams009b8f92018-05-08 13:20:06 -04002974 struct ca0132_spec *spec = codec->spec;
Takashi Iwai4e76a882014-02-25 12:21:03 +01002975 codec_dbg(codec, "---- dspload_post_setup ------\n");
Connor McAdams009b8f92018-05-08 13:20:06 -04002976 if (!spec->use_alt_functions) {
2977 /*set DSP speaker to 2.0 configuration*/
2978 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2979 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
Ian Minett01ef7db2012-09-20 20:29:16 -07002980
Connor McAdams009b8f92018-05-08 13:20:06 -04002981 /*update write pointer*/
2982 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2983 }
Ian Minett01ef7db2012-09-20 20:29:16 -07002984}
2985
Ian Minettd5c21b82012-09-20 20:29:18 -07002986/**
Takashi Iwaie60b2c72014-11-10 16:47:26 +01002987 * dspload_image - Download DSP from a DSP Image Fast Load structure.
Ian Minettd5c21b82012-09-20 20:29:18 -07002988 *
2989 * @codec: the HDA codec
2990 * @fls: pointer to a fast load image
2991 * @ovly: TRUE if overlay format is required
2992 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2993 * no relocation
2994 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2995 * @router_chans: number of audio router channels to be allocated (0 means use
2996 * internal defaults; max is 32)
2997 *
Takashi Iwaie60b2c72014-11-10 16:47:26 +01002998 * Download DSP from a DSP Image Fast Load structure. This structure is a
2999 * linear, non-constant sized element array of structures, each of which
3000 * contain the count of the data to be loaded, the data itself, and the
3001 * corresponding starting chip address of the starting data location.
Ian Minettd5c21b82012-09-20 20:29:18 -07003002 * Returns zero or a negative error code.
3003 */
Ian Minett01ef7db2012-09-20 20:29:16 -07003004static int dspload_image(struct hda_codec *codec,
3005 const struct dsp_image_seg *fls,
3006 bool ovly,
3007 unsigned int reloc,
3008 bool autostart,
3009 int router_chans)
3010{
3011 int status = 0;
Ian Minette97249d2012-09-20 20:29:21 -07003012 unsigned int sample_rate;
3013 unsigned short channels;
Ian Minett01ef7db2012-09-20 20:29:16 -07003014
Takashi Iwai4e76a882014-02-25 12:21:03 +01003015 codec_dbg(codec, "---- dspload_image begin ------\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07003016 if (router_chans == 0) {
3017 if (!ovly)
3018 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3019 else
3020 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3021 }
3022
Ian Minette97249d2012-09-20 20:29:21 -07003023 sample_rate = 48000;
3024 channels = (unsigned short)router_chans;
Ian Minett01ef7db2012-09-20 20:29:16 -07003025
Ian Minette97249d2012-09-20 20:29:21 -07003026 while (channels > 16) {
3027 sample_rate *= 2;
3028 channels /= 2;
Ian Minett01ef7db2012-09-20 20:29:16 -07003029 }
3030
Ian Minett01ef7db2012-09-20 20:29:16 -07003031 do {
Takashi Iwai4e76a882014-02-25 12:21:03 +01003032 codec_dbg(codec, "Ready to program DMA\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07003033 if (!ovly)
3034 status = dsp_reset(codec);
3035
3036 if (status < 0)
3037 break;
3038
Takashi Iwai4e76a882014-02-25 12:21:03 +01003039 codec_dbg(codec, "dsp_reset() complete\n");
Ian Minette97249d2012-09-20 20:29:21 -07003040 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3041 ovly);
Ian Minett01ef7db2012-09-20 20:29:16 -07003042
3043 if (status < 0)
3044 break;
3045
Takashi Iwai4e76a882014-02-25 12:21:03 +01003046 codec_dbg(codec, "dspxfr_image() complete\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07003047 if (autostart && !ovly) {
3048 dspload_post_setup(codec);
3049 status = dsp_set_run_state(codec);
3050 }
3051
Takashi Iwai4e76a882014-02-25 12:21:03 +01003052 codec_dbg(codec, "LOAD FINISHED\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07003053 } while (0);
3054
3055 return status;
3056}
3057
Takashi Iwaif6644172013-02-11 14:18:29 +01003058#ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
Ian Minett01ef7db2012-09-20 20:29:16 -07003059static bool dspload_is_loaded(struct hda_codec *codec)
3060{
3061 unsigned int data = 0;
3062 int status = 0;
3063
3064 status = chipio_read(codec, 0x40004, &data);
3065 if ((status < 0) || (data != 1))
3066 return false;
3067
3068 return true;
3069}
Takashi Iwaif6644172013-02-11 14:18:29 +01003070#else
3071#define dspload_is_loaded(codec) false
3072#endif
Ian Minett01ef7db2012-09-20 20:29:16 -07003073
3074static bool dspload_wait_loaded(struct hda_codec *codec)
3075{
Ian Minett6d675302013-02-08 18:31:43 -08003076 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
Ian Minett01ef7db2012-09-20 20:29:16 -07003077
3078 do {
Ian Minett01ef7db2012-09-20 20:29:16 -07003079 if (dspload_is_loaded(codec)) {
Takashi Iwaid9684bb2015-10-26 16:54:16 +01003080 codec_info(codec, "ca0132 DSP downloaded and running\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07003081 return true;
3082 }
Ian Minett6d675302013-02-08 18:31:43 -08003083 msleep(20);
3084 } while (time_before(jiffies, timeout));
Ian Minett01ef7db2012-09-20 20:29:16 -07003085
Takashi Iwaid9684bb2015-10-26 16:54:16 +01003086 codec_err(codec, "ca0132 failed to download DSP\n");
Ian Minett01ef7db2012-09-20 20:29:16 -07003087 return false;
3088}
3089
Ian Minett5aaca442012-12-20 18:53:34 -08003090/*
Connor McAdamse93ac302018-05-08 13:20:05 -04003091 * Setup GPIO for the other variants of Core3D.
3092 */
3093
3094/*
Connor McAdamsa62e4732018-08-08 13:34:12 -04003095 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3096 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3097 * The first eight bits are just the number of the pin. So far, I've only seen
3098 * this number go to 7.
3099 */
3100static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3101 bool enable)
3102{
3103 struct ca0132_spec *spec = codec->spec;
3104 unsigned short gpio_data;
3105
3106 gpio_data = gpio_pin & 0xF;
3107 gpio_data |= ((enable << 8) & 0x100);
3108
3109 writew(gpio_data, spec->mem_base + 0x320);
3110}
3111
3112/*
Connor McAdamse93ac302018-05-08 13:20:05 -04003113 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3114 * the card shows as having no GPIO pins.
3115 */
3116static void ca0132_gpio_init(struct hda_codec *codec)
3117{
3118 struct ca0132_spec *spec = codec->spec;
3119
3120 switch (spec->quirk) {
3121 case QUIRK_SBZ:
3122 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3123 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3124 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3125 break;
3126 case QUIRK_R3DI:
3127 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3128 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3129 break;
3130 }
3131
3132}
3133
3134/* Sets the GPIO for audio output. */
3135static void ca0132_gpio_setup(struct hda_codec *codec)
3136{
3137 struct ca0132_spec *spec = codec->spec;
3138
3139 switch (spec->quirk) {
3140 case QUIRK_SBZ:
3141 snd_hda_codec_write(codec, 0x01, 0,
3142 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3143 snd_hda_codec_write(codec, 0x01, 0,
3144 AC_VERB_SET_GPIO_MASK, 0x07);
3145 snd_hda_codec_write(codec, 0x01, 0,
3146 AC_VERB_SET_GPIO_DATA, 0x04);
3147 snd_hda_codec_write(codec, 0x01, 0,
3148 AC_VERB_SET_GPIO_DATA, 0x06);
3149 break;
3150 case QUIRK_R3DI:
3151 snd_hda_codec_write(codec, 0x01, 0,
3152 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3153 snd_hda_codec_write(codec, 0x01, 0,
3154 AC_VERB_SET_GPIO_MASK, 0x1F);
3155 snd_hda_codec_write(codec, 0x01, 0,
3156 AC_VERB_SET_GPIO_DATA, 0x0C);
3157 break;
3158 }
3159}
3160
3161/*
Connor McAdams7e6ed622018-05-08 13:20:08 -04003162 * GPIO control functions for the Recon3D integrated.
3163 */
3164
3165enum r3di_gpio_bit {
3166 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3167 R3DI_MIC_SELECT_BIT = 1,
3168 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3169 R3DI_OUT_SELECT_BIT = 2,
3170 /*
3171 * I dunno what this actually does, but it stays on until the dsp
3172 * is downloaded.
3173 */
3174 R3DI_GPIO_DSP_DOWNLOADING = 3,
3175 /*
3176 * Same as above, no clue what it does, but it comes on after the dsp
3177 * is downloaded.
3178 */
3179 R3DI_GPIO_DSP_DOWNLOADED = 4
3180};
3181
3182enum r3di_mic_select {
3183 /* Set GPIO bit 1 to 0 for rear mic */
3184 R3DI_REAR_MIC = 0,
3185 /* Set GPIO bit 1 to 1 for front microphone*/
3186 R3DI_FRONT_MIC = 1
3187};
3188
3189enum r3di_out_select {
3190 /* Set GPIO bit 2 to 0 for headphone */
3191 R3DI_HEADPHONE_OUT = 0,
3192 /* Set GPIO bit 2 to 1 for speaker */
3193 R3DI_LINE_OUT = 1
3194};
3195enum r3di_dsp_status {
3196 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3197 R3DI_DSP_DOWNLOADING = 0,
3198 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3199 R3DI_DSP_DOWNLOADED = 1
3200};
3201
Connor McAdams7cb9d942018-05-08 13:20:10 -04003202
3203static void r3di_gpio_mic_set(struct hda_codec *codec,
3204 enum r3di_mic_select cur_mic)
3205{
3206 unsigned int cur_gpio;
3207
3208 /* Get the current GPIO Data setup */
3209 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3210
3211 switch (cur_mic) {
3212 case R3DI_REAR_MIC:
3213 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3214 break;
3215 case R3DI_FRONT_MIC:
3216 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3217 break;
3218 }
3219 snd_hda_codec_write(codec, codec->core.afg, 0,
3220 AC_VERB_SET_GPIO_DATA, cur_gpio);
3221}
3222
3223static void r3di_gpio_out_set(struct hda_codec *codec,
3224 enum r3di_out_select cur_out)
3225{
3226 unsigned int cur_gpio;
3227
3228 /* Get the current GPIO Data setup */
3229 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3230
3231 switch (cur_out) {
3232 case R3DI_HEADPHONE_OUT:
3233 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3234 break;
3235 case R3DI_LINE_OUT:
3236 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3237 break;
3238 }
3239 snd_hda_codec_write(codec, codec->core.afg, 0,
3240 AC_VERB_SET_GPIO_DATA, cur_gpio);
3241}
3242
Connor McAdams7e6ed622018-05-08 13:20:08 -04003243static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3244 enum r3di_dsp_status dsp_status)
3245{
3246 unsigned int cur_gpio;
3247
3248 /* Get the current GPIO Data setup */
3249 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3250
3251 switch (dsp_status) {
3252 case R3DI_DSP_DOWNLOADING:
3253 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3254 snd_hda_codec_write(codec, codec->core.afg, 0,
3255 AC_VERB_SET_GPIO_DATA, cur_gpio);
3256 break;
3257 case R3DI_DSP_DOWNLOADED:
3258 /* Set DOWNLOADING bit to 0. */
3259 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3260
3261 snd_hda_codec_write(codec, codec->core.afg, 0,
3262 AC_VERB_SET_GPIO_DATA, cur_gpio);
3263
3264 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3265 break;
3266 }
3267
3268 snd_hda_codec_write(codec, codec->core.afg, 0,
3269 AC_VERB_SET_GPIO_DATA, cur_gpio);
3270}
3271
3272/*
Ian Minett825315b2012-12-20 18:53:36 -08003273 * PCM callbacks
3274 */
Ian Minett95c6e9c2011-06-15 15:35:17 -07003275static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3276 struct hda_codec *codec,
3277 unsigned int stream_tag,
3278 unsigned int format,
3279 struct snd_pcm_substream *substream)
3280{
3281 struct ca0132_spec *spec = codec->spec;
Ian Minett825315b2012-12-20 18:53:36 -08003282
Hsin-Yu Chao28fba952014-02-19 14:27:07 +08003283 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
Ian Minett825315b2012-12-20 18:53:36 -08003284
3285 return 0;
Ian Minett95c6e9c2011-06-15 15:35:17 -07003286}
3287
3288static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3289 struct hda_codec *codec,
3290 struct snd_pcm_substream *substream)
3291{
3292 struct ca0132_spec *spec = codec->spec;
Ian Minett825315b2012-12-20 18:53:36 -08003293
3294 if (spec->dsp_state == DSP_DOWNLOADING)
3295 return 0;
3296
3297 /*If Playback effects are on, allow stream some time to flush
3298 *effects tail*/
3299 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3300 msleep(50);
3301
Hsin-Yu Chao28fba952014-02-19 14:27:07 +08003302 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
Ian Minett825315b2012-12-20 18:53:36 -08003303
3304 return 0;
Ian Minett95c6e9c2011-06-15 15:35:17 -07003305}
3306
Dylan Reide8412ca2013-04-04 13:55:09 -07003307static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3308 struct hda_codec *codec,
3309 struct snd_pcm_substream *substream)
3310{
3311 struct ca0132_spec *spec = codec->spec;
3312 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3313 struct snd_pcm_runtime *runtime = substream->runtime;
3314
3315 if (spec->dsp_state != DSP_DOWNLOADED)
3316 return 0;
3317
3318 /* Add latency if playback enhancement and either effect is enabled. */
3319 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3320 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3321 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3322 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3323 }
3324
3325 /* Applying Speaker EQ adds latency as well. */
3326 if (spec->cur_out_type == SPEAKER_OUT)
3327 latency += DSP_SPEAKER_OUT_LATENCY;
3328
3329 return (latency * runtime->rate) / 1000;
3330}
3331
Ian Minett95c6e9c2011-06-15 15:35:17 -07003332/*
3333 * Digital out
3334 */
Takashi Iwai27ebeb02012-08-08 17:20:18 +02003335static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3336 struct hda_codec *codec,
3337 struct snd_pcm_substream *substream)
3338{
3339 struct ca0132_spec *spec = codec->spec;
3340 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3341}
3342
Ian Minett95c6e9c2011-06-15 15:35:17 -07003343static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3344 struct hda_codec *codec,
3345 unsigned int stream_tag,
3346 unsigned int format,
3347 struct snd_pcm_substream *substream)
3348{
3349 struct ca0132_spec *spec = codec->spec;
Takashi Iwai27ebeb02012-08-08 17:20:18 +02003350 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3351 stream_tag, format, substream);
Ian Minett95c6e9c2011-06-15 15:35:17 -07003352}
3353
3354static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3355 struct hda_codec *codec,
3356 struct snd_pcm_substream *substream)
3357{
3358 struct ca0132_spec *spec = codec->spec;
Takashi Iwai27ebeb02012-08-08 17:20:18 +02003359 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
Ian Minett95c6e9c2011-06-15 15:35:17 -07003360}
3361
Takashi Iwai27ebeb02012-08-08 17:20:18 +02003362static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3363 struct hda_codec *codec,
3364 struct snd_pcm_substream *substream)
Ian Minett95c6e9c2011-06-15 15:35:17 -07003365{
3366 struct ca0132_spec *spec = codec->spec;
Takashi Iwai27ebeb02012-08-08 17:20:18 +02003367 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
Ian Minett95c6e9c2011-06-15 15:35:17 -07003368}
3369
3370/*
Ian Minett825315b2012-12-20 18:53:36 -08003371 * Analog capture
3372 */
3373static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3374 struct hda_codec *codec,
3375 unsigned int stream_tag,
3376 unsigned int format,
3377 struct snd_pcm_substream *substream)
3378{
Hsin-Yu Chao13c12db2014-02-19 14:30:35 +08003379 snd_hda_codec_setup_stream(codec, hinfo->nid,
Hsin-Yu Chao28fba952014-02-19 14:27:07 +08003380 stream_tag, 0, format);
Ian Minett825315b2012-12-20 18:53:36 -08003381
3382 return 0;
3383}
3384
3385static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3386 struct hda_codec *codec,
3387 struct snd_pcm_substream *substream)
3388{
3389 struct ca0132_spec *spec = codec->spec;
3390
3391 if (spec->dsp_state == DSP_DOWNLOADING)
3392 return 0;
3393
Hsin-Yu Chao28fba952014-02-19 14:27:07 +08003394 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
Ian Minett825315b2012-12-20 18:53:36 -08003395 return 0;
3396}
3397
Dylan Reide8412ca2013-04-04 13:55:09 -07003398static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3399 struct hda_codec *codec,
3400 struct snd_pcm_substream *substream)
3401{
3402 struct ca0132_spec *spec = codec->spec;
3403 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3404 struct snd_pcm_runtime *runtime = substream->runtime;
3405
3406 if (spec->dsp_state != DSP_DOWNLOADED)
3407 return 0;
3408
3409 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3410 latency += DSP_CRYSTAL_VOICE_LATENCY;
3411
3412 return (latency * runtime->rate) / 1000;
3413}
3414
Ian Minette90f29e2012-12-20 18:53:39 -08003415/*
3416 * Controls stuffs.
3417 */
3418
3419/*
3420 * Mixer controls helpers.
3421 */
3422#define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3423 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3424 .name = xname, \
3425 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3426 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3427 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3428 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3429 .info = ca0132_volume_info, \
3430 .get = ca0132_volume_get, \
3431 .put = ca0132_volume_put, \
3432 .tlv = { .c = ca0132_volume_tlv }, \
3433 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3434
Connor McAdams017310f2018-05-08 13:20:11 -04003435/*
3436 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3437 * volume put, which is used for setting the DSP volume. This was done because
3438 * the ca0132 functions were taking too much time and causing lag.
3439 */
3440#define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3441 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3442 .name = xname, \
3443 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3444 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3445 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3446 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3447 .info = snd_hda_mixer_amp_volume_info, \
3448 .get = snd_hda_mixer_amp_volume_get, \
3449 .put = ca0132_alt_volume_put, \
3450 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3451 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3452
Ian Minette90f29e2012-12-20 18:53:39 -08003453#define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3454 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3455 .name = xname, \
3456 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3457 .info = snd_hda_mixer_amp_switch_info, \
3458 .get = ca0132_switch_get, \
3459 .put = ca0132_switch_put, \
3460 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3461
3462/* stereo */
3463#define CA0132_CODEC_VOL(xname, nid, dir) \
3464 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
Connor McAdams017310f2018-05-08 13:20:11 -04003465#define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3466 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
Ian Minette90f29e2012-12-20 18:53:39 -08003467#define CA0132_CODEC_MUTE(xname, nid, dir) \
3468 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3469
Connor McAdams017310f2018-05-08 13:20:11 -04003470/* lookup tables */
3471/*
3472 * Lookup table with decibel values for the DSP. When volume is changed in
3473 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3474 * these values have decimal points, probably because the Windows driver
3475 * actually uses floating point. We can't here, so I made a lookup table of
3476 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3477 * DAC's, and 9 is the maximum.
3478 */
3479static const unsigned int float_vol_db_lookup[] = {
34800xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
34810xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
34820xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
34830xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
34840xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
34850xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
34860xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
34870xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
34880xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
34890xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
34900xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
34910xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
34920xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
34930xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
34940xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
34950x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
34960x40C00000, 0x40E00000, 0x41000000, 0x41100000
3497};
3498
Connor McAdams47cdf762018-05-08 13:20:13 -04003499/*
3500 * This table counts from float 0 to 1 in increments of .01, which is
3501 * useful for a few different sliders.
3502 */
3503static const unsigned int float_zero_to_one_lookup[] = {
35040x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
35050x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
35060x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
35070x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
35080x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
35090x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
35100x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
35110x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
35120x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
35130x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
35140x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
35150x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
35160x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
35170x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
35180x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
35190x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
35200x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3521};
3522
3523/*
3524 * This table counts from float 10 to 1000, which is the range of the x-bass
3525 * crossover slider in Windows.
3526 */
3527static const unsigned int float_xbass_xover_lookup[] = {
35280x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
35290x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
35300x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
35310x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
35320x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
35330x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
35340x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
35350x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
35360x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
35370x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
35380x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
35390x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
35400x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
35410x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
35420x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
35430x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
35440x44728000, 0x44750000, 0x44778000, 0x447A0000
3545};
3546
Masahiro Yamada4091fb92017-02-27 14:29:56 -08003547/* The following are for tuning of products */
Ian Minett44f0c972012-12-20 18:53:38 -08003548#ifdef ENABLE_TUNING_CONTROLS
3549
3550static unsigned int voice_focus_vals_lookup[] = {
35510x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
35520x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
35530x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
35540x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
35550x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
35560x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
35570x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
35580x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
35590x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
35600x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
35610x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
35620x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
35630x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
35640x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
35650x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
35660x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
35670x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
35680x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
35690x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
35700x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
35710x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
35720x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
35730x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
35740x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
35750x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
35760x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
35770x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3578};
3579
3580static unsigned int mic_svm_vals_lookup[] = {
35810x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
35820x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
35830x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
35840x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
35850x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
35860x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
35870x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
35880x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
35890x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
35900x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
35910x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
35920x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
35930x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
35940x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
35950x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
35960x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
35970x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3598};
3599
3600static unsigned int equalizer_vals_lookup[] = {
36010xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
36020xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
36030xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
36040xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
36050x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
36060x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
36070x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
36080x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
36090x41C00000
3610};
3611
3612static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3613 unsigned int *lookup, int idx)
3614{
3615 int i = 0;
3616
3617 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3618 if (nid == ca0132_tuning_ctls[i].nid)
3619 break;
3620
3621 snd_hda_power_up(codec);
Connor McAdams447fd8e2018-05-08 13:20:09 -04003622 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
Ian Minett44f0c972012-12-20 18:53:38 -08003623 ca0132_tuning_ctls[i].req,
3624 &(lookup[idx]), sizeof(unsigned int));
3625 snd_hda_power_down(codec);
3626
3627 return 1;
3628}
3629
3630static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3631 struct snd_ctl_elem_value *ucontrol)
3632{
3633 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3634 struct ca0132_spec *spec = codec->spec;
3635 hda_nid_t nid = get_amp_nid(kcontrol);
3636 long *valp = ucontrol->value.integer.value;
3637 int idx = nid - TUNING_CTL_START_NID;
3638
3639 *valp = spec->cur_ctl_vals[idx];
3640 return 0;
3641}
3642
3643static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3644 struct snd_ctl_elem_info *uinfo)
3645{
3646 int chs = get_amp_channels(kcontrol);
3647 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3648 uinfo->count = chs == 3 ? 2 : 1;
3649 uinfo->value.integer.min = 20;
3650 uinfo->value.integer.max = 180;
3651 uinfo->value.integer.step = 1;
3652
3653 return 0;
3654}
3655
3656static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3657 struct snd_ctl_elem_value *ucontrol)
3658{
3659 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3660 struct ca0132_spec *spec = codec->spec;
3661 hda_nid_t nid = get_amp_nid(kcontrol);
3662 long *valp = ucontrol->value.integer.value;
3663 int idx;
3664
3665 idx = nid - TUNING_CTL_START_NID;
3666 /* any change? */
3667 if (spec->cur_ctl_vals[idx] == *valp)
3668 return 0;
3669
3670 spec->cur_ctl_vals[idx] = *valp;
3671
3672 idx = *valp - 20;
3673 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3674
3675 return 1;
3676}
3677
3678static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3679 struct snd_ctl_elem_info *uinfo)
3680{
3681 int chs = get_amp_channels(kcontrol);
3682 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3683 uinfo->count = chs == 3 ? 2 : 1;
3684 uinfo->value.integer.min = 0;
3685 uinfo->value.integer.max = 100;
3686 uinfo->value.integer.step = 1;
3687
3688 return 0;
3689}
3690
3691static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3692 struct snd_ctl_elem_value *ucontrol)
3693{
3694 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3695 struct ca0132_spec *spec = codec->spec;
3696 hda_nid_t nid = get_amp_nid(kcontrol);
3697 long *valp = ucontrol->value.integer.value;
3698 int idx;
3699
3700 idx = nid - TUNING_CTL_START_NID;
3701 /* any change? */
3702 if (spec->cur_ctl_vals[idx] == *valp)
3703 return 0;
3704
3705 spec->cur_ctl_vals[idx] = *valp;
3706
3707 idx = *valp;
3708 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3709
3710 return 0;
3711}
3712
3713static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3714 struct snd_ctl_elem_info *uinfo)
3715{
3716 int chs = get_amp_channels(kcontrol);
3717 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3718 uinfo->count = chs == 3 ? 2 : 1;
3719 uinfo->value.integer.min = 0;
3720 uinfo->value.integer.max = 48;
3721 uinfo->value.integer.step = 1;
3722
3723 return 0;
3724}
3725
3726static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3727 struct snd_ctl_elem_value *ucontrol)
3728{
3729 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3730 struct ca0132_spec *spec = codec->spec;
3731 hda_nid_t nid = get_amp_nid(kcontrol);
3732 long *valp = ucontrol->value.integer.value;
3733 int idx;
3734
3735 idx = nid - TUNING_CTL_START_NID;
3736 /* any change? */
3737 if (spec->cur_ctl_vals[idx] == *valp)
3738 return 0;
3739
3740 spec->cur_ctl_vals[idx] = *valp;
3741
3742 idx = *valp;
3743 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3744
3745 return 1;
3746}
3747
Takashi Sakamoto8e142e92018-05-02 22:48:16 +09003748static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3749static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
Ian Minett44f0c972012-12-20 18:53:38 -08003750
3751static int add_tuning_control(struct hda_codec *codec,
3752 hda_nid_t pnid, hda_nid_t nid,
3753 const char *name, int dir)
3754{
Takashi Iwai975cc022013-06-28 11:56:49 +02003755 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
Ian Minett44f0c972012-12-20 18:53:38 -08003756 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3757 struct snd_kcontrol_new knew =
3758 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3759
3760 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3761 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3762 knew.tlv.c = 0;
3763 knew.tlv.p = 0;
3764 switch (pnid) {
3765 case VOICE_FOCUS:
3766 knew.info = voice_focus_ctl_info;
3767 knew.get = tuning_ctl_get;
3768 knew.put = voice_focus_ctl_put;
3769 knew.tlv.p = voice_focus_db_scale;
3770 break;
3771 case MIC_SVM:
3772 knew.info = mic_svm_ctl_info;
3773 knew.get = tuning_ctl_get;
3774 knew.put = mic_svm_ctl_put;
3775 break;
3776 case EQUALIZER:
3777 knew.info = equalizer_ctl_info;
3778 knew.get = tuning_ctl_get;
3779 knew.put = equalizer_ctl_put;
3780 knew.tlv.p = eq_db_scale;
3781 break;
3782 default:
3783 return 0;
3784 }
3785 knew.private_value =
3786 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3787 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3788 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3789}
3790
3791static int add_tuning_ctls(struct hda_codec *codec)
3792{
3793 int i;
3794 int err;
3795
3796 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3797 err = add_tuning_control(codec,
3798 ca0132_tuning_ctls[i].parent_nid,
3799 ca0132_tuning_ctls[i].nid,
3800 ca0132_tuning_ctls[i].name,
3801 ca0132_tuning_ctls[i].direct);
3802 if (err < 0)
3803 return err;
3804 }
3805
3806 return 0;
3807}
3808
3809static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3810{
3811 struct ca0132_spec *spec = codec->spec;
3812 int i;
3813
3814 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3815 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3816 /* SVM level defaults to 0.74. */
3817 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3818
3819 /* EQ defaults to 0dB. */
3820 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3821 spec->cur_ctl_vals[i] = 24;
3822}
3823#endif /*ENABLE_TUNING_CONTROLS*/
3824
Ian Minett825315b2012-12-20 18:53:36 -08003825/*
Ian Minett5aaca442012-12-20 18:53:34 -08003826 * Select the active output.
3827 * If autodetect is enabled, output will be selected based on jack detection.
3828 * If jack inserted, headphone will be selected, else built-in speakers
3829 * If autodetect is disabled, output will be selected based on selection.
3830 */
3831static int ca0132_select_out(struct hda_codec *codec)
3832{
3833 struct ca0132_spec *spec = codec->spec;
3834 unsigned int pin_ctl;
3835 int jack_present;
3836 int auto_jack;
3837 unsigned int tmp;
3838 int err;
3839
Takashi Iwai4e76a882014-02-25 12:21:03 +01003840 codec_dbg(codec, "ca0132_select_out\n");
Ian Minett5aaca442012-12-20 18:53:34 -08003841
Takashi Iwai664c7152015-04-08 11:43:14 +02003842 snd_hda_power_up_pm(codec);
Ian Minett5aaca442012-12-20 18:53:34 -08003843
3844 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3845
3846 if (auto_jack)
Takashi Iwaife14f392015-08-10 16:53:32 +02003847 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
Ian Minett5aaca442012-12-20 18:53:34 -08003848 else
3849 jack_present =
3850 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3851
3852 if (jack_present)
3853 spec->cur_out_type = HEADPHONE_OUT;
3854 else
3855 spec->cur_out_type = SPEAKER_OUT;
3856
3857 if (spec->cur_out_type == SPEAKER_OUT) {
Takashi Iwai4e76a882014-02-25 12:21:03 +01003858 codec_dbg(codec, "ca0132_select_out speaker\n");
Ian Minett5aaca442012-12-20 18:53:34 -08003859 /*speaker out config*/
3860 tmp = FLOAT_ONE;
3861 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3862 if (err < 0)
3863 goto exit;
3864 /*enable speaker EQ*/
3865 tmp = FLOAT_ONE;
3866 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3867 if (err < 0)
3868 goto exit;
3869
3870 /* Setup EAPD */
3871 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3872 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3873 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3874 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3875 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3876 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3877 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3878 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3879
3880 /* disable headphone node */
3881 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3882 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
Takashi Iwaia0c041c2013-01-15 17:13:31 +01003883 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3884 pin_ctl & ~PIN_HP);
Ian Minett5aaca442012-12-20 18:53:34 -08003885 /* enable speaker node */
3886 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
Connor McAdams8a19bce2018-05-08 13:20:01 -04003887 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
Takashi Iwaia0c041c2013-01-15 17:13:31 +01003888 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3889 pin_ctl | PIN_OUT);
Ian Minett5aaca442012-12-20 18:53:34 -08003890 } else {
Takashi Iwai4e76a882014-02-25 12:21:03 +01003891 codec_dbg(codec, "ca0132_select_out hp\n");
Ian Minett5aaca442012-12-20 18:53:34 -08003892 /*headphone out config*/
3893 tmp = FLOAT_ZERO;
3894 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3895 if (err < 0)
3896 goto exit;
3897 /*disable speaker EQ*/
3898 tmp = FLOAT_ZERO;
3899 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3900 if (err < 0)
3901 goto exit;
3902
3903 /* Setup EAPD */
3904 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3905 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3906 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3907 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3908 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3909 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3910 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3911 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3912
3913 /* disable speaker*/
3914 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3915 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
Takashi Iwaia0c041c2013-01-15 17:13:31 +01003916 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3917 pin_ctl & ~PIN_HP);
Ian Minett5aaca442012-12-20 18:53:34 -08003918 /* enable headphone*/
3919 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3920 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
Takashi Iwaia0c041c2013-01-15 17:13:31 +01003921 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3922 pin_ctl | PIN_HP);
Ian Minett5aaca442012-12-20 18:53:34 -08003923 }
3924
3925exit:
Takashi Iwai664c7152015-04-08 11:43:14 +02003926 snd_hda_power_down_pm(codec);
Ian Minett5aaca442012-12-20 18:53:34 -08003927
3928 return err < 0 ? err : 0;
3929}
3930
Connor McAdams7cb9d942018-05-08 13:20:10 -04003931/*
3932 * This function behaves similarly to the ca0132_select_out funciton above,
3933 * except with a few differences. It adds the ability to select the current
3934 * output with an enumerated control "output source" if the auto detect
3935 * mute switch is set to off. If the auto detect mute switch is enabled, it
3936 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3937 * It also adds the ability to auto-detect the front headphone port. The only
3938 * way to select surround is to disable auto detect, and set Surround with the
3939 * enumerated control.
3940 */
3941static int ca0132_alt_select_out(struct hda_codec *codec)
3942{
3943 struct ca0132_spec *spec = codec->spec;
3944 unsigned int pin_ctl;
3945 int jack_present;
3946 int auto_jack;
3947 unsigned int i;
3948 unsigned int tmp;
3949 int err;
3950 /* Default Headphone is rear headphone */
3951 hda_nid_t headphone_nid = spec->out_pins[1];
3952
3953 codec_dbg(codec, "%s\n", __func__);
3954
3955 snd_hda_power_up_pm(codec);
3956
3957 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3958
3959 /*
3960 * If headphone rear or front is plugged in, set to headphone.
3961 * If neither is plugged in, set to rear line out. Only if
3962 * hp/speaker auto detect is enabled.
3963 */
3964 if (auto_jack) {
3965 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3966 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3967
3968 if (jack_present)
3969 spec->cur_out_type = HEADPHONE_OUT;
3970 else
3971 spec->cur_out_type = SPEAKER_OUT;
3972 } else
3973 spec->cur_out_type = spec->out_enum_val;
3974
3975 /* Begin DSP output switch */
3976 tmp = FLOAT_ONE;
3977 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3978 if (err < 0)
3979 goto exit;
3980
3981 switch (spec->cur_out_type) {
3982 case SPEAKER_OUT:
3983 codec_dbg(codec, "%s speaker\n", __func__);
3984 /*speaker out config*/
3985 switch (spec->quirk) {
3986 case QUIRK_SBZ:
Connor McAdamsa62e4732018-08-08 13:34:12 -04003987 ca0132_mmio_gpio_set(codec, 7, false);
3988 ca0132_mmio_gpio_set(codec, 4, true);
3989 ca0132_mmio_gpio_set(codec, 1, true);
Connor McAdams7cb9d942018-05-08 13:20:10 -04003990 chipio_set_control_param(codec, 0x0D, 0x18);
3991 break;
3992 case QUIRK_R3DI:
3993 chipio_set_control_param(codec, 0x0D, 0x24);
3994 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3995 break;
3996 }
3997
3998 /* disable headphone node */
3999 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4000 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4001 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4002 pin_ctl & ~PIN_HP);
4003 /* enable line-out node */
4004 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4005 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4006 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4007 pin_ctl | PIN_OUT);
4008 /* Enable EAPD */
4009 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4010 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4011
4012 /* If PlayEnhancement is enabled, set different source */
4013 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4014 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4015 else
4016 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4017 break;
4018 case HEADPHONE_OUT:
4019 codec_dbg(codec, "%s hp\n", __func__);
4020 /* Headphone out config*/
4021 switch (spec->quirk) {
4022 case QUIRK_SBZ:
Connor McAdamsa62e4732018-08-08 13:34:12 -04004023 ca0132_mmio_gpio_set(codec, 7, true);
4024 ca0132_mmio_gpio_set(codec, 4, true);
4025 ca0132_mmio_gpio_set(codec, 1, false);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004026 chipio_set_control_param(codec, 0x0D, 0x12);
4027 break;
4028 case QUIRK_R3DI:
4029 chipio_set_control_param(codec, 0x0D, 0x21);
4030 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4031 break;
4032 }
4033
4034 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4035 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4036
4037 /* disable speaker*/
4038 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4039 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4040 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4041 pin_ctl & ~PIN_HP);
4042
4043 /* enable headphone, either front or rear */
4044
4045 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4046 headphone_nid = spec->out_pins[2];
4047 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4048 headphone_nid = spec->out_pins[1];
4049
4050 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4051 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4052 snd_hda_set_pin_ctl(codec, headphone_nid,
4053 pin_ctl | PIN_HP);
4054
4055 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4056 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4057 else
4058 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4059 break;
4060 case SURROUND_OUT:
4061 codec_dbg(codec, "%s surround\n", __func__);
4062 /* Surround out config*/
4063 switch (spec->quirk) {
4064 case QUIRK_SBZ:
Connor McAdamsa62e4732018-08-08 13:34:12 -04004065 ca0132_mmio_gpio_set(codec, 7, false);
4066 ca0132_mmio_gpio_set(codec, 4, true);
4067 ca0132_mmio_gpio_set(codec, 1, true);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004068 chipio_set_control_param(codec, 0x0D, 0x18);
4069 break;
4070 case QUIRK_R3DI:
4071 chipio_set_control_param(codec, 0x0D, 0x24);
4072 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4073 break;
4074 }
4075 /* enable line out node */
4076 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4077 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4078 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4079 pin_ctl | PIN_OUT);
4080 /* Disable headphone out */
4081 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4082 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4083 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4084 pin_ctl & ~PIN_HP);
4085 /* Enable EAPD on line out */
4086 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4087 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4088 /* enable center/lfe out node */
4089 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4090 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4091 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4092 pin_ctl | PIN_OUT);
4093 /* Now set rear surround node as out. */
4094 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4095 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4096 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4097 pin_ctl | PIN_OUT);
4098
4099 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4100 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4101 else
4102 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4103 break;
4104 }
4105
4106 /* run through the output dsp commands for line-out */
4107 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4108 err = dspio_set_uint_param(codec,
4109 alt_out_presets[spec->cur_out_type].mids[i],
4110 alt_out_presets[spec->cur_out_type].reqs[i],
4111 alt_out_presets[spec->cur_out_type].vals[i]);
4112
4113 if (err < 0)
4114 goto exit;
4115 }
4116
4117exit:
4118 snd_hda_power_down_pm(codec);
4119
4120 return err < 0 ? err : 0;
4121}
4122
Chih-Chung Chang993884f2013-03-25 10:39:23 -07004123static void ca0132_unsol_hp_delayed(struct work_struct *work)
4124{
4125 struct ca0132_spec *spec = container_of(
4126 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
Takashi Iwaif8fb1172014-09-11 15:53:26 +02004127 struct hda_jack_tbl *jack;
4128
Connor McAdams7cb9d942018-05-08 13:20:10 -04004129 if (spec->use_alt_functions)
4130 ca0132_alt_select_out(spec->codec);
4131 else
4132 ca0132_select_out(spec->codec);
4133
Gabriele Martinod5c016b2015-05-18 21:15:13 +02004134 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
Takashi Iwaif8fb1172014-09-11 15:53:26 +02004135 if (jack) {
4136 jack->block_report = 0;
4137 snd_hda_jack_report_sync(spec->codec);
4138 }
Chih-Chung Chang993884f2013-03-25 10:39:23 -07004139}
4140
Ian Minett5aaca442012-12-20 18:53:34 -08004141static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4142static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4143static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
Connor McAdamse0026d02018-05-08 13:20:12 -04004144static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4145static int stop_mic1(struct hda_codec *codec);
4146static int ca0132_cvoice_switch_set(struct hda_codec *codec);
Connor McAdams47cdf762018-05-08 13:20:13 -04004147static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
Ian Minett5aaca442012-12-20 18:53:34 -08004148
4149/*
4150 * Select the active VIP source
4151 */
4152static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4153{
4154 struct ca0132_spec *spec = codec->spec;
4155 unsigned int tmp;
4156
Dylan Reide8f1bd52013-03-14 17:27:45 -07004157 if (spec->dsp_state != DSP_DOWNLOADED)
Ian Minett5aaca442012-12-20 18:53:34 -08004158 return 0;
4159
4160 /* if CrystalVoice if off, vipsource should be 0 */
4161 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4162 (val == 0)) {
4163 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4164 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4165 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4166 if (spec->cur_mic_type == DIGITAL_MIC)
4167 tmp = FLOAT_TWO;
4168 else
4169 tmp = FLOAT_ONE;
4170 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4171 tmp = FLOAT_ZERO;
4172 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4173 } else {
4174 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4175 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4176 if (spec->cur_mic_type == DIGITAL_MIC)
4177 tmp = FLOAT_TWO;
4178 else
4179 tmp = FLOAT_ONE;
4180 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4181 tmp = FLOAT_ONE;
4182 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4183 msleep(20);
4184 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4185 }
4186
4187 return 1;
4188}
4189
Connor McAdamse0026d02018-05-08 13:20:12 -04004190static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4191{
4192 struct ca0132_spec *spec = codec->spec;
4193 unsigned int tmp;
4194
4195 if (spec->dsp_state != DSP_DOWNLOADED)
4196 return 0;
4197
4198 codec_dbg(codec, "%s\n", __func__);
4199
4200 chipio_set_stream_control(codec, 0x03, 0);
4201 chipio_set_stream_control(codec, 0x04, 0);
4202
4203 /* if CrystalVoice is off, vipsource should be 0 */
4204 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4205 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4206 codec_dbg(codec, "%s: off.", __func__);
4207 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4208
4209 tmp = FLOAT_ZERO;
4210 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4211
4212 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4213 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4214 if (spec->quirk == QUIRK_R3DI)
4215 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4216
4217
4218 if (spec->in_enum_val == REAR_LINE_IN)
4219 tmp = FLOAT_ZERO;
4220 else {
4221 if (spec->quirk == QUIRK_SBZ)
4222 tmp = FLOAT_THREE;
4223 else
4224 tmp = FLOAT_ONE;
4225 }
4226
4227 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4228
4229 } else {
4230 codec_dbg(codec, "%s: on.", __func__);
4231 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4232 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4233 if (spec->quirk == QUIRK_R3DI)
4234 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4235
4236 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4237 tmp = FLOAT_TWO;
4238 else
4239 tmp = FLOAT_ONE;
4240 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4241
4242 tmp = FLOAT_ONE;
4243 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4244
4245 msleep(20);
4246 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4247 }
4248
4249 chipio_set_stream_control(codec, 0x03, 1);
4250 chipio_set_stream_control(codec, 0x04, 1);
4251
4252 return 1;
4253}
4254
Ian Minett5aaca442012-12-20 18:53:34 -08004255/*
4256 * Select the active microphone.
4257 * If autodetect is enabled, mic will be selected based on jack detection.
4258 * If jack inserted, ext.mic will be selected, else built-in mic
4259 * If autodetect is disabled, mic will be selected based on selection.
4260 */
4261static int ca0132_select_mic(struct hda_codec *codec)
4262{
4263 struct ca0132_spec *spec = codec->spec;
4264 int jack_present;
4265 int auto_jack;
4266
Takashi Iwai4e76a882014-02-25 12:21:03 +01004267 codec_dbg(codec, "ca0132_select_mic\n");
Ian Minett5aaca442012-12-20 18:53:34 -08004268
Takashi Iwai664c7152015-04-08 11:43:14 +02004269 snd_hda_power_up_pm(codec);
Ian Minett5aaca442012-12-20 18:53:34 -08004270
4271 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4272
4273 if (auto_jack)
Takashi Iwaife14f392015-08-10 16:53:32 +02004274 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
Ian Minett5aaca442012-12-20 18:53:34 -08004275 else
4276 jack_present =
4277 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4278
4279 if (jack_present)
4280 spec->cur_mic_type = LINE_MIC_IN;
4281 else
4282 spec->cur_mic_type = DIGITAL_MIC;
4283
4284 if (spec->cur_mic_type == DIGITAL_MIC) {
4285 /* enable digital Mic */
4286 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4287 ca0132_set_dmic(codec, 1);
4288 ca0132_mic_boost_set(codec, 0);
4289 /* set voice focus */
4290 ca0132_effects_set(codec, VOICE_FOCUS,
4291 spec->effects_switch
4292 [VOICE_FOCUS - EFFECT_START_NID]);
4293 } else {
4294 /* disable digital Mic */
4295 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4296 ca0132_set_dmic(codec, 0);
4297 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4298 /* disable voice focus */
4299 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4300 }
4301
Takashi Iwai664c7152015-04-08 11:43:14 +02004302 snd_hda_power_down_pm(codec);
Ian Minett5aaca442012-12-20 18:53:34 -08004303
4304 return 0;
4305}
4306
4307/*
Connor McAdams7cb9d942018-05-08 13:20:10 -04004308 * Select the active input.
4309 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4310 * The front mic has no jack-detection, so the only way to switch to it
4311 * is to do it manually in alsamixer.
4312 */
4313static int ca0132_alt_select_in(struct hda_codec *codec)
4314{
4315 struct ca0132_spec *spec = codec->spec;
4316 unsigned int tmp;
4317
4318 codec_dbg(codec, "%s\n", __func__);
4319
4320 snd_hda_power_up_pm(codec);
4321
4322 chipio_set_stream_control(codec, 0x03, 0);
4323 chipio_set_stream_control(codec, 0x04, 0);
4324
4325 spec->cur_mic_type = spec->in_enum_val;
4326
4327 switch (spec->cur_mic_type) {
4328 case REAR_MIC:
4329 switch (spec->quirk) {
4330 case QUIRK_SBZ:
Connor McAdamsa62e4732018-08-08 13:34:12 -04004331 ca0132_mmio_gpio_set(codec, 0, false);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004332 tmp = FLOAT_THREE;
4333 break;
4334 case QUIRK_R3DI:
4335 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4336 tmp = FLOAT_ONE;
4337 break;
4338 default:
4339 tmp = FLOAT_ONE;
4340 break;
4341 }
4342
4343 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4344 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4345 if (spec->quirk == QUIRK_R3DI)
4346 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4347
4348 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4349
4350 chipio_set_stream_control(codec, 0x03, 1);
4351 chipio_set_stream_control(codec, 0x04, 1);
4352
4353 if (spec->quirk == QUIRK_SBZ) {
4354 chipio_write(codec, 0x18B098, 0x0000000C);
4355 chipio_write(codec, 0x18B09C, 0x0000000C);
4356 }
Connor McAdams47cdf762018-05-08 13:20:13 -04004357 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004358 break;
4359 case REAR_LINE_IN:
4360 ca0132_mic_boost_set(codec, 0);
4361 switch (spec->quirk) {
4362 case QUIRK_SBZ:
Connor McAdamsa62e4732018-08-08 13:34:12 -04004363 ca0132_mmio_gpio_set(codec, 0, false);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004364 break;
4365 case QUIRK_R3DI:
4366 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4367 break;
4368 }
4369
4370 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4371 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4372 if (spec->quirk == QUIRK_R3DI)
4373 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4374
4375 tmp = FLOAT_ZERO;
4376 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4377
4378 if (spec->quirk == QUIRK_SBZ) {
4379 chipio_write(codec, 0x18B098, 0x00000000);
4380 chipio_write(codec, 0x18B09C, 0x00000000);
4381 }
4382
4383 chipio_set_stream_control(codec, 0x03, 1);
4384 chipio_set_stream_control(codec, 0x04, 1);
4385 break;
4386 case FRONT_MIC:
4387 switch (spec->quirk) {
4388 case QUIRK_SBZ:
Connor McAdamsa62e4732018-08-08 13:34:12 -04004389 ca0132_mmio_gpio_set(codec, 0, true);
4390 ca0132_mmio_gpio_set(codec, 5, false);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004391 tmp = FLOAT_THREE;
4392 break;
4393 case QUIRK_R3DI:
4394 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4395 tmp = FLOAT_ONE;
4396 break;
4397 default:
4398 tmp = FLOAT_ONE;
4399 break;
4400 }
4401
4402 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4403 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4404 if (spec->quirk == QUIRK_R3DI)
4405 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4406
4407 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4408
4409 chipio_set_stream_control(codec, 0x03, 1);
4410 chipio_set_stream_control(codec, 0x04, 1);
4411
4412 if (spec->quirk == QUIRK_SBZ) {
4413 chipio_write(codec, 0x18B098, 0x0000000C);
4414 chipio_write(codec, 0x18B09C, 0x000000CC);
4415 }
Connor McAdams47cdf762018-05-08 13:20:13 -04004416 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004417 break;
4418 }
Connor McAdamse0026d02018-05-08 13:20:12 -04004419 ca0132_cvoice_switch_set(codec);
Connor McAdams7cb9d942018-05-08 13:20:10 -04004420
4421 snd_hda_power_down_pm(codec);
4422 return 0;
4423
4424}
4425
4426/*
Ian Minetta7e76272012-12-20 18:53:35 -08004427 * Check if VNODE settings take effect immediately.
4428 */
4429static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4430 hda_nid_t vnid,
4431 hda_nid_t *shared_nid)
4432{
4433 struct ca0132_spec *spec = codec->spec;
4434 hda_nid_t nid;
Ian Minetta7e76272012-12-20 18:53:35 -08004435
4436 switch (vnid) {
4437 case VNID_SPK:
4438 nid = spec->shared_out_nid;
Ian Minetta7e76272012-12-20 18:53:35 -08004439 break;
4440 case VNID_MIC:
4441 nid = spec->shared_mic_nid;
Ian Minetta7e76272012-12-20 18:53:35 -08004442 break;
4443 default:
Takashi Iwai9a0869f2013-02-07 12:41:40 +01004444 return false;
Ian Minetta7e76272012-12-20 18:53:35 -08004445 }
4446
Takashi Iwai9a0869f2013-02-07 12:41:40 +01004447 if (shared_nid)
Ian Minetta7e76272012-12-20 18:53:35 -08004448 *shared_nid = nid;
4449
Takashi Iwai9a0869f2013-02-07 12:41:40 +01004450 return true;
Ian Minetta7e76272012-12-20 18:53:35 -08004451}
4452
4453/*
4454* The following functions are control change helpers.
4455* They return 0 if no changed. Return 1 if changed.
4456*/
4457static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4458{
4459 struct ca0132_spec *spec = codec->spec;
4460 unsigned int tmp;
4461
4462 /* based on CrystalVoice state to enable VoiceFX. */
4463 if (enable) {
4464 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4465 FLOAT_ONE : FLOAT_ZERO;
4466 } else {
4467 tmp = FLOAT_ZERO;
4468 }
4469
4470 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4471 ca0132_voicefx.reqs[0], tmp);
4472
4473 return 1;
4474}
4475
4476/*
Ian Minett5aaca442012-12-20 18:53:34 -08004477 * Set the effects parameters
4478 */
4479static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4480{
4481 struct ca0132_spec *spec = codec->spec;
Connor McAdams009b8f92018-05-08 13:20:06 -04004482 unsigned int on, tmp;
Ian Minett5aaca442012-12-20 18:53:34 -08004483 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4484 int err = 0;
4485 int idx = nid - EFFECT_START_NID;
4486
4487 if ((idx < 0) || (idx >= num_fx))
4488 return 0; /* no changed */
4489
4490 /* for out effect, qualify with PE */
4491 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4492 /* if PE if off, turn off out effects. */
4493 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4494 val = 0;
4495 }
4496
4497 /* for in effect, qualify with CrystalVoice */
4498 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4499 /* if CrystalVoice if off, turn off in effects. */
4500 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4501 val = 0;
4502
4503 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4504 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4505 val = 0;
Connor McAdams009b8f92018-05-08 13:20:06 -04004506
4507 /* If Voice Focus on SBZ, set to two channel. */
Connor McAdams7cb9d942018-05-08 13:20:10 -04004508 if ((nid == VOICE_FOCUS) && (spec->quirk == QUIRK_SBZ)
4509 && (spec->cur_mic_type != REAR_LINE_IN)) {
Connor McAdams009b8f92018-05-08 13:20:06 -04004510 if (spec->effects_switch[CRYSTAL_VOICE -
4511 EFFECT_START_NID]) {
4512
4513 if (spec->effects_switch[VOICE_FOCUS -
4514 EFFECT_START_NID]) {
4515 tmp = FLOAT_TWO;
4516 val = 1;
4517 } else
4518 tmp = FLOAT_ONE;
4519
4520 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4521 }
4522 }
4523 /*
4524 * For SBZ noise reduction, there's an extra command
4525 * to module ID 0x47. No clue why.
4526 */
Connor McAdams7cb9d942018-05-08 13:20:10 -04004527 if ((nid == NOISE_REDUCTION) && (spec->quirk == QUIRK_SBZ)
4528 && (spec->cur_mic_type != REAR_LINE_IN)) {
Connor McAdams009b8f92018-05-08 13:20:06 -04004529 if (spec->effects_switch[CRYSTAL_VOICE -
4530 EFFECT_START_NID]) {
4531 if (spec->effects_switch[NOISE_REDUCTION -
4532 EFFECT_START_NID])
4533 tmp = FLOAT_ONE;
4534 else
4535 tmp = FLOAT_ZERO;
4536 } else
4537 tmp = FLOAT_ZERO;
4538
4539 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4540 }
Connor McAdams7cb9d942018-05-08 13:20:10 -04004541
4542 /* If rear line in disable effects. */
4543 if (spec->use_alt_functions &&
4544 spec->in_enum_val == REAR_LINE_IN)
4545 val = 0;
Ian Minett5aaca442012-12-20 18:53:34 -08004546 }
4547
Takashi Iwai4e76a882014-02-25 12:21:03 +01004548 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
Ian Minett5aaca442012-12-20 18:53:34 -08004549 nid, val);
4550
4551 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4552 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4553 ca0132_effects[idx].reqs[0], on);
4554
4555 if (err < 0)
4556 return 0; /* no changed */
4557
4558 return 1;
4559}
4560
Ian Minetta7e76272012-12-20 18:53:35 -08004561/*
4562 * Turn on/off Playback Enhancements
4563 */
4564static int ca0132_pe_switch_set(struct hda_codec *codec)
4565{
4566 struct ca0132_spec *spec = codec->spec;
4567 hda_nid_t nid;
4568 int i, ret = 0;
4569
Takashi Iwai4e76a882014-02-25 12:21:03 +01004570 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
Ian Minetta7e76272012-12-20 18:53:35 -08004571 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4572
Connor McAdams7cb9d942018-05-08 13:20:10 -04004573 if (spec->use_alt_functions)
4574 ca0132_alt_select_out(codec);
4575
Ian Minetta7e76272012-12-20 18:53:35 -08004576 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4577 nid = OUT_EFFECT_START_NID;
4578 /* PE affects all out effects */
4579 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4580 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4581
4582 return ret;
4583}
4584
Ian Minett5aaca442012-12-20 18:53:34 -08004585/* Check if Mic1 is streaming, if so, stop streaming */
4586static int stop_mic1(struct hda_codec *codec)
4587{
4588 struct ca0132_spec *spec = codec->spec;
4589 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4590 AC_VERB_GET_CONV, 0);
4591 if (oldval != 0)
4592 snd_hda_codec_write(codec, spec->adcs[0], 0,
4593 AC_VERB_SET_CHANNEL_STREAMID,
4594 0);
4595 return oldval;
4596}
4597
4598/* Resume Mic1 streaming if it was stopped. */
4599static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4600{
4601 struct ca0132_spec *spec = codec->spec;
4602 /* Restore the previous stream and channel */
4603 if (oldval != 0)
4604 snd_hda_codec_write(codec, spec->adcs[0], 0,
4605 AC_VERB_SET_CHANNEL_STREAMID,
4606 oldval);
4607}
4608
4609/*
Ian Minetta7e76272012-12-20 18:53:35 -08004610 * Turn on/off CrystalVoice
Ian Minett5aaca442012-12-20 18:53:34 -08004611 */
Ian Minetta7e76272012-12-20 18:53:35 -08004612static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4613{
4614 struct ca0132_spec *spec = codec->spec;
4615 hda_nid_t nid;
4616 int i, ret = 0;
4617 unsigned int oldval;
4618
Takashi Iwai4e76a882014-02-25 12:21:03 +01004619 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
Ian Minetta7e76272012-12-20 18:53:35 -08004620 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4621
4622 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4623 nid = IN_EFFECT_START_NID;
4624 /* CrystalVoice affects all in effects */
4625 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4626 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4627
4628 /* including VoiceFX */
4629 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4630
4631 /* set correct vipsource */
4632 oldval = stop_mic1(codec);
Connor McAdamse0026d02018-05-08 13:20:12 -04004633 if (spec->use_alt_functions)
4634 ret |= ca0132_alt_set_vipsource(codec, 1);
4635 else
4636 ret |= ca0132_set_vipsource(codec, 1);
Ian Minetta7e76272012-12-20 18:53:35 -08004637 resume_mic1(codec, oldval);
4638 return ret;
4639}
4640
Ian Minett5aaca442012-12-20 18:53:34 -08004641static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4642{
4643 struct ca0132_spec *spec = codec->spec;
4644 int ret = 0;
4645
4646 if (val) /* on */
4647 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4648 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4649 else /* off */
4650 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4651 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4652
4653 return ret;
4654}
4655
Connor McAdams47cdf762018-05-08 13:20:13 -04004656static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4657{
4658 struct ca0132_spec *spec = codec->spec;
4659 int ret = 0;
4660
4661 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4662 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4663 return ret;
4664}
4665
Ian Minetta7e76272012-12-20 18:53:35 -08004666static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4667 struct snd_ctl_elem_value *ucontrol)
4668{
4669 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4670 hda_nid_t nid = get_amp_nid(kcontrol);
4671 hda_nid_t shared_nid = 0;
4672 bool effective;
4673 int ret = 0;
4674 struct ca0132_spec *spec = codec->spec;
4675 int auto_jack;
4676
4677 if (nid == VNID_HP_SEL) {
4678 auto_jack =
4679 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
Connor McAdams7cb9d942018-05-08 13:20:10 -04004680 if (!auto_jack) {
4681 if (spec->use_alt_functions)
4682 ca0132_alt_select_out(codec);
4683 else
4684 ca0132_select_out(codec);
4685 }
Ian Minetta7e76272012-12-20 18:53:35 -08004686 return 1;
4687 }
4688
4689 if (nid == VNID_AMIC1_SEL) {
4690 auto_jack =
4691 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4692 if (!auto_jack)
4693 ca0132_select_mic(codec);
4694 return 1;
4695 }
4696
4697 if (nid == VNID_HP_ASEL) {
Connor McAdams7cb9d942018-05-08 13:20:10 -04004698 if (spec->use_alt_functions)
4699 ca0132_alt_select_out(codec);
4700 else
4701 ca0132_select_out(codec);
Ian Minetta7e76272012-12-20 18:53:35 -08004702 return 1;
4703 }
4704
4705 if (nid == VNID_AMIC1_ASEL) {
4706 ca0132_select_mic(codec);
4707 return 1;
4708 }
4709
4710 /* if effective conditions, then update hw immediately. */
4711 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4712 if (effective) {
4713 int dir = get_amp_direction(kcontrol);
4714 int ch = get_amp_channels(kcontrol);
4715 unsigned long pval;
4716
4717 mutex_lock(&codec->control_mutex);
4718 pval = kcontrol->private_value;
4719 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4720 0, dir);
4721 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4722 kcontrol->private_value = pval;
4723 mutex_unlock(&codec->control_mutex);
4724 }
4725
4726 return ret;
4727}
4728/* End of control change helpers. */
Connor McAdams47cdf762018-05-08 13:20:13 -04004729/*
4730 * Below I've added controls to mess with the effect levels, I've only enabled
4731 * them on the Sound Blaster Z, but they would probably also work on the
4732 * Chromebook. I figured they were probably tuned specifically for it, and left
4733 * out for a reason.
4734 */
4735
4736/* Sets DSP effect level from the sliders above the controls */
4737static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4738 const unsigned int *lookup, int idx)
4739{
4740 int i = 0;
4741 unsigned int y;
4742 /*
4743 * For X_BASS, req 2 is actually crossover freq instead of
4744 * effect level
4745 */
4746 if (nid == X_BASS)
4747 y = 2;
4748 else
4749 y = 1;
4750
4751 snd_hda_power_up(codec);
4752 if (nid == XBASS_XOVER) {
4753 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4754 if (ca0132_effects[i].nid == X_BASS)
4755 break;
4756
4757 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4758 ca0132_effects[i].reqs[1],
4759 &(lookup[idx - 1]), sizeof(unsigned int));
4760 } else {
4761 /* Find the actual effect structure */
4762 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4763 if (nid == ca0132_effects[i].nid)
4764 break;
4765
4766 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4767 ca0132_effects[i].reqs[y],
4768 &(lookup[idx]), sizeof(unsigned int));
4769 }
4770
4771 snd_hda_power_down(codec);
4772
4773 return 0;
4774}
4775
4776static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4777 struct snd_ctl_elem_value *ucontrol)
4778{
4779 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4780 struct ca0132_spec *spec = codec->spec;
4781 long *valp = ucontrol->value.integer.value;
4782
4783 *valp = spec->xbass_xover_freq;
4784 return 0;
4785}
4786
4787static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4788 struct snd_ctl_elem_value *ucontrol)
4789{
4790 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4791 struct ca0132_spec *spec = codec->spec;
4792 hda_nid_t nid = get_amp_nid(kcontrol);
4793 long *valp = ucontrol->value.integer.value;
4794 int idx = nid - OUT_EFFECT_START_NID;
4795
4796 *valp = spec->fx_ctl_val[idx];
4797 return 0;
4798}
4799
4800/*
4801 * The X-bass crossover starts at 10hz, so the min is 1. The
4802 * frequency is set in multiples of 10.
4803 */
4804static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4805 struct snd_ctl_elem_info *uinfo)
4806{
4807 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4808 uinfo->count = 1;
4809 uinfo->value.integer.min = 1;
4810 uinfo->value.integer.max = 100;
4811 uinfo->value.integer.step = 1;
4812
4813 return 0;
4814}
4815
4816static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4817 struct snd_ctl_elem_info *uinfo)
4818{
4819 int chs = get_amp_channels(kcontrol);
4820
4821 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4822 uinfo->count = chs == 3 ? 2 : 1;
4823 uinfo->value.integer.min = 0;
4824 uinfo->value.integer.max = 100;
4825 uinfo->value.integer.step = 1;
4826
4827 return 0;
4828}
4829
4830static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4831 struct snd_ctl_elem_value *ucontrol)
4832{
4833 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4834 struct ca0132_spec *spec = codec->spec;
4835 hda_nid_t nid = get_amp_nid(kcontrol);
4836 long *valp = ucontrol->value.integer.value;
4837 int idx;
4838
4839 /* any change? */
4840 if (spec->xbass_xover_freq == *valp)
4841 return 0;
4842
4843 spec->xbass_xover_freq = *valp;
4844
4845 idx = *valp;
4846 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4847
4848 return 0;
4849}
4850
4851static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4852 struct snd_ctl_elem_value *ucontrol)
4853{
4854 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4855 struct ca0132_spec *spec = codec->spec;
4856 hda_nid_t nid = get_amp_nid(kcontrol);
4857 long *valp = ucontrol->value.integer.value;
4858 int idx;
4859
4860 idx = nid - EFFECT_START_NID;
4861 /* any change? */
4862 if (spec->fx_ctl_val[idx] == *valp)
4863 return 0;
4864
4865 spec->fx_ctl_val[idx] = *valp;
4866
4867 idx = *valp;
4868 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4869
4870 return 0;
4871}
4872
4873
4874/*
4875 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4876 * only has off or full 30 dB, and didn't like making a volume slider that has
4877 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4878 */
4879#define MIC_BOOST_NUM_OF_STEPS 4
4880#define MIC_BOOST_ENUM_MAX_STRLEN 10
4881
4882static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4883 struct snd_ctl_elem_info *uinfo)
4884{
4885 char *sfx = "dB";
4886 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4887
4888 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4889 uinfo->count = 1;
4890 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4891 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4892 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4893 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4894 strcpy(uinfo->value.enumerated.name, namestr);
4895 return 0;
4896}
4897
4898static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4899 struct snd_ctl_elem_value *ucontrol)
4900{
4901 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4902 struct ca0132_spec *spec = codec->spec;
4903
4904 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4905 return 0;
4906}
4907
4908static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4909 struct snd_ctl_elem_value *ucontrol)
4910{
4911 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4912 struct ca0132_spec *spec = codec->spec;
4913 int sel = ucontrol->value.enumerated.item[0];
4914 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4915
4916 if (sel >= items)
4917 return 0;
4918
4919 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4920 sel);
4921
4922 spec->mic_boost_enum_val = sel;
4923
4924 if (spec->in_enum_val != REAR_LINE_IN)
4925 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4926
4927 return 1;
4928}
4929
Ian Minetta7e76272012-12-20 18:53:35 -08004930
Connor McAdams7cb9d942018-05-08 13:20:10 -04004931/*
4932 * Input Select Control for alternative ca0132 codecs. This exists because
4933 * front microphone has no auto-detect, and we need a way to set the rear
4934 * as line-in
4935 */
4936static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4937 struct snd_ctl_elem_info *uinfo)
4938{
4939 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4940 uinfo->count = 1;
4941 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4942 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4943 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4944 strcpy(uinfo->value.enumerated.name,
4945 in_src_str[uinfo->value.enumerated.item]);
4946 return 0;
4947}
4948
4949static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4950 struct snd_ctl_elem_value *ucontrol)
4951{
4952 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4953 struct ca0132_spec *spec = codec->spec;
4954
4955 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4956 return 0;
4957}
4958
4959static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4960 struct snd_ctl_elem_value *ucontrol)
4961{
4962 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4963 struct ca0132_spec *spec = codec->spec;
4964 int sel = ucontrol->value.enumerated.item[0];
4965 unsigned int items = IN_SRC_NUM_OF_INPUTS;
4966
4967 if (sel >= items)
4968 return 0;
4969
4970 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4971 sel, in_src_str[sel]);
4972
4973 spec->in_enum_val = sel;
4974
4975 ca0132_alt_select_in(codec);
4976
4977 return 1;
4978}
4979
4980/* Sound Blaster Z Output Select Control */
4981static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
4982 struct snd_ctl_elem_info *uinfo)
4983{
4984 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4985 uinfo->count = 1;
4986 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
4987 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
4988 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
4989 strcpy(uinfo->value.enumerated.name,
4990 alt_out_presets[uinfo->value.enumerated.item].name);
4991 return 0;
4992}
4993
4994static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
4995 struct snd_ctl_elem_value *ucontrol)
4996{
4997 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4998 struct ca0132_spec *spec = codec->spec;
4999
5000 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5001 return 0;
5002}
5003
5004static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5005 struct snd_ctl_elem_value *ucontrol)
5006{
5007 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5008 struct ca0132_spec *spec = codec->spec;
5009 int sel = ucontrol->value.enumerated.item[0];
5010 unsigned int items = NUM_OF_OUTPUTS;
5011 unsigned int auto_jack;
5012
5013 if (sel >= items)
5014 return 0;
5015
5016 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5017 sel, alt_out_presets[sel].name);
5018
5019 spec->out_enum_val = sel;
5020
5021 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5022
5023 if (!auto_jack)
5024 ca0132_alt_select_out(codec);
5025
5026 return 1;
5027}
5028
Connor McAdams47cdf762018-05-08 13:20:13 -04005029/*
5030 * Smart Volume output setting control. Three different settings, Normal,
5031 * which takes the value from the smart volume slider. The two others, loud
5032 * and night, disregard the slider value and have uneditable values.
5033 */
5034#define NUM_OF_SVM_SETTINGS 3
Takashi Sakamoto3a03f832018-05-15 22:12:58 +09005035static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
Connor McAdams47cdf762018-05-08 13:20:13 -04005036
5037static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5038 struct snd_ctl_elem_info *uinfo)
5039{
5040 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5041 uinfo->count = 1;
5042 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5043 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5044 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5045 strcpy(uinfo->value.enumerated.name,
5046 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5047 return 0;
5048}
5049
5050static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5051 struct snd_ctl_elem_value *ucontrol)
5052{
5053 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5054 struct ca0132_spec *spec = codec->spec;
5055
5056 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5057 return 0;
5058}
5059
5060static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5061 struct snd_ctl_elem_value *ucontrol)
5062{
5063 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5064 struct ca0132_spec *spec = codec->spec;
5065 int sel = ucontrol->value.enumerated.item[0];
5066 unsigned int items = NUM_OF_SVM_SETTINGS;
5067 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5068 unsigned int tmp;
5069
5070 if (sel >= items)
5071 return 0;
5072
5073 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5074 sel, out_svm_set_enum_str[sel]);
5075
5076 spec->smart_volume_setting = sel;
5077
5078 switch (sel) {
5079 case 0:
5080 tmp = FLOAT_ZERO;
5081 break;
5082 case 1:
5083 tmp = FLOAT_ONE;
5084 break;
5085 case 2:
5086 tmp = FLOAT_TWO;
5087 break;
5088 default:
5089 tmp = FLOAT_ZERO;
5090 break;
5091 }
5092 /* Req 2 is the Smart Volume Setting req. */
5093 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5094 ca0132_effects[idx].reqs[2], tmp);
5095 return 1;
5096}
5097
5098/* Sound Blaster Z EQ preset controls */
5099static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5100 struct snd_ctl_elem_info *uinfo)
5101{
Fengguang Wuc5f13d72018-05-15 03:02:14 +08005102 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
Connor McAdams47cdf762018-05-08 13:20:13 -04005103
5104 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5105 uinfo->count = 1;
5106 uinfo->value.enumerated.items = items;
5107 if (uinfo->value.enumerated.item >= items)
5108 uinfo->value.enumerated.item = items - 1;
5109 strcpy(uinfo->value.enumerated.name,
5110 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5111 return 0;
5112}
5113
5114static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5115 struct snd_ctl_elem_value *ucontrol)
5116{
5117 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5118 struct ca0132_spec *spec = codec->spec;
5119
5120 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5121 return 0;
5122}
5123
5124static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5125 struct snd_ctl_elem_value *ucontrol)
5126{
5127 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5128 struct ca0132_spec *spec = codec->spec;
5129 int i, err = 0;
5130 int sel = ucontrol->value.enumerated.item[0];
Fengguang Wuc5f13d72018-05-15 03:02:14 +08005131 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
Connor McAdams47cdf762018-05-08 13:20:13 -04005132
5133 if (sel >= items)
5134 return 0;
5135
5136 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5137 ca0132_alt_eq_presets[sel].name);
5138 /*
5139 * Idx 0 is default.
5140 * Default needs to qualify with CrystalVoice state.
5141 */
5142 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5143 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5144 ca0132_alt_eq_enum.reqs[i],
5145 ca0132_alt_eq_presets[sel].vals[i]);
5146 if (err < 0)
5147 break;
5148 }
5149
5150 if (err >= 0)
5151 spec->eq_preset_val = sel;
5152
5153 return 1;
5154}
5155
Ian Minetta7e76272012-12-20 18:53:35 -08005156static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5157 struct snd_ctl_elem_info *uinfo)
5158{
Jérémy Lefaurea9291f42017-10-12 22:36:31 -04005159 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
Ian Minetta7e76272012-12-20 18:53:35 -08005160
5161 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5162 uinfo->count = 1;
5163 uinfo->value.enumerated.items = items;
5164 if (uinfo->value.enumerated.item >= items)
5165 uinfo->value.enumerated.item = items - 1;
5166 strcpy(uinfo->value.enumerated.name,
5167 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5168 return 0;
5169}
5170
5171static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5172 struct snd_ctl_elem_value *ucontrol)
5173{
5174 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5175 struct ca0132_spec *spec = codec->spec;
5176
5177 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5178 return 0;
5179}
5180
5181static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5182 struct snd_ctl_elem_value *ucontrol)
5183{
5184 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5185 struct ca0132_spec *spec = codec->spec;
5186 int i, err = 0;
5187 int sel = ucontrol->value.enumerated.item[0];
Ian Minetta7e76272012-12-20 18:53:35 -08005188
Jérémy Lefaurea9291f42017-10-12 22:36:31 -04005189 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
Ian Minetta7e76272012-12-20 18:53:35 -08005190 return 0;
5191
Takashi Iwai4e76a882014-02-25 12:21:03 +01005192 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
Ian Minetta7e76272012-12-20 18:53:35 -08005193 sel, ca0132_voicefx_presets[sel].name);
5194
5195 /*
5196 * Idx 0 is default.
5197 * Default needs to qualify with CrystalVoice state.
5198 */
5199 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5200 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5201 ca0132_voicefx.reqs[i],
5202 ca0132_voicefx_presets[sel].vals[i]);
5203 if (err < 0)
5204 break;
5205 }
5206
5207 if (err >= 0) {
5208 spec->voicefx_val = sel;
5209 /* enable voice fx */
5210 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5211 }
5212
5213 return 1;
5214}
5215
5216static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5217 struct snd_ctl_elem_value *ucontrol)
5218{
5219 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5220 struct ca0132_spec *spec = codec->spec;
5221 hda_nid_t nid = get_amp_nid(kcontrol);
5222 int ch = get_amp_channels(kcontrol);
5223 long *valp = ucontrol->value.integer.value;
5224
5225 /* vnode */
5226 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5227 if (ch & 1) {
5228 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5229 valp++;
5230 }
5231 if (ch & 2) {
5232 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5233 valp++;
5234 }
5235 return 0;
5236 }
5237
5238 /* effects, include PE and CrystalVoice */
5239 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5240 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5241 return 0;
5242 }
5243
5244 /* mic boost */
5245 if (nid == spec->input_pins[0]) {
5246 *valp = spec->cur_mic_boost;
5247 return 0;
5248 }
5249
5250 return 0;
5251}
5252
5253static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5254 struct snd_ctl_elem_value *ucontrol)
5255{
5256 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5257 struct ca0132_spec *spec = codec->spec;
5258 hda_nid_t nid = get_amp_nid(kcontrol);
5259 int ch = get_amp_channels(kcontrol);
5260 long *valp = ucontrol->value.integer.value;
5261 int changed = 1;
5262
Takashi Iwai4e76a882014-02-25 12:21:03 +01005263 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
Ian Minetta7e76272012-12-20 18:53:35 -08005264 nid, *valp);
5265
5266 snd_hda_power_up(codec);
5267 /* vnode */
5268 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5269 if (ch & 1) {
5270 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5271 valp++;
5272 }
5273 if (ch & 2) {
5274 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5275 valp++;
5276 }
5277 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5278 goto exit;
5279 }
5280
5281 /* PE */
5282 if (nid == PLAY_ENHANCEMENT) {
5283 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5284 changed = ca0132_pe_switch_set(codec);
5285 goto exit;
5286 }
5287
5288 /* CrystalVoice */
5289 if (nid == CRYSTAL_VOICE) {
5290 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5291 changed = ca0132_cvoice_switch_set(codec);
5292 goto exit;
5293 }
5294
5295 /* out and in effects */
5296 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5297 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5298 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5299 changed = ca0132_effects_set(codec, nid, *valp);
5300 goto exit;
5301 }
5302
5303 /* mic boost */
5304 if (nid == spec->input_pins[0]) {
5305 spec->cur_mic_boost = *valp;
Connor McAdams7cb9d942018-05-08 13:20:10 -04005306 if (spec->use_alt_functions) {
5307 if (spec->in_enum_val != REAR_LINE_IN)
5308 changed = ca0132_mic_boost_set(codec, *valp);
5309 } else {
5310 /* Mic boost does not apply to Digital Mic */
5311 if (spec->cur_mic_type != DIGITAL_MIC)
5312 changed = ca0132_mic_boost_set(codec, *valp);
5313 }
Ian Minetta7e76272012-12-20 18:53:35 -08005314
Ian Minetta7e76272012-12-20 18:53:35 -08005315 goto exit;
5316 }
5317
5318exit:
5319 snd_hda_power_down(codec);
5320 return changed;
5321}
5322
5323/*
5324 * Volume related
5325 */
Connor McAdams017310f2018-05-08 13:20:11 -04005326/*
5327 * Sets the internal DSP decibel level to match the DAC for output, and the
5328 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5329 * all alternative codecs set DSP playback volume.
5330 */
5331static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5332{
5333 struct ca0132_spec *spec = codec->spec;
5334 unsigned int dsp_dir;
5335 unsigned int lookup_val;
5336
5337 if (nid == VNID_SPK)
5338 dsp_dir = DSP_VOL_OUT;
5339 else
5340 dsp_dir = DSP_VOL_IN;
5341
5342 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5343
5344 dspio_set_uint_param(codec,
5345 ca0132_alt_vol_ctls[dsp_dir].mid,
5346 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5347 float_vol_db_lookup[lookup_val]);
5348
5349 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5350
5351 dspio_set_uint_param(codec,
5352 ca0132_alt_vol_ctls[dsp_dir].mid,
5353 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5354 float_vol_db_lookup[lookup_val]);
5355
5356 dspio_set_uint_param(codec,
5357 ca0132_alt_vol_ctls[dsp_dir].mid,
5358 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5359}
5360
Ian Minetta7e76272012-12-20 18:53:35 -08005361static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5362 struct snd_ctl_elem_info *uinfo)
5363{
5364 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5365 struct ca0132_spec *spec = codec->spec;
5366 hda_nid_t nid = get_amp_nid(kcontrol);
5367 int ch = get_amp_channels(kcontrol);
5368 int dir = get_amp_direction(kcontrol);
5369 unsigned long pval;
5370 int err;
5371
5372 switch (nid) {
5373 case VNID_SPK:
5374 /* follow shared_out info */
5375 nid = spec->shared_out_nid;
5376 mutex_lock(&codec->control_mutex);
5377 pval = kcontrol->private_value;
5378 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5379 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5380 kcontrol->private_value = pval;
5381 mutex_unlock(&codec->control_mutex);
5382 break;
5383 case VNID_MIC:
5384 /* follow shared_mic info */
5385 nid = spec->shared_mic_nid;
5386 mutex_lock(&codec->control_mutex);
5387 pval = kcontrol->private_value;
5388 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5389 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5390 kcontrol->private_value = pval;
5391 mutex_unlock(&codec->control_mutex);
5392 break;
5393 default:
5394 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5395 }
5396 return err;
5397}
5398
5399static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5400 struct snd_ctl_elem_value *ucontrol)
5401{
5402 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5403 struct ca0132_spec *spec = codec->spec;
5404 hda_nid_t nid = get_amp_nid(kcontrol);
5405 int ch = get_amp_channels(kcontrol);
5406 long *valp = ucontrol->value.integer.value;
5407
5408 /* store the left and right volume */
5409 if (ch & 1) {
5410 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5411 valp++;
5412 }
5413 if (ch & 2) {
5414 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5415 valp++;
5416 }
5417 return 0;
5418}
5419
5420static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5421 struct snd_ctl_elem_value *ucontrol)
5422{
5423 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5424 struct ca0132_spec *spec = codec->spec;
5425 hda_nid_t nid = get_amp_nid(kcontrol);
5426 int ch = get_amp_channels(kcontrol);
5427 long *valp = ucontrol->value.integer.value;
5428 hda_nid_t shared_nid = 0;
5429 bool effective;
5430 int changed = 1;
5431
5432 /* store the left and right volume */
5433 if (ch & 1) {
5434 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5435 valp++;
5436 }
5437 if (ch & 2) {
5438 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5439 valp++;
5440 }
5441
5442 /* if effective conditions, then update hw immediately. */
5443 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5444 if (effective) {
5445 int dir = get_amp_direction(kcontrol);
5446 unsigned long pval;
5447
5448 snd_hda_power_up(codec);
5449 mutex_lock(&codec->control_mutex);
5450 pval = kcontrol->private_value;
5451 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5452 0, dir);
5453 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5454 kcontrol->private_value = pval;
5455 mutex_unlock(&codec->control_mutex);
5456 snd_hda_power_down(codec);
5457 }
5458
5459 return changed;
5460}
5461
Connor McAdams017310f2018-05-08 13:20:11 -04005462/*
5463 * This function is the same as the one above, because using an if statement
5464 * inside of the above volume control for the DSP volume would cause too much
5465 * lag. This is a lot more smooth.
5466 */
5467static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5468 struct snd_ctl_elem_value *ucontrol)
5469{
5470 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5471 struct ca0132_spec *spec = codec->spec;
5472 hda_nid_t nid = get_amp_nid(kcontrol);
5473 int ch = get_amp_channels(kcontrol);
5474 long *valp = ucontrol->value.integer.value;
5475 hda_nid_t vnid = 0;
5476 int changed = 1;
5477
5478 switch (nid) {
5479 case 0x02:
5480 vnid = VNID_SPK;
5481 break;
5482 case 0x07:
5483 vnid = VNID_MIC;
5484 break;
5485 }
5486
5487 /* store the left and right volume */
5488 if (ch & 1) {
5489 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5490 valp++;
5491 }
5492 if (ch & 2) {
5493 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5494 valp++;
5495 }
5496
5497 snd_hda_power_up(codec);
5498 ca0132_alt_dsp_volume_put(codec, vnid);
5499 mutex_lock(&codec->control_mutex);
5500 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5501 mutex_unlock(&codec->control_mutex);
5502 snd_hda_power_down(codec);
5503
5504 return changed;
5505}
5506
Ian Minetta7e76272012-12-20 18:53:35 -08005507static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5508 unsigned int size, unsigned int __user *tlv)
5509{
5510 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5511 struct ca0132_spec *spec = codec->spec;
5512 hda_nid_t nid = get_amp_nid(kcontrol);
5513 int ch = get_amp_channels(kcontrol);
5514 int dir = get_amp_direction(kcontrol);
5515 unsigned long pval;
5516 int err;
5517
5518 switch (nid) {
5519 case VNID_SPK:
5520 /* follow shared_out tlv */
5521 nid = spec->shared_out_nid;
5522 mutex_lock(&codec->control_mutex);
5523 pval = kcontrol->private_value;
5524 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5525 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5526 kcontrol->private_value = pval;
5527 mutex_unlock(&codec->control_mutex);
5528 break;
5529 case VNID_MIC:
5530 /* follow shared_mic tlv */
5531 nid = spec->shared_mic_nid;
5532 mutex_lock(&codec->control_mutex);
5533 pval = kcontrol->private_value;
5534 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5535 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5536 kcontrol->private_value = pval;
5537 mutex_unlock(&codec->control_mutex);
5538 break;
5539 default:
5540 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5541 }
5542 return err;
5543}
5544
Connor McAdams47cdf762018-05-08 13:20:13 -04005545/* Add volume slider control for effect level */
5546static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5547 const char *pfx, int dir)
5548{
Connor McAdams47cdf762018-05-08 13:20:13 -04005549 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5550 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5551 struct snd_kcontrol_new knew =
5552 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5553
Takashi Sakamoto0cc1aa72018-05-15 22:12:59 +09005554 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
Connor McAdams47cdf762018-05-08 13:20:13 -04005555
Takashi Iwaibb86124c2018-07-25 23:00:49 +02005556 knew.tlv.c = NULL;
Connor McAdams47cdf762018-05-08 13:20:13 -04005557
5558 switch (nid) {
5559 case XBASS_XOVER:
5560 knew.info = ca0132_alt_xbass_xover_slider_info;
5561 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5562 knew.put = ca0132_alt_xbass_xover_slider_put;
5563 break;
5564 default:
5565 knew.info = ca0132_alt_effect_slider_info;
5566 knew.get = ca0132_alt_slider_ctl_get;
5567 knew.put = ca0132_alt_effect_slider_put;
5568 knew.private_value =
5569 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5570 break;
5571 }
5572
5573 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5574}
5575
5576/*
5577 * Added FX: prefix for the alternative codecs, because otherwise the surround
5578 * effect would conflict with the Surround sound volume control. Also seems more
5579 * clear as to what the switches do. Left alone for others.
5580 */
Ian Minetta7e76272012-12-20 18:53:35 -08005581static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5582 const char *pfx, int dir)
5583{
Connor McAdams47cdf762018-05-08 13:20:13 -04005584 struct ca0132_spec *spec = codec->spec;
Takashi Iwai975cc022013-06-28 11:56:49 +02005585 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
Ian Minetta7e76272012-12-20 18:53:35 -08005586 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5587 struct snd_kcontrol_new knew =
5588 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
Connor McAdams47cdf762018-05-08 13:20:13 -04005589 /* If using alt_controls, add FX: prefix. But, don't add FX:
5590 * prefix to OutFX or InFX enable controls.
5591 */
5592 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
Takashi Sakamoto0cc1aa72018-05-15 22:12:59 +09005593 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
Connor McAdams47cdf762018-05-08 13:20:13 -04005594 else
5595 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5596
Ian Minetta7e76272012-12-20 18:53:35 -08005597 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5598}
5599
5600static int add_voicefx(struct hda_codec *codec)
5601{
5602 struct snd_kcontrol_new knew =
5603 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5604 VOICEFX, 1, 0, HDA_INPUT);
5605 knew.info = ca0132_voicefx_info;
5606 knew.get = ca0132_voicefx_get;
5607 knew.put = ca0132_voicefx_put;
5608 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5609}
5610
Connor McAdams47cdf762018-05-08 13:20:13 -04005611/* Create the EQ Preset control */
5612static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5613{
5614 struct snd_kcontrol_new knew =
5615 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5616 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5617 knew.info = ca0132_alt_eq_preset_info;
5618 knew.get = ca0132_alt_eq_preset_get;
5619 knew.put = ca0132_alt_eq_preset_put;
5620 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5621 snd_ctl_new1(&knew, codec));
5622}
5623
5624/*
5625 * Add enumerated control for the three different settings of the smart volume
5626 * output effect. Normal just uses the slider value, and loud and night are
5627 * their own things that ignore that value.
5628 */
5629static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5630{
5631 struct snd_kcontrol_new knew =
5632 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5633 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5634 knew.info = ca0132_alt_svm_setting_info;
5635 knew.get = ca0132_alt_svm_setting_get;
5636 knew.put = ca0132_alt_svm_setting_put;
5637 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5638 snd_ctl_new1(&knew, codec));
5639
5640}
5641
Ian Minetta7e76272012-12-20 18:53:35 -08005642/*
Connor McAdams7cb9d942018-05-08 13:20:10 -04005643 * Create an Output Select enumerated control for codecs with surround
5644 * out capabilities.
5645 */
5646static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5647{
5648 struct snd_kcontrol_new knew =
5649 HDA_CODEC_MUTE_MONO("Output Select",
5650 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5651 knew.info = ca0132_alt_output_select_get_info;
5652 knew.get = ca0132_alt_output_select_get;
5653 knew.put = ca0132_alt_output_select_put;
5654 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5655 snd_ctl_new1(&knew, codec));
5656}
5657
5658/*
5659 * Create an Input Source enumerated control for the alternate ca0132 codecs
5660 * because the front microphone has no auto-detect, and Line-in has to be set
5661 * somehow.
5662 */
5663static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5664{
5665 struct snd_kcontrol_new knew =
5666 HDA_CODEC_MUTE_MONO("Input Source",
5667 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5668 knew.info = ca0132_alt_input_source_info;
5669 knew.get = ca0132_alt_input_source_get;
5670 knew.put = ca0132_alt_input_source_put;
5671 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5672 snd_ctl_new1(&knew, codec));
5673}
5674
5675/*
Connor McAdams47cdf762018-05-08 13:20:13 -04005676 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5677 * more control than the original mic boost, which is either full 30dB or off.
5678 */
5679static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5680{
5681 struct snd_kcontrol_new knew =
5682 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5683 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5684 knew.info = ca0132_alt_mic_boost_info;
5685 knew.get = ca0132_alt_mic_boost_get;
5686 knew.put = ca0132_alt_mic_boost_put;
5687 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5688 snd_ctl_new1(&knew, codec));
5689
5690}
5691
5692/*
5693 * Need to create slave controls for the alternate codecs that have surround
5694 * capabilities.
5695 */
5696static const char * const ca0132_alt_slave_pfxs[] = {
5697 "Front", "Surround", "Center", "LFE", NULL,
5698};
5699
5700/*
5701 * Also need special channel map, because the default one is incorrect.
5702 * I think this has to do with the pin for rear surround being 0x11,
5703 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5704 */
Colin Ian King9c4a6652018-06-21 19:34:57 +01005705static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
Connor McAdams47cdf762018-05-08 13:20:13 -04005706 { .channels = 2,
5707 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5708 { .channels = 4,
5709 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5710 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5711 { .channels = 6,
5712 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5713 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5714 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5715 { }
5716};
5717
5718/* Add the correct chmap for streams with 6 channels. */
5719static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5720{
5721 int err = 0;
5722 struct hda_pcm *pcm;
5723
5724 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5725 struct hda_pcm_stream *hinfo =
5726 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5727 struct snd_pcm_chmap *chmap;
5728 const struct snd_pcm_chmap_elem *elem;
5729
5730 elem = ca0132_alt_chmaps;
5731 if (hinfo->channels_max == 6) {
5732 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5733 SNDRV_PCM_STREAM_PLAYBACK,
5734 elem, hinfo->channels_max, 0, &chmap);
5735 if (err < 0)
5736 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5737 }
5738 }
5739}
5740
5741/*
Ian Minetta7e76272012-12-20 18:53:35 -08005742 * When changing Node IDs for Mixer Controls below, make sure to update
5743 * Node IDs in ca0132_config() as well.
5744 */
Takashi Sakamotob0eaa072018-05-15 22:12:57 +09005745static const struct snd_kcontrol_new ca0132_mixer[] = {
Ian Minetta7e76272012-12-20 18:53:35 -08005746 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5747 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5748 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5749 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5750 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5751 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5752 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5753 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5754 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5755 0x12, 1, HDA_INPUT),
5756 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5757 VNID_HP_SEL, 1, HDA_OUTPUT),
5758 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5759 VNID_AMIC1_SEL, 1, HDA_INPUT),
5760 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5761 VNID_HP_ASEL, 1, HDA_OUTPUT),
5762 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5763 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5764 { } /* end */
5765};
5766
Connor McAdams017310f2018-05-08 13:20:11 -04005767/*
5768 * SBZ specific control mixer. Removes auto-detect for mic, and adds surround
5769 * controls. Also sets both the Front Playback and Capture Volume controls to
5770 * alt so they set the DSP's decibel level.
5771 */
Takashi Sakamotob0eaa072018-05-15 22:12:57 +09005772static const struct snd_kcontrol_new sbz_mixer[] = {
Connor McAdams017310f2018-05-08 13:20:11 -04005773 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5774 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
Connor McAdams47cdf762018-05-08 13:20:13 -04005775 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5776 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5777 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5778 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5779 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5780 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
Connor McAdams017310f2018-05-08 13:20:11 -04005781 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5782 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5783 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5784 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5785 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5786 VNID_HP_ASEL, 1, HDA_OUTPUT),
5787 { } /* end */
5788};
5789
5790/*
5791 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5792 * because it doesn't set decibel levels for the DSP for capture.
5793 */
Takashi Sakamotob0eaa072018-05-15 22:12:57 +09005794static const struct snd_kcontrol_new r3di_mixer[] = {
Connor McAdams017310f2018-05-08 13:20:11 -04005795 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5796 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
Connor McAdams47cdf762018-05-08 13:20:13 -04005797 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5798 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5799 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5800 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5801 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5802 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
Connor McAdams017310f2018-05-08 13:20:11 -04005803 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5804 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5805 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5806 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5807 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5808 VNID_HP_ASEL, 1, HDA_OUTPUT),
5809 { } /* end */
5810};
5811
Ian Minette90f29e2012-12-20 18:53:39 -08005812static int ca0132_build_controls(struct hda_codec *codec)
5813{
5814 struct ca0132_spec *spec = codec->spec;
Connor McAdams47cdf762018-05-08 13:20:13 -04005815 int i, num_fx, num_sliders;
Ian Minette90f29e2012-12-20 18:53:39 -08005816 int err = 0;
5817
5818 /* Add Mixer controls */
5819 for (i = 0; i < spec->num_mixers; i++) {
5820 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5821 if (err < 0)
5822 return err;
5823 }
Connor McAdams47cdf762018-05-08 13:20:13 -04005824 /* Setup vmaster with surround slaves for desktop ca0132 devices */
5825 if (spec->use_alt_functions) {
5826 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5827 spec->tlv);
5828 snd_hda_add_vmaster(codec, "Master Playback Volume",
5829 spec->tlv, ca0132_alt_slave_pfxs,
5830 "Playback Volume");
5831 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5832 NULL, ca0132_alt_slave_pfxs,
5833 "Playback Switch",
5834 true, &spec->vmaster_mute.sw_kctl);
5835
5836 }
Ian Minette90f29e2012-12-20 18:53:39 -08005837
5838 /* Add in and out effects controls.
5839 * VoiceFX, PE and CrystalVoice are added separately.
5840 */
5841 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5842 for (i = 0; i < num_fx; i++) {
Connor McAdams47cdf762018-05-08 13:20:13 -04005843 /* SBZ breaks if Echo Cancellation is used */
5844 if (spec->quirk == QUIRK_SBZ) {
5845 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5846 OUT_EFFECTS_COUNT))
5847 continue;
5848 }
5849
Ian Minette90f29e2012-12-20 18:53:39 -08005850 err = add_fx_switch(codec, ca0132_effects[i].nid,
5851 ca0132_effects[i].name,
5852 ca0132_effects[i].direct);
5853 if (err < 0)
5854 return err;
5855 }
Connor McAdams47cdf762018-05-08 13:20:13 -04005856 /*
5857 * If codec has use_alt_controls set to true, add effect level sliders,
5858 * EQ presets, and Smart Volume presets. Also, change names to add FX
5859 * prefix, and change PlayEnhancement and CrystalVoice to match.
5860 */
5861 if (spec->use_alt_controls) {
5862 ca0132_alt_add_svm_enum(codec);
5863 add_ca0132_alt_eq_presets(codec);
5864 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5865 "Enable OutFX", 0);
5866 if (err < 0)
5867 return err;
Ian Minette90f29e2012-12-20 18:53:39 -08005868
Connor McAdams47cdf762018-05-08 13:20:13 -04005869 err = add_fx_switch(codec, CRYSTAL_VOICE,
5870 "Enable InFX", 1);
5871 if (err < 0)
5872 return err;
Ian Minette90f29e2012-12-20 18:53:39 -08005873
Connor McAdams47cdf762018-05-08 13:20:13 -04005874 num_sliders = OUT_EFFECTS_COUNT - 1;
5875 for (i = 0; i < num_sliders; i++) {
5876 err = ca0132_alt_add_effect_slider(codec,
5877 ca0132_effects[i].nid,
5878 ca0132_effects[i].name,
5879 ca0132_effects[i].direct);
5880 if (err < 0)
5881 return err;
5882 }
Ian Minette90f29e2012-12-20 18:53:39 -08005883
Connor McAdams47cdf762018-05-08 13:20:13 -04005884 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5885 "X-Bass Crossover", EFX_DIR_OUT);
5886
5887 if (err < 0)
5888 return err;
5889 } else {
5890 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5891 "PlayEnhancement", 0);
5892 if (err < 0)
5893 return err;
5894
5895 err = add_fx_switch(codec, CRYSTAL_VOICE,
5896 "CrystalVoice", 1);
5897 if (err < 0)
5898 return err;
5899 }
Ian Minette90f29e2012-12-20 18:53:39 -08005900 add_voicefx(codec);
5901
Connor McAdams7cb9d942018-05-08 13:20:10 -04005902 /*
5903 * If the codec uses alt_functions, you need the enumerated controls
5904 * to select the new outputs and inputs, plus add the new mic boost
5905 * setting control.
5906 */
5907 if (spec->use_alt_functions) {
5908 ca0132_alt_add_output_enum(codec);
5909 ca0132_alt_add_input_enum(codec);
Connor McAdams47cdf762018-05-08 13:20:13 -04005910 ca0132_alt_add_mic_boost_enum(codec);
Connor McAdams7cb9d942018-05-08 13:20:10 -04005911 }
Ian Minette90f29e2012-12-20 18:53:39 -08005912#ifdef ENABLE_TUNING_CONTROLS
5913 add_tuning_ctls(codec);
5914#endif
5915
5916 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5917 if (err < 0)
5918 return err;
5919
5920 if (spec->dig_out) {
5921 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5922 spec->dig_out);
5923 if (err < 0)
5924 return err;
5925 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5926 if (err < 0)
5927 return err;
5928 /* spec->multiout.share_spdif = 1; */
5929 }
5930
5931 if (spec->dig_in) {
5932 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5933 if (err < 0)
5934 return err;
5935 }
Connor McAdams47cdf762018-05-08 13:20:13 -04005936
5937 if (spec->use_alt_functions)
5938 ca0132_alt_add_chmap_ctls(codec);
5939
Ian Minette90f29e2012-12-20 18:53:39 -08005940 return 0;
5941}
5942
Ian Minett5aaca442012-12-20 18:53:34 -08005943/*
Ian Minette90f29e2012-12-20 18:53:39 -08005944 * PCM
Ian Minett95c6e9c2011-06-15 15:35:17 -07005945 */
Julia Lawall071f1342016-09-11 15:05:43 +02005946static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
Ian Minett95c6e9c2011-06-15 15:35:17 -07005947 .substreams = 1,
5948 .channels_min = 2,
Ian Minett825315b2012-12-20 18:53:36 -08005949 .channels_max = 6,
Ian Minett95c6e9c2011-06-15 15:35:17 -07005950 .ops = {
5951 .prepare = ca0132_playback_pcm_prepare,
Dylan Reide8412ca2013-04-04 13:55:09 -07005952 .cleanup = ca0132_playback_pcm_cleanup,
5953 .get_delay = ca0132_playback_pcm_delay,
Ian Minett95c6e9c2011-06-15 15:35:17 -07005954 },
5955};
5956
Julia Lawall071f1342016-09-11 15:05:43 +02005957static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
Ian Minett95c6e9c2011-06-15 15:35:17 -07005958 .substreams = 1,
5959 .channels_min = 2,
5960 .channels_max = 2,
Ian Minett825315b2012-12-20 18:53:36 -08005961 .ops = {
5962 .prepare = ca0132_capture_pcm_prepare,
Dylan Reide8412ca2013-04-04 13:55:09 -07005963 .cleanup = ca0132_capture_pcm_cleanup,
5964 .get_delay = ca0132_capture_pcm_delay,
Ian Minett825315b2012-12-20 18:53:36 -08005965 },
Ian Minett95c6e9c2011-06-15 15:35:17 -07005966};
5967
Julia Lawall071f1342016-09-11 15:05:43 +02005968static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
Ian Minett95c6e9c2011-06-15 15:35:17 -07005969 .substreams = 1,
5970 .channels_min = 2,
5971 .channels_max = 2,
5972 .ops = {
Takashi Iwai27ebeb02012-08-08 17:20:18 +02005973 .open = ca0132_dig_playback_pcm_open,
5974 .close = ca0132_dig_playback_pcm_close,
Ian Minett95c6e9c2011-06-15 15:35:17 -07005975 .prepare = ca0132_dig_playback_pcm_prepare,
5976 .cleanup = ca0132_dig_playback_pcm_cleanup
5977 },
5978};
5979
Julia Lawall071f1342016-09-11 15:05:43 +02005980static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
Ian Minett95c6e9c2011-06-15 15:35:17 -07005981 .substreams = 1,
5982 .channels_min = 2,
5983 .channels_max = 2,
Ian Minett95c6e9c2011-06-15 15:35:17 -07005984};
5985
5986static int ca0132_build_pcms(struct hda_codec *codec)
5987{
5988 struct ca0132_spec *spec = codec->spec;
Takashi Iwaibbbc7e82015-02-27 17:43:19 +01005989 struct hda_pcm *info;
Ian Minett95c6e9c2011-06-15 15:35:17 -07005990
Takashi Iwaibbbc7e82015-02-27 17:43:19 +01005991 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
5992 if (!info)
5993 return -ENOMEM;
Connor McAdams47cdf762018-05-08 13:20:13 -04005994 if (spec->use_alt_functions) {
5995 info->own_chmap = true;
5996 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
5997 = ca0132_alt_chmaps;
5998 }
Ian Minett95c6e9c2011-06-15 15:35:17 -07005999 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6000 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6001 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6002 spec->multiout.max_channels;
6003 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
Ian Minett825315b2012-12-20 18:53:36 -08006004 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
Ian Minett95c6e9c2011-06-15 15:35:17 -07006005 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
Ian Minett95c6e9c2011-06-15 15:35:17 -07006006
Connor McAdams009b8f92018-05-08 13:20:06 -04006007 /* With the DSP enabled, desktops don't use this ADC. */
Alastair Bridgewater5f8ddc62018-06-15 21:56:19 -04006008 if (!spec->use_alt_functions) {
Connor McAdams009b8f92018-05-08 13:20:06 -04006009 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6010 if (!info)
6011 return -ENOMEM;
6012 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6013 ca0132_pcm_analog_capture;
6014 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6015 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6016 }
Ian Minett825315b2012-12-20 18:53:36 -08006017
Takashi Iwaibbbc7e82015-02-27 17:43:19 +01006018 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6019 if (!info)
6020 return -ENOMEM;
Ian Minett825315b2012-12-20 18:53:36 -08006021 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6022 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6023 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
Ian Minett825315b2012-12-20 18:53:36 -08006024
Ian Minett95c6e9c2011-06-15 15:35:17 -07006025 if (!spec->dig_out && !spec->dig_in)
6026 return 0;
6027
Takashi Iwaibbbc7e82015-02-27 17:43:19 +01006028 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6029 if (!info)
6030 return -ENOMEM;
Ian Minett95c6e9c2011-06-15 15:35:17 -07006031 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6032 if (spec->dig_out) {
6033 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6034 ca0132_pcm_digital_playback;
6035 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6036 }
6037 if (spec->dig_in) {
6038 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6039 ca0132_pcm_digital_capture;
6040 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6041 }
Ian Minett95c6e9c2011-06-15 15:35:17 -07006042
6043 return 0;
6044}
6045
Ian Minett441aa6a2012-12-20 18:53:40 -08006046static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6047{
6048 if (pin) {
Takashi Iwaia0c041c2013-01-15 17:13:31 +01006049 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
Ian Minett441aa6a2012-12-20 18:53:40 -08006050 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6051 snd_hda_codec_write(codec, pin, 0,
6052 AC_VERB_SET_AMP_GAIN_MUTE,
6053 AMP_OUT_UNMUTE);
6054 }
6055 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6056 snd_hda_codec_write(codec, dac, 0,
6057 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6058}
6059
6060static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6061{
6062 if (pin) {
Takashi Iwaia0c041c2013-01-15 17:13:31 +01006063 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
Ian Minett441aa6a2012-12-20 18:53:40 -08006064 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6065 snd_hda_codec_write(codec, pin, 0,
6066 AC_VERB_SET_AMP_GAIN_MUTE,
6067 AMP_IN_UNMUTE(0));
6068 }
6069 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6070 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6071 AMP_IN_UNMUTE(0));
6072
6073 /* init to 0 dB and unmute. */
6074 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6075 HDA_AMP_VOLMASK, 0x5a);
6076 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6077 HDA_AMP_MUTE, 0);
6078 }
6079}
6080
Ian Minett5aaca442012-12-20 18:53:34 -08006081static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6082{
6083 unsigned int caps;
6084
6085 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6086 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6087 snd_hda_override_amp_caps(codec, nid, dir, caps);
6088}
6089
6090/*
6091 * Switch between Digital built-in mic and analog mic.
6092 */
6093static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6094{
6095 struct ca0132_spec *spec = codec->spec;
6096 unsigned int tmp;
6097 u8 val;
6098 unsigned int oldval;
6099
Takashi Iwai4e76a882014-02-25 12:21:03 +01006100 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
Ian Minett5aaca442012-12-20 18:53:34 -08006101
6102 oldval = stop_mic1(codec);
6103 ca0132_set_vipsource(codec, 0);
6104 if (enable) {
6105 /* set DMic input as 2-ch */
6106 tmp = FLOAT_TWO;
6107 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6108
6109 val = spec->dmic_ctl;
6110 val |= 0x80;
6111 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6112 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6113
6114 if (!(spec->dmic_ctl & 0x20))
6115 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6116 } else {
6117 /* set AMic input as mono */
6118 tmp = FLOAT_ONE;
6119 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6120
6121 val = spec->dmic_ctl;
6122 /* clear bit7 and bit5 to disable dmic */
6123 val &= 0x5f;
6124 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6125 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6126
6127 if (!(spec->dmic_ctl & 0x20))
6128 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6129 }
6130 ca0132_set_vipsource(codec, 1);
6131 resume_mic1(codec, oldval);
6132}
6133
6134/*
6135 * Initialization for Digital Mic.
6136 */
6137static void ca0132_init_dmic(struct hda_codec *codec)
6138{
6139 struct ca0132_spec *spec = codec->spec;
6140 u8 val;
6141
6142 /* Setup Digital Mic here, but don't enable.
6143 * Enable based on jack detect.
6144 */
6145
6146 /* MCLK uses MPIO1, set to enable.
6147 * Bit 2-0: MPIO select
6148 * Bit 3: set to disable
6149 * Bit 7-4: reserved
6150 */
6151 val = 0x01;
6152 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6153 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6154
6155 /* Data1 uses MPIO3. Data2 not use
6156 * Bit 2-0: Data1 MPIO select
6157 * Bit 3: set disable Data1
6158 * Bit 6-4: Data2 MPIO select
6159 * Bit 7: set disable Data2
6160 */
6161 val = 0x83;
6162 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6163 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6164
6165 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6166 * Bit 3-0: Channel mask
6167 * Bit 4: set for 48KHz, clear for 32KHz
6168 * Bit 5: mode
6169 * Bit 6: set to select Data2, clear for Data1
6170 * Bit 7: set to enable DMic, clear for AMic
6171 */
Alastair Bridgewatera57a46b2018-06-15 21:56:20 -04006172 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6173 val = 0x33;
6174 else
6175 val = 0x23;
Ian Minett5aaca442012-12-20 18:53:34 -08006176 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6177 spec->dmic_ctl = val;
6178 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6179 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6180}
6181
6182/*
6183 * Initialization for Analog Mic 2
6184 */
6185static void ca0132_init_analog_mic2(struct hda_codec *codec)
6186{
6187 struct ca0132_spec *spec = codec->spec;
6188
6189 mutex_lock(&spec->chipio_mutex);
6190 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6191 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6192 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6193 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6194 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6195 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6196 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6197 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6198 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6199 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6200 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6201 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6202 mutex_unlock(&spec->chipio_mutex);
6203}
6204
6205static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6206{
6207 struct ca0132_spec *spec = codec->spec;
6208 int i;
Ian Minett5aaca442012-12-20 18:53:34 -08006209
Takashi Iwai4e76a882014-02-25 12:21:03 +01006210 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
Takashi Iwai7639a062015-03-03 10:07:24 +01006211 snd_hda_codec_update_widgets(codec);
Ian Minett5aaca442012-12-20 18:53:34 -08006212
6213 for (i = 0; i < spec->multiout.num_dacs; i++)
6214 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6215
6216 for (i = 0; i < spec->num_outputs; i++)
6217 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6218
6219 for (i = 0; i < spec->num_inputs; i++) {
6220 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6221 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6222 }
6223}
6224
6225/*
Connor McAdams7e6ed622018-05-08 13:20:08 -04006226 * Recon3Di r3di_setup_defaults sub functions.
6227 */
6228
Connor McAdams447fd8e2018-05-08 13:20:09 -04006229static void r3di_dsp_scp_startup(struct hda_codec *codec)
6230{
6231 unsigned int tmp;
6232
6233 tmp = 0x00000000;
6234 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6235
6236 tmp = 0x00000001;
6237 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6238
6239 tmp = 0x00000004;
6240 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6241
6242 tmp = 0x00000005;
6243 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6244
6245 tmp = 0x00000000;
6246 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6247
6248}
6249
Connor McAdams7e6ed622018-05-08 13:20:08 -04006250static void r3di_dsp_initial_mic_setup(struct hda_codec *codec)
6251{
6252 unsigned int tmp;
6253
6254 /* Mic 1 Setup */
6255 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6256 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6257 /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6258 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6259 tmp = FLOAT_ONE;
6260 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6261
6262 /* Mic 2 Setup, even though it isn't connected on SBZ */
6263 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6264 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6265 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6266 tmp = FLOAT_ZERO;
6267 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6268}
6269
6270/*
Connor McAdams38ba69f2018-05-08 13:20:07 -04006271 * Initialize Sound Blaster Z analog microphones.
6272 */
6273static void sbz_init_analog_mics(struct hda_codec *codec)
6274{
6275 unsigned int tmp;
6276
6277 /* Mic 1 Setup */
6278 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6279 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6280 tmp = FLOAT_THREE;
6281 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6282
6283 /* Mic 2 Setup, even though it isn't connected on SBZ */
6284 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6285 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6286 tmp = FLOAT_ZERO;
6287 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6288
6289}
6290
6291/*
6292 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6293 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6294 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6295 * having an updated DAC, which changes the destination to that DAC.
6296 */
6297static void sbz_connect_streams(struct hda_codec *codec)
6298{
6299 struct ca0132_spec *spec = codec->spec;
6300
6301 mutex_lock(&spec->chipio_mutex);
6302
6303 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6304
6305 chipio_set_stream_channels(codec, 0x0C, 6);
6306 chipio_set_stream_control(codec, 0x0C, 1);
6307
6308 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6309 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6310
6311 /* Setup stream 0x14 with it's source and destination points */
6312 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6313 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6314 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6315 chipio_set_stream_channels(codec, 0x14, 2);
6316 chipio_set_stream_control(codec, 0x14, 1);
6317
6318 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6319
6320 mutex_unlock(&spec->chipio_mutex);
6321
6322}
6323
6324/*
6325 * Write data through ChipIO to setup proper stream destinations.
6326 * Not sure how it exactly works, but it seems to direct data
6327 * to different destinations. Example is f8 to c0, e0 to c0.
6328 * All I know is, if you don't set these, you get no sound.
6329 */
6330static void sbz_chipio_startup_data(struct hda_codec *codec)
6331{
6332 struct ca0132_spec *spec = codec->spec;
6333
6334 mutex_lock(&spec->chipio_mutex);
6335 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6336
6337 /* These control audio output */
6338 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6339 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6340 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6341 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6342 /* Signal to update I think */
6343 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6344
6345 chipio_set_stream_channels(codec, 0x0C, 6);
6346 chipio_set_stream_control(codec, 0x0C, 1);
6347 /* No clue what these control */
6348 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6349 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6350 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6351 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6352 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6353 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6354 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6355 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6356 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6357 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6358 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6359 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6360
6361 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6362
6363 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6364 mutex_unlock(&spec->chipio_mutex);
6365}
6366
Connor McAdams447fd8e2018-05-08 13:20:09 -04006367/*
6368 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6369 * without a 0x20 source like normal.
6370 */
6371static void sbz_dsp_scp_startup(struct hda_codec *codec)
6372{
6373 unsigned int tmp;
6374
6375 tmp = 0x00000003;
6376 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6377
6378 tmp = 0x00000000;
6379 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6380
6381 tmp = 0x00000001;
6382 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6383
6384 tmp = 0x00000004;
6385 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6386
6387 tmp = 0x00000005;
6388 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6389
6390 tmp = 0x00000000;
6391 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6392
6393}
6394
Connor McAdams38ba69f2018-05-08 13:20:07 -04006395static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6396{
6397 unsigned int tmp;
6398
6399 chipio_set_stream_control(codec, 0x03, 0);
6400 chipio_set_stream_control(codec, 0x04, 0);
6401
6402 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6403 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6404
6405 tmp = FLOAT_THREE;
6406 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6407
6408 chipio_set_stream_control(codec, 0x03, 1);
6409 chipio_set_stream_control(codec, 0x04, 1);
6410
6411 chipio_write(codec, 0x18b098, 0x0000000c);
6412 chipio_write(codec, 0x18b09C, 0x0000000c);
6413}
6414
6415/*
Ian Minett5aaca442012-12-20 18:53:34 -08006416 * Setup default parameters for DSP
6417 */
6418static void ca0132_setup_defaults(struct hda_codec *codec)
6419{
Dylan Reide8f1bd52013-03-14 17:27:45 -07006420 struct ca0132_spec *spec = codec->spec;
Ian Minett5aaca442012-12-20 18:53:34 -08006421 unsigned int tmp;
6422 int num_fx;
6423 int idx, i;
6424
Dylan Reide8f1bd52013-03-14 17:27:45 -07006425 if (spec->dsp_state != DSP_DOWNLOADED)
Ian Minett5aaca442012-12-20 18:53:34 -08006426 return;
6427
6428 /* out, in effects + voicefx */
6429 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6430 for (idx = 0; idx < num_fx; idx++) {
6431 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6432 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6433 ca0132_effects[idx].reqs[i],
6434 ca0132_effects[idx].def_vals[i]);
6435 }
6436 }
6437
6438 /*remove DSP headroom*/
6439 tmp = FLOAT_ZERO;
6440 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6441
6442 /*set speaker EQ bypass attenuation*/
6443 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6444
6445 /* set AMic1 and AMic2 as mono mic */
6446 tmp = FLOAT_ONE;
6447 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6448 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6449
6450 /* set AMic1 as CrystalVoice input */
6451 tmp = FLOAT_ONE;
6452 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6453
6454 /* set WUH source */
6455 tmp = FLOAT_TWO;
6456 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6457}
6458
6459/*
Connor McAdams7e6ed622018-05-08 13:20:08 -04006460 * Setup default parameters for Recon3Di DSP.
6461 */
6462
6463static void r3di_setup_defaults(struct hda_codec *codec)
6464{
6465 struct ca0132_spec *spec = codec->spec;
6466 unsigned int tmp;
6467 int num_fx;
6468 int idx, i;
6469
6470 if (spec->dsp_state != DSP_DOWNLOADED)
6471 return;
6472
Connor McAdams447fd8e2018-05-08 13:20:09 -04006473 r3di_dsp_scp_startup(codec);
Connor McAdams7e6ed622018-05-08 13:20:08 -04006474
6475 r3di_dsp_initial_mic_setup(codec);
6476
6477 /*remove DSP headroom*/
6478 tmp = FLOAT_ZERO;
6479 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6480
6481 /* set WUH source */
6482 tmp = FLOAT_TWO;
6483 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6484 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6485
6486 /* Set speaker source? */
6487 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6488
6489 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6490
6491 /* Setup effect defaults */
6492 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6493 for (idx = 0; idx < num_fx; idx++) {
6494 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6495 dspio_set_uint_param(codec,
6496 ca0132_effects[idx].mid,
6497 ca0132_effects[idx].reqs[i],
6498 ca0132_effects[idx].def_vals[i]);
6499 }
6500 }
6501
6502}
6503
6504/*
Connor McAdams38ba69f2018-05-08 13:20:07 -04006505 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6506 * than the Chromebook setup.
6507 */
6508static void sbz_setup_defaults(struct hda_codec *codec)
6509{
6510 struct ca0132_spec *spec = codec->spec;
6511 unsigned int tmp, stream_format;
6512 int num_fx;
6513 int idx, i;
6514
6515 if (spec->dsp_state != DSP_DOWNLOADED)
6516 return;
6517
Connor McAdams447fd8e2018-05-08 13:20:09 -04006518 sbz_dsp_scp_startup(codec);
Connor McAdams38ba69f2018-05-08 13:20:07 -04006519
6520 sbz_init_analog_mics(codec);
6521
6522 sbz_connect_streams(codec);
6523
6524 sbz_chipio_startup_data(codec);
6525
6526 chipio_set_stream_control(codec, 0x03, 1);
6527 chipio_set_stream_control(codec, 0x04, 1);
6528
6529 /*
6530 * Sets internal input loopback to off, used to have a switch to
6531 * enable input loopback, but turned out to be way too buggy.
6532 */
6533 tmp = FLOAT_ONE;
6534 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6535 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6536
6537 /*remove DSP headroom*/
6538 tmp = FLOAT_ZERO;
6539 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6540
6541 /* set WUH source */
6542 tmp = FLOAT_TWO;
6543 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6544 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6545
6546 /* Set speaker source? */
6547 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6548
6549 sbz_dsp_initial_mic_setup(codec);
6550
6551
6552 /* out, in effects + voicefx */
6553 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6554 for (idx = 0; idx < num_fx; idx++) {
6555 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6556 dspio_set_uint_param(codec,
6557 ca0132_effects[idx].mid,
6558 ca0132_effects[idx].reqs[i],
6559 ca0132_effects[idx].def_vals[i]);
6560 }
6561 }
6562
6563 /*
6564 * Have to make a stream to bind the sound output to, otherwise
6565 * you'll get dead audio. Before I did this, it would bind to an
6566 * audio input, and would never work
6567 */
6568 stream_format = snd_hdac_calc_stream_format(48000, 2,
6569 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6570
6571 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6572 0, stream_format);
6573
6574 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6575
6576 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6577 0, stream_format);
6578
6579 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6580}
6581
6582/*
Ian Minett5aaca442012-12-20 18:53:34 -08006583 * Initialization of flags in chip
6584 */
6585static void ca0132_init_flags(struct hda_codec *codec)
6586{
Connor McAdams009b8f92018-05-08 13:20:06 -04006587 struct ca0132_spec *spec = codec->spec;
6588
6589 if (spec->use_alt_functions) {
6590 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6591 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6592 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6593 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6594 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6595 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6596 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6597 chipio_set_control_flag(codec,
6598 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6599 chipio_set_control_flag(codec,
6600 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6601 } else {
6602 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6603 chipio_set_control_flag(codec,
6604 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6605 chipio_set_control_flag(codec,
6606 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6607 chipio_set_control_flag(codec,
6608 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6609 chipio_set_control_flag(codec,
6610 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6611 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6612 }
Ian Minett5aaca442012-12-20 18:53:34 -08006613}
6614
6615/*
6616 * Initialization of parameters in chip
6617 */
6618static void ca0132_init_params(struct hda_codec *codec)
6619{
Connor McAdams009b8f92018-05-08 13:20:06 -04006620 struct ca0132_spec *spec = codec->spec;
6621
6622 if (spec->use_alt_functions) {
6623 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6624 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6625 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6626 chipio_set_control_param(codec, 0, 0);
6627 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6628 }
6629
Ian Minett5aaca442012-12-20 18:53:34 -08006630 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6631 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6632}
Ian Minett95c6e9c2011-06-15 15:35:17 -07006633
Ian Minette90f29e2012-12-20 18:53:39 -08006634static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6635{
6636 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6637 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6638 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6639 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6640 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6641 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6642
Ian Minett406261c2012-12-20 18:53:41 -08006643 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6644 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
Ian Minette90f29e2012-12-20 18:53:39 -08006645 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6646}
6647
6648static bool ca0132_download_dsp_images(struct hda_codec *codec)
6649{
6650 bool dsp_loaded = false;
Connor McAdams8a19bce2018-05-08 13:20:01 -04006651 struct ca0132_spec *spec = codec->spec;
Ian Minette90f29e2012-12-20 18:53:39 -08006652 const struct dsp_image_seg *dsp_os_image;
Takashi Iwai15e4ba62013-01-15 17:08:38 +01006653 const struct firmware *fw_entry;
Connor McAdams8a19bce2018-05-08 13:20:01 -04006654 /*
6655 * Alternate firmwares for different variants. The Recon3Di apparently
6656 * can use the default firmware, but I'll leave the option in case
6657 * it needs it again.
6658 */
6659 switch (spec->quirk) {
6660 case QUIRK_SBZ:
6661 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6662 codec->card->dev) != 0) {
6663 codec_dbg(codec, "SBZ alt firmware not detected. ");
6664 spec->alt_firmware_present = false;
6665 } else {
6666 codec_dbg(codec, "Sound Blaster Z firmware selected.");
6667 spec->alt_firmware_present = true;
6668 }
6669 break;
6670 case QUIRK_R3DI:
6671 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6672 codec->card->dev) != 0) {
6673 codec_dbg(codec, "Recon3Di alt firmware not detected.");
6674 spec->alt_firmware_present = false;
6675 } else {
6676 codec_dbg(codec, "Recon3Di firmware selected.");
6677 spec->alt_firmware_present = true;
6678 }
6679 break;
6680 default:
6681 spec->alt_firmware_present = false;
6682 break;
6683 }
6684 /*
6685 * Use default ctefx.bin if no alt firmware is detected, or if none
6686 * exists for your particular codec.
6687 */
6688 if (!spec->alt_firmware_present) {
6689 codec_dbg(codec, "Default firmware selected.");
6690 if (request_firmware(&fw_entry, EFX_FILE,
6691 codec->card->dev) != 0)
6692 return false;
6693 }
Ian Minette90f29e2012-12-20 18:53:39 -08006694
Takashi Iwai15e4ba62013-01-15 17:08:38 +01006695 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
Dylan Reidd1d28502013-03-14 17:27:44 -07006696 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
Takashi Iwaid9684bb2015-10-26 16:54:16 +01006697 codec_err(codec, "ca0132 DSP load image failed\n");
Dylan Reidd1d28502013-03-14 17:27:44 -07006698 goto exit_download;
6699 }
6700
Ian Minette90f29e2012-12-20 18:53:39 -08006701 dsp_loaded = dspload_wait_loaded(codec);
6702
Dylan Reidd1d28502013-03-14 17:27:44 -07006703exit_download:
Takashi Iwai15e4ba62013-01-15 17:08:38 +01006704 release_firmware(fw_entry);
6705
Ian Minette90f29e2012-12-20 18:53:39 -08006706 return dsp_loaded;
6707}
6708
6709static void ca0132_download_dsp(struct hda_codec *codec)
6710{
6711 struct ca0132_spec *spec = codec->spec;
6712
Takashi Iwai9a0869f2013-02-07 12:41:40 +01006713#ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6714 return; /* NOP */
6715#endif
Ian Minette90f29e2012-12-20 18:53:39 -08006716
Takashi Iwaie24aa0a2014-08-10 13:30:08 +02006717 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6718 return; /* don't retry failures */
6719
Dylan Reidb714a712013-03-14 17:27:46 -07006720 chipio_enable_clocks(codec);
Connor McAdamse93ac302018-05-08 13:20:05 -04006721 if (spec->dsp_state != DSP_DOWNLOADED) {
6722 spec->dsp_state = DSP_DOWNLOADING;
6723
6724 if (!ca0132_download_dsp_images(codec))
6725 spec->dsp_state = DSP_DOWNLOAD_FAILED;
6726 else
6727 spec->dsp_state = DSP_DOWNLOADED;
6728 }
Ian Minette90f29e2012-12-20 18:53:39 -08006729
Connor McAdams009b8f92018-05-08 13:20:06 -04006730 /* For codecs using alt functions, this is already done earlier */
6731 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
Ian Minette90f29e2012-12-20 18:53:39 -08006732 ca0132_set_dsp_msr(codec, true);
6733}
6734
Takashi Iwaif8fb1172014-09-11 15:53:26 +02006735static void ca0132_process_dsp_response(struct hda_codec *codec,
6736 struct hda_jack_callback *callback)
Ian Minette90f29e2012-12-20 18:53:39 -08006737{
6738 struct ca0132_spec *spec = codec->spec;
6739
Takashi Iwai4e76a882014-02-25 12:21:03 +01006740 codec_dbg(codec, "ca0132_process_dsp_response\n");
Ian Minette90f29e2012-12-20 18:53:39 -08006741 if (spec->wait_scp) {
6742 if (dspio_get_response_data(codec) >= 0)
6743 spec->wait_scp = 0;
6744 }
6745
6746 dspio_clear_response_queue(codec);
6747}
6748
Takashi Iwaif8fb1172014-09-11 15:53:26 +02006749static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
Ian Minette90f29e2012-12-20 18:53:39 -08006750{
Chih-Chung Chang993884f2013-03-25 10:39:23 -07006751 struct ca0132_spec *spec = codec->spec;
Takashi Iwai2ebab402016-02-09 10:23:52 +01006752 struct hda_jack_tbl *tbl;
Ian Minette90f29e2012-12-20 18:53:39 -08006753
Takashi Iwaif8fb1172014-09-11 15:53:26 +02006754 /* Delay enabling the HP amp, to let the mic-detection
6755 * state machine run.
6756 */
6757 cancel_delayed_work_sync(&spec->unsol_hp_work);
Takashi Iwai2f35c632015-02-27 22:43:26 +01006758 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
Takashi Iwai2ebab402016-02-09 10:23:52 +01006759 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6760 if (tbl)
6761 tbl->block_report = 1;
Takashi Iwaif8fb1172014-09-11 15:53:26 +02006762}
Ian Minette90f29e2012-12-20 18:53:39 -08006763
Takashi Iwaif8fb1172014-09-11 15:53:26 +02006764static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6765{
Connor McAdamsa1b7f012018-08-08 13:34:14 -04006766 struct ca0132_spec *spec = codec->spec;
6767
6768 if (spec->use_alt_functions)
6769 ca0132_alt_select_in(codec);
6770 else
6771 ca0132_select_mic(codec);
Takashi Iwaif8fb1172014-09-11 15:53:26 +02006772}
6773
6774static void ca0132_init_unsol(struct hda_codec *codec)
6775{
Gabriele Martinod5c016b2015-05-18 21:15:13 +02006776 struct ca0132_spec *spec = codec->spec;
6777 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6778 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
Takashi Iwaif8fb1172014-09-11 15:53:26 +02006779 amic_callback);
6780 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6781 ca0132_process_dsp_response);
Connor McAdams63177af2018-05-08 13:20:02 -04006782 /* Front headphone jack detection */
Connor McAdams009b8f92018-05-08 13:20:06 -04006783 if (spec->use_alt_functions)
Connor McAdams63177af2018-05-08 13:20:02 -04006784 snd_hda_jack_detect_enable_callback(codec,
6785 spec->unsol_tag_front_hp, hp_callback);
Ian Minette90f29e2012-12-20 18:53:39 -08006786}
6787
Ian Minett5aaca442012-12-20 18:53:34 -08006788/*
6789 * Verbs tables.
6790 */
6791
6792/* Sends before DSP download. */
6793static struct hda_verb ca0132_base_init_verbs[] = {
6794 /*enable ct extension*/
6795 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
Ian Minett5aaca442012-12-20 18:53:34 -08006796 {}
6797};
6798
6799/* Send at exit. */
6800static struct hda_verb ca0132_base_exit_verbs[] = {
6801 /*set afg to D3*/
6802 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6803 /*disable ct extension*/
6804 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6805 {}
6806};
6807
Connor McAdams8a19bce2018-05-08 13:20:01 -04006808/* Other verbs tables. Sends after DSP download. */
Connor McAdamse93ac302018-05-08 13:20:05 -04006809
Ian Minett5aaca442012-12-20 18:53:34 -08006810static struct hda_verb ca0132_init_verbs0[] = {
6811 /* chip init verbs */
6812 {0x15, 0x70D, 0xF0},
6813 {0x15, 0x70E, 0xFE},
6814 {0x15, 0x707, 0x75},
6815 {0x15, 0x707, 0xD3},
6816 {0x15, 0x707, 0x09},
6817 {0x15, 0x707, 0x53},
6818 {0x15, 0x707, 0xD4},
6819 {0x15, 0x707, 0xEF},
6820 {0x15, 0x707, 0x75},
6821 {0x15, 0x707, 0xD3},
6822 {0x15, 0x707, 0x09},
6823 {0x15, 0x707, 0x02},
6824 {0x15, 0x707, 0x37},
6825 {0x15, 0x707, 0x78},
6826 {0x15, 0x53C, 0xCE},
6827 {0x15, 0x575, 0xC9},
6828 {0x15, 0x53D, 0xCE},
6829 {0x15, 0x5B7, 0xC9},
6830 {0x15, 0x70D, 0xE8},
6831 {0x15, 0x70E, 0xFE},
6832 {0x15, 0x707, 0x02},
6833 {0x15, 0x707, 0x68},
6834 {0x15, 0x707, 0x62},
6835 {0x15, 0x53A, 0xCE},
6836 {0x15, 0x546, 0xC9},
6837 {0x15, 0x53B, 0xCE},
6838 {0x15, 0x5E8, 0xC9},
Connor McAdamse93ac302018-05-08 13:20:05 -04006839 {}
6840};
6841
Connor McAdamse42c7c72018-08-08 13:34:18 -04006842/* Extra init verbs for desktop cards. */
6843static struct hda_verb ca0132_init_verbs1[] = {
Connor McAdamse93ac302018-05-08 13:20:05 -04006844 {0x15, 0x70D, 0x20},
6845 {0x15, 0x70E, 0x19},
6846 {0x15, 0x707, 0x00},
6847 {0x15, 0x539, 0xCE},
6848 {0x15, 0x546, 0xC9},
6849 {0x15, 0x70D, 0xB7},
6850 {0x15, 0x70E, 0x09},
6851 {0x15, 0x707, 0x10},
6852 {0x15, 0x70D, 0xAF},
6853 {0x15, 0x70E, 0x09},
6854 {0x15, 0x707, 0x01},
6855 {0x15, 0x707, 0x05},
6856 {0x15, 0x70D, 0x73},
6857 {0x15, 0x70E, 0x09},
6858 {0x15, 0x707, 0x14},
6859 {0x15, 0x6FF, 0xC4},
Ian Minett5aaca442012-12-20 18:53:34 -08006860 {}
6861};
6862
Ian Minett95c6e9c2011-06-15 15:35:17 -07006863static void ca0132_init_chip(struct hda_codec *codec)
6864{
6865 struct ca0132_spec *spec = codec->spec;
Ian Minett5aaca442012-12-20 18:53:34 -08006866 int num_fx;
6867 int i;
6868 unsigned int on;
Ian Minett95c6e9c2011-06-15 15:35:17 -07006869
6870 mutex_init(&spec->chipio_mutex);
Ian Minett5aaca442012-12-20 18:53:34 -08006871
6872 spec->cur_out_type = SPEAKER_OUT;
Connor McAdams7cb9d942018-05-08 13:20:10 -04006873 if (!spec->use_alt_functions)
6874 spec->cur_mic_type = DIGITAL_MIC;
6875 else
6876 spec->cur_mic_type = REAR_MIC;
6877
Ian Minett5aaca442012-12-20 18:53:34 -08006878 spec->cur_mic_boost = 0;
6879
6880 for (i = 0; i < VNODES_COUNT; i++) {
6881 spec->vnode_lvol[i] = 0x5a;
6882 spec->vnode_rvol[i] = 0x5a;
6883 spec->vnode_lswitch[i] = 0;
6884 spec->vnode_rswitch[i] = 0;
6885 }
6886
6887 /*
6888 * Default states for effects are in ca0132_effects[].
6889 */
6890 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6891 for (i = 0; i < num_fx; i++) {
6892 on = (unsigned int)ca0132_effects[i].reqs[0];
6893 spec->effects_switch[i] = on ? 1 : 0;
6894 }
Connor McAdams47cdf762018-05-08 13:20:13 -04006895 /*
6896 * Sets defaults for the effect slider controls, only for alternative
6897 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6898 */
6899 if (spec->use_alt_controls) {
6900 spec->xbass_xover_freq = 8;
6901 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6902 spec->fx_ctl_val[i] = effect_slider_defaults[i];
6903 }
Ian Minett5aaca442012-12-20 18:53:34 -08006904
6905 spec->voicefx_val = 0;
6906 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6907 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6908
Ian Minett44f0c972012-12-20 18:53:38 -08006909#ifdef ENABLE_TUNING_CONTROLS
6910 ca0132_init_tuning_defaults(codec);
6911#endif
Ian Minett95c6e9c2011-06-15 15:35:17 -07006912}
6913
Connor McAdams2e48b2b2018-05-08 13:20:04 -04006914/*
6915 * Recon3Di exit specific commands.
6916 */
6917/* prevents popping noise on shutdown */
6918static void r3di_gpio_shutdown(struct hda_codec *codec)
6919{
6920 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6921}
6922
6923/*
6924 * Sound Blaster Z exit specific commands.
6925 */
6926static void sbz_region2_exit(struct hda_codec *codec)
6927{
6928 struct ca0132_spec *spec = codec->spec;
6929 unsigned int i;
6930
6931 for (i = 0; i < 4; i++)
6932 writeb(0x0, spec->mem_base + 0x100);
6933 for (i = 0; i < 8; i++)
6934 writeb(0xb3, spec->mem_base + 0x304);
Connor McAdamsa62e4732018-08-08 13:34:12 -04006935
6936 ca0132_mmio_gpio_set(codec, 0, false);
6937 ca0132_mmio_gpio_set(codec, 1, false);
6938 ca0132_mmio_gpio_set(codec, 4, true);
6939 ca0132_mmio_gpio_set(codec, 5, false);
6940 ca0132_mmio_gpio_set(codec, 7, false);
Connor McAdams2e48b2b2018-05-08 13:20:04 -04006941}
6942
6943static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6944{
6945 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6946 unsigned int i;
6947
6948 snd_hda_codec_write(codec, 0x11, 0,
6949 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6950
6951 for (i = 0; i < 5; i++)
6952 snd_hda_codec_write(codec, pins[i], 0,
6953 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6954}
6955
6956static void sbz_clear_unsolicited(struct hda_codec *codec)
6957{
6958 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6959 unsigned int i;
6960
6961 for (i = 0; i < 7; i++) {
6962 snd_hda_codec_write(codec, pins[i], 0,
6963 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6964 }
6965}
6966
6967/* On shutdown, sends commands in sets of three */
6968static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6969 int mask, int data)
6970{
6971 if (dir >= 0)
6972 snd_hda_codec_write(codec, 0x01, 0,
6973 AC_VERB_SET_GPIO_DIRECTION, dir);
6974 if (mask >= 0)
6975 snd_hda_codec_write(codec, 0x01, 0,
6976 AC_VERB_SET_GPIO_MASK, mask);
6977
6978 if (data >= 0)
6979 snd_hda_codec_write(codec, 0x01, 0,
6980 AC_VERB_SET_GPIO_DATA, data);
6981}
6982
6983static void sbz_exit_chip(struct hda_codec *codec)
6984{
Connor McAdams009b8f92018-05-08 13:20:06 -04006985 chipio_set_stream_control(codec, 0x03, 0);
6986 chipio_set_stream_control(codec, 0x04, 0);
Connor McAdams2e48b2b2018-05-08 13:20:04 -04006987
6988 /* Mess with GPIO */
6989 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
6990 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
6991 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
6992
Connor McAdams009b8f92018-05-08 13:20:06 -04006993 chipio_set_stream_control(codec, 0x14, 0);
6994 chipio_set_stream_control(codec, 0x0C, 0);
Connor McAdams2e48b2b2018-05-08 13:20:04 -04006995
6996 chipio_set_conn_rate(codec, 0x41, SR_192_000);
6997 chipio_set_conn_rate(codec, 0x91, SR_192_000);
6998
6999 chipio_write(codec, 0x18a020, 0x00000083);
7000
7001 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7002 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7003 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7004
Connor McAdams009b8f92018-05-08 13:20:06 -04007005 chipio_set_stream_control(codec, 0x0C, 0);
Connor McAdams2e48b2b2018-05-08 13:20:04 -04007006
7007 chipio_set_control_param(codec, 0x0D, 0x24);
7008
7009 sbz_clear_unsolicited(codec);
7010 sbz_set_pin_ctl_default(codec);
7011
7012 snd_hda_codec_write(codec, 0x0B, 0,
7013 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7014
7015 if (dspload_is_loaded(codec))
7016 dsp_reset(codec);
7017
7018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7019 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x00);
7020
7021 sbz_region2_exit(codec);
7022}
7023
Ian Minett95c6e9c2011-06-15 15:35:17 -07007024static void ca0132_exit_chip(struct hda_codec *codec)
7025{
7026 /* put any chip cleanup stuffs here. */
Ian Minett5aaca442012-12-20 18:53:34 -08007027
7028 if (dspload_is_loaded(codec))
7029 dsp_reset(codec);
Ian Minett95c6e9c2011-06-15 15:35:17 -07007030}
7031
Connor McAdamse93ac302018-05-08 13:20:05 -04007032/*
Connor McAdams38ba69f2018-05-08 13:20:07 -04007033 * This fixes a problem that was hard to reproduce. Very rarely, I would
7034 * boot up, and there would be no sound, but the DSP indicated it had loaded
7035 * properly. I did a few memory dumps to see if anything was different, and
7036 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7037 * checks if those areas are uninitialized, and if they are, it'll attempt to
7038 * reload the card 3 times. Usually it fixes by the second.
7039 */
7040static void sbz_dsp_startup_check(struct hda_codec *codec)
7041{
7042 struct ca0132_spec *spec = codec->spec;
7043 unsigned int dsp_data_check[4];
7044 unsigned int cur_address = 0x390;
7045 unsigned int i;
7046 unsigned int failure = 0;
7047 unsigned int reload = 3;
7048
7049 if (spec->startup_check_entered)
7050 return;
7051
7052 spec->startup_check_entered = true;
7053
7054 for (i = 0; i < 4; i++) {
7055 chipio_read(codec, cur_address, &dsp_data_check[i]);
7056 cur_address += 0x4;
7057 }
7058 for (i = 0; i < 4; i++) {
7059 if (dsp_data_check[i] == 0xa1a2a3a4)
7060 failure = 1;
7061 }
7062
7063 codec_dbg(codec, "Startup Check: %d ", failure);
7064 if (failure)
7065 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7066 /*
7067 * While the failure condition is true, and we haven't reached our
7068 * three reload limit, continue trying to reload the driver and
7069 * fix the issue.
7070 */
7071 while (failure && (reload != 0)) {
7072 codec_info(codec, "Reloading... Tries left: %d", reload);
7073 sbz_exit_chip(codec);
7074 spec->dsp_state = DSP_DOWNLOAD_INIT;
7075 codec->patch_ops.init(codec);
7076 failure = 0;
7077 for (i = 0; i < 4; i++) {
7078 chipio_read(codec, cur_address, &dsp_data_check[i]);
7079 cur_address += 0x4;
7080 }
7081 for (i = 0; i < 4; i++) {
7082 if (dsp_data_check[i] == 0xa1a2a3a4)
7083 failure = 1;
7084 }
7085 reload--;
7086 }
7087
7088 if (!failure && reload < 3)
7089 codec_info(codec, "DSP fixed.");
7090
7091 if (!failure)
7092 return;
7093
7094 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7095}
7096
7097/*
Connor McAdamse93ac302018-05-08 13:20:05 -04007098 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7099 * extra precision for decibel values. If you had the dB value in floating point
7100 * you would take the value after the decimal point, multiply by 64, and divide
7101 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7102 * implement fixed point or floating point dB volumes. For now, I'll set them
7103 * to 0 just incase a value has lingered from a boot into Windows.
7104 */
7105static void ca0132_alt_vol_setup(struct hda_codec *codec)
7106{
7107 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7108 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7109 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7110 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7111 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7112 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7113 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7114 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7115}
7116
7117/*
7118 * Extra commands that don't really fit anywhere else.
7119 */
7120static void sbz_pre_dsp_setup(struct hda_codec *codec)
7121{
7122 struct ca0132_spec *spec = codec->spec;
7123
7124 writel(0x00820680, spec->mem_base + 0x01C);
7125 writel(0x00820680, spec->mem_base + 0x01C);
7126
7127 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7128 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7129 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7130 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7131
7132 chipio_write(codec, 0x18b0a4, 0x000000c2);
7133
7134 snd_hda_codec_write(codec, 0x11, 0,
7135 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7136}
7137
Connor McAdamse42c7c72018-08-08 13:34:18 -04007138static void r3d_pre_dsp_setup(struct hda_codec *codec)
7139{
7140
7141 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7142 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7143 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7144 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7145
7146 chipio_write(codec, 0x18b0a4, 0x000000c2);
7147
7148 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7149 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7150 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7151 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7152 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7153 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7154
7155 snd_hda_codec_write(codec, 0x11, 0,
7156 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7157}
7158
Connor McAdamse93ac302018-05-08 13:20:05 -04007159static void r3di_pre_dsp_setup(struct hda_codec *codec)
7160{
7161 chipio_write(codec, 0x18b0a4, 0x000000c2);
7162
7163 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7164 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7165 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7166 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7167 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7168 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7169
7170 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7171 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7172 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7173 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7174 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7175 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7176 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7177 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7178
7179 snd_hda_codec_write(codec, 0x11, 0,
7180 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7181}
7182
Connor McAdamse93ac302018-05-08 13:20:05 -04007183/*
7184 * These are sent before the DSP is downloaded. Not sure
7185 * what they do, or if they're necessary. Could possibly
7186 * be removed. Figure they're better to leave in.
7187 */
Connor McAdamse42c7c72018-08-08 13:34:18 -04007188static void ca0132_mmio_init(struct hda_codec *codec)
Connor McAdamse93ac302018-05-08 13:20:05 -04007189{
7190 struct ca0132_spec *spec = codec->spec;
7191
7192 writel(0x00000000, spec->mem_base + 0x400);
7193 writel(0x00000000, spec->mem_base + 0x408);
7194 writel(0x00000000, spec->mem_base + 0x40C);
7195 writel(0x00880680, spec->mem_base + 0x01C);
7196 writel(0x00000083, spec->mem_base + 0xC0C);
7197 writel(0x00000030, spec->mem_base + 0xC00);
7198 writel(0x00000000, spec->mem_base + 0xC04);
7199 writel(0x00000003, spec->mem_base + 0xC0C);
7200 writel(0x00000003, spec->mem_base + 0xC0C);
7201 writel(0x00000003, spec->mem_base + 0xC0C);
7202 writel(0x00000003, spec->mem_base + 0xC0C);
7203 writel(0x000000C1, spec->mem_base + 0xC08);
7204 writel(0x000000F1, spec->mem_base + 0xC08);
7205 writel(0x00000001, spec->mem_base + 0xC08);
7206 writel(0x000000C7, spec->mem_base + 0xC08);
7207 writel(0x000000C1, spec->mem_base + 0xC08);
7208 writel(0x00000080, spec->mem_base + 0xC04);
7209}
7210
7211/*
7212 * Extra init functions for alternative ca0132 codecs. Done
7213 * here so they don't clutter up the main ca0132_init function
7214 * anymore than they have to.
7215 */
7216static void ca0132_alt_init(struct hda_codec *codec)
7217{
7218 struct ca0132_spec *spec = codec->spec;
7219
7220 ca0132_alt_vol_setup(codec);
7221
7222 switch (spec->quirk) {
7223 case QUIRK_SBZ:
7224 codec_dbg(codec, "SBZ alt_init");
7225 ca0132_gpio_init(codec);
7226 sbz_pre_dsp_setup(codec);
7227 snd_hda_sequence_write(codec, spec->chip_init_verbs);
Connor McAdamse42c7c72018-08-08 13:34:18 -04007228 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
Connor McAdamse93ac302018-05-08 13:20:05 -04007229 break;
7230 case QUIRK_R3DI:
7231 codec_dbg(codec, "R3DI alt_init");
7232 ca0132_gpio_init(codec);
7233 ca0132_gpio_setup(codec);
Connor McAdams7e6ed622018-05-08 13:20:08 -04007234 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
Connor McAdamse93ac302018-05-08 13:20:05 -04007235 r3di_pre_dsp_setup(codec);
7236 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7237 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7238 break;
Connor McAdamse42c7c72018-08-08 13:34:18 -04007239 case QUIRK_R3D:
7240 r3d_pre_dsp_setup(codec);
7241 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7242 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7243 break;
Connor McAdamse93ac302018-05-08 13:20:05 -04007244 }
7245}
7246
Ian Minett95c6e9c2011-06-15 15:35:17 -07007247static int ca0132_init(struct hda_codec *codec)
7248{
7249 struct ca0132_spec *spec = codec->spec;
7250 struct auto_pin_cfg *cfg = &spec->autocfg;
7251 int i;
Connor McAdamse93ac302018-05-08 13:20:05 -04007252 bool dsp_loaded;
7253
7254 /*
7255 * If the DSP is already downloaded, and init has been entered again,
7256 * there's only two reasons for it. One, the codec has awaken from a
7257 * suspended state, and in that case dspload_is_loaded will return
7258 * false, and the init will be ran again. The other reason it gets
7259 * re entered is on startup for some reason it triggers a suspend and
7260 * resume state. In this case, it will check if the DSP is downloaded,
7261 * and not run the init function again. For codecs using alt_functions,
7262 * it will check if the DSP is loaded properly.
7263 */
7264 if (spec->dsp_state == DSP_DOWNLOADED) {
7265 dsp_loaded = dspload_is_loaded(codec);
7266 if (!dsp_loaded) {
7267 spec->dsp_reload = true;
7268 spec->dsp_state = DSP_DOWNLOAD_INIT;
Connor McAdams38ba69f2018-05-08 13:20:07 -04007269 } else {
7270 if (spec->quirk == QUIRK_SBZ)
7271 sbz_dsp_startup_check(codec);
Connor McAdamse93ac302018-05-08 13:20:05 -04007272 return 0;
Connor McAdams38ba69f2018-05-08 13:20:07 -04007273 }
Connor McAdamse93ac302018-05-08 13:20:05 -04007274 }
Ian Minett95c6e9c2011-06-15 15:35:17 -07007275
Takashi Iwaie24aa0a2014-08-10 13:30:08 +02007276 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7277 spec->dsp_state = DSP_DOWNLOAD_INIT;
Takashi Iwai4a8b89f2013-02-12 10:15:15 +01007278 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
Ian Minett5aaca442012-12-20 18:53:34 -08007279
Connor McAdamse42c7c72018-08-08 13:34:18 -04007280 if (spec->use_pci_mmio)
7281 ca0132_mmio_init(codec);
Connor McAdamse93ac302018-05-08 13:20:05 -04007282
Takashi Iwai664c7152015-04-08 11:43:14 +02007283 snd_hda_power_up_pm(codec);
Ian Minett5aaca442012-12-20 18:53:34 -08007284
Takashi Iwaif8fb1172014-09-11 15:53:26 +02007285 ca0132_init_unsol(codec);
Ian Minett5aaca442012-12-20 18:53:34 -08007286 ca0132_init_params(codec);
7287 ca0132_init_flags(codec);
Connor McAdams7e6ed622018-05-08 13:20:08 -04007288
Ian Minett5aaca442012-12-20 18:53:34 -08007289 snd_hda_sequence_write(codec, spec->base_init_verbs);
Connor McAdamse93ac302018-05-08 13:20:05 -04007290
Alastair Bridgewater365c7f22018-06-15 21:56:17 -04007291 if (spec->use_alt_functions)
Connor McAdamse93ac302018-05-08 13:20:05 -04007292 ca0132_alt_init(codec);
7293
Ian Minett01ef7db2012-09-20 20:29:16 -07007294 ca0132_download_dsp(codec);
Connor McAdams7e6ed622018-05-08 13:20:08 -04007295
Ian Minett5aaca442012-12-20 18:53:34 -08007296 ca0132_refresh_widget_caps(codec);
Connor McAdamse93ac302018-05-08 13:20:05 -04007297
Connor McAdams7e6ed622018-05-08 13:20:08 -04007298 switch (spec->quirk) {
7299 case QUIRK_R3DI:
7300 r3di_setup_defaults(codec);
7301 break;
Alastair Bridgewater126b75e2018-06-15 21:56:18 -04007302 case QUIRK_SBZ:
Connor McAdamsd97420d2018-08-08 13:34:13 -04007303 sbz_setup_defaults(codec);
Alastair Bridgewater126b75e2018-06-15 21:56:18 -04007304 break;
7305 default:
Connor McAdams38ba69f2018-05-08 13:20:07 -04007306 ca0132_setup_defaults(codec);
7307 ca0132_init_analog_mic2(codec);
7308 ca0132_init_dmic(codec);
Connor McAdams7e6ed622018-05-08 13:20:08 -04007309 break;
Connor McAdams38ba69f2018-05-08 13:20:07 -04007310 }
Ian Minett01ef7db2012-09-20 20:29:16 -07007311
Ian Minett5aaca442012-12-20 18:53:34 -08007312 for (i = 0; i < spec->num_outputs; i++)
7313 init_output(codec, spec->out_pins[i], spec->dacs[0]);
7314
Ian Minett95c6e9c2011-06-15 15:35:17 -07007315 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7316
7317 for (i = 0; i < spec->num_inputs; i++)
7318 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7319
7320 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7321
Connor McAdams009b8f92018-05-08 13:20:06 -04007322 if (!spec->use_alt_functions) {
Connor McAdamse93ac302018-05-08 13:20:05 -04007323 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7324 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7325 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7326 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7327 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7328 }
7329
Connor McAdams7cb9d942018-05-08 13:20:10 -04007330 if (spec->quirk == QUIRK_SBZ)
Connor McAdamse93ac302018-05-08 13:20:05 -04007331 ca0132_gpio_setup(codec);
7332
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007333 snd_hda_sequence_write(codec, spec->spec_init_verbs);
Connor McAdamsd97420d2018-08-08 13:34:13 -04007334 if (spec->use_alt_functions) {
Connor McAdams7cb9d942018-05-08 13:20:10 -04007335 ca0132_alt_select_out(codec);
7336 ca0132_alt_select_in(codec);
Connor McAdamsd97420d2018-08-08 13:34:13 -04007337 } else {
Connor McAdams7cb9d942018-05-08 13:20:10 -04007338 ca0132_select_out(codec);
7339 ca0132_select_mic(codec);
Connor McAdams7cb9d942018-05-08 13:20:10 -04007340 }
Ian Minett5aaca442012-12-20 18:53:34 -08007341
Ian Minetta73d5112012-12-20 18:53:37 -08007342 snd_hda_jack_report_sync(codec);
7343
Connor McAdamse93ac302018-05-08 13:20:05 -04007344 /*
7345 * Re set the PlayEnhancement switch on a resume event, because the
7346 * controls will not be reloaded.
7347 */
7348 if (spec->dsp_reload) {
7349 spec->dsp_reload = false;
7350 ca0132_pe_switch_set(codec);
7351 }
7352
Takashi Iwai664c7152015-04-08 11:43:14 +02007353 snd_hda_power_down_pm(codec);
Ian Minett95c6e9c2011-06-15 15:35:17 -07007354
7355 return 0;
7356}
7357
Ian Minett95c6e9c2011-06-15 15:35:17 -07007358static void ca0132_free(struct hda_codec *codec)
7359{
Ian Minett5aaca442012-12-20 18:53:34 -08007360 struct ca0132_spec *spec = codec->spec;
7361
Chih-Chung Chang993884f2013-03-25 10:39:23 -07007362 cancel_delayed_work_sync(&spec->unsol_hp_work);
Ian Minett5aaca442012-12-20 18:53:34 -08007363 snd_hda_power_up(codec);
Connor McAdams2e48b2b2018-05-08 13:20:04 -04007364 switch (spec->quirk) {
7365 case QUIRK_SBZ:
7366 sbz_exit_chip(codec);
7367 break;
7368 case QUIRK_R3DI:
7369 r3di_gpio_shutdown(codec);
7370 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7371 ca0132_exit_chip(codec);
7372 break;
7373 default:
7374 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7375 ca0132_exit_chip(codec);
7376 break;
7377 }
Ian Minett5aaca442012-12-20 18:53:34 -08007378 snd_hda_power_down(codec);
Connor McAdamsaa317042018-05-08 13:20:03 -04007379 if (spec->mem_base)
7380 iounmap(spec->mem_base);
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007381 kfree(spec->spec_init_verbs);
Ian Minett95c6e9c2011-06-15 15:35:17 -07007382 kfree(codec->spec);
7383}
7384
Connor McAdams2e48b2b2018-05-08 13:20:04 -04007385static void ca0132_reboot_notify(struct hda_codec *codec)
7386{
7387 codec->patch_ops.free(codec);
7388}
7389
Julia Lawall071f1342016-09-11 15:05:43 +02007390static const struct hda_codec_ops ca0132_patch_ops = {
Ian Minett95c6e9c2011-06-15 15:35:17 -07007391 .build_controls = ca0132_build_controls,
7392 .build_pcms = ca0132_build_pcms,
7393 .init = ca0132_init,
7394 .free = ca0132_free,
Takashi Iwaif8fb1172014-09-11 15:53:26 +02007395 .unsol_event = snd_hda_jack_unsol_event,
Connor McAdams2e48b2b2018-05-08 13:20:04 -04007396 .reboot_notify = ca0132_reboot_notify,
Ian Minett95c6e9c2011-06-15 15:35:17 -07007397};
7398
Ian Minett441aa6a2012-12-20 18:53:40 -08007399static void ca0132_config(struct hda_codec *codec)
7400{
7401 struct ca0132_spec *spec = codec->spec;
Ian Minett441aa6a2012-12-20 18:53:40 -08007402
7403 spec->dacs[0] = 0x2;
7404 spec->dacs[1] = 0x3;
7405 spec->dacs[2] = 0x4;
7406
7407 spec->multiout.dac_nids = spec->dacs;
7408 spec->multiout.num_dacs = 3;
Ian Minett441aa6a2012-12-20 18:53:40 -08007409
Connor McAdams009b8f92018-05-08 13:20:06 -04007410 if (!spec->use_alt_functions)
Connor McAdams63177af2018-05-08 13:20:02 -04007411 spec->multiout.max_channels = 2;
7412 else
7413 spec->multiout.max_channels = 6;
7414
7415 switch (spec->quirk) {
7416 case QUIRK_ALIENWARE:
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007417 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
Takashi Iwaife14f392015-08-10 16:53:32 +02007418 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7419
7420 spec->num_outputs = 2;
7421 spec->out_pins[0] = 0x0b; /* speaker out */
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007422 spec->out_pins[1] = 0x0f;
Takashi Iwaife14f392015-08-10 16:53:32 +02007423 spec->shared_out_nid = 0x2;
7424 spec->unsol_tag_hp = 0x0f;
7425
7426 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7427 spec->adcs[1] = 0x8; /* analog mic2 */
7428 spec->adcs[2] = 0xa; /* what u hear */
7429
7430 spec->num_inputs = 3;
7431 spec->input_pins[0] = 0x12;
7432 spec->input_pins[1] = 0x11;
7433 spec->input_pins[2] = 0x13;
7434 spec->shared_mic_nid = 0x7;
7435 spec->unsol_tag_amic1 = 0x11;
Connor McAdams63177af2018-05-08 13:20:02 -04007436 break;
7437 case QUIRK_SBZ:
Connor McAdams7f73df92018-08-08 13:34:16 -04007438 case QUIRK_R3D:
7439 if (spec->quirk == QUIRK_SBZ) {
7440 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7441 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7442 }
7443 if (spec->quirk == QUIRK_R3D) {
7444 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7445 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7446 }
Connor McAdams63177af2018-05-08 13:20:02 -04007447
7448 spec->num_outputs = 2;
7449 spec->out_pins[0] = 0x0B; /* Line out */
7450 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7451 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7452 spec->out_pins[3] = 0x11; /* Rear surround */
7453 spec->shared_out_nid = 0x2;
7454 spec->unsol_tag_hp = spec->out_pins[1];
7455 spec->unsol_tag_front_hp = spec->out_pins[2];
7456
7457 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7458 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7459 spec->adcs[2] = 0xa; /* what u hear */
7460
7461 spec->num_inputs = 2;
7462 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7463 spec->input_pins[1] = 0x13; /* What U Hear */
7464 spec->shared_mic_nid = 0x7;
7465 spec->unsol_tag_amic1 = spec->input_pins[0];
7466
7467 /* SPDIF I/O */
7468 spec->dig_out = 0x05;
7469 spec->multiout.dig_out_nid = spec->dig_out;
Connor McAdams63177af2018-05-08 13:20:02 -04007470 spec->dig_in = 0x09;
Connor McAdams63177af2018-05-08 13:20:02 -04007471 break;
7472 case QUIRK_R3DI:
7473 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7474 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7475
7476 spec->num_outputs = 2;
7477 spec->out_pins[0] = 0x0B; /* Line out */
7478 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7479 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7480 spec->out_pins[3] = 0x11; /* Rear surround */
7481 spec->shared_out_nid = 0x2;
7482 spec->unsol_tag_hp = spec->out_pins[1];
7483 spec->unsol_tag_front_hp = spec->out_pins[2];
7484
7485 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7486 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7487 spec->adcs[2] = 0x0a; /* what u hear */
7488
7489 spec->num_inputs = 2;
7490 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7491 spec->input_pins[1] = 0x13; /* What U Hear */
7492 spec->shared_mic_nid = 0x7;
7493 spec->unsol_tag_amic1 = spec->input_pins[0];
7494
7495 /* SPDIF I/O */
7496 spec->dig_out = 0x05;
7497 spec->multiout.dig_out_nid = spec->dig_out;
Connor McAdams63177af2018-05-08 13:20:02 -04007498 break;
7499 default:
Takashi Iwaife14f392015-08-10 16:53:32 +02007500 spec->num_outputs = 2;
7501 spec->out_pins[0] = 0x0b; /* speaker out */
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007502 spec->out_pins[1] = 0x10; /* headphone out */
Takashi Iwaife14f392015-08-10 16:53:32 +02007503 spec->shared_out_nid = 0x2;
7504 spec->unsol_tag_hp = spec->out_pins[1];
7505
7506 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7507 spec->adcs[1] = 0x8; /* analog mic2 */
7508 spec->adcs[2] = 0xa; /* what u hear */
7509
7510 spec->num_inputs = 3;
7511 spec->input_pins[0] = 0x12;
7512 spec->input_pins[1] = 0x11;
7513 spec->input_pins[2] = 0x13;
7514 spec->shared_mic_nid = 0x7;
7515 spec->unsol_tag_amic1 = spec->input_pins[0];
7516
7517 /* SPDIF I/O */
7518 spec->dig_out = 0x05;
7519 spec->multiout.dig_out_nid = spec->dig_out;
Takashi Iwaife14f392015-08-10 16:53:32 +02007520 spec->dig_in = 0x09;
Connor McAdams63177af2018-05-08 13:20:02 -04007521 break;
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007522 }
Ian Minett441aa6a2012-12-20 18:53:40 -08007523}
7524
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007525static int ca0132_prepare_verbs(struct hda_codec *codec)
7526{
7527/* Verbs + terminator (an empty element) */
Alastair Bridgewatera3d90d62018-06-15 21:56:16 -04007528#define NUM_SPEC_VERBS 2
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007529 struct ca0132_spec *spec = codec->spec;
7530
7531 spec->chip_init_verbs = ca0132_init_verbs0;
Connor McAdamse42c7c72018-08-08 13:34:18 -04007532 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D)
7533 spec->desktop_init_verbs = ca0132_init_verbs1;
Kees Cook6396bb22018-06-12 14:03:40 -07007534 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7535 sizeof(struct hda_verb),
7536 GFP_KERNEL);
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007537 if (!spec->spec_init_verbs)
7538 return -ENOMEM;
7539
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007540 /* config EAPD */
Alastair Bridgewatera3d90d62018-06-15 21:56:16 -04007541 spec->spec_init_verbs[0].nid = 0x0b;
7542 spec->spec_init_verbs[0].param = 0x78D;
7543 spec->spec_init_verbs[0].verb = 0x00;
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007544
7545 /* Previously commented configuration */
7546 /*
Alastair Bridgewatera3d90d62018-06-15 21:56:16 -04007547 spec->spec_init_verbs[2].nid = 0x0b;
7548 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7549 spec->spec_init_verbs[2].verb = 0x02;
7550
7551 spec->spec_init_verbs[3].nid = 0x10;
7552 spec->spec_init_verbs[3].param = 0x78D;
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007553 spec->spec_init_verbs[3].verb = 0x02;
7554
7555 spec->spec_init_verbs[4].nid = 0x10;
Alastair Bridgewatera3d90d62018-06-15 21:56:16 -04007556 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007557 spec->spec_init_verbs[4].verb = 0x02;
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007558 */
7559
7560 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7561 return 0;
7562}
7563
Ian Minett95c6e9c2011-06-15 15:35:17 -07007564static int patch_ca0132(struct hda_codec *codec)
7565{
7566 struct ca0132_spec *spec;
Ian Minetta73d5112012-12-20 18:53:37 -08007567 int err;
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007568 const struct snd_pci_quirk *quirk;
Ian Minett95c6e9c2011-06-15 15:35:17 -07007569
Takashi Iwai4e76a882014-02-25 12:21:03 +01007570 codec_dbg(codec, "patch_ca0132\n");
Ian Minett95c6e9c2011-06-15 15:35:17 -07007571
7572 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7573 if (!spec)
7574 return -ENOMEM;
7575 codec->spec = spec;
Chih-Chung Chang993884f2013-03-25 10:39:23 -07007576 spec->codec = codec;
Ian Minett95c6e9c2011-06-15 15:35:17 -07007577
Takashi Iwai225068a2015-05-29 10:42:14 +02007578 codec->patch_ops = ca0132_patch_ops;
7579 codec->pcm_format_first = 1;
7580 codec->no_sticky_stream = 1;
7581
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007582 /* Detect codec quirk */
7583 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7584 if (quirk)
7585 spec->quirk = quirk->value;
7586 else
7587 spec->quirk = QUIRK_NONE;
7588
Takashi Iwaie24aa0a2014-08-10 13:30:08 +02007589 spec->dsp_state = DSP_DOWNLOAD_INIT;
Ian Minetta7e76272012-12-20 18:53:35 -08007590 spec->num_mixers = 1;
Connor McAdams017310f2018-05-08 13:20:11 -04007591
7592 /* Set which mixers each quirk uses. */
7593 switch (spec->quirk) {
7594 case QUIRK_SBZ:
7595 spec->mixers[0] = sbz_mixer;
7596 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7597 break;
7598 case QUIRK_R3DI:
7599 spec->mixers[0] = r3di_mixer;
7600 snd_hda_codec_set_name(codec, "Recon3Di");
7601 break;
7602 default:
7603 spec->mixers[0] = ca0132_mixer;
7604 break;
7605 }
Ian Minetta7e76272012-12-20 18:53:35 -08007606
Connor McAdams08eca6b2018-08-08 13:34:17 -04007607 /* Setup whether or not to use alt functions/controls/pci_mmio */
Connor McAdams009b8f92018-05-08 13:20:06 -04007608 switch (spec->quirk) {
7609 case QUIRK_SBZ:
Connor McAdamse42c7c72018-08-08 13:34:18 -04007610 case QUIRK_R3D:
Connor McAdams08eca6b2018-08-08 13:34:17 -04007611 spec->use_alt_controls = true;
7612 spec->use_alt_functions = true;
7613 spec->use_pci_mmio = true;
7614 break;
Connor McAdams009b8f92018-05-08 13:20:06 -04007615 case QUIRK_R3DI:
Connor McAdams47cdf762018-05-08 13:20:13 -04007616 spec->use_alt_controls = true;
Connor McAdams009b8f92018-05-08 13:20:06 -04007617 spec->use_alt_functions = true;
Connor McAdams08eca6b2018-08-08 13:34:17 -04007618 spec->use_pci_mmio = false;
Connor McAdams009b8f92018-05-08 13:20:06 -04007619 break;
7620 default:
Connor McAdams47cdf762018-05-08 13:20:13 -04007621 spec->use_alt_controls = false;
Connor McAdams009b8f92018-05-08 13:20:06 -04007622 spec->use_alt_functions = false;
Connor McAdams08eca6b2018-08-08 13:34:17 -04007623 spec->use_pci_mmio = false;
Connor McAdams009b8f92018-05-08 13:20:06 -04007624 break;
7625 }
7626
Connor McAdams08eca6b2018-08-08 13:34:17 -04007627 if (spec->use_pci_mmio) {
7628 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7629 if (spec->mem_base == NULL) {
7630 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
7631 spec->quirk = QUIRK_NONE;
7632 }
7633 }
7634
Ian Minett5aaca442012-12-20 18:53:34 -08007635 spec->base_init_verbs = ca0132_base_init_verbs;
7636 spec->base_exit_verbs = ca0132_base_exit_verbs;
Ian Minett5aaca442012-12-20 18:53:34 -08007637
Chih-Chung Chang993884f2013-03-25 10:39:23 -07007638 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7639
Ian Minett95c6e9c2011-06-15 15:35:17 -07007640 ca0132_init_chip(codec);
7641
7642 ca0132_config(codec);
7643
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007644 err = ca0132_prepare_verbs(codec);
7645 if (err < 0)
Takashi Iwaicc91cea2017-09-04 17:38:36 +02007646 goto error;
Gabriele Martinod5c016b2015-05-18 21:15:13 +02007647
Ian Minetta73d5112012-12-20 18:53:37 -08007648 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7649 if (err < 0)
Takashi Iwaicc91cea2017-09-04 17:38:36 +02007650 goto error;
Ian Minetta73d5112012-12-20 18:53:37 -08007651
Ian Minett95c6e9c2011-06-15 15:35:17 -07007652 return 0;
Takashi Iwaicc91cea2017-09-04 17:38:36 +02007653
7654 error:
7655 ca0132_free(codec);
7656 return err;
Ian Minett95c6e9c2011-06-15 15:35:17 -07007657}
7658
7659/*
7660 * patch entries
7661 */
Takashi Iwaib9a94a92015-10-01 16:20:04 +02007662static struct hda_device_id snd_hda_id_ca0132[] = {
7663 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
Ian Minett95c6e9c2011-06-15 15:35:17 -07007664 {} /* terminator */
7665};
Takashi Iwaib9a94a92015-10-01 16:20:04 +02007666MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
Ian Minett95c6e9c2011-06-15 15:35:17 -07007667
7668MODULE_LICENSE("GPL");
Ian Minett406261c2012-12-20 18:53:41 -08007669MODULE_DESCRIPTION("Creative Sound Core3D codec");
Ian Minett95c6e9c2011-06-15 15:35:17 -07007670
Takashi Iwaid8a766a2015-02-17 15:25:37 +01007671static struct hda_codec_driver ca0132_driver = {
Takashi Iwaib9a94a92015-10-01 16:20:04 +02007672 .id = snd_hda_id_ca0132,
Ian Minett95c6e9c2011-06-15 15:35:17 -07007673};
7674
Takashi Iwaid8a766a2015-02-17 15:25:37 +01007675module_hda_codec_driver(ca0132_driver);