Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 1 | /* |
Joerg Roedel | 5d0d715 | 2010-10-13 11:13:21 +0200 | [diff] [blame] | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
Joerg Roedel | 63ce3ae | 2015-02-04 16:12:55 +0100 | [diff] [blame] | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 4 | * Leo Duran <leo.duran@amd.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 20 | #include <linux/ratelimit.h> |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 21 | #include <linux/pci.h> |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 22 | #include <linux/acpi.h> |
Wan Zongshun | 9a4d3bf5 | 2016-04-01 09:06:05 -0400 | [diff] [blame] | 23 | #include <linux/amba/bus.h> |
Wan Zongshun | 0076cd3 | 2016-05-10 09:21:01 -0400 | [diff] [blame] | 24 | #include <linux/platform_device.h> |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 25 | #include <linux/pci-ats.h> |
Akinobu Mita | a66022c | 2009-12-15 16:48:28 -0800 | [diff] [blame] | 26 | #include <linux/bitmap.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 27 | #include <linux/slab.h> |
Joerg Roedel | 7f26508 | 2008-12-12 13:50:21 +0100 | [diff] [blame] | 28 | #include <linux/debugfs.h> |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 29 | #include <linux/scatterlist.h> |
FUJITA Tomonori | 5149136 | 2009-01-05 23:47:25 +0900 | [diff] [blame] | 30 | #include <linux/dma-mapping.h> |
Christoph Hellwig | fec777c | 2018-03-19 11:38:15 +0100 | [diff] [blame] | 31 | #include <linux/dma-direct.h> |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 32 | #include <linux/iommu-helper.h> |
Joerg Roedel | c156e34 | 2008-12-02 18:13:27 +0100 | [diff] [blame] | 33 | #include <linux/iommu.h> |
Joerg Roedel | 815b33f | 2011-04-06 17:26:49 +0200 | [diff] [blame] | 34 | #include <linux/delay.h> |
Joerg Roedel | 403f81d | 2011-06-14 16:44:25 +0200 | [diff] [blame] | 35 | #include <linux/amd-iommu.h> |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 36 | #include <linux/notifier.h> |
| 37 | #include <linux/export.h> |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 38 | #include <linux/irq.h> |
| 39 | #include <linux/msi.h> |
Joerg Roedel | 3b839a5 | 2015-04-01 14:58:47 +0200 | [diff] [blame] | 40 | #include <linux/dma-contiguous.h> |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 41 | #include <linux/irqdomain.h> |
Joerg Roedel | 5f6bed5 | 2015-12-22 13:34:22 +0100 | [diff] [blame] | 42 | #include <linux/percpu.h> |
Joerg Roedel | 307d585 | 2016-07-05 11:54:04 +0200 | [diff] [blame] | 43 | #include <linux/iova.h> |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 44 | #include <asm/irq_remapping.h> |
| 45 | #include <asm/io_apic.h> |
| 46 | #include <asm/apic.h> |
| 47 | #include <asm/hw_irq.h> |
Joerg Roedel | 17f5b56 | 2011-07-06 17:14:44 +0200 | [diff] [blame] | 48 | #include <asm/msidef.h> |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 49 | #include <asm/proto.h> |
FUJITA Tomonori | 46a7fa2 | 2008-07-11 10:23:42 +0900 | [diff] [blame] | 50 | #include <asm/iommu.h> |
Joerg Roedel | 1d9b16d | 2008-11-27 18:39:15 +0100 | [diff] [blame] | 51 | #include <asm/gart.h> |
Joerg Roedel | 27c2127 | 2011-05-30 15:56:24 +0200 | [diff] [blame] | 52 | #include <asm/dma.h> |
Joerg Roedel | 403f81d | 2011-06-14 16:44:25 +0200 | [diff] [blame] | 53 | |
| 54 | #include "amd_iommu_proto.h" |
| 55 | #include "amd_iommu_types.h" |
Joerg Roedel | 6b474b8 | 2012-06-26 16:46:04 +0200 | [diff] [blame] | 56 | #include "irq_remapping.h" |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 57 | |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 58 | #define AMD_IOMMU_MAPPING_ERROR 0 |
| 59 | |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 60 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) |
| 61 | |
Joerg Roedel | 815b33f | 2011-04-06 17:26:49 +0200 | [diff] [blame] | 62 | #define LOOP_TIMEOUT 100000 |
Joerg Roedel | 136f78a | 2008-07-11 17:14:27 +0200 | [diff] [blame] | 63 | |
Joerg Roedel | 307d585 | 2016-07-05 11:54:04 +0200 | [diff] [blame] | 64 | /* IO virtual address start page frame number */ |
| 65 | #define IOVA_START_PFN (1) |
| 66 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
Joerg Roedel | 307d585 | 2016-07-05 11:54:04 +0200 | [diff] [blame] | 67 | |
Joerg Roedel | 81cd07b | 2016-07-07 18:01:10 +0200 | [diff] [blame] | 68 | /* Reserved IOVA ranges */ |
| 69 | #define MSI_RANGE_START (0xfee00000) |
| 70 | #define MSI_RANGE_END (0xfeefffff) |
| 71 | #define HT_RANGE_START (0xfd00000000ULL) |
| 72 | #define HT_RANGE_END (0xffffffffffULL) |
| 73 | |
Ohad Ben-Cohen | aa3de9c | 2011-11-10 11:32:29 +0200 | [diff] [blame] | 74 | /* |
| 75 | * This bitmap is used to advertise the page sizes our hardware support |
| 76 | * to the IOMMU core, which will then use this information to split |
| 77 | * physically contiguous memory regions it is mapping into page sizes |
| 78 | * that we support. |
| 79 | * |
Joerg Roedel | 954e3dd | 2012-12-02 15:35:37 +0100 | [diff] [blame] | 80 | * 512GB Pages are not supported due to a hardware bug |
Ohad Ben-Cohen | aa3de9c | 2011-11-10 11:32:29 +0200 | [diff] [blame] | 81 | */ |
Joerg Roedel | 954e3dd | 2012-12-02 15:35:37 +0100 | [diff] [blame] | 82 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
Ohad Ben-Cohen | aa3de9c | 2011-11-10 11:32:29 +0200 | [diff] [blame] | 83 | |
Sebastian Andrzej Siewior | 2cd1083 | 2018-03-22 16:22:41 +0100 | [diff] [blame] | 84 | static DEFINE_SPINLOCK(amd_iommu_devtable_lock); |
Sebastian Andrzej Siewior | 2bc0018 | 2018-03-22 16:22:35 +0100 | [diff] [blame] | 85 | static DEFINE_SPINLOCK(pd_bitmap_lock); |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 86 | |
Joerg Roedel | 8fa5f80 | 2011-06-09 12:24:45 +0200 | [diff] [blame] | 87 | /* List of all available dev_data structures */ |
Sebastian Andrzej Siewior | 779da73 | 2018-03-22 16:22:34 +0100 | [diff] [blame] | 88 | static LLIST_HEAD(dev_data_list); |
Joerg Roedel | 8fa5f80 | 2011-06-09 12:24:45 +0200 | [diff] [blame] | 89 | |
Joerg Roedel | 6efed63 | 2012-06-14 15:52:58 +0200 | [diff] [blame] | 90 | LIST_HEAD(ioapic_map); |
| 91 | LIST_HEAD(hpet_map); |
Wan Zongshun | 2a0cb4e | 2016-04-01 09:06:00 -0400 | [diff] [blame] | 92 | LIST_HEAD(acpihid_map); |
Joerg Roedel | 6efed63 | 2012-06-14 15:52:58 +0200 | [diff] [blame] | 93 | |
Joerg Roedel | 0feae53 | 2009-08-26 15:26:30 +0200 | [diff] [blame] | 94 | /* |
| 95 | * Domain for untranslated devices - only allocated |
| 96 | * if iommu=pt passed on kernel cmd line. |
| 97 | */ |
Joerg Roedel | b0119e8 | 2017-02-01 13:23:08 +0100 | [diff] [blame] | 98 | const struct iommu_ops amd_iommu_ops; |
Joerg Roedel | 26961ef | 2008-12-03 17:00:17 +0100 | [diff] [blame] | 99 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 100 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 101 | int amd_iommu_max_glx_val = -1; |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 102 | |
Bart Van Assche | 5299709 | 2017-01-20 13:04:01 -0800 | [diff] [blame] | 103 | static const struct dma_map_ops amd_iommu_dma_ops; |
Joerg Roedel | ac1534a | 2012-06-21 14:52:40 +0200 | [diff] [blame] | 104 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 105 | /* |
| 106 | * general struct to manage commands send to an IOMMU |
| 107 | */ |
Joerg Roedel | d644953 | 2008-07-11 17:14:28 +0200 | [diff] [blame] | 108 | struct iommu_cmd { |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 109 | u32 data[4]; |
| 110 | }; |
| 111 | |
Joerg Roedel | 05152a0 | 2012-06-15 16:53:51 +0200 | [diff] [blame] | 112 | struct kmem_cache *amd_iommu_irq_cache; |
| 113 | |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 114 | static void update_domain(struct protection_domain *domain); |
Joerg Roedel | 7a5a566 | 2015-06-30 08:56:11 +0200 | [diff] [blame] | 115 | static int protection_domain_init(struct protection_domain *domain); |
Joerg Roedel | b6809ee | 2016-02-26 16:48:59 +0100 | [diff] [blame] | 116 | static void detach_device(struct device *dev); |
Joerg Roedel | 9003d61 | 2017-08-10 17:19:13 +0200 | [diff] [blame] | 117 | static void iova_domain_flush_tlb(struct iova_domain *iovad); |
Joerg Roedel | d4241a2 | 2017-06-02 14:55:56 +0200 | [diff] [blame] | 118 | |
Joerg Roedel | 007b74b | 2015-12-21 12:53:54 +0100 | [diff] [blame] | 119 | /* |
Joerg Roedel | 007b74b | 2015-12-21 12:53:54 +0100 | [diff] [blame] | 120 | * Data container for a dma_ops specific protection domain |
| 121 | */ |
| 122 | struct dma_ops_domain { |
| 123 | /* generic protection domain information */ |
| 124 | struct protection_domain domain; |
| 125 | |
Joerg Roedel | 307d585 | 2016-07-05 11:54:04 +0200 | [diff] [blame] | 126 | /* IOVA RB-Tree */ |
| 127 | struct iova_domain iovad; |
Joerg Roedel | 007b74b | 2015-12-21 12:53:54 +0100 | [diff] [blame] | 128 | }; |
| 129 | |
Joerg Roedel | 81cd07b | 2016-07-07 18:01:10 +0200 | [diff] [blame] | 130 | static struct iova_domain reserved_iova_ranges; |
| 131 | static struct lock_class_key reserved_rbtree_key; |
| 132 | |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 133 | /**************************************************************************** |
| 134 | * |
| 135 | * Helper functions |
| 136 | * |
| 137 | ****************************************************************************/ |
| 138 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 139 | static inline int match_hid_uid(struct device *dev, |
| 140 | struct acpihid_map_entry *entry) |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 141 | { |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 142 | const char *hid, *uid; |
| 143 | |
| 144 | hid = acpi_device_hid(ACPI_COMPANION(dev)); |
| 145 | uid = acpi_device_uid(ACPI_COMPANION(dev)); |
| 146 | |
| 147 | if (!hid || !(*hid)) |
| 148 | return -ENODEV; |
| 149 | |
| 150 | if (!uid || !(*uid)) |
| 151 | return strcmp(hid, entry->hid); |
| 152 | |
| 153 | if (!(*entry->uid)) |
| 154 | return strcmp(hid, entry->hid); |
| 155 | |
| 156 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 157 | } |
| 158 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 159 | static inline u16 get_pci_device_id(struct device *dev) |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 160 | { |
| 161 | struct pci_dev *pdev = to_pci_dev(dev); |
| 162 | |
| 163 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
| 164 | } |
| 165 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 166 | static inline int get_acpihid_device_id(struct device *dev, |
| 167 | struct acpihid_map_entry **entry) |
| 168 | { |
| 169 | struct acpihid_map_entry *p; |
| 170 | |
| 171 | list_for_each_entry(p, &acpihid_map, list) { |
| 172 | if (!match_hid_uid(dev, p)) { |
| 173 | if (entry) |
| 174 | *entry = p; |
| 175 | return p->devid; |
| 176 | } |
| 177 | } |
| 178 | return -EINVAL; |
| 179 | } |
| 180 | |
| 181 | static inline int get_device_id(struct device *dev) |
| 182 | { |
| 183 | int devid; |
| 184 | |
| 185 | if (dev_is_pci(dev)) |
| 186 | devid = get_pci_device_id(dev); |
| 187 | else |
| 188 | devid = get_acpihid_device_id(dev, NULL); |
| 189 | |
| 190 | return devid; |
| 191 | } |
| 192 | |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 193 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
| 194 | { |
| 195 | return container_of(dom, struct protection_domain, domain); |
| 196 | } |
| 197 | |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 198 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) |
| 199 | { |
| 200 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); |
| 201 | return container_of(domain, struct dma_ops_domain, domain); |
| 202 | } |
| 203 | |
Joerg Roedel | f62dda6 | 2011-06-09 12:55:35 +0200 | [diff] [blame] | 204 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
Joerg Roedel | 8fa5f80 | 2011-06-09 12:24:45 +0200 | [diff] [blame] | 205 | { |
| 206 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 8fa5f80 | 2011-06-09 12:24:45 +0200 | [diff] [blame] | 207 | |
| 208 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); |
| 209 | if (!dev_data) |
| 210 | return NULL; |
| 211 | |
Joerg Roedel | f62dda6 | 2011-06-09 12:55:35 +0200 | [diff] [blame] | 212 | dev_data->devid = devid; |
Joerg Roedel | 30bf2df | 2017-05-15 16:25:03 +0200 | [diff] [blame] | 213 | ratelimit_default_init(&dev_data->rs); |
| 214 | |
Sebastian Andrzej Siewior | 779da73 | 2018-03-22 16:22:34 +0100 | [diff] [blame] | 215 | llist_add(&dev_data->dev_data_list, &dev_data_list); |
Joerg Roedel | 8fa5f80 | 2011-06-09 12:24:45 +0200 | [diff] [blame] | 216 | return dev_data; |
| 217 | } |
| 218 | |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 219 | static struct iommu_dev_data *search_dev_data(u16 devid) |
| 220 | { |
| 221 | struct iommu_dev_data *dev_data; |
Sebastian Andrzej Siewior | 779da73 | 2018-03-22 16:22:34 +0100 | [diff] [blame] | 222 | struct llist_node *node; |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 223 | |
Sebastian Andrzej Siewior | 779da73 | 2018-03-22 16:22:34 +0100 | [diff] [blame] | 224 | if (llist_empty(&dev_data_list)) |
| 225 | return NULL; |
| 226 | |
| 227 | node = dev_data_list.first; |
| 228 | llist_for_each_entry(dev_data, node, dev_data_list) { |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 229 | if (dev_data->devid == devid) |
Sebastian Andrzej Siewior | 779da73 | 2018-03-22 16:22:34 +0100 | [diff] [blame] | 230 | return dev_data; |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 231 | } |
| 232 | |
Sebastian Andrzej Siewior | 779da73 | 2018-03-22 16:22:34 +0100 | [diff] [blame] | 233 | return NULL; |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 234 | } |
| 235 | |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 236 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
| 237 | { |
| 238 | *(u16 *)data = alias; |
| 239 | return 0; |
| 240 | } |
| 241 | |
| 242 | static u16 get_alias(struct device *dev) |
| 243 | { |
| 244 | struct pci_dev *pdev = to_pci_dev(dev); |
| 245 | u16 devid, ivrs_alias, pci_alias; |
| 246 | |
Joerg Roedel | 6c0b43d | 2016-05-09 19:39:17 +0200 | [diff] [blame] | 247 | /* The callers make sure that get_device_id() does not fail here */ |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 248 | devid = get_device_id(dev); |
| 249 | ivrs_alias = amd_iommu_alias_table[devid]; |
| 250 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); |
| 251 | |
| 252 | if (ivrs_alias == pci_alias) |
| 253 | return ivrs_alias; |
| 254 | |
| 255 | /* |
| 256 | * DMA alias showdown |
| 257 | * |
| 258 | * The IVRS is fairly reliable in telling us about aliases, but it |
| 259 | * can't know about every screwy device. If we don't have an IVRS |
| 260 | * reported alias, use the PCI reported alias. In that case we may |
| 261 | * still need to initialize the rlookup and dev_table entries if the |
| 262 | * alias is to a non-existent device. |
| 263 | */ |
| 264 | if (ivrs_alias == devid) { |
| 265 | if (!amd_iommu_rlookup_table[pci_alias]) { |
| 266 | amd_iommu_rlookup_table[pci_alias] = |
| 267 | amd_iommu_rlookup_table[devid]; |
| 268 | memcpy(amd_iommu_dev_table[pci_alias].data, |
| 269 | amd_iommu_dev_table[devid].data, |
| 270 | sizeof(amd_iommu_dev_table[pci_alias].data)); |
| 271 | } |
| 272 | |
| 273 | return pci_alias; |
| 274 | } |
| 275 | |
| 276 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " |
| 277 | "for device %s[%04x:%04x], kernel reported alias " |
| 278 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), |
| 279 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, |
| 280 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), |
| 281 | PCI_FUNC(pci_alias)); |
| 282 | |
| 283 | /* |
| 284 | * If we don't have a PCI DMA alias and the IVRS alias is on the same |
| 285 | * bus, then the IVRS table may know about a quirk that we don't. |
| 286 | */ |
| 287 | if (pci_alias == devid && |
| 288 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { |
Linus Torvalds | 7afd16f | 2016-05-19 13:10:54 -0700 | [diff] [blame] | 289 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 290 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", |
| 291 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), |
| 292 | dev_name(dev)); |
| 293 | } |
| 294 | |
| 295 | return ivrs_alias; |
| 296 | } |
| 297 | |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 298 | static struct iommu_dev_data *find_dev_data(u16 devid) |
| 299 | { |
| 300 | struct iommu_dev_data *dev_data; |
Baoquan He | df3f7a6 | 2017-08-09 16:33:41 +0800 | [diff] [blame] | 301 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 302 | |
| 303 | dev_data = search_dev_data(devid); |
| 304 | |
Baoquan He | df3f7a6 | 2017-08-09 16:33:41 +0800 | [diff] [blame] | 305 | if (dev_data == NULL) { |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 306 | dev_data = alloc_dev_data(devid); |
Sebastian Andrzej Siewior | 39ffe39 | 2018-03-22 16:22:33 +0100 | [diff] [blame] | 307 | if (!dev_data) |
| 308 | return NULL; |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 309 | |
Baoquan He | df3f7a6 | 2017-08-09 16:33:41 +0800 | [diff] [blame] | 310 | if (translation_pre_enabled(iommu)) |
| 311 | dev_data->defer_attach = true; |
| 312 | } |
| 313 | |
Joerg Roedel | 3b03bb7 | 2011-06-09 18:53:25 +0200 | [diff] [blame] | 314 | return dev_data; |
| 315 | } |
| 316 | |
Baoquan He | daae2d2 | 2017-08-09 16:33:43 +0800 | [diff] [blame] | 317 | struct iommu_dev_data *get_dev_data(struct device *dev) |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 318 | { |
| 319 | return dev->archdata.iommu; |
| 320 | } |
Baoquan He | daae2d2 | 2017-08-09 16:33:43 +0800 | [diff] [blame] | 321 | EXPORT_SYMBOL(get_dev_data); |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 322 | |
Wan Zongshun | b097d11 | 2016-04-01 09:06:04 -0400 | [diff] [blame] | 323 | /* |
| 324 | * Find or create an IOMMU group for a acpihid device. |
| 325 | */ |
| 326 | static struct iommu_group *acpihid_device_group(struct device *dev) |
| 327 | { |
| 328 | struct acpihid_map_entry *p, *entry = NULL; |
Dan Carpenter | 2d8e1f0 | 2016-04-11 10:14:46 +0300 | [diff] [blame] | 329 | int devid; |
Wan Zongshun | b097d11 | 2016-04-01 09:06:04 -0400 | [diff] [blame] | 330 | |
| 331 | devid = get_acpihid_device_id(dev, &entry); |
| 332 | if (devid < 0) |
| 333 | return ERR_PTR(devid); |
| 334 | |
| 335 | list_for_each_entry(p, &acpihid_map, list) { |
| 336 | if ((devid == p->devid) && p->group) |
| 337 | entry->group = p->group; |
| 338 | } |
| 339 | |
| 340 | if (!entry->group) |
| 341 | entry->group = generic_device_group(dev); |
Robin Murphy | f2f101f | 2016-11-11 17:59:23 +0000 | [diff] [blame] | 342 | else |
| 343 | iommu_group_ref_get(entry->group); |
Wan Zongshun | b097d11 | 2016-04-01 09:06:04 -0400 | [diff] [blame] | 344 | |
| 345 | return entry->group; |
| 346 | } |
| 347 | |
Joerg Roedel | 5abcdba | 2011-12-01 15:49:45 +0100 | [diff] [blame] | 348 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
| 349 | { |
| 350 | static const int caps[] = { |
| 351 | PCI_EXT_CAP_ID_ATS, |
Joerg Roedel | 46277b7 | 2011-12-07 14:34:02 +0100 | [diff] [blame] | 352 | PCI_EXT_CAP_ID_PRI, |
| 353 | PCI_EXT_CAP_ID_PASID, |
Joerg Roedel | 5abcdba | 2011-12-01 15:49:45 +0100 | [diff] [blame] | 354 | }; |
| 355 | int i, pos; |
| 356 | |
Gil Kupfer | cef7440 | 2018-05-10 17:56:02 -0500 | [diff] [blame] | 357 | if (pci_ats_disabled()) |
| 358 | return false; |
| 359 | |
Joerg Roedel | 5abcdba | 2011-12-01 15:49:45 +0100 | [diff] [blame] | 360 | for (i = 0; i < 3; ++i) { |
| 361 | pos = pci_find_ext_capability(pdev, caps[i]); |
| 362 | if (pos == 0) |
| 363 | return false; |
| 364 | } |
| 365 | |
| 366 | return true; |
| 367 | } |
| 368 | |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 369 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
| 370 | { |
| 371 | struct iommu_dev_data *dev_data; |
| 372 | |
| 373 | dev_data = get_dev_data(&pdev->dev); |
| 374 | |
| 375 | return dev_data->errata & (1 << erratum) ? true : false; |
| 376 | } |
| 377 | |
Joerg Roedel | 71c7098 | 2009-11-24 16:43:06 +0100 | [diff] [blame] | 378 | /* |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 379 | * This function checks if the driver got a valid device from the caller to |
| 380 | * avoid dereferencing invalid pointers. |
| 381 | */ |
| 382 | static bool check_device(struct device *dev) |
| 383 | { |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 384 | int devid; |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 385 | |
| 386 | if (!dev || !dev->dma_mask) |
| 387 | return false; |
| 388 | |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 389 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 390 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 391 | return false; |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 392 | |
| 393 | /* Out of our scope? */ |
| 394 | if (devid > amd_iommu_last_bdf) |
| 395 | return false; |
| 396 | |
| 397 | if (amd_iommu_rlookup_table[devid] == NULL) |
| 398 | return false; |
| 399 | |
| 400 | return true; |
| 401 | } |
| 402 | |
Alex Williamson | 25b11ce | 2014-09-19 10:03:13 -0600 | [diff] [blame] | 403 | static void init_iommu_group(struct device *dev) |
Alex Williamson | 2851db2 | 2012-10-08 22:49:41 -0600 | [diff] [blame] | 404 | { |
Alex Williamson | 2851db2 | 2012-10-08 22:49:41 -0600 | [diff] [blame] | 405 | struct iommu_group *group; |
Alex Williamson | 2851db2 | 2012-10-08 22:49:41 -0600 | [diff] [blame] | 406 | |
Alex Williamson | 65d5352 | 2014-07-03 09:51:30 -0600 | [diff] [blame] | 407 | group = iommu_group_get_for_dev(dev); |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 408 | if (IS_ERR(group)) |
| 409 | return; |
| 410 | |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 411 | iommu_group_put(group); |
Alex Williamson | eb9c952 | 2012-10-08 22:49:35 -0600 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | static int iommu_init_device(struct device *dev) |
| 415 | { |
Alex Williamson | eb9c952 | 2012-10-08 22:49:35 -0600 | [diff] [blame] | 416 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 39ab955 | 2017-02-01 16:56:46 +0100 | [diff] [blame] | 417 | struct amd_iommu *iommu; |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 418 | int devid; |
Alex Williamson | eb9c952 | 2012-10-08 22:49:35 -0600 | [diff] [blame] | 419 | |
| 420 | if (dev->archdata.iommu) |
| 421 | return 0; |
| 422 | |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 423 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 424 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 425 | return devid; |
| 426 | |
Joerg Roedel | 39ab955 | 2017-02-01 16:56:46 +0100 | [diff] [blame] | 427 | iommu = amd_iommu_rlookup_table[devid]; |
| 428 | |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 429 | dev_data = find_dev_data(devid); |
Alex Williamson | eb9c952 | 2012-10-08 22:49:35 -0600 | [diff] [blame] | 430 | if (!dev_data) |
| 431 | return -ENOMEM; |
| 432 | |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 433 | dev_data->alias = get_alias(dev); |
| 434 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 435 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
Joerg Roedel | 5abcdba | 2011-12-01 15:49:45 +0100 | [diff] [blame] | 436 | struct amd_iommu *iommu; |
| 437 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 438 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
Joerg Roedel | 5abcdba | 2011-12-01 15:49:45 +0100 | [diff] [blame] | 439 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
| 440 | } |
| 441 | |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 442 | dev->archdata.iommu = dev_data; |
| 443 | |
Joerg Roedel | e3d10af | 2017-02-01 17:23:22 +0100 | [diff] [blame] | 444 | iommu_device_link(&iommu->iommu, dev); |
Alex Williamson | 066f2e9 | 2014-06-12 16:12:37 -0600 | [diff] [blame] | 445 | |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 446 | return 0; |
| 447 | } |
| 448 | |
Joerg Roedel | 2601887 | 2011-06-06 16:50:14 +0200 | [diff] [blame] | 449 | static void iommu_ignore_device(struct device *dev) |
| 450 | { |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 451 | u16 alias; |
| 452 | int devid; |
Joerg Roedel | 2601887 | 2011-06-06 16:50:14 +0200 | [diff] [blame] | 453 | |
| 454 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 455 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 456 | return; |
| 457 | |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 458 | alias = get_alias(dev); |
Joerg Roedel | 2601887 | 2011-06-06 16:50:14 +0200 | [diff] [blame] | 459 | |
| 460 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); |
| 461 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); |
| 462 | |
| 463 | amd_iommu_rlookup_table[devid] = NULL; |
| 464 | amd_iommu_rlookup_table[alias] = NULL; |
| 465 | } |
| 466 | |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 467 | static void iommu_uninit_device(struct device *dev) |
| 468 | { |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 469 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 39ab955 | 2017-02-01 16:56:46 +0100 | [diff] [blame] | 470 | struct amd_iommu *iommu; |
| 471 | int devid; |
Alex Williamson | c193109 | 2014-07-03 09:51:24 -0600 | [diff] [blame] | 472 | |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 473 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 474 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 475 | return; |
| 476 | |
Joerg Roedel | 39ab955 | 2017-02-01 16:56:46 +0100 | [diff] [blame] | 477 | iommu = amd_iommu_rlookup_table[devid]; |
| 478 | |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 479 | dev_data = search_dev_data(devid); |
Alex Williamson | c193109 | 2014-07-03 09:51:24 -0600 | [diff] [blame] | 480 | if (!dev_data) |
| 481 | return; |
| 482 | |
Joerg Roedel | b6809ee | 2016-02-26 16:48:59 +0100 | [diff] [blame] | 483 | if (dev_data->domain) |
| 484 | detach_device(dev); |
| 485 | |
Joerg Roedel | e3d10af | 2017-02-01 17:23:22 +0100 | [diff] [blame] | 486 | iommu_device_unlink(&iommu->iommu, dev); |
Alex Williamson | 066f2e9 | 2014-06-12 16:12:37 -0600 | [diff] [blame] | 487 | |
Alex Williamson | 9dcd613 | 2012-05-30 14:19:07 -0600 | [diff] [blame] | 488 | iommu_group_remove_device(dev); |
| 489 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 490 | /* Remove dma-ops */ |
Bart Van Assche | 5657933 | 2017-01-20 13:04:02 -0800 | [diff] [blame] | 491 | dev->dma_ops = NULL; |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 492 | |
Joerg Roedel | 8fa5f80 | 2011-06-09 12:24:45 +0200 | [diff] [blame] | 493 | /* |
Alex Williamson | c193109 | 2014-07-03 09:51:24 -0600 | [diff] [blame] | 494 | * We keep dev_data around for unplugged devices and reuse it when the |
| 495 | * device is re-plugged - not doing so would introduce a ton of races. |
Joerg Roedel | 8fa5f80 | 2011-06-09 12:24:45 +0200 | [diff] [blame] | 496 | */ |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 497 | } |
Joerg Roedel | b7cc955 | 2009-12-10 11:03:39 +0100 | [diff] [blame] | 498 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 499 | /**************************************************************************** |
| 500 | * |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 501 | * Interrupt handling functions |
| 502 | * |
| 503 | ****************************************************************************/ |
| 504 | |
Joerg Roedel | e3e5987 | 2009-09-03 14:02:10 +0200 | [diff] [blame] | 505 | static void dump_dte_entry(u16 devid) |
| 506 | { |
| 507 | int i; |
| 508 | |
Joerg Roedel | ee6c286 | 2011-11-09 12:06:03 +0100 | [diff] [blame] | 509 | for (i = 0; i < 4; ++i) |
| 510 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, |
Joerg Roedel | e3e5987 | 2009-09-03 14:02:10 +0200 | [diff] [blame] | 511 | amd_iommu_dev_table[devid].data[i]); |
| 512 | } |
| 513 | |
Joerg Roedel | 945b4ac | 2009-09-03 14:25:02 +0200 | [diff] [blame] | 514 | static void dump_command(unsigned long phys_addr) |
| 515 | { |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 516 | struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); |
Joerg Roedel | 945b4ac | 2009-09-03 14:25:02 +0200 | [diff] [blame] | 517 | int i; |
| 518 | |
| 519 | for (i = 0; i < 4; ++i) |
| 520 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); |
| 521 | } |
| 522 | |
Joerg Roedel | 30bf2df | 2017-05-15 16:25:03 +0200 | [diff] [blame] | 523 | static void amd_iommu_report_page_fault(u16 devid, u16 domain_id, |
| 524 | u64 address, int flags) |
| 525 | { |
| 526 | struct iommu_dev_data *dev_data = NULL; |
| 527 | struct pci_dev *pdev; |
| 528 | |
Sinan Kaya | d5bf0f4 | 2017-12-19 00:37:47 -0500 | [diff] [blame] | 529 | pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid), |
| 530 | devid & 0xff); |
Joerg Roedel | 30bf2df | 2017-05-15 16:25:03 +0200 | [diff] [blame] | 531 | if (pdev) |
| 532 | dev_data = get_dev_data(&pdev->dev); |
| 533 | |
| 534 | if (dev_data && __ratelimit(&dev_data->rs)) { |
| 535 | dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n", |
| 536 | domain_id, address, flags); |
| 537 | } else if (printk_ratelimit()) { |
| 538 | pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n", |
| 539 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
| 540 | domain_id, address, flags); |
| 541 | } |
| 542 | |
| 543 | if (pdev) |
| 544 | pci_dev_put(pdev); |
| 545 | } |
| 546 | |
Joerg Roedel | a345b23 | 2009-09-03 15:01:43 +0200 | [diff] [blame] | 547 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 548 | { |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 549 | struct device *dev = iommu->iommu.dev; |
Gary R Hook | e7f63ff | 2018-05-01 14:53:00 -0500 | [diff] [blame] | 550 | int type, devid, pasid, flags, tag; |
Joerg Roedel | 3d06fca | 2012-04-12 14:12:00 +0200 | [diff] [blame] | 551 | volatile u32 *event = __evt; |
| 552 | int count = 0; |
| 553 | u64 address; |
| 554 | |
| 555 | retry: |
| 556 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; |
| 557 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 558 | pasid = PPR_PASID(*(u64 *)&event[0]); |
Joerg Roedel | 3d06fca | 2012-04-12 14:12:00 +0200 | [diff] [blame] | 559 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; |
| 560 | address = (u64)(((u64)event[3]) << 32) | event[2]; |
| 561 | |
| 562 | if (type == 0) { |
| 563 | /* Did we hit the erratum? */ |
| 564 | if (++count == LOOP_TIMEOUT) { |
| 565 | pr_err("AMD-Vi: No event written to event log\n"); |
| 566 | return; |
| 567 | } |
| 568 | udelay(1); |
| 569 | goto retry; |
| 570 | } |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 571 | |
Joerg Roedel | 30bf2df | 2017-05-15 16:25:03 +0200 | [diff] [blame] | 572 | if (type == EVENT_TYPE_IO_FAULT) { |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 573 | amd_iommu_report_page_fault(devid, pasid, address, flags); |
Joerg Roedel | 30bf2df | 2017-05-15 16:25:03 +0200 | [diff] [blame] | 574 | return; |
| 575 | } else { |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 576 | dev_err(dev, "AMD-Vi: Event logged ["); |
Joerg Roedel | 30bf2df | 2017-05-15 16:25:03 +0200 | [diff] [blame] | 577 | } |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 578 | |
| 579 | switch (type) { |
| 580 | case EVENT_TYPE_ILL_DEV: |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 581 | dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n", |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 582 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 583 | pasid, address, flags); |
Joerg Roedel | e3e5987 | 2009-09-03 14:02:10 +0200 | [diff] [blame] | 584 | dump_dte_entry(devid); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 585 | break; |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 586 | case EVENT_TYPE_DEV_TAB_ERR: |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 587 | dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " |
| 588 | "address=0x%016llx flags=0x%04x]\n", |
| 589 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
| 590 | address, flags); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 591 | break; |
| 592 | case EVENT_TYPE_PAGE_TAB_ERR: |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 593 | dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n", |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 594 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 595 | pasid, address, flags); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 596 | break; |
| 597 | case EVENT_TYPE_ILL_CMD: |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 598 | dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); |
Joerg Roedel | 945b4ac | 2009-09-03 14:25:02 +0200 | [diff] [blame] | 599 | dump_command(address); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 600 | break; |
| 601 | case EVENT_TYPE_CMD_HARD_ERR: |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 602 | dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n", |
| 603 | address, flags); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 604 | break; |
| 605 | case EVENT_TYPE_IOTLB_INV_TO: |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 606 | dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n", |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 607 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
| 608 | address); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 609 | break; |
| 610 | case EVENT_TYPE_INV_DEV_REQ: |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 611 | dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n", |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 612 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 613 | pasid, address, flags); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 614 | break; |
Gary R Hook | e7f63ff | 2018-05-01 14:53:00 -0500 | [diff] [blame] | 615 | case EVENT_TYPE_INV_PPR_REQ: |
| 616 | pasid = ((event[0] >> 16) & 0xFFFF) |
| 617 | | ((event[1] << 6) & 0xF0000); |
| 618 | tag = event[1] & 0x03FF; |
| 619 | dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n", |
| 620 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
| 621 | pasid, address, flags); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 622 | break; |
| 623 | default: |
Gary R Hook | d64c048 | 2018-05-01 14:52:52 -0500 | [diff] [blame] | 624 | dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n", |
Gary R Hook | 90ca385 | 2018-03-08 18:34:41 -0600 | [diff] [blame] | 625 | event[0], event[1], event[2], event[3]); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 626 | } |
Joerg Roedel | 3d06fca | 2012-04-12 14:12:00 +0200 | [diff] [blame] | 627 | |
| 628 | memset(__evt, 0, 4 * sizeof(u32)); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | static void iommu_poll_events(struct amd_iommu *iommu) |
| 632 | { |
| 633 | u32 head, tail; |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 634 | |
| 635 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); |
| 636 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); |
| 637 | |
| 638 | while (head != tail) { |
Joerg Roedel | a345b23 | 2009-09-03 15:01:43 +0200 | [diff] [blame] | 639 | iommu_print_event(iommu, iommu->evt_buf + head); |
Joerg Roedel | deba4bc | 2015-10-20 17:33:41 +0200 | [diff] [blame] | 640 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 644 | } |
| 645 | |
Joerg Roedel | eee5353 | 2012-06-01 15:20:23 +0200 | [diff] [blame] | 646 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 647 | { |
| 648 | struct amd_iommu_fault fault; |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 649 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 650 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
| 651 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); |
| 652 | return; |
| 653 | } |
| 654 | |
| 655 | fault.address = raw[1]; |
| 656 | fault.pasid = PPR_PASID(raw[0]); |
| 657 | fault.device_id = PPR_DEVID(raw[0]); |
| 658 | fault.tag = PPR_TAG(raw[0]); |
| 659 | fault.flags = PPR_FLAGS(raw[0]); |
| 660 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 661 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
| 662 | } |
| 663 | |
| 664 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) |
| 665 | { |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 666 | u32 head, tail; |
| 667 | |
| 668 | if (iommu->ppr_log == NULL) |
| 669 | return; |
| 670 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 671 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
| 672 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
| 673 | |
| 674 | while (head != tail) { |
Joerg Roedel | eee5353 | 2012-06-01 15:20:23 +0200 | [diff] [blame] | 675 | volatile u64 *raw; |
| 676 | u64 entry[2]; |
| 677 | int i; |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 678 | |
Joerg Roedel | eee5353 | 2012-06-01 15:20:23 +0200 | [diff] [blame] | 679 | raw = (u64 *)(iommu->ppr_log + head); |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 680 | |
Joerg Roedel | eee5353 | 2012-06-01 15:20:23 +0200 | [diff] [blame] | 681 | /* |
| 682 | * Hardware bug: Interrupt may arrive before the entry is |
| 683 | * written to memory. If this happens we need to wait for the |
| 684 | * entry to arrive. |
| 685 | */ |
| 686 | for (i = 0; i < LOOP_TIMEOUT; ++i) { |
| 687 | if (PPR_REQ_TYPE(raw[0]) != 0) |
| 688 | break; |
| 689 | udelay(1); |
| 690 | } |
| 691 | |
| 692 | /* Avoid memcpy function-call overhead */ |
| 693 | entry[0] = raw[0]; |
| 694 | entry[1] = raw[1]; |
| 695 | |
| 696 | /* |
| 697 | * To detect the hardware bug we need to clear the entry |
| 698 | * back to zero. |
| 699 | */ |
| 700 | raw[0] = raw[1] = 0UL; |
| 701 | |
| 702 | /* Update head pointer of hardware ring-buffer */ |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 703 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
| 704 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
Joerg Roedel | eee5353 | 2012-06-01 15:20:23 +0200 | [diff] [blame] | 705 | |
Joerg Roedel | eee5353 | 2012-06-01 15:20:23 +0200 | [diff] [blame] | 706 | /* Handle PPR entry */ |
| 707 | iommu_handle_ppr_entry(iommu, entry); |
| 708 | |
Joerg Roedel | eee5353 | 2012-06-01 15:20:23 +0200 | [diff] [blame] | 709 | /* Refresh ring-buffer information */ |
| 710 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 711 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
| 712 | } |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 713 | } |
| 714 | |
Suravee Suthikulpanit | bd6fcef | 2016-08-23 13:52:37 -0500 | [diff] [blame] | 715 | #ifdef CONFIG_IRQ_REMAP |
| 716 | static int (*iommu_ga_log_notifier)(u32); |
| 717 | |
| 718 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) |
| 719 | { |
| 720 | iommu_ga_log_notifier = notifier; |
| 721 | |
| 722 | return 0; |
| 723 | } |
| 724 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); |
| 725 | |
| 726 | static void iommu_poll_ga_log(struct amd_iommu *iommu) |
| 727 | { |
| 728 | u32 head, tail, cnt = 0; |
| 729 | |
| 730 | if (iommu->ga_log == NULL) |
| 731 | return; |
| 732 | |
| 733 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); |
| 734 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); |
| 735 | |
| 736 | while (head != tail) { |
| 737 | volatile u64 *raw; |
| 738 | u64 log_entry; |
| 739 | |
| 740 | raw = (u64 *)(iommu->ga_log + head); |
| 741 | cnt++; |
| 742 | |
| 743 | /* Avoid memcpy function-call overhead */ |
| 744 | log_entry = *raw; |
| 745 | |
| 746 | /* Update head pointer of hardware ring-buffer */ |
| 747 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; |
| 748 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); |
| 749 | |
| 750 | /* Handle GA entry */ |
| 751 | switch (GA_REQ_TYPE(log_entry)) { |
| 752 | case GA_GUEST_NR: |
| 753 | if (!iommu_ga_log_notifier) |
| 754 | break; |
| 755 | |
| 756 | pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n", |
| 757 | __func__, GA_DEVID(log_entry), |
| 758 | GA_TAG(log_entry)); |
| 759 | |
| 760 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) |
| 761 | pr_err("AMD-Vi: GA log notifier failed.\n"); |
| 762 | break; |
| 763 | default: |
| 764 | break; |
| 765 | } |
| 766 | } |
| 767 | } |
| 768 | #endif /* CONFIG_IRQ_REMAP */ |
| 769 | |
| 770 | #define AMD_IOMMU_INT_MASK \ |
| 771 | (MMIO_STATUS_EVT_INT_MASK | \ |
| 772 | MMIO_STATUS_PPR_INT_MASK | \ |
| 773 | MMIO_STATUS_GALOG_INT_MASK) |
| 774 | |
Joerg Roedel | 72fe00f | 2011-05-10 10:50:42 +0200 | [diff] [blame] | 775 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 776 | { |
Suravee Suthikulpanit | 3f398bc | 2013-04-22 16:32:34 -0500 | [diff] [blame] | 777 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
| 778 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 779 | |
Suravee Suthikulpanit | bd6fcef | 2016-08-23 13:52:37 -0500 | [diff] [blame] | 780 | while (status & AMD_IOMMU_INT_MASK) { |
| 781 | /* Enable EVT and PPR and GA interrupts again */ |
| 782 | writel(AMD_IOMMU_INT_MASK, |
Suravee Suthikulpanit | 3f398bc | 2013-04-22 16:32:34 -0500 | [diff] [blame] | 783 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
| 784 | |
| 785 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
| 786 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); |
| 787 | iommu_poll_events(iommu); |
| 788 | } |
| 789 | |
| 790 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
| 791 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); |
| 792 | iommu_poll_ppr_log(iommu); |
| 793 | } |
| 794 | |
Suravee Suthikulpanit | bd6fcef | 2016-08-23 13:52:37 -0500 | [diff] [blame] | 795 | #ifdef CONFIG_IRQ_REMAP |
| 796 | if (status & MMIO_STATUS_GALOG_INT_MASK) { |
| 797 | pr_devel("AMD-Vi: Processing IOMMU GA Log\n"); |
| 798 | iommu_poll_ga_log(iommu); |
| 799 | } |
| 800 | #endif |
| 801 | |
Suravee Suthikulpanit | 3f398bc | 2013-04-22 16:32:34 -0500 | [diff] [blame] | 802 | /* |
| 803 | * Hardware bug: ERBT1312 |
| 804 | * When re-enabling interrupt (by writing 1 |
| 805 | * to clear the bit), the hardware might also try to set |
| 806 | * the interrupt bit in the event status register. |
| 807 | * In this scenario, the bit will be set, and disable |
| 808 | * subsequent interrupts. |
| 809 | * |
| 810 | * Workaround: The IOMMU driver should read back the |
| 811 | * status register and check if the interrupt bits are cleared. |
| 812 | * If not, driver will need to go through the interrupt handler |
| 813 | * again and re-clear the bits |
| 814 | */ |
| 815 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 816 | } |
Joerg Roedel | 90008ee | 2008-09-09 16:41:05 +0200 | [diff] [blame] | 817 | return IRQ_HANDLED; |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 818 | } |
| 819 | |
Joerg Roedel | 72fe00f | 2011-05-10 10:50:42 +0200 | [diff] [blame] | 820 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
| 821 | { |
| 822 | return IRQ_WAKE_THREAD; |
| 823 | } |
| 824 | |
Joerg Roedel | a80dc3e | 2008-09-11 16:51:41 +0200 | [diff] [blame] | 825 | /**************************************************************************** |
| 826 | * |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 827 | * IOMMU command queuing functions |
| 828 | * |
| 829 | ****************************************************************************/ |
| 830 | |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 831 | static int wait_on_sem(volatile u64 *sem) |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 832 | { |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 833 | int i = 0; |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 834 | |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 835 | while (*sem == 0 && i < LOOP_TIMEOUT) { |
| 836 | udelay(1); |
| 837 | i += 1; |
| 838 | } |
| 839 | |
| 840 | if (i == LOOP_TIMEOUT) { |
| 841 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); |
| 842 | return -EIO; |
| 843 | } |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 844 | |
| 845 | return 0; |
| 846 | } |
| 847 | |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 848 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 849 | struct iommu_cmd *cmd) |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 850 | { |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 851 | u8 *target; |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 852 | |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 853 | target = iommu->cmd_buf + iommu->cmd_buf_tail; |
| 854 | |
| 855 | iommu->cmd_buf_tail += sizeof(*cmd); |
| 856 | iommu->cmd_buf_tail %= CMD_BUFFER_SIZE; |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 857 | |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 858 | /* Copy command to buffer */ |
| 859 | memcpy(target, cmd, sizeof(*cmd)); |
| 860 | |
| 861 | /* Tell the IOMMU about it */ |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 862 | writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 863 | } |
| 864 | |
Joerg Roedel | 815b33f | 2011-04-06 17:26:49 +0200 | [diff] [blame] | 865 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
Joerg Roedel | ded4673 | 2011-04-06 10:53:48 +0200 | [diff] [blame] | 866 | { |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 867 | u64 paddr = iommu_virt_to_phys((void *)address); |
| 868 | |
Joerg Roedel | 815b33f | 2011-04-06 17:26:49 +0200 | [diff] [blame] | 869 | WARN_ON(address & 0x7ULL); |
| 870 | |
Joerg Roedel | ded4673 | 2011-04-06 10:53:48 +0200 | [diff] [blame] | 871 | memset(cmd, 0, sizeof(*cmd)); |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 872 | cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; |
| 873 | cmd->data[1] = upper_32_bits(paddr); |
Joerg Roedel | 815b33f | 2011-04-06 17:26:49 +0200 | [diff] [blame] | 874 | cmd->data[2] = 1; |
Joerg Roedel | ded4673 | 2011-04-06 10:53:48 +0200 | [diff] [blame] | 875 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
| 876 | } |
| 877 | |
Joerg Roedel | 94fe79e | 2011-04-06 11:07:21 +0200 | [diff] [blame] | 878 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
| 879 | { |
| 880 | memset(cmd, 0, sizeof(*cmd)); |
| 881 | cmd->data[0] = devid; |
| 882 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); |
| 883 | } |
| 884 | |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 885 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
| 886 | size_t size, u16 domid, int pde) |
| 887 | { |
| 888 | u64 pages; |
Quentin Lambert | ae0cbbb | 2015-02-04 11:40:07 +0100 | [diff] [blame] | 889 | bool s; |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 890 | |
| 891 | pages = iommu_num_pages(address, size, PAGE_SIZE); |
Quentin Lambert | ae0cbbb | 2015-02-04 11:40:07 +0100 | [diff] [blame] | 892 | s = false; |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 893 | |
| 894 | if (pages > 1) { |
| 895 | /* |
| 896 | * If we have to flush more than one page, flush all |
| 897 | * TLB entries for this domain |
| 898 | */ |
| 899 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; |
Quentin Lambert | ae0cbbb | 2015-02-04 11:40:07 +0100 | [diff] [blame] | 900 | s = true; |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 901 | } |
| 902 | |
| 903 | address &= PAGE_MASK; |
| 904 | |
| 905 | memset(cmd, 0, sizeof(*cmd)); |
| 906 | cmd->data[1] |= domid; |
| 907 | cmd->data[2] = lower_32_bits(address); |
| 908 | cmd->data[3] = upper_32_bits(address); |
| 909 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); |
| 910 | if (s) /* size bit - we flush more than one 4kb page */ |
| 911 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
Frank Arnold | df805ab | 2012-08-27 19:21:04 +0200 | [diff] [blame] | 912 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 913 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
| 914 | } |
| 915 | |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 916 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
| 917 | u64 address, size_t size) |
| 918 | { |
| 919 | u64 pages; |
Quentin Lambert | ae0cbbb | 2015-02-04 11:40:07 +0100 | [diff] [blame] | 920 | bool s; |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 921 | |
| 922 | pages = iommu_num_pages(address, size, PAGE_SIZE); |
Quentin Lambert | ae0cbbb | 2015-02-04 11:40:07 +0100 | [diff] [blame] | 923 | s = false; |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 924 | |
| 925 | if (pages > 1) { |
| 926 | /* |
| 927 | * If we have to flush more than one page, flush all |
| 928 | * TLB entries for this domain |
| 929 | */ |
| 930 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; |
Quentin Lambert | ae0cbbb | 2015-02-04 11:40:07 +0100 | [diff] [blame] | 931 | s = true; |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 932 | } |
| 933 | |
| 934 | address &= PAGE_MASK; |
| 935 | |
| 936 | memset(cmd, 0, sizeof(*cmd)); |
| 937 | cmd->data[0] = devid; |
| 938 | cmd->data[0] |= (qdep & 0xff) << 24; |
| 939 | cmd->data[1] = devid; |
| 940 | cmd->data[2] = lower_32_bits(address); |
| 941 | cmd->data[3] = upper_32_bits(address); |
| 942 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); |
| 943 | if (s) |
| 944 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
| 945 | } |
| 946 | |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 947 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
| 948 | u64 address, bool size) |
| 949 | { |
| 950 | memset(cmd, 0, sizeof(*cmd)); |
| 951 | |
| 952 | address &= ~(0xfffULL); |
| 953 | |
Suravee Suthikulpanit | a919a01 | 2014-03-05 18:54:18 -0600 | [diff] [blame] | 954 | cmd->data[0] = pasid; |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 955 | cmd->data[1] = domid; |
| 956 | cmd->data[2] = lower_32_bits(address); |
| 957 | cmd->data[3] = upper_32_bits(address); |
| 958 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
| 959 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; |
| 960 | if (size) |
| 961 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
| 962 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); |
| 963 | } |
| 964 | |
| 965 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, |
| 966 | int qdep, u64 address, bool size) |
| 967 | { |
| 968 | memset(cmd, 0, sizeof(*cmd)); |
| 969 | |
| 970 | address &= ~(0xfffULL); |
| 971 | |
| 972 | cmd->data[0] = devid; |
Jay Cornwall | e8d2d82 | 2014-02-26 15:49:31 -0600 | [diff] [blame] | 973 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 974 | cmd->data[0] |= (qdep & 0xff) << 24; |
| 975 | cmd->data[1] = devid; |
Jay Cornwall | e8d2d82 | 2014-02-26 15:49:31 -0600 | [diff] [blame] | 976 | cmd->data[1] |= (pasid & 0xff) << 16; |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 977 | cmd->data[2] = lower_32_bits(address); |
| 978 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; |
| 979 | cmd->data[3] = upper_32_bits(address); |
| 980 | if (size) |
| 981 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; |
| 982 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); |
| 983 | } |
| 984 | |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 985 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
| 986 | int status, int tag, bool gn) |
| 987 | { |
| 988 | memset(cmd, 0, sizeof(*cmd)); |
| 989 | |
| 990 | cmd->data[0] = devid; |
| 991 | if (gn) { |
Suravee Suthikulpanit | a919a01 | 2014-03-05 18:54:18 -0600 | [diff] [blame] | 992 | cmd->data[1] = pasid; |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 993 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
| 994 | } |
| 995 | cmd->data[3] = tag & 0x1ff; |
| 996 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; |
| 997 | |
| 998 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); |
| 999 | } |
| 1000 | |
Joerg Roedel | 58fc7f1 | 2011-04-11 11:13:24 +0200 | [diff] [blame] | 1001 | static void build_inv_all(struct iommu_cmd *cmd) |
| 1002 | { |
| 1003 | memset(cmd, 0, sizeof(*cmd)); |
| 1004 | CMD_SET_TYPE(cmd, CMD_INV_ALL); |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1005 | } |
| 1006 | |
Joerg Roedel | 7ef2798 | 2012-06-21 16:46:04 +0200 | [diff] [blame] | 1007 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
| 1008 | { |
| 1009 | memset(cmd, 0, sizeof(*cmd)); |
| 1010 | cmd->data[0] = devid; |
| 1011 | CMD_SET_TYPE(cmd, CMD_INV_IRT); |
| 1012 | } |
| 1013 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1014 | /* |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 1015 | * Writes the command to the IOMMUs command buffer and informs the |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 1016 | * hardware about the new command. |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1017 | */ |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1018 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
| 1019 | struct iommu_cmd *cmd, |
| 1020 | bool sync) |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1021 | { |
Tom Lendacky | 23e967e | 2017-06-05 14:52:26 -0500 | [diff] [blame] | 1022 | unsigned int count = 0; |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 1023 | u32 left, next_tail; |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1024 | |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 1025 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 1026 | again: |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 1027 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 1028 | |
Huang Rui | 432abf6 | 2016-12-12 07:28:26 -0500 | [diff] [blame] | 1029 | if (left <= 0x20) { |
Tom Lendacky | 23e967e | 2017-06-05 14:52:26 -0500 | [diff] [blame] | 1030 | /* Skip udelay() the first time around */ |
| 1031 | if (count++) { |
| 1032 | if (count == LOOP_TIMEOUT) { |
| 1033 | pr_err("AMD-Vi: Command buffer timeout\n"); |
| 1034 | return -EIO; |
| 1035 | } |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 1036 | |
Tom Lendacky | 23e967e | 2017-06-05 14:52:26 -0500 | [diff] [blame] | 1037 | udelay(1); |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 1038 | } |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1039 | |
Tom Lendacky | 23e967e | 2017-06-05 14:52:26 -0500 | [diff] [blame] | 1040 | /* Update head and recheck remaining space */ |
| 1041 | iommu->cmd_buf_head = readl(iommu->mmio_base + |
| 1042 | MMIO_CMD_HEAD_OFFSET); |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 1043 | |
| 1044 | goto again; |
Joerg Roedel | 136f78a | 2008-07-11 17:14:27 +0200 | [diff] [blame] | 1045 | } |
| 1046 | |
Tom Lendacky | d334a56 | 2017-06-05 14:52:12 -0500 | [diff] [blame] | 1047 | copy_cmd_to_buffer(iommu, cmd); |
Joerg Roedel | 519c31b | 2008-08-14 19:55:15 +0200 | [diff] [blame] | 1048 | |
Tom Lendacky | 23e967e | 2017-06-05 14:52:26 -0500 | [diff] [blame] | 1049 | /* Do we need to make sure all commands are processed? */ |
Joerg Roedel | f1ca151 | 2011-09-02 14:10:32 +0200 | [diff] [blame] | 1050 | iommu->need_sync = sync; |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 1051 | |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1052 | return 0; |
| 1053 | } |
| 1054 | |
| 1055 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
| 1056 | struct iommu_cmd *cmd, |
| 1057 | bool sync) |
| 1058 | { |
| 1059 | unsigned long flags; |
| 1060 | int ret; |
| 1061 | |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 1062 | raw_spin_lock_irqsave(&iommu->lock, flags); |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1063 | ret = __iommu_queue_command_sync(iommu, cmd, sync); |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 1064 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1065 | |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1066 | return ret; |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1067 | } |
| 1068 | |
Joerg Roedel | f1ca151 | 2011-09-02 14:10:32 +0200 | [diff] [blame] | 1069 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
| 1070 | { |
| 1071 | return iommu_queue_command_sync(iommu, cmd, true); |
| 1072 | } |
| 1073 | |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1074 | /* |
| 1075 | * This function queues a completion wait command into the command |
| 1076 | * buffer of an IOMMU |
| 1077 | */ |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1078 | static int iommu_completion_wait(struct amd_iommu *iommu) |
| 1079 | { |
Joerg Roedel | 815b33f | 2011-04-06 17:26:49 +0200 | [diff] [blame] | 1080 | struct iommu_cmd cmd; |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1081 | unsigned long flags; |
Joerg Roedel | ac0ea6e | 2011-04-06 18:38:20 +0200 | [diff] [blame] | 1082 | int ret; |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1083 | |
| 1084 | if (!iommu->need_sync) |
Joerg Roedel | 815b33f | 2011-04-06 17:26:49 +0200 | [diff] [blame] | 1085 | return 0; |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1086 | |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1087 | |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1088 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); |
| 1089 | |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 1090 | raw_spin_lock_irqsave(&iommu->lock, flags); |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1091 | |
| 1092 | iommu->cmd_sem = 0; |
| 1093 | |
| 1094 | ret = __iommu_queue_command_sync(iommu, &cmd, false); |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1095 | if (ret) |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1096 | goto out_unlock; |
Joerg Roedel | 8d20196 | 2008-12-02 20:34:41 +0100 | [diff] [blame] | 1097 | |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1098 | ret = wait_on_sem(&iommu->cmd_sem); |
| 1099 | |
| 1100 | out_unlock: |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 1101 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
Joerg Roedel | 4bf5bee | 2016-09-14 11:41:59 +0200 | [diff] [blame] | 1102 | |
| 1103 | return ret; |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1104 | } |
| 1105 | |
Joerg Roedel | d8c1308 | 2011-04-06 18:51:26 +0200 | [diff] [blame] | 1106 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1107 | { |
| 1108 | struct iommu_cmd cmd; |
| 1109 | |
Joerg Roedel | d8c1308 | 2011-04-06 18:51:26 +0200 | [diff] [blame] | 1110 | build_inv_dte(&cmd, devid); |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1111 | |
Joerg Roedel | d8c1308 | 2011-04-06 18:51:26 +0200 | [diff] [blame] | 1112 | return iommu_queue_command(iommu, &cmd); |
| 1113 | } |
| 1114 | |
Joerg Roedel | 0688a09 | 2017-08-23 15:50:03 +0200 | [diff] [blame] | 1115 | static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) |
Joerg Roedel | 7d0c5cc | 2011-04-07 08:16:10 +0200 | [diff] [blame] | 1116 | { |
| 1117 | u32 devid; |
| 1118 | |
| 1119 | for (devid = 0; devid <= 0xffff; ++devid) |
| 1120 | iommu_flush_dte(iommu, devid); |
| 1121 | |
| 1122 | iommu_completion_wait(iommu); |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1123 | } |
| 1124 | |
| 1125 | /* |
Joerg Roedel | 7d0c5cc | 2011-04-07 08:16:10 +0200 | [diff] [blame] | 1126 | * This function uses heavy locking and may disable irqs for some time. But |
| 1127 | * this is no issue because it is only called during resume. |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1128 | */ |
Joerg Roedel | 0688a09 | 2017-08-23 15:50:03 +0200 | [diff] [blame] | 1129 | static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1130 | { |
Joerg Roedel | 7d0c5cc | 2011-04-07 08:16:10 +0200 | [diff] [blame] | 1131 | u32 dom_id; |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1132 | |
Joerg Roedel | 7d0c5cc | 2011-04-07 08:16:10 +0200 | [diff] [blame] | 1133 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
| 1134 | struct iommu_cmd cmd; |
| 1135 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
| 1136 | dom_id, 1); |
| 1137 | iommu_queue_command(iommu, &cmd); |
| 1138 | } |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1139 | |
Joerg Roedel | 7d0c5cc | 2011-04-07 08:16:10 +0200 | [diff] [blame] | 1140 | iommu_completion_wait(iommu); |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1141 | } |
| 1142 | |
Joerg Roedel | 0688a09 | 2017-08-23 15:50:03 +0200 | [diff] [blame] | 1143 | static void amd_iommu_flush_all(struct amd_iommu *iommu) |
Joerg Roedel | 58fc7f1 | 2011-04-11 11:13:24 +0200 | [diff] [blame] | 1144 | { |
| 1145 | struct iommu_cmd cmd; |
| 1146 | |
| 1147 | build_inv_all(&cmd); |
| 1148 | |
| 1149 | iommu_queue_command(iommu, &cmd); |
| 1150 | iommu_completion_wait(iommu); |
| 1151 | } |
| 1152 | |
Joerg Roedel | 7ef2798 | 2012-06-21 16:46:04 +0200 | [diff] [blame] | 1153 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
| 1154 | { |
| 1155 | struct iommu_cmd cmd; |
| 1156 | |
| 1157 | build_inv_irt(&cmd, devid); |
| 1158 | |
| 1159 | iommu_queue_command(iommu, &cmd); |
| 1160 | } |
| 1161 | |
Joerg Roedel | 0688a09 | 2017-08-23 15:50:03 +0200 | [diff] [blame] | 1162 | static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) |
Joerg Roedel | 7ef2798 | 2012-06-21 16:46:04 +0200 | [diff] [blame] | 1163 | { |
| 1164 | u32 devid; |
| 1165 | |
| 1166 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) |
| 1167 | iommu_flush_irt(iommu, devid); |
| 1168 | |
| 1169 | iommu_completion_wait(iommu); |
| 1170 | } |
| 1171 | |
Joerg Roedel | 7d0c5cc | 2011-04-07 08:16:10 +0200 | [diff] [blame] | 1172 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
| 1173 | { |
Joerg Roedel | 58fc7f1 | 2011-04-11 11:13:24 +0200 | [diff] [blame] | 1174 | if (iommu_feature(iommu, FEATURE_IA)) { |
Joerg Roedel | 0688a09 | 2017-08-23 15:50:03 +0200 | [diff] [blame] | 1175 | amd_iommu_flush_all(iommu); |
Joerg Roedel | 58fc7f1 | 2011-04-11 11:13:24 +0200 | [diff] [blame] | 1176 | } else { |
Joerg Roedel | 0688a09 | 2017-08-23 15:50:03 +0200 | [diff] [blame] | 1177 | amd_iommu_flush_dte_all(iommu); |
| 1178 | amd_iommu_flush_irt_all(iommu); |
| 1179 | amd_iommu_flush_tlb_all(iommu); |
Joerg Roedel | 58fc7f1 | 2011-04-11 11:13:24 +0200 | [diff] [blame] | 1180 | } |
Joerg Roedel | 7d0c5cc | 2011-04-07 08:16:10 +0200 | [diff] [blame] | 1181 | } |
| 1182 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1183 | /* |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1184 | * Command send function for flushing on-device TLB |
| 1185 | */ |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1186 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
| 1187 | u64 address, size_t size) |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1188 | { |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1189 | struct amd_iommu *iommu; |
| 1190 | struct iommu_cmd cmd; |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1191 | int qdep; |
| 1192 | |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 1193 | qdep = dev_data->ats.qdep; |
| 1194 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1195 | |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 1196 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1197 | |
| 1198 | return iommu_queue_command(iommu, &cmd); |
| 1199 | } |
| 1200 | |
| 1201 | /* |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1202 | * Command send function for invalidating a device table entry |
| 1203 | */ |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1204 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
Joerg Roedel | 3fa4365 | 2009-11-26 15:04:38 +0100 | [diff] [blame] | 1205 | { |
| 1206 | struct amd_iommu *iommu; |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1207 | u16 alias; |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1208 | int ret; |
Joerg Roedel | 3fa4365 | 2009-11-26 15:04:38 +0100 | [diff] [blame] | 1209 | |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1210 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 1211 | alias = dev_data->alias; |
Joerg Roedel | 3fa4365 | 2009-11-26 15:04:38 +0100 | [diff] [blame] | 1212 | |
Joerg Roedel | f62dda6 | 2011-06-09 12:55:35 +0200 | [diff] [blame] | 1213 | ret = iommu_flush_dte(iommu, dev_data->devid); |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1214 | if (!ret && alias != dev_data->devid) |
| 1215 | ret = iommu_flush_dte(iommu, alias); |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1216 | if (ret) |
| 1217 | return ret; |
| 1218 | |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 1219 | if (dev_data->ats.enabled) |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1220 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1221 | |
| 1222 | return ret; |
Joerg Roedel | 3fa4365 | 2009-11-26 15:04:38 +0100 | [diff] [blame] | 1223 | } |
| 1224 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1225 | /* |
| 1226 | * TLB invalidation function which is called from the mapping functions. |
| 1227 | * It invalidates a single PTE if the range to flush is within a single |
| 1228 | * page. Otherwise it flushes the whole TLB of the IOMMU. |
| 1229 | */ |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1230 | static void __domain_flush_pages(struct protection_domain *domain, |
| 1231 | u64 address, size_t size, int pde) |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1232 | { |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1233 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 1234 | struct iommu_cmd cmd; |
| 1235 | int ret = 0, i; |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1236 | |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 1237 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
Joerg Roedel | 999ba41 | 2008-07-03 19:35:08 +0200 | [diff] [blame] | 1238 | |
Suravee Suthikulpanit | 6b9376e | 2017-02-24 02:48:17 -0600 | [diff] [blame] | 1239 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
Joerg Roedel | 6de8ad9 | 2009-11-23 18:30:32 +0100 | [diff] [blame] | 1240 | if (!domain->dev_iommu[i]) |
| 1241 | continue; |
| 1242 | |
| 1243 | /* |
| 1244 | * Devices of this domain are behind this IOMMU |
| 1245 | * We need a TLB flush |
| 1246 | */ |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 1247 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
Joerg Roedel | 6de8ad9 | 2009-11-23 18:30:32 +0100 | [diff] [blame] | 1248 | } |
| 1249 | |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1250 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1251 | |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 1252 | if (!dev_data->ats.enabled) |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1253 | continue; |
| 1254 | |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1255 | ret |= device_flush_iotlb(dev_data, address, size); |
Joerg Roedel | cb41ed8 | 2011-04-05 11:00:53 +0200 | [diff] [blame] | 1256 | } |
| 1257 | |
Joerg Roedel | 11b6402 | 2011-04-06 11:49:28 +0200 | [diff] [blame] | 1258 | WARN_ON(ret); |
Joerg Roedel | 6de8ad9 | 2009-11-23 18:30:32 +0100 | [diff] [blame] | 1259 | } |
| 1260 | |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1261 | static void domain_flush_pages(struct protection_domain *domain, |
| 1262 | u64 address, size_t size) |
Joerg Roedel | 6de8ad9 | 2009-11-23 18:30:32 +0100 | [diff] [blame] | 1263 | { |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1264 | __domain_flush_pages(domain, address, size, 0); |
Joerg Roedel | a19ae1e | 2008-06-26 21:27:55 +0200 | [diff] [blame] | 1265 | } |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 1266 | |
Joerg Roedel | 1c65577 | 2008-09-04 18:40:05 +0200 | [diff] [blame] | 1267 | /* Flush the whole IO/TLB for a given protection domain */ |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1268 | static void domain_flush_tlb(struct protection_domain *domain) |
Joerg Roedel | 1c65577 | 2008-09-04 18:40:05 +0200 | [diff] [blame] | 1269 | { |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1270 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
Joerg Roedel | 1c65577 | 2008-09-04 18:40:05 +0200 | [diff] [blame] | 1271 | } |
| 1272 | |
Chris Wright | 42a49f9 | 2009-06-15 15:42:00 +0200 | [diff] [blame] | 1273 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1274 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
Chris Wright | 42a49f9 | 2009-06-15 15:42:00 +0200 | [diff] [blame] | 1275 | { |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1276 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
| 1277 | } |
| 1278 | |
| 1279 | static void domain_flush_complete(struct protection_domain *domain) |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 1280 | { |
| 1281 | int i; |
| 1282 | |
Suravee Suthikulpanit | 6b9376e | 2017-02-24 02:48:17 -0600 | [diff] [blame] | 1283 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
Joerg Roedel | f1eae7c | 2016-07-06 12:50:35 +0200 | [diff] [blame] | 1284 | if (domain && !domain->dev_iommu[i]) |
Joerg Roedel | b6c0271 | 2008-06-26 21:27:53 +0200 | [diff] [blame] | 1285 | continue; |
| 1286 | |
| 1287 | /* |
| 1288 | * Devices of this domain are behind this IOMMU |
| 1289 | * We need to wait for completion of all commands. |
| 1290 | */ |
| 1291 | iommu_completion_wait(amd_iommus[i]); |
| 1292 | } |
| 1293 | } |
| 1294 | |
Joerg Roedel | b00d3bc | 2009-11-26 15:35:33 +0100 | [diff] [blame] | 1295 | |
Joerg Roedel | 43f4960 | 2008-12-02 21:01:12 +0100 | [diff] [blame] | 1296 | /* |
Joerg Roedel | b00d3bc | 2009-11-26 15:35:33 +0100 | [diff] [blame] | 1297 | * This function flushes the DTEs for all devices in domain |
Joerg Roedel | 43f4960 | 2008-12-02 21:01:12 +0100 | [diff] [blame] | 1298 | */ |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 1299 | static void domain_flush_devices(struct protection_domain *domain) |
Joerg Roedel | bfd1be1 | 2009-05-05 15:33:57 +0200 | [diff] [blame] | 1300 | { |
Joerg Roedel | b00d3bc | 2009-11-26 15:35:33 +0100 | [diff] [blame] | 1301 | struct iommu_dev_data *dev_data; |
Joerg Roedel | b00d3bc | 2009-11-26 15:35:33 +0100 | [diff] [blame] | 1302 | |
| 1303 | list_for_each_entry(dev_data, &domain->dev_list, list) |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1304 | device_flush_dte(dev_data); |
Joerg Roedel | b00d3bc | 2009-11-26 15:35:33 +0100 | [diff] [blame] | 1305 | } |
| 1306 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1307 | /**************************************************************************** |
| 1308 | * |
| 1309 | * The functions below are used the create the page table mappings for |
| 1310 | * unity mapped regions. |
| 1311 | * |
| 1312 | ****************************************************************************/ |
| 1313 | |
| 1314 | /* |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1315 | * This function is used to add another level to an IO page table. Adding |
| 1316 | * another level increases the size of the address space by 9 bits to a size up |
| 1317 | * to 64 bits. |
| 1318 | */ |
| 1319 | static bool increase_address_space(struct protection_domain *domain, |
| 1320 | gfp_t gfp) |
| 1321 | { |
| 1322 | u64 *pte; |
| 1323 | |
| 1324 | if (domain->mode == PAGE_MODE_6_LEVEL) |
| 1325 | /* address space already 64 bit large */ |
| 1326 | return false; |
| 1327 | |
| 1328 | pte = (void *)get_zeroed_page(gfp); |
| 1329 | if (!pte) |
| 1330 | return false; |
| 1331 | |
| 1332 | *pte = PM_LEVEL_PDE(domain->mode, |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 1333 | iommu_virt_to_phys(domain->pt_root)); |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1334 | domain->pt_root = pte; |
| 1335 | domain->mode += 1; |
| 1336 | domain->updated = true; |
| 1337 | |
| 1338 | return true; |
| 1339 | } |
| 1340 | |
| 1341 | static u64 *alloc_pte(struct protection_domain *domain, |
| 1342 | unsigned long address, |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1343 | unsigned long page_size, |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1344 | u64 **pte_page, |
| 1345 | gfp_t gfp) |
| 1346 | { |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1347 | int level, end_lvl; |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1348 | u64 *pte, *page; |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1349 | |
| 1350 | BUG_ON(!is_power_of_2(page_size)); |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1351 | |
| 1352 | while (address > PM_LEVEL_SIZE(domain->mode)) |
| 1353 | increase_address_space(domain, gfp); |
| 1354 | |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1355 | level = domain->mode - 1; |
| 1356 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; |
| 1357 | address = PAGE_SIZE_ALIGN(address, page_size); |
| 1358 | end_lvl = PAGE_SIZE_LEVEL(page_size); |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1359 | |
| 1360 | while (level > end_lvl) { |
Joerg Roedel | 7bfa5bd | 2015-12-21 19:07:50 +0100 | [diff] [blame] | 1361 | u64 __pte, __npte; |
| 1362 | |
| 1363 | __pte = *pte; |
| 1364 | |
| 1365 | if (!IOMMU_PTE_PRESENT(__pte)) { |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1366 | page = (u64 *)get_zeroed_page(gfp); |
| 1367 | if (!page) |
| 1368 | return NULL; |
Joerg Roedel | 7bfa5bd | 2015-12-21 19:07:50 +0100 | [diff] [blame] | 1369 | |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 1370 | __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page)); |
Joerg Roedel | 7bfa5bd | 2015-12-21 19:07:50 +0100 | [diff] [blame] | 1371 | |
Baoquan He | 134414f | 2016-09-15 16:50:50 +0800 | [diff] [blame] | 1372 | /* pte could have been changed somewhere. */ |
| 1373 | if (cmpxchg64(pte, __pte, __npte) != __pte) { |
Joerg Roedel | 7bfa5bd | 2015-12-21 19:07:50 +0100 | [diff] [blame] | 1374 | free_page((unsigned long)page); |
| 1375 | continue; |
| 1376 | } |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1377 | } |
| 1378 | |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1379 | /* No level skipping support yet */ |
| 1380 | if (PM_PTE_LEVEL(*pte) != level) |
| 1381 | return NULL; |
| 1382 | |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1383 | level -= 1; |
| 1384 | |
| 1385 | pte = IOMMU_PTE_PAGE(*pte); |
| 1386 | |
| 1387 | if (pte_page && level == end_lvl) |
| 1388 | *pte_page = pte; |
| 1389 | |
| 1390 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
| 1391 | } |
| 1392 | |
| 1393 | return pte; |
| 1394 | } |
| 1395 | |
| 1396 | /* |
| 1397 | * This function checks if there is a PTE for a given dma address. If |
| 1398 | * there is one, it returns the pointer to it. |
| 1399 | */ |
Joerg Roedel | 3039ca1 | 2015-04-01 14:58:48 +0200 | [diff] [blame] | 1400 | static u64 *fetch_pte(struct protection_domain *domain, |
| 1401 | unsigned long address, |
| 1402 | unsigned long *page_size) |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1403 | { |
| 1404 | int level; |
| 1405 | u64 *pte; |
| 1406 | |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1407 | if (address > PM_LEVEL_SIZE(domain->mode)) |
| 1408 | return NULL; |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1409 | |
Joerg Roedel | 3039ca1 | 2015-04-01 14:58:48 +0200 | [diff] [blame] | 1410 | level = domain->mode - 1; |
| 1411 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; |
| 1412 | *page_size = PTE_LEVEL_PAGE_SIZE(level); |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1413 | |
| 1414 | while (level > 0) { |
| 1415 | |
| 1416 | /* Not Present */ |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1417 | if (!IOMMU_PTE_PRESENT(*pte)) |
| 1418 | return NULL; |
| 1419 | |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1420 | /* Large PTE */ |
Joerg Roedel | 3039ca1 | 2015-04-01 14:58:48 +0200 | [diff] [blame] | 1421 | if (PM_PTE_LEVEL(*pte) == 7 || |
| 1422 | PM_PTE_LEVEL(*pte) == 0) |
| 1423 | break; |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1424 | |
| 1425 | /* No level skipping support yet */ |
| 1426 | if (PM_PTE_LEVEL(*pte) != level) |
| 1427 | return NULL; |
| 1428 | |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1429 | level -= 1; |
| 1430 | |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1431 | /* Walk to the next level */ |
Joerg Roedel | 3039ca1 | 2015-04-01 14:58:48 +0200 | [diff] [blame] | 1432 | pte = IOMMU_PTE_PAGE(*pte); |
| 1433 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
| 1434 | *page_size = PTE_LEVEL_PAGE_SIZE(level); |
| 1435 | } |
| 1436 | |
| 1437 | if (PM_PTE_LEVEL(*pte) == 0x07) { |
| 1438 | unsigned long pte_mask; |
| 1439 | |
| 1440 | /* |
| 1441 | * If we have a series of large PTEs, make |
| 1442 | * sure to return a pointer to the first one. |
| 1443 | */ |
| 1444 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); |
| 1445 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); |
| 1446 | pte = (u64 *)(((unsigned long)pte) & pte_mask); |
Joerg Roedel | 308973d | 2009-11-24 17:43:32 +0100 | [diff] [blame] | 1447 | } |
| 1448 | |
| 1449 | return pte; |
| 1450 | } |
| 1451 | |
| 1452 | /* |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1453 | * Generic mapping functions. It maps a physical address into a DMA |
| 1454 | * address space. It allocates the page table pages if necessary. |
| 1455 | * In the future it can be extended to a generic mapping function |
| 1456 | * supporting all features of AMD IOMMU page tables like level skipping |
| 1457 | * and full 64 bit address spaces. |
| 1458 | */ |
Joerg Roedel | 38e817f | 2008-12-02 17:27:52 +0100 | [diff] [blame] | 1459 | static int iommu_map_page(struct protection_domain *dom, |
| 1460 | unsigned long bus_addr, |
| 1461 | unsigned long phys_addr, |
Joerg Roedel | b911b89 | 2016-07-05 14:29:11 +0200 | [diff] [blame] | 1462 | unsigned long page_size, |
Joerg Roedel | abdc5eb | 2009-09-03 11:33:51 +0200 | [diff] [blame] | 1463 | int prot, |
Joerg Roedel | b911b89 | 2016-07-05 14:29:11 +0200 | [diff] [blame] | 1464 | gfp_t gfp) |
Joerg Roedel | bd0e521 | 2008-06-26 21:27:56 +0200 | [diff] [blame] | 1465 | { |
Joerg Roedel | 8bda309 | 2009-05-12 12:02:46 +0200 | [diff] [blame] | 1466 | u64 __pte, *pte; |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1467 | int i, count; |
Joerg Roedel | abdc5eb | 2009-09-03 11:33:51 +0200 | [diff] [blame] | 1468 | |
Joerg Roedel | d4b0366 | 2015-04-01 14:58:52 +0200 | [diff] [blame] | 1469 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
| 1470 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); |
| 1471 | |
Joerg Roedel | bad1cac | 2009-09-02 16:52:23 +0200 | [diff] [blame] | 1472 | if (!(prot & IOMMU_PROT_MASK)) |
Joerg Roedel | bd0e521 | 2008-06-26 21:27:56 +0200 | [diff] [blame] | 1473 | return -EINVAL; |
| 1474 | |
Joerg Roedel | d4b0366 | 2015-04-01 14:58:52 +0200 | [diff] [blame] | 1475 | count = PAGE_SIZE_PTE_COUNT(page_size); |
Joerg Roedel | b911b89 | 2016-07-05 14:29:11 +0200 | [diff] [blame] | 1476 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
Joerg Roedel | bd0e521 | 2008-06-26 21:27:56 +0200 | [diff] [blame] | 1477 | |
Maurizio Lombardi | 63eaa75 | 2014-09-11 12:28:03 +0200 | [diff] [blame] | 1478 | if (!pte) |
| 1479 | return -ENOMEM; |
| 1480 | |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1481 | for (i = 0; i < count; ++i) |
| 1482 | if (IOMMU_PTE_PRESENT(pte[i])) |
| 1483 | return -EBUSY; |
Joerg Roedel | bd0e521 | 2008-06-26 21:27:56 +0200 | [diff] [blame] | 1484 | |
Joerg Roedel | d4b0366 | 2015-04-01 14:58:52 +0200 | [diff] [blame] | 1485 | if (count > 1) { |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 1486 | __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size); |
Baoquan He | 07a80a6 | 2017-08-09 16:33:36 +0800 | [diff] [blame] | 1487 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1488 | } else |
Linus Torvalds | 4dfc278 | 2017-09-09 15:03:24 -0700 | [diff] [blame] | 1489 | __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1490 | |
Joerg Roedel | bd0e521 | 2008-06-26 21:27:56 +0200 | [diff] [blame] | 1491 | if (prot & IOMMU_PROT_IR) |
| 1492 | __pte |= IOMMU_PTE_IR; |
| 1493 | if (prot & IOMMU_PROT_IW) |
| 1494 | __pte |= IOMMU_PTE_IW; |
| 1495 | |
Joerg Roedel | cbb9d72 | 2010-01-15 14:41:15 +0100 | [diff] [blame] | 1496 | for (i = 0; i < count; ++i) |
| 1497 | pte[i] = __pte; |
Joerg Roedel | bd0e521 | 2008-06-26 21:27:56 +0200 | [diff] [blame] | 1498 | |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 1499 | update_domain(dom); |
| 1500 | |
Joerg Roedel | bd0e521 | 2008-06-26 21:27:56 +0200 | [diff] [blame] | 1501 | return 0; |
| 1502 | } |
| 1503 | |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1504 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
| 1505 | unsigned long bus_addr, |
| 1506 | unsigned long page_size) |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 1507 | { |
Joerg Roedel | 71b390e | 2015-04-01 14:58:49 +0200 | [diff] [blame] | 1508 | unsigned long long unmapped; |
| 1509 | unsigned long unmap_size; |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1510 | u64 *pte; |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 1511 | |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1512 | BUG_ON(!is_power_of_2(page_size)); |
| 1513 | |
| 1514 | unmapped = 0; |
| 1515 | |
| 1516 | while (unmapped < page_size) { |
| 1517 | |
Joerg Roedel | 71b390e | 2015-04-01 14:58:49 +0200 | [diff] [blame] | 1518 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1519 | |
Joerg Roedel | 71b390e | 2015-04-01 14:58:49 +0200 | [diff] [blame] | 1520 | if (pte) { |
| 1521 | int i, count; |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1522 | |
Joerg Roedel | 71b390e | 2015-04-01 14:58:49 +0200 | [diff] [blame] | 1523 | count = PAGE_SIZE_PTE_COUNT(unmap_size); |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1524 | for (i = 0; i < count; i++) |
| 1525 | pte[i] = 0ULL; |
| 1526 | } |
| 1527 | |
| 1528 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; |
| 1529 | unmapped += unmap_size; |
| 1530 | } |
| 1531 | |
Alex Williamson | 60d0ca3 | 2013-06-21 14:33:19 -0600 | [diff] [blame] | 1532 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
Joerg Roedel | 24cd772 | 2010-01-19 17:27:39 +0100 | [diff] [blame] | 1533 | |
| 1534 | return unmapped; |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 1535 | } |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 1536 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1537 | /**************************************************************************** |
| 1538 | * |
| 1539 | * The next functions belong to the address allocator for the dma_ops |
Joerg Roedel | 2d4c515 | 2016-07-05 16:21:32 +0200 | [diff] [blame] | 1540 | * interface functions. |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1541 | * |
| 1542 | ****************************************************************************/ |
Joerg Roedel | d308644 | 2008-06-26 21:27:57 +0200 | [diff] [blame] | 1543 | |
Joerg Roedel | 9cabe89 | 2009-05-18 16:38:55 +0200 | [diff] [blame] | 1544 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1545 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
| 1546 | struct dma_ops_domain *dma_dom, |
| 1547 | unsigned int pages, u64 dma_mask) |
Joerg Roedel | a0f5144 | 2015-12-21 16:20:09 +0100 | [diff] [blame] | 1548 | { |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1549 | unsigned long pfn = 0; |
Joerg Roedel | a0f5144 | 2015-12-21 16:20:09 +0100 | [diff] [blame] | 1550 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1551 | pages = __roundup_pow_of_two(pages); |
Joerg Roedel | a0f5144 | 2015-12-21 16:20:09 +0100 | [diff] [blame] | 1552 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1553 | if (dma_mask > DMA_BIT_MASK(32)) |
| 1554 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, |
Tomasz Nowicki | 538d5b3 | 2017-09-20 10:52:02 +0200 | [diff] [blame] | 1555 | IOVA_PFN(DMA_BIT_MASK(32)), false); |
Joerg Roedel | 7b5e25b | 2015-12-22 13:38:12 +0100 | [diff] [blame] | 1556 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1557 | if (!pfn) |
Tomasz Nowicki | 538d5b3 | 2017-09-20 10:52:02 +0200 | [diff] [blame] | 1558 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, |
| 1559 | IOVA_PFN(dma_mask), true); |
Joerg Roedel | 60e6a7c | 2015-12-21 16:53:17 +0100 | [diff] [blame] | 1560 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1561 | return (pfn << PAGE_SHIFT); |
Joerg Roedel | a0f5144 | 2015-12-21 16:20:09 +0100 | [diff] [blame] | 1562 | } |
| 1563 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1564 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
| 1565 | unsigned long address, |
| 1566 | unsigned int pages) |
Joerg Roedel | 384de72 | 2009-05-15 12:30:05 +0200 | [diff] [blame] | 1567 | { |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1568 | pages = __roundup_pow_of_two(pages); |
| 1569 | address >>= PAGE_SHIFT; |
Joerg Roedel | 5f6bed5 | 2015-12-22 13:34:22 +0100 | [diff] [blame] | 1570 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 1571 | free_iova_fast(&dma_dom->iovad, address, pages); |
Joerg Roedel | d308644 | 2008-06-26 21:27:57 +0200 | [diff] [blame] | 1572 | } |
| 1573 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1574 | /**************************************************************************** |
| 1575 | * |
| 1576 | * The next functions belong to the domain allocation. A domain is |
| 1577 | * allocated for every IOMMU as the default domain. If device isolation |
| 1578 | * is enabled, every device get its own domain. The most important thing |
| 1579 | * about domains is the page table mapping the DMA address space they |
| 1580 | * contain. |
| 1581 | * |
| 1582 | ****************************************************************************/ |
| 1583 | |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 1584 | /* |
| 1585 | * This function adds a protection domain to the global protection domain list |
| 1586 | */ |
| 1587 | static void add_domain_to_list(struct protection_domain *domain) |
| 1588 | { |
| 1589 | unsigned long flags; |
| 1590 | |
| 1591 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
| 1592 | list_add(&domain->list, &amd_iommu_pd_list); |
| 1593 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
| 1594 | } |
| 1595 | |
| 1596 | /* |
| 1597 | * This function removes a protection domain to the global |
| 1598 | * protection domain list |
| 1599 | */ |
| 1600 | static void del_domain_from_list(struct protection_domain *domain) |
| 1601 | { |
| 1602 | unsigned long flags; |
| 1603 | |
| 1604 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
| 1605 | list_del(&domain->list); |
| 1606 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
| 1607 | } |
| 1608 | |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1609 | static u16 domain_id_alloc(void) |
| 1610 | { |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1611 | int id; |
| 1612 | |
Sebastian Andrzej Siewior | 2bc0018 | 2018-03-22 16:22:35 +0100 | [diff] [blame] | 1613 | spin_lock(&pd_bitmap_lock); |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1614 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); |
| 1615 | BUG_ON(id == 0); |
| 1616 | if (id > 0 && id < MAX_DOMAIN_ID) |
| 1617 | __set_bit(id, amd_iommu_pd_alloc_bitmap); |
| 1618 | else |
| 1619 | id = 0; |
Sebastian Andrzej Siewior | 2bc0018 | 2018-03-22 16:22:35 +0100 | [diff] [blame] | 1620 | spin_unlock(&pd_bitmap_lock); |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1621 | |
| 1622 | return id; |
| 1623 | } |
| 1624 | |
Joerg Roedel | a2acfb7 | 2008-12-02 18:28:53 +0100 | [diff] [blame] | 1625 | static void domain_id_free(int id) |
| 1626 | { |
Sebastian Andrzej Siewior | 2bc0018 | 2018-03-22 16:22:35 +0100 | [diff] [blame] | 1627 | spin_lock(&pd_bitmap_lock); |
Joerg Roedel | a2acfb7 | 2008-12-02 18:28:53 +0100 | [diff] [blame] | 1628 | if (id > 0 && id < MAX_DOMAIN_ID) |
| 1629 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); |
Sebastian Andrzej Siewior | 2bc0018 | 2018-03-22 16:22:35 +0100 | [diff] [blame] | 1630 | spin_unlock(&pd_bitmap_lock); |
Joerg Roedel | a2acfb7 | 2008-12-02 18:28:53 +0100 | [diff] [blame] | 1631 | } |
Joerg Roedel | a2acfb7 | 2008-12-02 18:28:53 +0100 | [diff] [blame] | 1632 | |
Joerg Roedel | 5c34c40 | 2013-06-20 20:22:58 +0200 | [diff] [blame] | 1633 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
| 1634 | static void free_pt_##LVL (unsigned long __pt) \ |
| 1635 | { \ |
| 1636 | unsigned long p; \ |
| 1637 | u64 *pt; \ |
| 1638 | int i; \ |
| 1639 | \ |
| 1640 | pt = (u64 *)__pt; \ |
| 1641 | \ |
| 1642 | for (i = 0; i < 512; ++i) { \ |
Joerg Roedel | 0b3fff5 | 2015-06-18 10:48:34 +0200 | [diff] [blame] | 1643 | /* PTE present? */ \ |
Joerg Roedel | 5c34c40 | 2013-06-20 20:22:58 +0200 | [diff] [blame] | 1644 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
| 1645 | continue; \ |
| 1646 | \ |
Joerg Roedel | 0b3fff5 | 2015-06-18 10:48:34 +0200 | [diff] [blame] | 1647 | /* Large PTE? */ \ |
| 1648 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ |
| 1649 | PM_PTE_LEVEL(pt[i]) == 7) \ |
| 1650 | continue; \ |
| 1651 | \ |
Joerg Roedel | 5c34c40 | 2013-06-20 20:22:58 +0200 | [diff] [blame] | 1652 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
| 1653 | FN(p); \ |
| 1654 | } \ |
| 1655 | free_page((unsigned long)pt); \ |
| 1656 | } |
| 1657 | |
| 1658 | DEFINE_FREE_PT_FN(l2, free_page) |
| 1659 | DEFINE_FREE_PT_FN(l3, free_pt_l2) |
| 1660 | DEFINE_FREE_PT_FN(l4, free_pt_l3) |
| 1661 | DEFINE_FREE_PT_FN(l5, free_pt_l4) |
| 1662 | DEFINE_FREE_PT_FN(l6, free_pt_l5) |
| 1663 | |
Joerg Roedel | 86db2e5 | 2008-12-02 18:20:21 +0100 | [diff] [blame] | 1664 | static void free_pagetable(struct protection_domain *domain) |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1665 | { |
Joerg Roedel | 5c34c40 | 2013-06-20 20:22:58 +0200 | [diff] [blame] | 1666 | unsigned long root = (unsigned long)domain->pt_root; |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1667 | |
Joerg Roedel | 5c34c40 | 2013-06-20 20:22:58 +0200 | [diff] [blame] | 1668 | switch (domain->mode) { |
| 1669 | case PAGE_MODE_NONE: |
| 1670 | break; |
| 1671 | case PAGE_MODE_1_LEVEL: |
| 1672 | free_page(root); |
| 1673 | break; |
| 1674 | case PAGE_MODE_2_LEVEL: |
| 1675 | free_pt_l2(root); |
| 1676 | break; |
| 1677 | case PAGE_MODE_3_LEVEL: |
| 1678 | free_pt_l3(root); |
| 1679 | break; |
| 1680 | case PAGE_MODE_4_LEVEL: |
| 1681 | free_pt_l4(root); |
| 1682 | break; |
| 1683 | case PAGE_MODE_5_LEVEL: |
| 1684 | free_pt_l5(root); |
| 1685 | break; |
| 1686 | case PAGE_MODE_6_LEVEL: |
| 1687 | free_pt_l6(root); |
| 1688 | break; |
| 1689 | default: |
| 1690 | BUG(); |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1691 | } |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1692 | } |
| 1693 | |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 1694 | static void free_gcr3_tbl_level1(u64 *tbl) |
| 1695 | { |
| 1696 | u64 *ptr; |
| 1697 | int i; |
| 1698 | |
| 1699 | for (i = 0; i < 512; ++i) { |
| 1700 | if (!(tbl[i] & GCR3_VALID)) |
| 1701 | continue; |
| 1702 | |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 1703 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 1704 | |
| 1705 | free_page((unsigned long)ptr); |
| 1706 | } |
| 1707 | } |
| 1708 | |
| 1709 | static void free_gcr3_tbl_level2(u64 *tbl) |
| 1710 | { |
| 1711 | u64 *ptr; |
| 1712 | int i; |
| 1713 | |
| 1714 | for (i = 0; i < 512; ++i) { |
| 1715 | if (!(tbl[i] & GCR3_VALID)) |
| 1716 | continue; |
| 1717 | |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 1718 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 1719 | |
| 1720 | free_gcr3_tbl_level1(ptr); |
| 1721 | } |
| 1722 | } |
| 1723 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 1724 | static void free_gcr3_table(struct protection_domain *domain) |
| 1725 | { |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 1726 | if (domain->glx == 2) |
| 1727 | free_gcr3_tbl_level2(domain->gcr3_tbl); |
| 1728 | else if (domain->glx == 1) |
| 1729 | free_gcr3_tbl_level1(domain->gcr3_tbl); |
Joerg Roedel | 23d3a98 | 2015-08-13 11:15:13 +0200 | [diff] [blame] | 1730 | else |
| 1731 | BUG_ON(domain->glx != 0); |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 1732 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 1733 | free_page((unsigned long)domain->gcr3_tbl); |
| 1734 | } |
| 1735 | |
Joerg Roedel | fca6af6 | 2017-06-02 18:13:37 +0200 | [diff] [blame] | 1736 | static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom) |
| 1737 | { |
Joerg Roedel | fca6af6 | 2017-06-02 18:13:37 +0200 | [diff] [blame] | 1738 | domain_flush_tlb(&dom->domain); |
| 1739 | domain_flush_complete(&dom->domain); |
Joerg Roedel | fca6af6 | 2017-06-02 18:13:37 +0200 | [diff] [blame] | 1740 | } |
| 1741 | |
Joerg Roedel | 9003d61 | 2017-08-10 17:19:13 +0200 | [diff] [blame] | 1742 | static void iova_domain_flush_tlb(struct iova_domain *iovad) |
Joerg Roedel | fd62190 | 2017-06-02 15:37:26 +0200 | [diff] [blame] | 1743 | { |
Joerg Roedel | 9003d61 | 2017-08-10 17:19:13 +0200 | [diff] [blame] | 1744 | struct dma_ops_domain *dom; |
Joerg Roedel | e241f8e76 | 2017-06-02 15:44:57 +0200 | [diff] [blame] | 1745 | |
Joerg Roedel | 9003d61 | 2017-08-10 17:19:13 +0200 | [diff] [blame] | 1746 | dom = container_of(iovad, struct dma_ops_domain, iovad); |
Joerg Roedel | fca6af6 | 2017-06-02 18:13:37 +0200 | [diff] [blame] | 1747 | |
| 1748 | dma_ops_domain_flush_tlb(dom); |
Joerg Roedel | fca6af6 | 2017-06-02 18:13:37 +0200 | [diff] [blame] | 1749 | } |
| 1750 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1751 | /* |
| 1752 | * Free a domain, only used if something went wrong in the |
| 1753 | * allocation path and we need to free an already allocated page table |
| 1754 | */ |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1755 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
| 1756 | { |
| 1757 | if (!dom) |
| 1758 | return; |
| 1759 | |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 1760 | del_domain_from_list(&dom->domain); |
| 1761 | |
Joerg Roedel | 2d4c515 | 2016-07-05 16:21:32 +0200 | [diff] [blame] | 1762 | put_iova_domain(&dom->iovad); |
| 1763 | |
Joerg Roedel | 86db2e5 | 2008-12-02 18:20:21 +0100 | [diff] [blame] | 1764 | free_pagetable(&dom->domain); |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1765 | |
Baoquan He | c3db901 | 2016-09-15 16:50:52 +0800 | [diff] [blame] | 1766 | if (dom->domain.id) |
| 1767 | domain_id_free(dom->domain.id); |
| 1768 | |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1769 | kfree(dom); |
| 1770 | } |
| 1771 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1772 | /* |
| 1773 | * Allocates a new protection domain usable for the dma_ops functions. |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 1774 | * It also initializes the page table and the address allocator data |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1775 | * structures required for the dma_ops interface |
| 1776 | */ |
Joerg Roedel | 87a64d5 | 2009-11-24 17:26:43 +0100 | [diff] [blame] | 1777 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1778 | { |
| 1779 | struct dma_ops_domain *dma_dom; |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1780 | |
| 1781 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); |
| 1782 | if (!dma_dom) |
| 1783 | return NULL; |
| 1784 | |
Joerg Roedel | 7a5a566 | 2015-06-30 08:56:11 +0200 | [diff] [blame] | 1785 | if (protection_domain_init(&dma_dom->domain)) |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1786 | goto free_dma_dom; |
Joerg Roedel | 7a5a566 | 2015-06-30 08:56:11 +0200 | [diff] [blame] | 1787 | |
Joerg Roedel | ffec219 | 2016-07-26 15:31:23 +0200 | [diff] [blame] | 1788 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1789 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
Joerg Roedel | 9fdb19d | 2008-12-02 17:46:25 +0100 | [diff] [blame] | 1790 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1791 | if (!dma_dom->domain.pt_root) |
| 1792 | goto free_dma_dom; |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1793 | |
Zhen Lei | aa3ac94 | 2017-09-21 16:52:45 +0100 | [diff] [blame] | 1794 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN); |
Joerg Roedel | 307d585 | 2016-07-05 11:54:04 +0200 | [diff] [blame] | 1795 | |
Joerg Roedel | 9003d61 | 2017-08-10 17:19:13 +0200 | [diff] [blame] | 1796 | if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL)) |
Joerg Roedel | d4241a2 | 2017-06-02 14:55:56 +0200 | [diff] [blame] | 1797 | goto free_dma_dom; |
| 1798 | |
Joerg Roedel | 9003d61 | 2017-08-10 17:19:13 +0200 | [diff] [blame] | 1799 | /* Initialize reserved ranges */ |
| 1800 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); |
Joerg Roedel | fca6af6 | 2017-06-02 18:13:37 +0200 | [diff] [blame] | 1801 | |
Joerg Roedel | 2d4c515 | 2016-07-05 16:21:32 +0200 | [diff] [blame] | 1802 | add_domain_to_list(&dma_dom->domain); |
| 1803 | |
Joerg Roedel | ec487d1 | 2008-06-26 21:27:58 +0200 | [diff] [blame] | 1804 | return dma_dom; |
| 1805 | |
| 1806 | free_dma_dom: |
| 1807 | dma_ops_domain_free(dma_dom); |
| 1808 | |
| 1809 | return NULL; |
| 1810 | } |
| 1811 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 1812 | /* |
Joerg Roedel | 5b28df6 | 2008-12-02 17:49:42 +0100 | [diff] [blame] | 1813 | * little helper function to check whether a given protection domain is a |
| 1814 | * dma_ops domain |
| 1815 | */ |
| 1816 | static bool dma_ops_domain(struct protection_domain *domain) |
| 1817 | { |
| 1818 | return domain->flags & PD_DMA_OPS_MASK; |
| 1819 | } |
| 1820 | |
Gary R Hook | ff18c4e | 2017-12-20 09:47:08 -0700 | [diff] [blame] | 1821 | static void set_dte_entry(u16 devid, struct protection_domain *domain, |
| 1822 | bool ats, bool ppr) |
Joerg Roedel | b20ac0d | 2008-06-26 21:27:59 +0200 | [diff] [blame] | 1823 | { |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 1824 | u64 pte_root = 0; |
Joerg Roedel | ee6c286 | 2011-11-09 12:06:03 +0100 | [diff] [blame] | 1825 | u64 flags = 0; |
Joerg Roedel | 863c74e | 2008-12-02 17:56:36 +0100 | [diff] [blame] | 1826 | |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 1827 | if (domain->mode != PAGE_MODE_NONE) |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 1828 | pte_root = iommu_virt_to_phys(domain->pt_root); |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 1829 | |
Joerg Roedel | 38ddf41 | 2008-09-11 10:38:32 +0200 | [diff] [blame] | 1830 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
| 1831 | << DEV_ENTRY_MODE_SHIFT; |
Baoquan He | 07a80a6 | 2017-08-09 16:33:36 +0800 | [diff] [blame] | 1832 | pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; |
Joerg Roedel | b20ac0d | 2008-06-26 21:27:59 +0200 | [diff] [blame] | 1833 | |
Joerg Roedel | ee6c286 | 2011-11-09 12:06:03 +0100 | [diff] [blame] | 1834 | flags = amd_iommu_dev_table[devid].data[1]; |
| 1835 | |
Joerg Roedel | fd7b553 | 2011-04-05 15:31:08 +0200 | [diff] [blame] | 1836 | if (ats) |
| 1837 | flags |= DTE_FLAG_IOTLB; |
| 1838 | |
Gary R Hook | ff18c4e | 2017-12-20 09:47:08 -0700 | [diff] [blame] | 1839 | if (ppr) { |
| 1840 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
| 1841 | |
| 1842 | if (iommu_feature(iommu, FEATURE_EPHSUP)) |
| 1843 | pte_root |= 1ULL << DEV_ENTRY_PPR; |
| 1844 | } |
| 1845 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 1846 | if (domain->flags & PD_IOMMUV2_MASK) { |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 1847 | u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 1848 | u64 glx = domain->glx; |
| 1849 | u64 tmp; |
| 1850 | |
| 1851 | pte_root |= DTE_FLAG_GV; |
| 1852 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; |
| 1853 | |
| 1854 | /* First mask out possible old values for GCR3 table */ |
| 1855 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; |
| 1856 | flags &= ~tmp; |
| 1857 | |
| 1858 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; |
| 1859 | flags &= ~tmp; |
| 1860 | |
| 1861 | /* Encode GCR3 table into DTE */ |
| 1862 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; |
| 1863 | pte_root |= tmp; |
| 1864 | |
| 1865 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; |
| 1866 | flags |= tmp; |
| 1867 | |
| 1868 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; |
| 1869 | flags |= tmp; |
| 1870 | } |
| 1871 | |
Baoquan He | 45a01c4 | 2017-08-09 16:33:37 +0800 | [diff] [blame] | 1872 | flags &= ~DEV_DOMID_MASK; |
Joerg Roedel | ee6c286 | 2011-11-09 12:06:03 +0100 | [diff] [blame] | 1873 | flags |= domain->id; |
| 1874 | |
| 1875 | amd_iommu_dev_table[devid].data[1] = flags; |
| 1876 | amd_iommu_dev_table[devid].data[0] = pte_root; |
Joerg Roedel | b20ac0d | 2008-06-26 21:27:59 +0200 | [diff] [blame] | 1877 | } |
| 1878 | |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 1879 | static void clear_dte_entry(u16 devid) |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 1880 | { |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 1881 | /* remove entry from the device table seen by the hardware */ |
Baoquan He | 07a80a6 | 2017-08-09 16:33:36 +0800 | [diff] [blame] | 1882 | amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV; |
Joerg Roedel | cbf3ccd | 2015-10-20 14:59:36 +0200 | [diff] [blame] | 1883 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 1884 | |
Joerg Roedel | c5cca14 | 2009-10-09 18:31:20 +0200 | [diff] [blame] | 1885 | amd_iommu_apply_erratum_63(devid); |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1886 | } |
| 1887 | |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 1888 | static void do_attach(struct iommu_dev_data *dev_data, |
| 1889 | struct protection_domain *domain) |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1890 | { |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1891 | struct amd_iommu *iommu; |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1892 | u16 alias; |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 1893 | bool ats; |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1894 | |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 1895 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 1896 | alias = dev_data->alias; |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 1897 | ats = dev_data->ats.enabled; |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1898 | |
| 1899 | /* Update data structures */ |
| 1900 | dev_data->domain = domain; |
| 1901 | list_add(&dev_data->list, &domain->dev_list); |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1902 | |
| 1903 | /* Do reference counting */ |
| 1904 | domain->dev_iommu[iommu->index] += 1; |
| 1905 | domain->dev_cnt += 1; |
| 1906 | |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1907 | /* Update device table */ |
Gary R Hook | ff18c4e | 2017-12-20 09:47:08 -0700 | [diff] [blame] | 1908 | set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2); |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1909 | if (alias != dev_data->devid) |
Gary R Hook | ff18c4e | 2017-12-20 09:47:08 -0700 | [diff] [blame] | 1910 | set_dte_entry(alias, domain, ats, dev_data->iommu_v2); |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1911 | |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1912 | device_flush_dte(dev_data); |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1913 | } |
| 1914 | |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 1915 | static void do_detach(struct iommu_dev_data *dev_data) |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1916 | { |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1917 | struct amd_iommu *iommu; |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1918 | u16 alias; |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1919 | |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 1920 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
Joerg Roedel | e315604 | 2016-04-08 15:12:24 +0200 | [diff] [blame] | 1921 | alias = dev_data->alias; |
Joerg Roedel | c5cca14 | 2009-10-09 18:31:20 +0200 | [diff] [blame] | 1922 | |
Joerg Roedel | c459611 | 2009-11-20 14:57:32 +0100 | [diff] [blame] | 1923 | /* decrease reference counters */ |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1924 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
| 1925 | dev_data->domain->dev_cnt -= 1; |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 1926 | |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1927 | /* Update data structures */ |
| 1928 | dev_data->domain = NULL; |
| 1929 | list_del(&dev_data->list); |
Joerg Roedel | f62dda6 | 2011-06-09 12:55:35 +0200 | [diff] [blame] | 1930 | clear_dte_entry(dev_data->devid); |
Joerg Roedel | e25bfb5 | 2015-10-20 17:33:38 +0200 | [diff] [blame] | 1931 | if (alias != dev_data->devid) |
| 1932 | clear_dte_entry(alias); |
Joerg Roedel | 7f760dd | 2009-11-26 14:49:59 +0100 | [diff] [blame] | 1933 | |
| 1934 | /* Flush the DTE entry */ |
Joerg Roedel | 6c54204 | 2011-06-09 17:07:31 +0200 | [diff] [blame] | 1935 | device_flush_dte(dev_data); |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 1936 | } |
| 1937 | |
| 1938 | /* |
Anna-Maria Gleixner | 29a0c41 | 2018-05-07 14:53:26 +0200 | [diff] [blame] | 1939 | * If a device is not yet associated with a domain, this function makes the |
| 1940 | * device visible in the domain |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 1941 | */ |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 1942 | static int __attach_device(struct iommu_dev_data *dev_data, |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 1943 | struct protection_domain *domain) |
| 1944 | { |
Julia Lawall | 84fe6c1 | 2010-05-27 12:31:51 +0200 | [diff] [blame] | 1945 | int ret; |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 1946 | |
Joerg Roedel | 272e4f9 | 2015-10-20 17:33:37 +0200 | [diff] [blame] | 1947 | /* |
| 1948 | * Must be called with IRQs disabled. Warn here to detect early |
| 1949 | * when its not. |
| 1950 | */ |
| 1951 | WARN_ON(!irqs_disabled()); |
| 1952 | |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 1953 | /* lock domain */ |
| 1954 | spin_lock(&domain->lock); |
| 1955 | |
Joerg Roedel | 397111a | 2014-08-05 17:31:51 +0200 | [diff] [blame] | 1956 | ret = -EBUSY; |
Joerg Roedel | 150952f | 2015-10-20 17:33:35 +0200 | [diff] [blame] | 1957 | if (dev_data->domain != NULL) |
Joerg Roedel | 397111a | 2014-08-05 17:31:51 +0200 | [diff] [blame] | 1958 | goto out_unlock; |
Joerg Roedel | 2410005 | 2009-11-25 15:59:57 +0100 | [diff] [blame] | 1959 | |
Joerg Roedel | 397111a | 2014-08-05 17:31:51 +0200 | [diff] [blame] | 1960 | /* Attach alias group root */ |
Joerg Roedel | 150952f | 2015-10-20 17:33:35 +0200 | [diff] [blame] | 1961 | do_attach(dev_data, domain); |
Joerg Roedel | 2410005 | 2009-11-25 15:59:57 +0100 | [diff] [blame] | 1962 | |
Julia Lawall | 84fe6c1 | 2010-05-27 12:31:51 +0200 | [diff] [blame] | 1963 | ret = 0; |
| 1964 | |
| 1965 | out_unlock: |
| 1966 | |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 1967 | /* ready */ |
| 1968 | spin_unlock(&domain->lock); |
Joerg Roedel | 21129f7 | 2009-09-01 11:59:42 +0200 | [diff] [blame] | 1969 | |
Julia Lawall | 84fe6c1 | 2010-05-27 12:31:51 +0200 | [diff] [blame] | 1970 | return ret; |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 1971 | } |
| 1972 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 1973 | |
| 1974 | static void pdev_iommuv2_disable(struct pci_dev *pdev) |
| 1975 | { |
| 1976 | pci_disable_ats(pdev); |
| 1977 | pci_disable_pri(pdev); |
| 1978 | pci_disable_pasid(pdev); |
| 1979 | } |
| 1980 | |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 1981 | /* FIXME: Change generic reset-function to do the same */ |
| 1982 | static int pri_reset_while_enabled(struct pci_dev *pdev) |
| 1983 | { |
| 1984 | u16 control; |
| 1985 | int pos; |
| 1986 | |
Joerg Roedel | 46277b7 | 2011-12-07 14:34:02 +0100 | [diff] [blame] | 1987 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 1988 | if (!pos) |
| 1989 | return -EINVAL; |
| 1990 | |
Joerg Roedel | 46277b7 | 2011-12-07 14:34:02 +0100 | [diff] [blame] | 1991 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
| 1992 | control |= PCI_PRI_CTRL_RESET; |
| 1993 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 1994 | |
| 1995 | return 0; |
| 1996 | } |
| 1997 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 1998 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
| 1999 | { |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 2000 | bool reset_enable; |
| 2001 | int reqs, ret; |
| 2002 | |
| 2003 | /* FIXME: Hardcode number of outstanding requests for now */ |
| 2004 | reqs = 32; |
| 2005 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) |
| 2006 | reqs = 1; |
| 2007 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2008 | |
| 2009 | /* Only allow access to user-accessible pages */ |
| 2010 | ret = pci_enable_pasid(pdev, 0); |
| 2011 | if (ret) |
| 2012 | goto out_err; |
| 2013 | |
| 2014 | /* First reset the PRI state of the device */ |
| 2015 | ret = pci_reset_pri(pdev); |
| 2016 | if (ret) |
| 2017 | goto out_err; |
| 2018 | |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 2019 | /* Enable PRI */ |
| 2020 | ret = pci_enable_pri(pdev, reqs); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2021 | if (ret) |
| 2022 | goto out_err; |
| 2023 | |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 2024 | if (reset_enable) { |
| 2025 | ret = pri_reset_while_enabled(pdev); |
| 2026 | if (ret) |
| 2027 | goto out_err; |
| 2028 | } |
| 2029 | |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2030 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
| 2031 | if (ret) |
| 2032 | goto out_err; |
| 2033 | |
| 2034 | return 0; |
| 2035 | |
| 2036 | out_err: |
| 2037 | pci_disable_pri(pdev); |
| 2038 | pci_disable_pasid(pdev); |
| 2039 | |
| 2040 | return ret; |
| 2041 | } |
| 2042 | |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 2043 | /* FIXME: Move this to PCI code */ |
Joerg Roedel | a3b9312 | 2012-04-12 12:49:26 +0200 | [diff] [blame] | 2044 | #define PCI_PRI_TLP_OFF (1 << 15) |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 2045 | |
Joerg Roedel | 98f1ad2 | 2012-07-06 13:28:37 +0200 | [diff] [blame] | 2046 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 2047 | { |
Joerg Roedel | a3b9312 | 2012-04-12 12:49:26 +0200 | [diff] [blame] | 2048 | u16 status; |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 2049 | int pos; |
| 2050 | |
Joerg Roedel | 46277b7 | 2011-12-07 14:34:02 +0100 | [diff] [blame] | 2051 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 2052 | if (!pos) |
| 2053 | return false; |
| 2054 | |
Joerg Roedel | a3b9312 | 2012-04-12 12:49:26 +0200 | [diff] [blame] | 2055 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 2056 | |
Joerg Roedel | a3b9312 | 2012-04-12 12:49:26 +0200 | [diff] [blame] | 2057 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 2058 | } |
| 2059 | |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2060 | /* |
Anna-Maria Gleixner | 29a0c41 | 2018-05-07 14:53:26 +0200 | [diff] [blame] | 2061 | * If a device is not yet associated with a domain, this function makes the |
| 2062 | * device visible in the domain |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2063 | */ |
| 2064 | static int attach_device(struct device *dev, |
| 2065 | struct protection_domain *domain) |
| 2066 | { |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 2067 | struct pci_dev *pdev; |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 2068 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2069 | unsigned long flags; |
| 2070 | int ret; |
| 2071 | |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 2072 | dev_data = get_dev_data(dev); |
| 2073 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 2074 | if (!dev_is_pci(dev)) |
| 2075 | goto skip_ats_check; |
| 2076 | |
| 2077 | pdev = to_pci_dev(dev); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2078 | if (domain->flags & PD_IOMMUV2_MASK) { |
Joerg Roedel | 02ca202 | 2015-07-28 16:58:49 +0200 | [diff] [blame] | 2079 | if (!dev_data->passthrough) |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2080 | return -EINVAL; |
| 2081 | |
Joerg Roedel | 02ca202 | 2015-07-28 16:58:49 +0200 | [diff] [blame] | 2082 | if (dev_data->iommu_v2) { |
| 2083 | if (pdev_iommuv2_enable(pdev) != 0) |
| 2084 | return -EINVAL; |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2085 | |
Joerg Roedel | 02ca202 | 2015-07-28 16:58:49 +0200 | [diff] [blame] | 2086 | dev_data->ats.enabled = true; |
| 2087 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); |
| 2088 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
| 2089 | } |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2090 | } else if (amd_iommu_iotlb_sup && |
| 2091 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 2092 | dev_data->ats.enabled = true; |
| 2093 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); |
| 2094 | } |
Joerg Roedel | fd7b553 | 2011-04-05 15:31:08 +0200 | [diff] [blame] | 2095 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 2096 | skip_ats_check: |
Sebastian Andrzej Siewior | 2cd1083 | 2018-03-22 16:22:41 +0100 | [diff] [blame] | 2097 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 2098 | ret = __attach_device(dev_data, domain); |
Sebastian Andrzej Siewior | 2cd1083 | 2018-03-22 16:22:41 +0100 | [diff] [blame] | 2099 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2100 | |
| 2101 | /* |
| 2102 | * We might boot into a crash-kernel here. The crashed kernel |
| 2103 | * left the caches in the IOMMU dirty. So we have to flush |
| 2104 | * here to evict all dirty stuff. |
| 2105 | */ |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 2106 | domain_flush_tlb_pde(domain); |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2107 | |
| 2108 | return ret; |
| 2109 | } |
| 2110 | |
| 2111 | /* |
| 2112 | * Removes a device from a protection domain (unlocked) |
| 2113 | */ |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 2114 | static void __detach_device(struct iommu_dev_data *dev_data) |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2115 | { |
Joerg Roedel | 2ca7627 | 2010-01-22 16:45:31 +0100 | [diff] [blame] | 2116 | struct protection_domain *domain; |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2117 | |
Joerg Roedel | 272e4f9 | 2015-10-20 17:33:37 +0200 | [diff] [blame] | 2118 | /* |
| 2119 | * Must be called with IRQs disabled. Warn here to detect early |
| 2120 | * when its not. |
| 2121 | */ |
| 2122 | WARN_ON(!irqs_disabled()); |
| 2123 | |
Joerg Roedel | 2ca7627 | 2010-01-22 16:45:31 +0100 | [diff] [blame] | 2124 | domain = dev_data->domain; |
| 2125 | |
Joerg Roedel | f1dd0a8 | 2015-10-20 17:33:36 +0200 | [diff] [blame] | 2126 | spin_lock(&domain->lock); |
Joerg Roedel | 2410005 | 2009-11-25 15:59:57 +0100 | [diff] [blame] | 2127 | |
Joerg Roedel | 150952f | 2015-10-20 17:33:35 +0200 | [diff] [blame] | 2128 | do_detach(dev_data); |
Joerg Roedel | 71f7758 | 2011-06-09 19:03:15 +0200 | [diff] [blame] | 2129 | |
Joerg Roedel | f1dd0a8 | 2015-10-20 17:33:36 +0200 | [diff] [blame] | 2130 | spin_unlock(&domain->lock); |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 2131 | } |
| 2132 | |
| 2133 | /* |
| 2134 | * Removes a device from a protection domain (with devtable_lock held) |
| 2135 | */ |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2136 | static void detach_device(struct device *dev) |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 2137 | { |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2138 | struct protection_domain *domain; |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 2139 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 2140 | unsigned long flags; |
| 2141 | |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 2142 | dev_data = get_dev_data(dev); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2143 | domain = dev_data->domain; |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 2144 | |
Anna-Maria Gleixner | ea3fd04 | 2018-05-07 14:53:27 +0200 | [diff] [blame] | 2145 | /* |
| 2146 | * First check if the device is still attached. It might already |
| 2147 | * be detached from its domain because the generic |
| 2148 | * iommu_detach_group code detached it and we try again here in |
| 2149 | * our alias handling. |
| 2150 | */ |
| 2151 | if (WARN_ON(!dev_data->domain)) |
| 2152 | return; |
| 2153 | |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 2154 | /* lock device table */ |
Sebastian Andrzej Siewior | 2cd1083 | 2018-03-22 16:22:41 +0100 | [diff] [blame] | 2155 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
Joerg Roedel | ec9e79e | 2011-06-09 17:25:50 +0200 | [diff] [blame] | 2156 | __detach_device(dev_data); |
Sebastian Andrzej Siewior | 2cd1083 | 2018-03-22 16:22:41 +0100 | [diff] [blame] | 2157 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
Joerg Roedel | fd7b553 | 2011-04-05 15:31:08 +0200 | [diff] [blame] | 2158 | |
Wan Zongshun | 2bf9a0a | 2016-04-01 09:06:03 -0400 | [diff] [blame] | 2159 | if (!dev_is_pci(dev)) |
| 2160 | return; |
| 2161 | |
Joerg Roedel | 02ca202 | 2015-07-28 16:58:49 +0200 | [diff] [blame] | 2162 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2163 | pdev_iommuv2_disable(to_pci_dev(dev)); |
| 2164 | else if (dev_data->ats.enabled) |
Joerg Roedel | ea61cdd | 2011-06-09 12:56:30 +0200 | [diff] [blame] | 2165 | pci_disable_ats(to_pci_dev(dev)); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2166 | |
| 2167 | dev_data->ats.enabled = false; |
Joerg Roedel | 355bf55 | 2008-12-08 12:02:41 +0100 | [diff] [blame] | 2168 | } |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2169 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2170 | static int amd_iommu_add_device(struct device *dev) |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2171 | { |
Joerg Roedel | 71f7758 | 2011-06-09 19:03:15 +0200 | [diff] [blame] | 2172 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 07ee869 | 2015-05-28 18:41:42 +0200 | [diff] [blame] | 2173 | struct iommu_domain *domain; |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2174 | struct amd_iommu *iommu; |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 2175 | int ret, devid; |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2176 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2177 | if (!check_device(dev) || get_dev_data(dev)) |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 2178 | return 0; |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2179 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2180 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 2181 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 2182 | return devid; |
| 2183 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2184 | iommu = amd_iommu_rlookup_table[devid]; |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2185 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2186 | ret = iommu_init_device(dev); |
Joerg Roedel | 4d58b8a | 2015-06-11 09:21:39 +0200 | [diff] [blame] | 2187 | if (ret) { |
| 2188 | if (ret != -ENOTSUPP) |
| 2189 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", |
| 2190 | dev_name(dev)); |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 2191 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2192 | iommu_ignore_device(dev); |
Christoph Hellwig | fec777c | 2018-03-19 11:38:15 +0100 | [diff] [blame] | 2193 | dev->dma_ops = &dma_direct_ops; |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2194 | goto out; |
| 2195 | } |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2196 | init_iommu_group(dev); |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2197 | |
Joerg Roedel | 07ee869 | 2015-05-28 18:41:42 +0200 | [diff] [blame] | 2198 | dev_data = get_dev_data(dev); |
Joerg Roedel | 4d58b8a | 2015-06-11 09:21:39 +0200 | [diff] [blame] | 2199 | |
| 2200 | BUG_ON(!dev_data); |
| 2201 | |
Joerg Roedel | 1e6a7b0 | 2015-07-28 16:58:48 +0200 | [diff] [blame] | 2202 | if (iommu_pass_through || dev_data->iommu_v2) |
Joerg Roedel | 07ee869 | 2015-05-28 18:41:42 +0200 | [diff] [blame] | 2203 | iommu_request_dm_for_dev(dev); |
| 2204 | |
| 2205 | /* Domains are initialized for this device - have a look what we ended up with */ |
| 2206 | domain = iommu_get_domain_for_dev(dev); |
Joerg Roedel | 3230232 | 2015-07-28 16:58:50 +0200 | [diff] [blame] | 2207 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
Joerg Roedel | 07ee869 | 2015-05-28 18:41:42 +0200 | [diff] [blame] | 2208 | dev_data->passthrough = true; |
Joerg Roedel | 3230232 | 2015-07-28 16:58:50 +0200 | [diff] [blame] | 2209 | else |
Bart Van Assche | 5657933 | 2017-01-20 13:04:02 -0800 | [diff] [blame] | 2210 | dev->dma_ops = &amd_iommu_dma_ops; |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2211 | |
| 2212 | out: |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2213 | iommu_completion_wait(iommu); |
| 2214 | |
Joerg Roedel | e275a2a | 2008-12-10 18:27:25 +0100 | [diff] [blame] | 2215 | return 0; |
| 2216 | } |
| 2217 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2218 | static void amd_iommu_remove_device(struct device *dev) |
Joerg Roedel | 8638c49 | 2009-12-10 11:12:25 +0100 | [diff] [blame] | 2219 | { |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2220 | struct amd_iommu *iommu; |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 2221 | int devid; |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2222 | |
| 2223 | if (!check_device(dev)) |
| 2224 | return; |
| 2225 | |
| 2226 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 2227 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 2228 | return; |
| 2229 | |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 2230 | iommu = amd_iommu_rlookup_table[devid]; |
| 2231 | |
| 2232 | iommu_uninit_device(dev); |
| 2233 | iommu_completion_wait(iommu); |
Joerg Roedel | 8638c49 | 2009-12-10 11:12:25 +0100 | [diff] [blame] | 2234 | } |
| 2235 | |
Wan Zongshun | b097d11 | 2016-04-01 09:06:04 -0400 | [diff] [blame] | 2236 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
| 2237 | { |
| 2238 | if (dev_is_pci(dev)) |
| 2239 | return pci_device_group(dev); |
| 2240 | |
| 2241 | return acpihid_device_group(dev); |
| 2242 | } |
| 2243 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2244 | /***************************************************************************** |
| 2245 | * |
| 2246 | * The next functions belong to the dma_ops mapping/unmapping code. |
| 2247 | * |
| 2248 | *****************************************************************************/ |
| 2249 | |
| 2250 | /* |
| 2251 | * In the dma_ops path we only have the struct device. This function |
| 2252 | * finds the corresponding IOMMU, the protection domain and the |
| 2253 | * requestor id for a given device. |
| 2254 | * If the device is not yet associated with a domain this is also done |
| 2255 | * in this function. |
| 2256 | */ |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2257 | static struct protection_domain *get_domain(struct device *dev) |
Joerg Roedel | b20ac0d | 2008-06-26 21:27:59 +0200 | [diff] [blame] | 2258 | { |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2259 | struct protection_domain *domain; |
Baoquan He | df3f7a6 | 2017-08-09 16:33:41 +0800 | [diff] [blame] | 2260 | struct iommu_domain *io_domain; |
Joerg Roedel | b20ac0d | 2008-06-26 21:27:59 +0200 | [diff] [blame] | 2261 | |
Joerg Roedel | f99c0f1 | 2009-11-23 16:52:56 +0100 | [diff] [blame] | 2262 | if (!check_device(dev)) |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2263 | return ERR_PTR(-EINVAL); |
Joerg Roedel | dbcc112 | 2008-09-04 15:04:26 +0200 | [diff] [blame] | 2264 | |
Joerg Roedel | d26592a | 2016-07-07 15:31:13 +0200 | [diff] [blame] | 2265 | domain = get_dev_data(dev)->domain; |
Baoquan He | df3f7a6 | 2017-08-09 16:33:41 +0800 | [diff] [blame] | 2266 | if (domain == NULL && get_dev_data(dev)->defer_attach) { |
| 2267 | get_dev_data(dev)->defer_attach = false; |
| 2268 | io_domain = iommu_get_domain_for_dev(dev); |
| 2269 | domain = to_pdomain(io_domain); |
| 2270 | attach_device(dev, domain); |
| 2271 | } |
Baoquan He | ec62b1a | 2017-08-24 21:13:57 +0800 | [diff] [blame] | 2272 | if (domain == NULL) |
| 2273 | return ERR_PTR(-EBUSY); |
| 2274 | |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 2275 | if (!dma_ops_domain(domain)) |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2276 | return ERR_PTR(-EBUSY); |
Joerg Roedel | f99c0f1 | 2009-11-23 16:52:56 +0100 | [diff] [blame] | 2277 | |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 2278 | return domain; |
Joerg Roedel | b20ac0d | 2008-06-26 21:27:59 +0200 | [diff] [blame] | 2279 | } |
| 2280 | |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 2281 | static void update_device_table(struct protection_domain *domain) |
| 2282 | { |
Joerg Roedel | 492667d | 2009-11-27 13:25:47 +0100 | [diff] [blame] | 2283 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 2284 | |
Joerg Roedel | 3254de6 | 2016-07-26 15:18:54 +0200 | [diff] [blame] | 2285 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
Gary R Hook | ff18c4e | 2017-12-20 09:47:08 -0700 | [diff] [blame] | 2286 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled, |
| 2287 | dev_data->iommu_v2); |
Joerg Roedel | 3254de6 | 2016-07-26 15:18:54 +0200 | [diff] [blame] | 2288 | |
| 2289 | if (dev_data->devid == dev_data->alias) |
| 2290 | continue; |
| 2291 | |
| 2292 | /* There is an alias, update device table entry for it */ |
Gary R Hook | ff18c4e | 2017-12-20 09:47:08 -0700 | [diff] [blame] | 2293 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled, |
| 2294 | dev_data->iommu_v2); |
Joerg Roedel | 3254de6 | 2016-07-26 15:18:54 +0200 | [diff] [blame] | 2295 | } |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 2296 | } |
| 2297 | |
| 2298 | static void update_domain(struct protection_domain *domain) |
| 2299 | { |
| 2300 | if (!domain->updated) |
| 2301 | return; |
| 2302 | |
| 2303 | update_device_table(domain); |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 2304 | |
| 2305 | domain_flush_devices(domain); |
| 2306 | domain_flush_tlb_pde(domain); |
Joerg Roedel | 04bfdd8 | 2009-09-02 16:00:23 +0200 | [diff] [blame] | 2307 | |
| 2308 | domain->updated = false; |
| 2309 | } |
| 2310 | |
Joerg Roedel | f37f7f3 | 2016-07-08 11:47:22 +0200 | [diff] [blame] | 2311 | static int dir2prot(enum dma_data_direction direction) |
| 2312 | { |
| 2313 | if (direction == DMA_TO_DEVICE) |
| 2314 | return IOMMU_PROT_IR; |
| 2315 | else if (direction == DMA_FROM_DEVICE) |
| 2316 | return IOMMU_PROT_IW; |
| 2317 | else if (direction == DMA_BIDIRECTIONAL) |
| 2318 | return IOMMU_PROT_IW | IOMMU_PROT_IR; |
| 2319 | else |
| 2320 | return 0; |
| 2321 | } |
Baoquan He | daae2d2 | 2017-08-09 16:33:43 +0800 | [diff] [blame] | 2322 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2323 | /* |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2324 | * This function contains common code for mapping of a physically |
Joerg Roedel | 24f8116 | 2008-12-08 14:25:39 +0100 | [diff] [blame] | 2325 | * contiguous memory region into DMA address space. It is used by all |
| 2326 | * mapping functions provided with this IOMMU driver. |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2327 | * Must be called with the domain lock held. |
| 2328 | */ |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2329 | static dma_addr_t __map_single(struct device *dev, |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2330 | struct dma_ops_domain *dma_dom, |
| 2331 | phys_addr_t paddr, |
| 2332 | size_t size, |
Joerg Roedel | f37f7f3 | 2016-07-08 11:47:22 +0200 | [diff] [blame] | 2333 | enum dma_data_direction direction, |
Joerg Roedel | 832a90c | 2008-09-18 15:54:23 +0200 | [diff] [blame] | 2334 | u64 dma_mask) |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2335 | { |
| 2336 | dma_addr_t offset = paddr & ~PAGE_MASK; |
Joerg Roedel | 53812c1 | 2009-05-12 12:17:38 +0200 | [diff] [blame] | 2337 | dma_addr_t address, start, ret; |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2338 | unsigned int pages; |
Joerg Roedel | 518d9b4 | 2016-07-05 14:39:47 +0200 | [diff] [blame] | 2339 | int prot = 0; |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2340 | int i; |
| 2341 | |
Joerg Roedel | e3c449f | 2008-10-15 22:02:11 -0700 | [diff] [blame] | 2342 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2343 | paddr &= PAGE_MASK; |
| 2344 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 2345 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 2346 | if (address == AMD_IOMMU_MAPPING_ERROR) |
Joerg Roedel | 266a3bd | 2015-12-21 18:54:24 +0100 | [diff] [blame] | 2347 | goto out; |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2348 | |
Joerg Roedel | f37f7f3 | 2016-07-08 11:47:22 +0200 | [diff] [blame] | 2349 | prot = dir2prot(direction); |
Joerg Roedel | 518d9b4 | 2016-07-05 14:39:47 +0200 | [diff] [blame] | 2350 | |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2351 | start = address; |
| 2352 | for (i = 0; i < pages; ++i) { |
Joerg Roedel | 518d9b4 | 2016-07-05 14:39:47 +0200 | [diff] [blame] | 2353 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
| 2354 | PAGE_SIZE, prot, GFP_ATOMIC); |
| 2355 | if (ret) |
Joerg Roedel | 53812c1 | 2009-05-12 12:17:38 +0200 | [diff] [blame] | 2356 | goto out_unmap; |
| 2357 | |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2358 | paddr += PAGE_SIZE; |
| 2359 | start += PAGE_SIZE; |
| 2360 | } |
| 2361 | address += offset; |
| 2362 | |
Joerg Roedel | ab7032b | 2015-12-21 18:47:11 +0100 | [diff] [blame] | 2363 | if (unlikely(amd_iommu_np_cache)) { |
Joerg Roedel | 17b124b | 2011-04-06 18:01:35 +0200 | [diff] [blame] | 2364 | domain_flush_pages(&dma_dom->domain, address, size); |
Joerg Roedel | ab7032b | 2015-12-21 18:47:11 +0100 | [diff] [blame] | 2365 | domain_flush_complete(&dma_dom->domain); |
| 2366 | } |
Joerg Roedel | 270cab24 | 2008-09-04 15:49:46 +0200 | [diff] [blame] | 2367 | |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2368 | out: |
| 2369 | return address; |
Joerg Roedel | 53812c1 | 2009-05-12 12:17:38 +0200 | [diff] [blame] | 2370 | |
| 2371 | out_unmap: |
| 2372 | |
| 2373 | for (--i; i >= 0; --i) { |
| 2374 | start -= PAGE_SIZE; |
Joerg Roedel | 518d9b4 | 2016-07-05 14:39:47 +0200 | [diff] [blame] | 2375 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
Joerg Roedel | 53812c1 | 2009-05-12 12:17:38 +0200 | [diff] [blame] | 2376 | } |
| 2377 | |
Joerg Roedel | 256e462 | 2016-07-05 14:23:01 +0200 | [diff] [blame] | 2378 | domain_flush_tlb(&dma_dom->domain); |
| 2379 | domain_flush_complete(&dma_dom->domain); |
| 2380 | |
| 2381 | dma_ops_free_iova(dma_dom, address, pages); |
Joerg Roedel | 53812c1 | 2009-05-12 12:17:38 +0200 | [diff] [blame] | 2382 | |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 2383 | return AMD_IOMMU_MAPPING_ERROR; |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2384 | } |
| 2385 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2386 | /* |
| 2387 | * Does the reverse of the __map_single function. Must be called with |
| 2388 | * the domain lock held too |
| 2389 | */ |
Joerg Roedel | cd8c82e | 2009-11-23 19:33:56 +0100 | [diff] [blame] | 2390 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2391 | dma_addr_t dma_addr, |
| 2392 | size_t size, |
| 2393 | int dir) |
| 2394 | { |
| 2395 | dma_addr_t i, start; |
| 2396 | unsigned int pages; |
| 2397 | |
Joerg Roedel | e3c449f | 2008-10-15 22:02:11 -0700 | [diff] [blame] | 2398 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2399 | dma_addr &= PAGE_MASK; |
| 2400 | start = dma_addr; |
| 2401 | |
| 2402 | for (i = 0; i < pages; ++i) { |
Joerg Roedel | 518d9b4 | 2016-07-05 14:39:47 +0200 | [diff] [blame] | 2403 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2404 | start += PAGE_SIZE; |
| 2405 | } |
| 2406 | |
Joerg Roedel | b1516a1 | 2016-07-06 13:07:22 +0200 | [diff] [blame] | 2407 | if (amd_iommu_unmap_flush) { |
| 2408 | dma_ops_free_iova(dma_dom, dma_addr, pages); |
| 2409 | domain_flush_tlb(&dma_dom->domain); |
| 2410 | domain_flush_complete(&dma_dom->domain); |
| 2411 | } else { |
Joerg Roedel | 9003d61 | 2017-08-10 17:19:13 +0200 | [diff] [blame] | 2412 | pages = __roundup_pow_of_two(pages); |
| 2413 | queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0); |
Joerg Roedel | b1516a1 | 2016-07-06 13:07:22 +0200 | [diff] [blame] | 2414 | } |
Joerg Roedel | cb76c32 | 2008-06-26 21:28:00 +0200 | [diff] [blame] | 2415 | } |
| 2416 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2417 | /* |
| 2418 | * The exported map_single function for dma_ops. |
| 2419 | */ |
FUJITA Tomonori | 5149136 | 2009-01-05 23:47:25 +0900 | [diff] [blame] | 2420 | static dma_addr_t map_page(struct device *dev, struct page *page, |
| 2421 | unsigned long offset, size_t size, |
| 2422 | enum dma_data_direction dir, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2423 | unsigned long attrs) |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2424 | { |
FUJITA Tomonori | 5149136 | 2009-01-05 23:47:25 +0900 | [diff] [blame] | 2425 | phys_addr_t paddr = page_to_phys(page) + offset; |
Joerg Roedel | 92d420e | 2015-12-21 19:31:33 +0100 | [diff] [blame] | 2426 | struct protection_domain *domain; |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2427 | struct dma_ops_domain *dma_dom; |
Joerg Roedel | 92d420e | 2015-12-21 19:31:33 +0100 | [diff] [blame] | 2428 | u64 dma_mask; |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2429 | |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2430 | domain = get_domain(dev); |
| 2431 | if (PTR_ERR(domain) == -EINVAL) |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2432 | return (dma_addr_t)paddr; |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2433 | else if (IS_ERR(domain)) |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 2434 | return AMD_IOMMU_MAPPING_ERROR; |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2435 | |
Joerg Roedel | f99c0f1 | 2009-11-23 16:52:56 +0100 | [diff] [blame] | 2436 | dma_mask = *dev->dma_mask; |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2437 | dma_dom = to_dma_ops_domain(domain); |
Joerg Roedel | f99c0f1 | 2009-11-23 16:52:56 +0100 | [diff] [blame] | 2438 | |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2439 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2440 | } |
| 2441 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2442 | /* |
| 2443 | * The exported unmap_single function for dma_ops. |
| 2444 | */ |
FUJITA Tomonori | 5149136 | 2009-01-05 23:47:25 +0900 | [diff] [blame] | 2445 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2446 | enum dma_data_direction dir, unsigned long attrs) |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2447 | { |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2448 | struct protection_domain *domain; |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2449 | struct dma_ops_domain *dma_dom; |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2450 | |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2451 | domain = get_domain(dev); |
| 2452 | if (IS_ERR(domain)) |
Joerg Roedel | 5b28df6 | 2008-12-02 17:49:42 +0100 | [diff] [blame] | 2453 | return; |
| 2454 | |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2455 | dma_dom = to_dma_ops_domain(domain); |
| 2456 | |
| 2457 | __unmap_single(dma_dom, dma_addr, size, dir); |
Joerg Roedel | 4da70b9 | 2008-06-26 21:28:01 +0200 | [diff] [blame] | 2458 | } |
| 2459 | |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2460 | static int sg_num_pages(struct device *dev, |
| 2461 | struct scatterlist *sglist, |
| 2462 | int nelems) |
| 2463 | { |
| 2464 | unsigned long mask, boundary_size; |
| 2465 | struct scatterlist *s; |
| 2466 | int i, npages = 0; |
| 2467 | |
| 2468 | mask = dma_get_seg_boundary(dev); |
| 2469 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : |
| 2470 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); |
| 2471 | |
| 2472 | for_each_sg(sglist, s, nelems, i) { |
| 2473 | int p, n; |
| 2474 | |
| 2475 | s->dma_address = npages << PAGE_SHIFT; |
| 2476 | p = npages % boundary_size; |
| 2477 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
| 2478 | if (p + n > boundary_size) |
| 2479 | npages += boundary_size - p; |
| 2480 | npages += n; |
| 2481 | } |
| 2482 | |
| 2483 | return npages; |
| 2484 | } |
| 2485 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2486 | /* |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2487 | * The exported map_sg function for dma_ops (handles scatter-gather |
| 2488 | * lists). |
| 2489 | */ |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2490 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2491 | int nelems, enum dma_data_direction direction, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2492 | unsigned long attrs) |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2493 | { |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2494 | int mapped_pages = 0, npages = 0, prot = 0, i; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2495 | struct protection_domain *domain; |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2496 | struct dma_ops_domain *dma_dom; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2497 | struct scatterlist *s; |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2498 | unsigned long address; |
Joerg Roedel | 832a90c | 2008-09-18 15:54:23 +0200 | [diff] [blame] | 2499 | u64 dma_mask; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2500 | |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2501 | domain = get_domain(dev); |
Joerg Roedel | a0e191b | 2013-04-09 15:04:36 +0200 | [diff] [blame] | 2502 | if (IS_ERR(domain)) |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2503 | return 0; |
Joerg Roedel | dbcc112 | 2008-09-04 15:04:26 +0200 | [diff] [blame] | 2504 | |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2505 | dma_dom = to_dma_ops_domain(domain); |
Joerg Roedel | 832a90c | 2008-09-18 15:54:23 +0200 | [diff] [blame] | 2506 | dma_mask = *dev->dma_mask; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2507 | |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2508 | npages = sg_num_pages(dev, sglist, nelems); |
| 2509 | |
| 2510 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 2511 | if (address == AMD_IOMMU_MAPPING_ERROR) |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2512 | goto out_err; |
| 2513 | |
| 2514 | prot = dir2prot(direction); |
| 2515 | |
| 2516 | /* Map all sg entries */ |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2517 | for_each_sg(sglist, s, nelems, i) { |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2518 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2519 | |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2520 | for (j = 0; j < pages; ++j) { |
| 2521 | unsigned long bus_addr, phys_addr; |
| 2522 | int ret; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2523 | |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2524 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
| 2525 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); |
| 2526 | ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC); |
| 2527 | if (ret) |
| 2528 | goto out_unmap; |
| 2529 | |
| 2530 | mapped_pages += 1; |
| 2531 | } |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2532 | } |
| 2533 | |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2534 | /* Everything is mapped - write the right values into s->dma_address */ |
| 2535 | for_each_sg(sglist, s, nelems, i) { |
| 2536 | s->dma_address += address + s->offset; |
| 2537 | s->dma_length = s->length; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2538 | } |
| 2539 | |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2540 | return nelems; |
| 2541 | |
| 2542 | out_unmap: |
| 2543 | pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n", |
| 2544 | dev_name(dev), npages); |
| 2545 | |
| 2546 | for_each_sg(sglist, s, nelems, i) { |
| 2547 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
| 2548 | |
| 2549 | for (j = 0; j < pages; ++j) { |
| 2550 | unsigned long bus_addr; |
| 2551 | |
| 2552 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
| 2553 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); |
| 2554 | |
| 2555 | if (--mapped_pages) |
| 2556 | goto out_free_iova; |
| 2557 | } |
| 2558 | } |
| 2559 | |
| 2560 | out_free_iova: |
| 2561 | free_iova_fast(&dma_dom->iovad, address, npages); |
| 2562 | |
| 2563 | out_err: |
Joerg Roedel | 92d420e | 2015-12-21 19:31:33 +0100 | [diff] [blame] | 2564 | return 0; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2565 | } |
| 2566 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2567 | /* |
| 2568 | * The exported map_sg function for dma_ops (handles scatter-gather |
| 2569 | * lists). |
| 2570 | */ |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2571 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
FUJITA Tomonori | 160c1d8 | 2009-01-05 23:59:02 +0900 | [diff] [blame] | 2572 | int nelems, enum dma_data_direction dir, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2573 | unsigned long attrs) |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2574 | { |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2575 | struct protection_domain *domain; |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2576 | struct dma_ops_domain *dma_dom; |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2577 | unsigned long startaddr; |
| 2578 | int npages = 2; |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2579 | |
Joerg Roedel | 94f6d19 | 2009-11-24 16:40:02 +0100 | [diff] [blame] | 2580 | domain = get_domain(dev); |
| 2581 | if (IS_ERR(domain)) |
Joerg Roedel | 5b28df6 | 2008-12-02 17:49:42 +0100 | [diff] [blame] | 2582 | return; |
| 2583 | |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2584 | startaddr = sg_dma_address(sglist) & PAGE_MASK; |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2585 | dma_dom = to_dma_ops_domain(domain); |
Joerg Roedel | 80187fd | 2016-07-06 17:20:54 +0200 | [diff] [blame] | 2586 | npages = sg_num_pages(dev, sglist, nelems); |
| 2587 | |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2588 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); |
Joerg Roedel | 65b050a | 2008-06-26 21:28:02 +0200 | [diff] [blame] | 2589 | } |
| 2590 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2591 | /* |
| 2592 | * The exported alloc_coherent function for dma_ops. |
| 2593 | */ |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2594 | static void *alloc_coherent(struct device *dev, size_t size, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 2595 | dma_addr_t *dma_addr, gfp_t flag, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2596 | unsigned long attrs) |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2597 | { |
Joerg Roedel | 832a90c | 2008-09-18 15:54:23 +0200 | [diff] [blame] | 2598 | u64 dma_mask = dev->coherent_dma_mask; |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2599 | struct protection_domain *domain; |
| 2600 | struct dma_ops_domain *dma_dom; |
| 2601 | struct page *page; |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2602 | |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2603 | domain = get_domain(dev); |
| 2604 | if (PTR_ERR(domain) == -EINVAL) { |
| 2605 | page = alloc_pages(flag, get_order(size)); |
| 2606 | *dma_addr = page_to_phys(page); |
| 2607 | return page_address(page); |
| 2608 | } else if (IS_ERR(domain)) |
| 2609 | return NULL; |
| 2610 | |
| 2611 | dma_dom = to_dma_ops_domain(domain); |
| 2612 | size = PAGE_ALIGN(size); |
| 2613 | dma_mask = dev->coherent_dma_mask; |
| 2614 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); |
| 2615 | flag |= __GFP_ZERO; |
| 2616 | |
| 2617 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
| 2618 | if (!page) { |
| 2619 | if (!gfpflags_allow_blocking(flag)) |
Joerg Roedel | 3b839a5 | 2015-04-01 14:58:47 +0200 | [diff] [blame] | 2620 | return NULL; |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2621 | |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2622 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
| 2623 | get_order(size), flag); |
| 2624 | if (!page) |
| 2625 | return NULL; |
| 2626 | } |
Christoph Hellwig | b468620 | 2018-03-19 11:38:19 +0100 | [diff] [blame] | 2627 | |
Joerg Roedel | 832a90c | 2008-09-18 15:54:23 +0200 | [diff] [blame] | 2628 | if (!dma_mask) |
| 2629 | dma_mask = *dev->dma_mask; |
| 2630 | |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2631 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), |
| 2632 | size, DMA_BIDIRECTIONAL, dma_mask); |
| 2633 | |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 2634 | if (*dma_addr == AMD_IOMMU_MAPPING_ERROR) |
Joerg Roedel | 5b28df6 | 2008-12-02 17:49:42 +0100 | [diff] [blame] | 2635 | goto out_free; |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2636 | |
| 2637 | return page_address(page); |
Joerg Roedel | 5b28df6 | 2008-12-02 17:49:42 +0100 | [diff] [blame] | 2638 | |
| 2639 | out_free: |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2640 | |
| 2641 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
| 2642 | __free_pages(page, get_order(size)); |
| 2643 | |
Joerg Roedel | 5b28df6 | 2008-12-02 17:49:42 +0100 | [diff] [blame] | 2644 | return NULL; |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2645 | } |
| 2646 | |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2647 | /* |
| 2648 | * The exported free_coherent function for dma_ops. |
Joerg Roedel | 431b2a2 | 2008-07-11 17:14:22 +0200 | [diff] [blame] | 2649 | */ |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2650 | static void free_coherent(struct device *dev, size_t size, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 2651 | void *virt_addr, dma_addr_t dma_addr, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2652 | unsigned long attrs) |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2653 | { |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2654 | struct protection_domain *domain; |
| 2655 | struct dma_ops_domain *dma_dom; |
| 2656 | struct page *page; |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2657 | |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2658 | page = virt_to_page(virt_addr); |
Joerg Roedel | 3b839a5 | 2015-04-01 14:58:47 +0200 | [diff] [blame] | 2659 | size = PAGE_ALIGN(size); |
| 2660 | |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2661 | domain = get_domain(dev); |
| 2662 | if (IS_ERR(domain)) |
| 2663 | goto free_mem; |
Joerg Roedel | 5b28df6 | 2008-12-02 17:49:42 +0100 | [diff] [blame] | 2664 | |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2665 | dma_dom = to_dma_ops_domain(domain); |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2666 | |
Linus Torvalds | e16c479 | 2018-06-11 12:22:12 -0700 | [diff] [blame^] | 2667 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); |
| 2668 | |
| 2669 | free_mem: |
| 2670 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
| 2671 | __free_pages(page, get_order(size)); |
Joerg Roedel | 5d8b53c | 2008-06-26 21:28:03 +0200 | [diff] [blame] | 2672 | } |
| 2673 | |
Joerg Roedel | c432f3d | 2008-06-26 21:28:04 +0200 | [diff] [blame] | 2674 | /* |
Joerg Roedel | b39ba6a | 2008-09-09 18:40:46 +0200 | [diff] [blame] | 2675 | * This function is called by the DMA layer to find out if we can handle a |
| 2676 | * particular device. It is part of the dma_ops. |
| 2677 | */ |
| 2678 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) |
| 2679 | { |
Christoph Hellwig | fec777c | 2018-03-19 11:38:15 +0100 | [diff] [blame] | 2680 | if (!dma_direct_supported(dev, mask)) |
Christoph Hellwig | 5860acc | 2017-05-22 11:38:27 +0200 | [diff] [blame] | 2681 | return 0; |
Joerg Roedel | 420aef8 | 2009-11-23 16:14:57 +0100 | [diff] [blame] | 2682 | return check_device(dev); |
Joerg Roedel | b39ba6a | 2008-09-09 18:40:46 +0200 | [diff] [blame] | 2683 | } |
| 2684 | |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 2685 | static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr) |
| 2686 | { |
| 2687 | return dma_addr == AMD_IOMMU_MAPPING_ERROR; |
| 2688 | } |
| 2689 | |
Bart Van Assche | 5299709 | 2017-01-20 13:04:01 -0800 | [diff] [blame] | 2690 | static const struct dma_map_ops amd_iommu_dma_ops = { |
Joerg Roedel | a639a8e | 2015-12-22 16:06:49 +0100 | [diff] [blame] | 2691 | .alloc = alloc_coherent, |
| 2692 | .free = free_coherent, |
| 2693 | .map_page = map_page, |
| 2694 | .unmap_page = unmap_page, |
| 2695 | .map_sg = map_sg, |
| 2696 | .unmap_sg = unmap_sg, |
| 2697 | .dma_supported = amd_iommu_dma_supported, |
Christoph Hellwig | a869572 | 2017-05-21 13:26:45 +0200 | [diff] [blame] | 2698 | .mapping_error = amd_iommu_mapping_error, |
Joerg Roedel | 6631ee9 | 2008-06-26 21:28:05 +0200 | [diff] [blame] | 2699 | }; |
| 2700 | |
Joerg Roedel | 81cd07b | 2016-07-07 18:01:10 +0200 | [diff] [blame] | 2701 | static int init_reserved_iova_ranges(void) |
| 2702 | { |
| 2703 | struct pci_dev *pdev = NULL; |
| 2704 | struct iova *val; |
| 2705 | |
Zhen Lei | aa3ac94 | 2017-09-21 16:52:45 +0100 | [diff] [blame] | 2706 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN); |
Joerg Roedel | 81cd07b | 2016-07-07 18:01:10 +0200 | [diff] [blame] | 2707 | |
| 2708 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, |
| 2709 | &reserved_rbtree_key); |
| 2710 | |
| 2711 | /* MSI memory range */ |
| 2712 | val = reserve_iova(&reserved_iova_ranges, |
| 2713 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); |
| 2714 | if (!val) { |
| 2715 | pr_err("Reserving MSI range failed\n"); |
| 2716 | return -ENOMEM; |
| 2717 | } |
| 2718 | |
| 2719 | /* HT memory range */ |
| 2720 | val = reserve_iova(&reserved_iova_ranges, |
| 2721 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); |
| 2722 | if (!val) { |
| 2723 | pr_err("Reserving HT range failed\n"); |
| 2724 | return -ENOMEM; |
| 2725 | } |
| 2726 | |
| 2727 | /* |
| 2728 | * Memory used for PCI resources |
| 2729 | * FIXME: Check whether we can reserve the PCI-hole completly |
| 2730 | */ |
| 2731 | for_each_pci_dev(pdev) { |
| 2732 | int i; |
| 2733 | |
| 2734 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { |
| 2735 | struct resource *r = &pdev->resource[i]; |
| 2736 | |
| 2737 | if (!(r->flags & IORESOURCE_MEM)) |
| 2738 | continue; |
| 2739 | |
| 2740 | val = reserve_iova(&reserved_iova_ranges, |
| 2741 | IOVA_PFN(r->start), |
| 2742 | IOVA_PFN(r->end)); |
| 2743 | if (!val) { |
| 2744 | pr_err("Reserve pci-resource range failed\n"); |
| 2745 | return -ENOMEM; |
| 2746 | } |
| 2747 | } |
| 2748 | } |
| 2749 | |
| 2750 | return 0; |
| 2751 | } |
| 2752 | |
Joerg Roedel | 3a18404c | 2015-05-28 18:41:45 +0200 | [diff] [blame] | 2753 | int __init amd_iommu_init_api(void) |
Joerg Roedel | 27c2127 | 2011-05-30 15:56:24 +0200 | [diff] [blame] | 2754 | { |
Joerg Roedel | 460c26d | 2017-06-02 14:28:01 +0200 | [diff] [blame] | 2755 | int ret, err = 0; |
Joerg Roedel | 307d585 | 2016-07-05 11:54:04 +0200 | [diff] [blame] | 2756 | |
| 2757 | ret = iova_cache_get(); |
| 2758 | if (ret) |
| 2759 | return ret; |
Wan Zongshun | 9a4d3bf5 | 2016-04-01 09:06:05 -0400 | [diff] [blame] | 2760 | |
Joerg Roedel | 81cd07b | 2016-07-07 18:01:10 +0200 | [diff] [blame] | 2761 | ret = init_reserved_iova_ranges(); |
| 2762 | if (ret) |
| 2763 | return ret; |
| 2764 | |
Wan Zongshun | 9a4d3bf5 | 2016-04-01 09:06:05 -0400 | [diff] [blame] | 2765 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
| 2766 | if (err) |
| 2767 | return err; |
| 2768 | #ifdef CONFIG_ARM_AMBA |
| 2769 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); |
| 2770 | if (err) |
| 2771 | return err; |
| 2772 | #endif |
Wan Zongshun | 0076cd3 | 2016-05-10 09:21:01 -0400 | [diff] [blame] | 2773 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
| 2774 | if (err) |
| 2775 | return err; |
Joerg Roedel | 460c26d | 2017-06-02 14:28:01 +0200 | [diff] [blame] | 2776 | |
Wan Zongshun | 9a4d3bf5 | 2016-04-01 09:06:05 -0400 | [diff] [blame] | 2777 | return 0; |
Joerg Roedel | f532509 | 2010-01-22 17:44:35 +0100 | [diff] [blame] | 2778 | } |
| 2779 | |
Joerg Roedel | 6631ee9 | 2008-06-26 21:28:05 +0200 | [diff] [blame] | 2780 | int __init amd_iommu_init_dma_ops(void) |
| 2781 | { |
Tom Lendacky | aba2d9a | 2017-10-06 16:35:40 -0500 | [diff] [blame] | 2782 | swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0; |
Joerg Roedel | 6631ee9 | 2008-06-26 21:28:05 +0200 | [diff] [blame] | 2783 | iommu_detected = 1; |
Joerg Roedel | 6631ee9 | 2008-06-26 21:28:05 +0200 | [diff] [blame] | 2784 | |
Joerg Roedel | 5271782 | 2015-07-28 16:58:51 +0200 | [diff] [blame] | 2785 | /* |
| 2786 | * In case we don't initialize SWIOTLB (actually the common case |
Tom Lendacky | aba2d9a | 2017-10-06 16:35:40 -0500 | [diff] [blame] | 2787 | * when AMD IOMMU is enabled and SME is not active), make sure there |
| 2788 | * are global dma_ops set as a fall-back for devices not handled by |
| 2789 | * this driver (for example non-PCI devices). When SME is active, |
| 2790 | * make sure that swiotlb variable remains set so the global dma_ops |
| 2791 | * continue to be SWIOTLB. |
Joerg Roedel | 5271782 | 2015-07-28 16:58:51 +0200 | [diff] [blame] | 2792 | */ |
| 2793 | if (!swiotlb) |
Christoph Hellwig | fec777c | 2018-03-19 11:38:15 +0100 | [diff] [blame] | 2794 | dma_ops = &dma_direct_ops; |
Joerg Roedel | 5271782 | 2015-07-28 16:58:51 +0200 | [diff] [blame] | 2795 | |
Joerg Roedel | 62410ee | 2012-06-12 16:42:43 +0200 | [diff] [blame] | 2796 | if (amd_iommu_unmap_flush) |
| 2797 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); |
| 2798 | else |
| 2799 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
| 2800 | |
Joerg Roedel | 6631ee9 | 2008-06-26 21:28:05 +0200 | [diff] [blame] | 2801 | return 0; |
Joerg Roedel | c5b5da9 | 2016-07-06 11:55:37 +0200 | [diff] [blame] | 2802 | |
Joerg Roedel | 6631ee9 | 2008-06-26 21:28:05 +0200 | [diff] [blame] | 2803 | } |
Joerg Roedel | 6d98cd8 | 2008-12-08 12:05:55 +0100 | [diff] [blame] | 2804 | |
| 2805 | /***************************************************************************** |
| 2806 | * |
| 2807 | * The following functions belong to the exported interface of AMD IOMMU |
| 2808 | * |
| 2809 | * This interface allows access to lower level functions of the IOMMU |
| 2810 | * like protection domain handling and assignement of devices to domains |
| 2811 | * which is not possible with the dma_ops interface. |
| 2812 | * |
| 2813 | *****************************************************************************/ |
| 2814 | |
Joerg Roedel | 6d98cd8 | 2008-12-08 12:05:55 +0100 | [diff] [blame] | 2815 | static void cleanup_domain(struct protection_domain *domain) |
| 2816 | { |
Joerg Roedel | 9b29d3c | 2014-08-05 17:50:15 +0200 | [diff] [blame] | 2817 | struct iommu_dev_data *entry; |
Joerg Roedel | 6d98cd8 | 2008-12-08 12:05:55 +0100 | [diff] [blame] | 2818 | unsigned long flags; |
Joerg Roedel | 6d98cd8 | 2008-12-08 12:05:55 +0100 | [diff] [blame] | 2819 | |
Sebastian Andrzej Siewior | 2cd1083 | 2018-03-22 16:22:41 +0100 | [diff] [blame] | 2820 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
Joerg Roedel | 6d98cd8 | 2008-12-08 12:05:55 +0100 | [diff] [blame] | 2821 | |
Joerg Roedel | 9b29d3c | 2014-08-05 17:50:15 +0200 | [diff] [blame] | 2822 | while (!list_empty(&domain->dev_list)) { |
| 2823 | entry = list_first_entry(&domain->dev_list, |
| 2824 | struct iommu_dev_data, list); |
Anna-Maria Gleixner | ea3fd04 | 2018-05-07 14:53:27 +0200 | [diff] [blame] | 2825 | BUG_ON(!entry->domain); |
Joerg Roedel | 9b29d3c | 2014-08-05 17:50:15 +0200 | [diff] [blame] | 2826 | __detach_device(entry); |
Joerg Roedel | 492667d | 2009-11-27 13:25:47 +0100 | [diff] [blame] | 2827 | } |
Joerg Roedel | 6d98cd8 | 2008-12-08 12:05:55 +0100 | [diff] [blame] | 2828 | |
Sebastian Andrzej Siewior | 2cd1083 | 2018-03-22 16:22:41 +0100 | [diff] [blame] | 2829 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
Joerg Roedel | 6d98cd8 | 2008-12-08 12:05:55 +0100 | [diff] [blame] | 2830 | } |
| 2831 | |
Joerg Roedel | 2650815 | 2009-08-26 16:52:40 +0200 | [diff] [blame] | 2832 | static void protection_domain_free(struct protection_domain *domain) |
| 2833 | { |
| 2834 | if (!domain) |
| 2835 | return; |
| 2836 | |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 2837 | del_domain_from_list(domain); |
| 2838 | |
Joerg Roedel | 2650815 | 2009-08-26 16:52:40 +0200 | [diff] [blame] | 2839 | if (domain->id) |
| 2840 | domain_id_free(domain->id); |
| 2841 | |
| 2842 | kfree(domain); |
| 2843 | } |
| 2844 | |
Joerg Roedel | 7a5a566 | 2015-06-30 08:56:11 +0200 | [diff] [blame] | 2845 | static int protection_domain_init(struct protection_domain *domain) |
| 2846 | { |
| 2847 | spin_lock_init(&domain->lock); |
| 2848 | mutex_init(&domain->api_lock); |
| 2849 | domain->id = domain_id_alloc(); |
| 2850 | if (!domain->id) |
| 2851 | return -ENOMEM; |
| 2852 | INIT_LIST_HEAD(&domain->dev_list); |
| 2853 | |
| 2854 | return 0; |
| 2855 | } |
| 2856 | |
Joerg Roedel | 2650815 | 2009-08-26 16:52:40 +0200 | [diff] [blame] | 2857 | static struct protection_domain *protection_domain_alloc(void) |
Joerg Roedel | c156e34 | 2008-12-02 18:13:27 +0100 | [diff] [blame] | 2858 | { |
| 2859 | struct protection_domain *domain; |
| 2860 | |
| 2861 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
| 2862 | if (!domain) |
Joerg Roedel | 2650815 | 2009-08-26 16:52:40 +0200 | [diff] [blame] | 2863 | return NULL; |
Joerg Roedel | c156e34 | 2008-12-02 18:13:27 +0100 | [diff] [blame] | 2864 | |
Joerg Roedel | 7a5a566 | 2015-06-30 08:56:11 +0200 | [diff] [blame] | 2865 | if (protection_domain_init(domain)) |
Joerg Roedel | 2650815 | 2009-08-26 16:52:40 +0200 | [diff] [blame] | 2866 | goto out_err; |
| 2867 | |
Joerg Roedel | aeb26f5 | 2009-11-20 16:44:01 +0100 | [diff] [blame] | 2868 | add_domain_to_list(domain); |
| 2869 | |
Joerg Roedel | 2650815 | 2009-08-26 16:52:40 +0200 | [diff] [blame] | 2870 | return domain; |
| 2871 | |
| 2872 | out_err: |
| 2873 | kfree(domain); |
| 2874 | |
| 2875 | return NULL; |
| 2876 | } |
| 2877 | |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 2878 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
| 2879 | { |
| 2880 | struct protection_domain *pdomain; |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 2881 | struct dma_ops_domain *dma_domain; |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 2882 | |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 2883 | switch (type) { |
| 2884 | case IOMMU_DOMAIN_UNMANAGED: |
| 2885 | pdomain = protection_domain_alloc(); |
| 2886 | if (!pdomain) |
| 2887 | return NULL; |
| 2888 | |
| 2889 | pdomain->mode = PAGE_MODE_3_LEVEL; |
| 2890 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
| 2891 | if (!pdomain->pt_root) { |
| 2892 | protection_domain_free(pdomain); |
| 2893 | return NULL; |
| 2894 | } |
| 2895 | |
| 2896 | pdomain->domain.geometry.aperture_start = 0; |
| 2897 | pdomain->domain.geometry.aperture_end = ~0ULL; |
| 2898 | pdomain->domain.geometry.force_aperture = true; |
| 2899 | |
| 2900 | break; |
| 2901 | case IOMMU_DOMAIN_DMA: |
| 2902 | dma_domain = dma_ops_domain_alloc(); |
| 2903 | if (!dma_domain) { |
| 2904 | pr_err("AMD-Vi: Failed to allocate\n"); |
| 2905 | return NULL; |
| 2906 | } |
| 2907 | pdomain = &dma_domain->domain; |
| 2908 | break; |
Joerg Roedel | 07f643a | 2015-05-28 18:41:41 +0200 | [diff] [blame] | 2909 | case IOMMU_DOMAIN_IDENTITY: |
| 2910 | pdomain = protection_domain_alloc(); |
| 2911 | if (!pdomain) |
| 2912 | return NULL; |
| 2913 | |
| 2914 | pdomain->mode = PAGE_MODE_NONE; |
| 2915 | break; |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 2916 | default: |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 2917 | return NULL; |
Joerg Roedel | 0bb6e24 | 2015-05-28 18:41:40 +0200 | [diff] [blame] | 2918 | } |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 2919 | |
| 2920 | return &pdomain->domain; |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 2921 | } |
| 2922 | |
| 2923 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
Joerg Roedel | 2650815 | 2009-08-26 16:52:40 +0200 | [diff] [blame] | 2924 | { |
| 2925 | struct protection_domain *domain; |
Joerg Roedel | cda7005 | 2016-07-07 15:57:04 +0200 | [diff] [blame] | 2926 | struct dma_ops_domain *dma_dom; |
Joerg Roedel | 98383fc | 2008-12-02 18:34:12 +0100 | [diff] [blame] | 2927 | |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 2928 | domain = to_pdomain(dom); |
| 2929 | |
Joerg Roedel | 98383fc | 2008-12-02 18:34:12 +0100 | [diff] [blame] | 2930 | if (domain->dev_cnt > 0) |
| 2931 | cleanup_domain(domain); |
| 2932 | |
| 2933 | BUG_ON(domain->dev_cnt != 0); |
| 2934 | |
Joerg Roedel | cda7005 | 2016-07-07 15:57:04 +0200 | [diff] [blame] | 2935 | if (!dom) |
| 2936 | return; |
Joerg Roedel | 98383fc | 2008-12-02 18:34:12 +0100 | [diff] [blame] | 2937 | |
Joerg Roedel | cda7005 | 2016-07-07 15:57:04 +0200 | [diff] [blame] | 2938 | switch (dom->type) { |
| 2939 | case IOMMU_DOMAIN_DMA: |
Joerg Roedel | 281e8cc | 2016-07-07 16:12:02 +0200 | [diff] [blame] | 2940 | /* Now release the domain */ |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 2941 | dma_dom = to_dma_ops_domain(domain); |
Joerg Roedel | cda7005 | 2016-07-07 15:57:04 +0200 | [diff] [blame] | 2942 | dma_ops_domain_free(dma_dom); |
| 2943 | break; |
| 2944 | default: |
| 2945 | if (domain->mode != PAGE_MODE_NONE) |
| 2946 | free_pagetable(domain); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 2947 | |
Joerg Roedel | cda7005 | 2016-07-07 15:57:04 +0200 | [diff] [blame] | 2948 | if (domain->flags & PD_IOMMUV2_MASK) |
| 2949 | free_gcr3_table(domain); |
| 2950 | |
| 2951 | protection_domain_free(domain); |
| 2952 | break; |
| 2953 | } |
Joerg Roedel | 98383fc | 2008-12-02 18:34:12 +0100 | [diff] [blame] | 2954 | } |
| 2955 | |
Joerg Roedel | 684f288 | 2008-12-08 12:07:44 +0100 | [diff] [blame] | 2956 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
| 2957 | struct device *dev) |
| 2958 | { |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 2959 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
Joerg Roedel | 684f288 | 2008-12-08 12:07:44 +0100 | [diff] [blame] | 2960 | struct amd_iommu *iommu; |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 2961 | int devid; |
Joerg Roedel | 684f288 | 2008-12-08 12:07:44 +0100 | [diff] [blame] | 2962 | |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 2963 | if (!check_device(dev)) |
Joerg Roedel | 684f288 | 2008-12-08 12:07:44 +0100 | [diff] [blame] | 2964 | return; |
| 2965 | |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 2966 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 2967 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 2968 | return; |
Joerg Roedel | 684f288 | 2008-12-08 12:07:44 +0100 | [diff] [blame] | 2969 | |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 2970 | if (dev_data->domain != NULL) |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2971 | detach_device(dev); |
Joerg Roedel | 684f288 | 2008-12-08 12:07:44 +0100 | [diff] [blame] | 2972 | |
| 2973 | iommu = amd_iommu_rlookup_table[devid]; |
| 2974 | if (!iommu) |
| 2975 | return; |
| 2976 | |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 2977 | #ifdef CONFIG_IRQ_REMAP |
| 2978 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && |
| 2979 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) |
| 2980 | dev_data->use_vapic = 0; |
| 2981 | #endif |
| 2982 | |
Joerg Roedel | 684f288 | 2008-12-08 12:07:44 +0100 | [diff] [blame] | 2983 | iommu_completion_wait(iommu); |
| 2984 | } |
| 2985 | |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 2986 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
| 2987 | struct device *dev) |
| 2988 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 2989 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 2990 | struct iommu_dev_data *dev_data; |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 2991 | struct amd_iommu *iommu; |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 2992 | int ret; |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 2993 | |
Joerg Roedel | 98fc5a6 | 2009-11-24 17:19:23 +0100 | [diff] [blame] | 2994 | if (!check_device(dev)) |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 2995 | return -EINVAL; |
| 2996 | |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 2997 | dev_data = dev->archdata.iommu; |
| 2998 | |
Joerg Roedel | f62dda6 | 2011-06-09 12:55:35 +0200 | [diff] [blame] | 2999 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 3000 | if (!iommu) |
| 3001 | return -EINVAL; |
| 3002 | |
Joerg Roedel | 657cbb6 | 2009-11-23 15:26:46 +0100 | [diff] [blame] | 3003 | if (dev_data->domain) |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 3004 | detach_device(dev); |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 3005 | |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 3006 | ret = attach_device(dev, domain); |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 3007 | |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 3008 | #ifdef CONFIG_IRQ_REMAP |
| 3009 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { |
| 3010 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) |
| 3011 | dev_data->use_vapic = 1; |
| 3012 | else |
| 3013 | dev_data->use_vapic = 0; |
| 3014 | } |
| 3015 | #endif |
| 3016 | |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 3017 | iommu_completion_wait(iommu); |
| 3018 | |
Joerg Roedel | 15898bb | 2009-11-24 15:39:42 +0100 | [diff] [blame] | 3019 | return ret; |
Joerg Roedel | 0110606 | 2008-12-02 19:34:11 +0100 | [diff] [blame] | 3020 | } |
| 3021 | |
Joerg Roedel | 468e236 | 2010-01-21 16:37:36 +0100 | [diff] [blame] | 3022 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 3023 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
Joerg Roedel | c6229ca | 2008-12-02 19:48:43 +0100 | [diff] [blame] | 3024 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3025 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | c6229ca | 2008-12-02 19:48:43 +0100 | [diff] [blame] | 3026 | int prot = 0; |
| 3027 | int ret; |
| 3028 | |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 3029 | if (domain->mode == PAGE_MODE_NONE) |
| 3030 | return -EINVAL; |
| 3031 | |
Joerg Roedel | c6229ca | 2008-12-02 19:48:43 +0100 | [diff] [blame] | 3032 | if (iommu_prot & IOMMU_READ) |
| 3033 | prot |= IOMMU_PROT_IR; |
| 3034 | if (iommu_prot & IOMMU_WRITE) |
| 3035 | prot |= IOMMU_PROT_IW; |
| 3036 | |
Joerg Roedel | 5d214fe | 2010-02-08 14:44:49 +0100 | [diff] [blame] | 3037 | mutex_lock(&domain->api_lock); |
Joerg Roedel | b911b89 | 2016-07-05 14:29:11 +0200 | [diff] [blame] | 3038 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
Joerg Roedel | 5d214fe | 2010-02-08 14:44:49 +0100 | [diff] [blame] | 3039 | mutex_unlock(&domain->api_lock); |
| 3040 | |
Joerg Roedel | 795e74f7 | 2010-05-11 17:40:57 +0200 | [diff] [blame] | 3041 | return ret; |
Joerg Roedel | c6229ca | 2008-12-02 19:48:43 +0100 | [diff] [blame] | 3042 | } |
| 3043 | |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 3044 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
| 3045 | size_t page_size) |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 3046 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3047 | struct protection_domain *domain = to_pdomain(dom); |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 3048 | size_t unmap_size; |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 3049 | |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 3050 | if (domain->mode == PAGE_MODE_NONE) |
Suravee Suthikulpanit | c5611a8 | 2018-02-05 05:45:53 -0500 | [diff] [blame] | 3051 | return 0; |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 3052 | |
Joerg Roedel | 5d214fe | 2010-02-08 14:44:49 +0100 | [diff] [blame] | 3053 | mutex_lock(&domain->api_lock); |
Joerg Roedel | 468e236 | 2010-01-21 16:37:36 +0100 | [diff] [blame] | 3054 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
Joerg Roedel | 795e74f7 | 2010-05-11 17:40:57 +0200 | [diff] [blame] | 3055 | mutex_unlock(&domain->api_lock); |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 3056 | |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 3057 | return unmap_size; |
Joerg Roedel | eb74ff6 | 2008-12-02 19:59:10 +0100 | [diff] [blame] | 3058 | } |
| 3059 | |
Joerg Roedel | 645c4c8 | 2008-12-02 20:05:50 +0100 | [diff] [blame] | 3060 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
Varun Sethi | bb5547a | 2013-03-29 01:23:58 +0530 | [diff] [blame] | 3061 | dma_addr_t iova) |
Joerg Roedel | 645c4c8 | 2008-12-02 20:05:50 +0100 | [diff] [blame] | 3062 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3063 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | 3039ca1 | 2015-04-01 14:58:48 +0200 | [diff] [blame] | 3064 | unsigned long offset_mask, pte_pgsize; |
Joerg Roedel | f03152b | 2010-01-21 16:15:24 +0100 | [diff] [blame] | 3065 | u64 *pte, __pte; |
Joerg Roedel | 645c4c8 | 2008-12-02 20:05:50 +0100 | [diff] [blame] | 3066 | |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 3067 | if (domain->mode == PAGE_MODE_NONE) |
| 3068 | return iova; |
| 3069 | |
Joerg Roedel | 3039ca1 | 2015-04-01 14:58:48 +0200 | [diff] [blame] | 3070 | pte = fetch_pte(domain, iova, &pte_pgsize); |
Joerg Roedel | 645c4c8 | 2008-12-02 20:05:50 +0100 | [diff] [blame] | 3071 | |
Joerg Roedel | a6d41a4 | 2009-09-02 17:08:55 +0200 | [diff] [blame] | 3072 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
Joerg Roedel | 645c4c8 | 2008-12-02 20:05:50 +0100 | [diff] [blame] | 3073 | return 0; |
| 3074 | |
Joerg Roedel | b24b1b6 | 2015-04-01 14:58:51 +0200 | [diff] [blame] | 3075 | offset_mask = pte_pgsize - 1; |
| 3076 | __pte = *pte & PM_ADDR_MASK; |
Joerg Roedel | f03152b | 2010-01-21 16:15:24 +0100 | [diff] [blame] | 3077 | |
Joerg Roedel | b24b1b6 | 2015-04-01 14:58:51 +0200 | [diff] [blame] | 3078 | return (__pte & ~offset_mask) | (iova & offset_mask); |
Joerg Roedel | 645c4c8 | 2008-12-02 20:05:50 +0100 | [diff] [blame] | 3079 | } |
| 3080 | |
Joerg Roedel | ab63648 | 2014-09-05 10:48:21 +0200 | [diff] [blame] | 3081 | static bool amd_iommu_capable(enum iommu_cap cap) |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 3082 | { |
Joerg Roedel | 80a506b | 2010-07-27 17:14:24 +0200 | [diff] [blame] | 3083 | switch (cap) { |
| 3084 | case IOMMU_CAP_CACHE_COHERENCY: |
Joerg Roedel | ab63648 | 2014-09-05 10:48:21 +0200 | [diff] [blame] | 3085 | return true; |
Joerg Roedel | bdddadc | 2012-07-02 18:38:13 +0200 | [diff] [blame] | 3086 | case IOMMU_CAP_INTR_REMAP: |
Joerg Roedel | ab63648 | 2014-09-05 10:48:21 +0200 | [diff] [blame] | 3087 | return (irq_remapping_enabled == 1); |
Will Deacon | cfdeec2 | 2014-10-27 11:24:48 +0000 | [diff] [blame] | 3088 | case IOMMU_CAP_NOEXEC: |
| 3089 | return false; |
Joerg Roedel | 80a506b | 2010-07-27 17:14:24 +0200 | [diff] [blame] | 3090 | } |
| 3091 | |
Joerg Roedel | ab63648 | 2014-09-05 10:48:21 +0200 | [diff] [blame] | 3092 | return false; |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 3093 | } |
| 3094 | |
Eric Auger | e5b5234 | 2017-01-19 20:57:47 +0000 | [diff] [blame] | 3095 | static void amd_iommu_get_resv_regions(struct device *dev, |
| 3096 | struct list_head *head) |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3097 | { |
Eric Auger | 4397f32 | 2017-01-19 20:57:54 +0000 | [diff] [blame] | 3098 | struct iommu_resv_region *region; |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3099 | struct unity_map_entry *entry; |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 3100 | int devid; |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3101 | |
| 3102 | devid = get_device_id(dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 3103 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 3104 | return; |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3105 | |
| 3106 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { |
Eric Auger | 4397f32 | 2017-01-19 20:57:54 +0000 | [diff] [blame] | 3107 | size_t length; |
| 3108 | int prot = 0; |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3109 | |
| 3110 | if (devid < entry->devid_start || devid > entry->devid_end) |
| 3111 | continue; |
| 3112 | |
Eric Auger | 4397f32 | 2017-01-19 20:57:54 +0000 | [diff] [blame] | 3113 | length = entry->address_end - entry->address_start; |
| 3114 | if (entry->prot & IOMMU_PROT_IR) |
| 3115 | prot |= IOMMU_READ; |
| 3116 | if (entry->prot & IOMMU_PROT_IW) |
| 3117 | prot |= IOMMU_WRITE; |
| 3118 | |
| 3119 | region = iommu_alloc_resv_region(entry->address_start, |
| 3120 | length, prot, |
| 3121 | IOMMU_RESV_DIRECT); |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3122 | if (!region) { |
| 3123 | pr_err("Out of memory allocating dm-regions for %s\n", |
| 3124 | dev_name(dev)); |
| 3125 | return; |
| 3126 | } |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3127 | list_add_tail(®ion->list, head); |
| 3128 | } |
Eric Auger | 4397f32 | 2017-01-19 20:57:54 +0000 | [diff] [blame] | 3129 | |
| 3130 | region = iommu_alloc_resv_region(MSI_RANGE_START, |
| 3131 | MSI_RANGE_END - MSI_RANGE_START + 1, |
Robin Murphy | 9d3a4de | 2017-03-16 17:00:16 +0000 | [diff] [blame] | 3132 | 0, IOMMU_RESV_MSI); |
Eric Auger | 4397f32 | 2017-01-19 20:57:54 +0000 | [diff] [blame] | 3133 | if (!region) |
| 3134 | return; |
| 3135 | list_add_tail(®ion->list, head); |
| 3136 | |
| 3137 | region = iommu_alloc_resv_region(HT_RANGE_START, |
| 3138 | HT_RANGE_END - HT_RANGE_START + 1, |
| 3139 | 0, IOMMU_RESV_RESERVED); |
| 3140 | if (!region) |
| 3141 | return; |
| 3142 | list_add_tail(®ion->list, head); |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3143 | } |
| 3144 | |
Eric Auger | e5b5234 | 2017-01-19 20:57:47 +0000 | [diff] [blame] | 3145 | static void amd_iommu_put_resv_regions(struct device *dev, |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3146 | struct list_head *head) |
| 3147 | { |
Eric Auger | e5b5234 | 2017-01-19 20:57:47 +0000 | [diff] [blame] | 3148 | struct iommu_resv_region *entry, *next; |
Joerg Roedel | 35cf248 | 2015-05-28 18:41:37 +0200 | [diff] [blame] | 3149 | |
| 3150 | list_for_each_entry_safe(entry, next, head, list) |
| 3151 | kfree(entry); |
| 3152 | } |
| 3153 | |
Eric Auger | e5b5234 | 2017-01-19 20:57:47 +0000 | [diff] [blame] | 3154 | static void amd_iommu_apply_resv_region(struct device *dev, |
Joerg Roedel | 8d54d6c | 2016-07-05 13:32:20 +0200 | [diff] [blame] | 3155 | struct iommu_domain *domain, |
Eric Auger | e5b5234 | 2017-01-19 20:57:47 +0000 | [diff] [blame] | 3156 | struct iommu_resv_region *region) |
Joerg Roedel | 8d54d6c | 2016-07-05 13:32:20 +0200 | [diff] [blame] | 3157 | { |
Joerg Roedel | b3311b0 | 2016-07-08 13:31:31 +0200 | [diff] [blame] | 3158 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); |
Joerg Roedel | 8d54d6c | 2016-07-05 13:32:20 +0200 | [diff] [blame] | 3159 | unsigned long start, end; |
| 3160 | |
| 3161 | start = IOVA_PFN(region->start); |
Gary R Hook | b92b4fb | 2017-11-03 10:50:34 -0600 | [diff] [blame] | 3162 | end = IOVA_PFN(region->start + region->length - 1); |
Joerg Roedel | 8d54d6c | 2016-07-05 13:32:20 +0200 | [diff] [blame] | 3163 | |
| 3164 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); |
| 3165 | } |
| 3166 | |
Baoquan He | df3f7a6 | 2017-08-09 16:33:41 +0800 | [diff] [blame] | 3167 | static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, |
| 3168 | struct device *dev) |
| 3169 | { |
| 3170 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
| 3171 | return dev_data->defer_attach; |
| 3172 | } |
| 3173 | |
Suravee Suthikulpanit | eb5ecd1 | 2018-02-21 14:19:45 +0700 | [diff] [blame] | 3174 | static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain) |
| 3175 | { |
| 3176 | struct protection_domain *dom = to_pdomain(domain); |
| 3177 | |
| 3178 | domain_flush_tlb_pde(dom); |
| 3179 | domain_flush_complete(dom); |
| 3180 | } |
| 3181 | |
| 3182 | static void amd_iommu_iotlb_range_add(struct iommu_domain *domain, |
| 3183 | unsigned long iova, size_t size) |
| 3184 | { |
| 3185 | } |
| 3186 | |
Joerg Roedel | b0119e8 | 2017-02-01 13:23:08 +0100 | [diff] [blame] | 3187 | const struct iommu_ops amd_iommu_ops = { |
Joerg Roedel | ab63648 | 2014-09-05 10:48:21 +0200 | [diff] [blame] | 3188 | .capable = amd_iommu_capable, |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3189 | .domain_alloc = amd_iommu_domain_alloc, |
| 3190 | .domain_free = amd_iommu_domain_free, |
Joerg Roedel | 26961ef | 2008-12-03 17:00:17 +0100 | [diff] [blame] | 3191 | .attach_dev = amd_iommu_attach_device, |
| 3192 | .detach_dev = amd_iommu_detach_device, |
Joerg Roedel | 468e236 | 2010-01-21 16:37:36 +0100 | [diff] [blame] | 3193 | .map = amd_iommu_map, |
| 3194 | .unmap = amd_iommu_unmap, |
Olav Haugan | 315786e | 2014-10-25 09:55:16 -0700 | [diff] [blame] | 3195 | .map_sg = default_iommu_map_sg, |
Joerg Roedel | 26961ef | 2008-12-03 17:00:17 +0100 | [diff] [blame] | 3196 | .iova_to_phys = amd_iommu_iova_to_phys, |
Joerg Roedel | aafd8ba | 2015-05-28 18:41:39 +0200 | [diff] [blame] | 3197 | .add_device = amd_iommu_add_device, |
| 3198 | .remove_device = amd_iommu_remove_device, |
Wan Zongshun | b097d11 | 2016-04-01 09:06:04 -0400 | [diff] [blame] | 3199 | .device_group = amd_iommu_device_group, |
Eric Auger | e5b5234 | 2017-01-19 20:57:47 +0000 | [diff] [blame] | 3200 | .get_resv_regions = amd_iommu_get_resv_regions, |
| 3201 | .put_resv_regions = amd_iommu_put_resv_regions, |
| 3202 | .apply_resv_region = amd_iommu_apply_resv_region, |
Baoquan He | df3f7a6 | 2017-08-09 16:33:41 +0800 | [diff] [blame] | 3203 | .is_attach_deferred = amd_iommu_is_attach_deferred, |
Ohad Ben-Cohen | aa3de9c | 2011-11-10 11:32:29 +0200 | [diff] [blame] | 3204 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
Suravee Suthikulpanit | eb5ecd1 | 2018-02-21 14:19:45 +0700 | [diff] [blame] | 3205 | .flush_iotlb_all = amd_iommu_flush_iotlb_all, |
| 3206 | .iotlb_range_add = amd_iommu_iotlb_range_add, |
| 3207 | .iotlb_sync = amd_iommu_flush_iotlb_all, |
Joerg Roedel | 26961ef | 2008-12-03 17:00:17 +0100 | [diff] [blame] | 3208 | }; |
| 3209 | |
Joerg Roedel | 0feae53 | 2009-08-26 15:26:30 +0200 | [diff] [blame] | 3210 | /***************************************************************************** |
| 3211 | * |
| 3212 | * The next functions do a basic initialization of IOMMU for pass through |
| 3213 | * mode |
| 3214 | * |
| 3215 | * In passthrough mode the IOMMU is initialized and enabled but not used for |
| 3216 | * DMA-API translation. |
| 3217 | * |
| 3218 | *****************************************************************************/ |
| 3219 | |
Joerg Roedel | 72e1dcc | 2011-11-10 19:13:51 +0100 | [diff] [blame] | 3220 | /* IOMMUv2 specific functions */ |
| 3221 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) |
| 3222 | { |
| 3223 | return atomic_notifier_chain_register(&ppr_notifier, nb); |
| 3224 | } |
| 3225 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); |
| 3226 | |
| 3227 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) |
| 3228 | { |
| 3229 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); |
| 3230 | } |
| 3231 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 3232 | |
| 3233 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) |
| 3234 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3235 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | 132bd68 | 2011-11-17 14:18:46 +0100 | [diff] [blame] | 3236 | unsigned long flags; |
| 3237 | |
| 3238 | spin_lock_irqsave(&domain->lock, flags); |
| 3239 | |
| 3240 | /* Update data structure */ |
| 3241 | domain->mode = PAGE_MODE_NONE; |
| 3242 | domain->updated = true; |
| 3243 | |
| 3244 | /* Make changes visible to IOMMUs */ |
| 3245 | update_domain(domain); |
| 3246 | |
| 3247 | /* Page-table is not visible to IOMMU anymore, so free it */ |
| 3248 | free_pagetable(domain); |
| 3249 | |
| 3250 | spin_unlock_irqrestore(&domain->lock, flags); |
| 3251 | } |
| 3252 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 3253 | |
| 3254 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) |
| 3255 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3256 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | 52815b7 | 2011-11-17 17:24:28 +0100 | [diff] [blame] | 3257 | unsigned long flags; |
| 3258 | int levels, ret; |
| 3259 | |
| 3260 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) |
| 3261 | return -EINVAL; |
| 3262 | |
| 3263 | /* Number of GCR3 table levels required */ |
| 3264 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) |
| 3265 | levels += 1; |
| 3266 | |
| 3267 | if (levels > amd_iommu_max_glx_val) |
| 3268 | return -EINVAL; |
| 3269 | |
| 3270 | spin_lock_irqsave(&domain->lock, flags); |
| 3271 | |
| 3272 | /* |
| 3273 | * Save us all sanity checks whether devices already in the |
| 3274 | * domain support IOMMUv2. Just force that the domain has no |
| 3275 | * devices attached when it is switched into IOMMUv2 mode. |
| 3276 | */ |
| 3277 | ret = -EBUSY; |
| 3278 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) |
| 3279 | goto out; |
| 3280 | |
| 3281 | ret = -ENOMEM; |
| 3282 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); |
| 3283 | if (domain->gcr3_tbl == NULL) |
| 3284 | goto out; |
| 3285 | |
| 3286 | domain->glx = levels; |
| 3287 | domain->flags |= PD_IOMMUV2_MASK; |
| 3288 | domain->updated = true; |
| 3289 | |
| 3290 | update_domain(domain); |
| 3291 | |
| 3292 | ret = 0; |
| 3293 | |
| 3294 | out: |
| 3295 | spin_unlock_irqrestore(&domain->lock, flags); |
| 3296 | |
| 3297 | return ret; |
| 3298 | } |
| 3299 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 3300 | |
| 3301 | static int __flush_pasid(struct protection_domain *domain, int pasid, |
| 3302 | u64 address, bool size) |
| 3303 | { |
| 3304 | struct iommu_dev_data *dev_data; |
| 3305 | struct iommu_cmd cmd; |
| 3306 | int i, ret; |
| 3307 | |
| 3308 | if (!(domain->flags & PD_IOMMUV2_MASK)) |
| 3309 | return -EINVAL; |
| 3310 | |
| 3311 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); |
| 3312 | |
| 3313 | /* |
| 3314 | * IOMMU TLB needs to be flushed before Device TLB to |
| 3315 | * prevent device TLB refill from IOMMU TLB |
| 3316 | */ |
Suravee Suthikulpanit | 6b9376e | 2017-02-24 02:48:17 -0600 | [diff] [blame] | 3317 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 3318 | if (domain->dev_iommu[i] == 0) |
| 3319 | continue; |
| 3320 | |
| 3321 | ret = iommu_queue_command(amd_iommus[i], &cmd); |
| 3322 | if (ret != 0) |
| 3323 | goto out; |
| 3324 | } |
| 3325 | |
| 3326 | /* Wait until IOMMU TLB flushes are complete */ |
| 3327 | domain_flush_complete(domain); |
| 3328 | |
| 3329 | /* Now flush device TLBs */ |
| 3330 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
| 3331 | struct amd_iommu *iommu; |
| 3332 | int qdep; |
| 3333 | |
Joerg Roedel | 1c1cc45 | 2015-07-30 11:24:45 +0200 | [diff] [blame] | 3334 | /* |
| 3335 | There might be non-IOMMUv2 capable devices in an IOMMUv2 |
| 3336 | * domain. |
| 3337 | */ |
| 3338 | if (!dev_data->ats.enabled) |
| 3339 | continue; |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 3340 | |
| 3341 | qdep = dev_data->ats.qdep; |
| 3342 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
| 3343 | |
| 3344 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, |
| 3345 | qdep, address, size); |
| 3346 | |
| 3347 | ret = iommu_queue_command(iommu, &cmd); |
| 3348 | if (ret != 0) |
| 3349 | goto out; |
| 3350 | } |
| 3351 | |
| 3352 | /* Wait until all device TLBs are flushed */ |
| 3353 | domain_flush_complete(domain); |
| 3354 | |
| 3355 | ret = 0; |
| 3356 | |
| 3357 | out: |
| 3358 | |
| 3359 | return ret; |
| 3360 | } |
| 3361 | |
| 3362 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, |
| 3363 | u64 address) |
| 3364 | { |
| 3365 | return __flush_pasid(domain, pasid, address, false); |
| 3366 | } |
| 3367 | |
| 3368 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, |
| 3369 | u64 address) |
| 3370 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3371 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 3372 | unsigned long flags; |
| 3373 | int ret; |
| 3374 | |
| 3375 | spin_lock_irqsave(&domain->lock, flags); |
| 3376 | ret = __amd_iommu_flush_page(domain, pasid, address); |
| 3377 | spin_unlock_irqrestore(&domain->lock, flags); |
| 3378 | |
| 3379 | return ret; |
| 3380 | } |
| 3381 | EXPORT_SYMBOL(amd_iommu_flush_page); |
| 3382 | |
| 3383 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) |
| 3384 | { |
| 3385 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
| 3386 | true); |
| 3387 | } |
| 3388 | |
| 3389 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) |
| 3390 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3391 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | 22e266c | 2011-11-21 15:59:08 +0100 | [diff] [blame] | 3392 | unsigned long flags; |
| 3393 | int ret; |
| 3394 | |
| 3395 | spin_lock_irqsave(&domain->lock, flags); |
| 3396 | ret = __amd_iommu_flush_tlb(domain, pasid); |
| 3397 | spin_unlock_irqrestore(&domain->lock, flags); |
| 3398 | |
| 3399 | return ret; |
| 3400 | } |
| 3401 | EXPORT_SYMBOL(amd_iommu_flush_tlb); |
| 3402 | |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 3403 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
| 3404 | { |
| 3405 | int index; |
| 3406 | u64 *pte; |
| 3407 | |
| 3408 | while (true) { |
| 3409 | |
| 3410 | index = (pasid >> (9 * level)) & 0x1ff; |
| 3411 | pte = &root[index]; |
| 3412 | |
| 3413 | if (level == 0) |
| 3414 | break; |
| 3415 | |
| 3416 | if (!(*pte & GCR3_VALID)) { |
| 3417 | if (!alloc) |
| 3418 | return NULL; |
| 3419 | |
| 3420 | root = (void *)get_zeroed_page(GFP_ATOMIC); |
| 3421 | if (root == NULL) |
| 3422 | return NULL; |
| 3423 | |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 3424 | *pte = iommu_virt_to_phys(root) | GCR3_VALID; |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 3425 | } |
| 3426 | |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 3427 | root = iommu_phys_to_virt(*pte & PAGE_MASK); |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 3428 | |
| 3429 | level -= 1; |
| 3430 | } |
| 3431 | |
| 3432 | return pte; |
| 3433 | } |
| 3434 | |
| 3435 | static int __set_gcr3(struct protection_domain *domain, int pasid, |
| 3436 | unsigned long cr3) |
| 3437 | { |
| 3438 | u64 *pte; |
| 3439 | |
| 3440 | if (domain->mode != PAGE_MODE_NONE) |
| 3441 | return -EINVAL; |
| 3442 | |
| 3443 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); |
| 3444 | if (pte == NULL) |
| 3445 | return -ENOMEM; |
| 3446 | |
| 3447 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; |
| 3448 | |
| 3449 | return __amd_iommu_flush_tlb(domain, pasid); |
| 3450 | } |
| 3451 | |
| 3452 | static int __clear_gcr3(struct protection_domain *domain, int pasid) |
| 3453 | { |
| 3454 | u64 *pte; |
| 3455 | |
| 3456 | if (domain->mode != PAGE_MODE_NONE) |
| 3457 | return -EINVAL; |
| 3458 | |
| 3459 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); |
| 3460 | if (pte == NULL) |
| 3461 | return 0; |
| 3462 | |
| 3463 | *pte = 0; |
| 3464 | |
| 3465 | return __amd_iommu_flush_tlb(domain, pasid); |
| 3466 | } |
| 3467 | |
| 3468 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, |
| 3469 | unsigned long cr3) |
| 3470 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3471 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 3472 | unsigned long flags; |
| 3473 | int ret; |
| 3474 | |
| 3475 | spin_lock_irqsave(&domain->lock, flags); |
| 3476 | ret = __set_gcr3(domain, pasid, cr3); |
| 3477 | spin_unlock_irqrestore(&domain->lock, flags); |
| 3478 | |
| 3479 | return ret; |
| 3480 | } |
| 3481 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); |
| 3482 | |
| 3483 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) |
| 3484 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3485 | struct protection_domain *domain = to_pdomain(dom); |
Joerg Roedel | b16137b | 2011-11-21 16:50:23 +0100 | [diff] [blame] | 3486 | unsigned long flags; |
| 3487 | int ret; |
| 3488 | |
| 3489 | spin_lock_irqsave(&domain->lock, flags); |
| 3490 | ret = __clear_gcr3(domain, pasid); |
| 3491 | spin_unlock_irqrestore(&domain->lock, flags); |
| 3492 | |
| 3493 | return ret; |
| 3494 | } |
| 3495 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); |
Joerg Roedel | c99afa2 | 2011-11-21 18:19:25 +0100 | [diff] [blame] | 3496 | |
| 3497 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, |
| 3498 | int status, int tag) |
| 3499 | { |
| 3500 | struct iommu_dev_data *dev_data; |
| 3501 | struct amd_iommu *iommu; |
| 3502 | struct iommu_cmd cmd; |
| 3503 | |
| 3504 | dev_data = get_dev_data(&pdev->dev); |
| 3505 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
| 3506 | |
| 3507 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, |
| 3508 | tag, dev_data->pri_tlp); |
| 3509 | |
| 3510 | return iommu_queue_command(iommu, &cmd); |
| 3511 | } |
| 3512 | EXPORT_SYMBOL(amd_iommu_complete_ppr); |
Joerg Roedel | f3572db | 2011-11-23 12:36:25 +0100 | [diff] [blame] | 3513 | |
| 3514 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) |
| 3515 | { |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3516 | struct protection_domain *pdomain; |
Joerg Roedel | f3572db | 2011-11-23 12:36:25 +0100 | [diff] [blame] | 3517 | |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3518 | pdomain = get_domain(&pdev->dev); |
| 3519 | if (IS_ERR(pdomain)) |
Joerg Roedel | f3572db | 2011-11-23 12:36:25 +0100 | [diff] [blame] | 3520 | return NULL; |
| 3521 | |
| 3522 | /* Only return IOMMUv2 domains */ |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3523 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
Joerg Roedel | f3572db | 2011-11-23 12:36:25 +0100 | [diff] [blame] | 3524 | return NULL; |
| 3525 | |
Joerg Roedel | 3f4b87b | 2015-03-26 13:43:07 +0100 | [diff] [blame] | 3526 | return &pdomain->domain; |
Joerg Roedel | f3572db | 2011-11-23 12:36:25 +0100 | [diff] [blame] | 3527 | } |
| 3528 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); |
Joerg Roedel | 6a113dd | 2011-12-01 12:04:58 +0100 | [diff] [blame] | 3529 | |
| 3530 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) |
| 3531 | { |
| 3532 | struct iommu_dev_data *dev_data; |
| 3533 | |
| 3534 | if (!amd_iommu_v2_supported()) |
| 3535 | return; |
| 3536 | |
| 3537 | dev_data = get_dev_data(&pdev->dev); |
| 3538 | dev_data->errata |= (1 << erratum); |
| 3539 | } |
| 3540 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); |
Joerg Roedel | 52efdb8 | 2011-12-07 12:01:36 +0100 | [diff] [blame] | 3541 | |
| 3542 | int amd_iommu_device_info(struct pci_dev *pdev, |
| 3543 | struct amd_iommu_device_info *info) |
| 3544 | { |
| 3545 | int max_pasids; |
| 3546 | int pos; |
| 3547 | |
| 3548 | if (pdev == NULL || info == NULL) |
| 3549 | return -EINVAL; |
| 3550 | |
| 3551 | if (!amd_iommu_v2_supported()) |
| 3552 | return -EINVAL; |
| 3553 | |
| 3554 | memset(info, 0, sizeof(*info)); |
| 3555 | |
Gil Kupfer | cef7440 | 2018-05-10 17:56:02 -0500 | [diff] [blame] | 3556 | if (!pci_ats_disabled()) { |
| 3557 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); |
| 3558 | if (pos) |
| 3559 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; |
| 3560 | } |
Joerg Roedel | 52efdb8 | 2011-12-07 12:01:36 +0100 | [diff] [blame] | 3561 | |
| 3562 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
| 3563 | if (pos) |
| 3564 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; |
| 3565 | |
| 3566 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); |
| 3567 | if (pos) { |
| 3568 | int features; |
| 3569 | |
| 3570 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); |
| 3571 | max_pasids = min(max_pasids, (1 << 20)); |
| 3572 | |
| 3573 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; |
| 3574 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); |
| 3575 | |
| 3576 | features = pci_pasid_features(pdev); |
| 3577 | if (features & PCI_PASID_CAP_EXEC) |
| 3578 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; |
| 3579 | if (features & PCI_PASID_CAP_PRIV) |
| 3580 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; |
| 3581 | } |
| 3582 | |
| 3583 | return 0; |
| 3584 | } |
| 3585 | EXPORT_SYMBOL(amd_iommu_device_info); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3586 | |
| 3587 | #ifdef CONFIG_IRQ_REMAP |
| 3588 | |
| 3589 | /***************************************************************************** |
| 3590 | * |
| 3591 | * Interrupt Remapping Implementation |
| 3592 | * |
| 3593 | *****************************************************************************/ |
| 3594 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 3595 | static struct irq_chip amd_ir_chip; |
Arnd Bergmann | 94c793a | 2018-04-04 12:56:59 +0200 | [diff] [blame] | 3596 | static DEFINE_SPINLOCK(iommu_table_lock); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 3597 | |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3598 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) |
| 3599 | { |
| 3600 | u64 dte; |
| 3601 | |
| 3602 | dte = amd_iommu_dev_table[devid].data[2]; |
| 3603 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; |
Tom Lendacky | 2543a78 | 2017-07-17 16:10:24 -0500 | [diff] [blame] | 3604 | dte |= iommu_virt_to_phys(table->table); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3605 | dte |= DTE_IRQ_REMAP_INTCTL; |
| 3606 | dte |= DTE_IRQ_TABLE_LEN; |
| 3607 | dte |= DTE_IRQ_REMAP_ENABLE; |
| 3608 | |
| 3609 | amd_iommu_dev_table[devid].data[2] = dte; |
| 3610 | } |
| 3611 | |
Scott Wood | df42a04 | 2018-02-14 17:36:28 -0600 | [diff] [blame] | 3612 | static struct irq_remap_table *get_irq_table(u16 devid) |
| 3613 | { |
| 3614 | struct irq_remap_table *table; |
| 3615 | |
| 3616 | if (WARN_ONCE(!amd_iommu_rlookup_table[devid], |
| 3617 | "%s: no iommu for devid %x\n", __func__, devid)) |
| 3618 | return NULL; |
| 3619 | |
| 3620 | table = irq_lookup_table[devid]; |
| 3621 | if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid)) |
| 3622 | return NULL; |
| 3623 | |
| 3624 | return table; |
| 3625 | } |
| 3626 | |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3627 | static struct irq_remap_table *__alloc_irq_table(void) |
| 3628 | { |
| 3629 | struct irq_remap_table *table; |
| 3630 | |
| 3631 | table = kzalloc(sizeof(*table), GFP_KERNEL); |
| 3632 | if (!table) |
| 3633 | return NULL; |
| 3634 | |
| 3635 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); |
| 3636 | if (!table->table) { |
| 3637 | kfree(table); |
| 3638 | return NULL; |
| 3639 | } |
| 3640 | raw_spin_lock_init(&table->lock); |
| 3641 | |
| 3642 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
| 3643 | memset(table->table, 0, |
| 3644 | MAX_IRQS_PER_TABLE * sizeof(u32)); |
| 3645 | else |
| 3646 | memset(table->table, 0, |
| 3647 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); |
| 3648 | return table; |
| 3649 | } |
| 3650 | |
Sebastian Andrzej Siewior | 2fcc1e8 | 2018-03-22 16:22:39 +0100 | [diff] [blame] | 3651 | static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid, |
| 3652 | struct irq_remap_table *table) |
| 3653 | { |
| 3654 | irq_lookup_table[devid] = table; |
| 3655 | set_dte_irq_entry(devid, table); |
| 3656 | iommu_flush_dte(iommu, devid); |
| 3657 | } |
| 3658 | |
Sebastian Andrzej Siewior | fde65dd | 2018-03-22 16:22:37 +0100 | [diff] [blame] | 3659 | static struct irq_remap_table *alloc_irq_table(u16 devid) |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3660 | { |
| 3661 | struct irq_remap_table *table = NULL; |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3662 | struct irq_remap_table *new_table = NULL; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3663 | struct amd_iommu *iommu; |
| 3664 | unsigned long flags; |
| 3665 | u16 alias; |
| 3666 | |
Sebastian Andrzej Siewior | ea6166f | 2018-03-22 16:22:36 +0100 | [diff] [blame] | 3667 | spin_lock_irqsave(&iommu_table_lock, flags); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3668 | |
| 3669 | iommu = amd_iommu_rlookup_table[devid]; |
| 3670 | if (!iommu) |
| 3671 | goto out_unlock; |
| 3672 | |
| 3673 | table = irq_lookup_table[devid]; |
| 3674 | if (table) |
Baoquan He | 09284b9 | 2016-09-20 09:05:34 +0800 | [diff] [blame] | 3675 | goto out_unlock; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3676 | |
| 3677 | alias = amd_iommu_alias_table[devid]; |
| 3678 | table = irq_lookup_table[alias]; |
| 3679 | if (table) { |
Sebastian Andrzej Siewior | 2fcc1e8 | 2018-03-22 16:22:39 +0100 | [diff] [blame] | 3680 | set_remap_table_entry(iommu, devid, table); |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3681 | goto out_wait; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3682 | } |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3683 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3684 | |
| 3685 | /* Nothing there yet, allocate new irq remapping table */ |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3686 | new_table = __alloc_irq_table(); |
| 3687 | if (!new_table) |
| 3688 | return NULL; |
| 3689 | |
| 3690 | spin_lock_irqsave(&iommu_table_lock, flags); |
| 3691 | |
| 3692 | table = irq_lookup_table[devid]; |
| 3693 | if (table) |
Baoquan He | 09284b9 | 2016-09-20 09:05:34 +0800 | [diff] [blame] | 3694 | goto out_unlock; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3695 | |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3696 | table = irq_lookup_table[alias]; |
| 3697 | if (table) { |
| 3698 | set_remap_table_entry(iommu, devid, table); |
| 3699 | goto out_wait; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3700 | } |
| 3701 | |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3702 | table = new_table; |
| 3703 | new_table = NULL; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3704 | |
Sebastian Andrzej Siewior | 2fcc1e8 | 2018-03-22 16:22:39 +0100 | [diff] [blame] | 3705 | set_remap_table_entry(iommu, devid, table); |
| 3706 | if (devid != alias) |
| 3707 | set_remap_table_entry(iommu, alias, table); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3708 | |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3709 | out_wait: |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3710 | iommu_completion_wait(iommu); |
| 3711 | |
| 3712 | out_unlock: |
Sebastian Andrzej Siewior | ea6166f | 2018-03-22 16:22:36 +0100 | [diff] [blame] | 3713 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3714 | |
Sebastian Andrzej Siewior | 993ca6e | 2018-03-22 16:22:40 +0100 | [diff] [blame] | 3715 | if (new_table) { |
| 3716 | kmem_cache_free(amd_iommu_irq_cache, new_table->table); |
| 3717 | kfree(new_table); |
| 3718 | } |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3719 | return table; |
| 3720 | } |
| 3721 | |
Joerg Roedel | 37946d9 | 2017-10-06 12:16:39 +0200 | [diff] [blame] | 3722 | static int alloc_irq_index(u16 devid, int count, bool align) |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3723 | { |
| 3724 | struct irq_remap_table *table; |
Joerg Roedel | 37946d9 | 2017-10-06 12:16:39 +0200 | [diff] [blame] | 3725 | int index, c, alignment = 1; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3726 | unsigned long flags; |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 3727 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
| 3728 | |
| 3729 | if (!iommu) |
| 3730 | return -ENODEV; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3731 | |
Sebastian Andrzej Siewior | fde65dd | 2018-03-22 16:22:37 +0100 | [diff] [blame] | 3732 | table = alloc_irq_table(devid); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3733 | if (!table) |
| 3734 | return -ENODEV; |
| 3735 | |
Joerg Roedel | 37946d9 | 2017-10-06 12:16:39 +0200 | [diff] [blame] | 3736 | if (align) |
| 3737 | alignment = roundup_pow_of_two(count); |
| 3738 | |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3739 | raw_spin_lock_irqsave(&table->lock, flags); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3740 | |
| 3741 | /* Scan table for free entries */ |
Joerg Roedel | 37946d9 | 2017-10-06 12:16:39 +0200 | [diff] [blame] | 3742 | for (index = ALIGN(table->min_index, alignment), c = 0; |
Alex Williamson | 07d1c91 | 2017-11-03 10:50:31 -0600 | [diff] [blame] | 3743 | index < MAX_IRQS_PER_TABLE;) { |
Joerg Roedel | 37946d9 | 2017-10-06 12:16:39 +0200 | [diff] [blame] | 3744 | if (!iommu->irte_ops->is_allocated(table, index)) { |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3745 | c += 1; |
Joerg Roedel | 37946d9 | 2017-10-06 12:16:39 +0200 | [diff] [blame] | 3746 | } else { |
| 3747 | c = 0; |
Alex Williamson | 07d1c91 | 2017-11-03 10:50:31 -0600 | [diff] [blame] | 3748 | index = ALIGN(index + 1, alignment); |
Joerg Roedel | 37946d9 | 2017-10-06 12:16:39 +0200 | [diff] [blame] | 3749 | continue; |
| 3750 | } |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3751 | |
| 3752 | if (c == count) { |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3753 | for (; c != 0; --c) |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 3754 | iommu->irte_ops->set_allocated(table, index - c + 1); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3755 | |
| 3756 | index -= count - 1; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3757 | goto out; |
| 3758 | } |
Alex Williamson | 07d1c91 | 2017-11-03 10:50:31 -0600 | [diff] [blame] | 3759 | |
| 3760 | index++; |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3761 | } |
| 3762 | |
| 3763 | index = -ENOSPC; |
| 3764 | |
| 3765 | out: |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3766 | raw_spin_unlock_irqrestore(&table->lock, flags); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3767 | |
| 3768 | return index; |
| 3769 | } |
| 3770 | |
Suravee Suthikulpanit | b9fc6b5 | 2016-08-23 13:52:39 -0500 | [diff] [blame] | 3771 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
| 3772 | struct amd_ir_data *data) |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3773 | { |
| 3774 | struct irq_remap_table *table; |
| 3775 | struct amd_iommu *iommu; |
| 3776 | unsigned long flags; |
| 3777 | struct irte_ga *entry; |
| 3778 | |
| 3779 | iommu = amd_iommu_rlookup_table[devid]; |
| 3780 | if (iommu == NULL) |
| 3781 | return -EINVAL; |
| 3782 | |
Scott Wood | df42a04 | 2018-02-14 17:36:28 -0600 | [diff] [blame] | 3783 | table = get_irq_table(devid); |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3784 | if (!table) |
| 3785 | return -ENOMEM; |
| 3786 | |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3787 | raw_spin_lock_irqsave(&table->lock, flags); |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3788 | |
| 3789 | entry = (struct irte_ga *)table->table; |
| 3790 | entry = &entry[index]; |
| 3791 | entry->lo.fields_remap.valid = 0; |
| 3792 | entry->hi.val = irte->hi.val; |
| 3793 | entry->lo.val = irte->lo.val; |
| 3794 | entry->lo.fields_remap.valid = 1; |
Suravee Suthikulpanit | b9fc6b5 | 2016-08-23 13:52:39 -0500 | [diff] [blame] | 3795 | if (data) |
| 3796 | data->ref = entry; |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3797 | |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3798 | raw_spin_unlock_irqrestore(&table->lock, flags); |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3799 | |
| 3800 | iommu_flush_irt(iommu, devid); |
| 3801 | iommu_completion_wait(iommu); |
| 3802 | |
| 3803 | return 0; |
| 3804 | } |
| 3805 | |
| 3806 | static int modify_irte(u16 devid, int index, union irte *irte) |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3807 | { |
| 3808 | struct irq_remap_table *table; |
| 3809 | struct amd_iommu *iommu; |
| 3810 | unsigned long flags; |
| 3811 | |
| 3812 | iommu = amd_iommu_rlookup_table[devid]; |
| 3813 | if (iommu == NULL) |
| 3814 | return -EINVAL; |
| 3815 | |
Scott Wood | df42a04 | 2018-02-14 17:36:28 -0600 | [diff] [blame] | 3816 | table = get_irq_table(devid); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3817 | if (!table) |
| 3818 | return -ENOMEM; |
| 3819 | |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3820 | raw_spin_lock_irqsave(&table->lock, flags); |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3821 | table->table[index] = irte->val; |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3822 | raw_spin_unlock_irqrestore(&table->lock, flags); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3823 | |
| 3824 | iommu_flush_irt(iommu, devid); |
| 3825 | iommu_completion_wait(iommu); |
| 3826 | |
| 3827 | return 0; |
| 3828 | } |
| 3829 | |
| 3830 | static void free_irte(u16 devid, int index) |
| 3831 | { |
| 3832 | struct irq_remap_table *table; |
| 3833 | struct amd_iommu *iommu; |
| 3834 | unsigned long flags; |
| 3835 | |
| 3836 | iommu = amd_iommu_rlookup_table[devid]; |
| 3837 | if (iommu == NULL) |
| 3838 | return; |
| 3839 | |
Scott Wood | df42a04 | 2018-02-14 17:36:28 -0600 | [diff] [blame] | 3840 | table = get_irq_table(devid); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3841 | if (!table) |
| 3842 | return; |
| 3843 | |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3844 | raw_spin_lock_irqsave(&table->lock, flags); |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 3845 | iommu->irte_ops->clear_allocated(table, index); |
Scott Wood | 2779039 | 2018-01-21 03:28:54 -0600 | [diff] [blame] | 3846 | raw_spin_unlock_irqrestore(&table->lock, flags); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 3847 | |
| 3848 | iommu_flush_irt(iommu, devid); |
| 3849 | iommu_completion_wait(iommu); |
| 3850 | } |
| 3851 | |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3852 | static void irte_prepare(void *entry, |
| 3853 | u32 delivery_mode, u32 dest_mode, |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 3854 | u8 vector, u32 dest_apicid, int devid) |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3855 | { |
| 3856 | union irte *irte = (union irte *) entry; |
| 3857 | |
| 3858 | irte->val = 0; |
| 3859 | irte->fields.vector = vector; |
| 3860 | irte->fields.int_type = delivery_mode; |
| 3861 | irte->fields.destination = dest_apicid; |
| 3862 | irte->fields.dm = dest_mode; |
| 3863 | irte->fields.valid = 1; |
| 3864 | } |
| 3865 | |
| 3866 | static void irte_ga_prepare(void *entry, |
| 3867 | u32 delivery_mode, u32 dest_mode, |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 3868 | u8 vector, u32 dest_apicid, int devid) |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3869 | { |
| 3870 | struct irte_ga *irte = (struct irte_ga *) entry; |
| 3871 | |
| 3872 | irte->lo.val = 0; |
| 3873 | irte->hi.val = 0; |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3874 | irte->lo.fields_remap.int_type = delivery_mode; |
| 3875 | irte->lo.fields_remap.dm = dest_mode; |
| 3876 | irte->hi.fields.vector = vector; |
| 3877 | irte->lo.fields_remap.destination = dest_apicid; |
| 3878 | irte->lo.fields_remap.valid = 1; |
| 3879 | } |
| 3880 | |
| 3881 | static void irte_activate(void *entry, u16 devid, u16 index) |
| 3882 | { |
| 3883 | union irte *irte = (union irte *) entry; |
| 3884 | |
| 3885 | irte->fields.valid = 1; |
| 3886 | modify_irte(devid, index, irte); |
| 3887 | } |
| 3888 | |
| 3889 | static void irte_ga_activate(void *entry, u16 devid, u16 index) |
| 3890 | { |
| 3891 | struct irte_ga *irte = (struct irte_ga *) entry; |
| 3892 | |
| 3893 | irte->lo.fields_remap.valid = 1; |
Suravee Suthikulpanit | b9fc6b5 | 2016-08-23 13:52:39 -0500 | [diff] [blame] | 3894 | modify_irte_ga(devid, index, irte, NULL); |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3895 | } |
| 3896 | |
| 3897 | static void irte_deactivate(void *entry, u16 devid, u16 index) |
| 3898 | { |
| 3899 | union irte *irte = (union irte *) entry; |
| 3900 | |
| 3901 | irte->fields.valid = 0; |
| 3902 | modify_irte(devid, index, irte); |
| 3903 | } |
| 3904 | |
| 3905 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) |
| 3906 | { |
| 3907 | struct irte_ga *irte = (struct irte_ga *) entry; |
| 3908 | |
| 3909 | irte->lo.fields_remap.valid = 0; |
Suravee Suthikulpanit | b9fc6b5 | 2016-08-23 13:52:39 -0500 | [diff] [blame] | 3910 | modify_irte_ga(devid, index, irte, NULL); |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3911 | } |
| 3912 | |
| 3913 | static void irte_set_affinity(void *entry, u16 devid, u16 index, |
| 3914 | u8 vector, u32 dest_apicid) |
| 3915 | { |
| 3916 | union irte *irte = (union irte *) entry; |
| 3917 | |
| 3918 | irte->fields.vector = vector; |
| 3919 | irte->fields.destination = dest_apicid; |
| 3920 | modify_irte(devid, index, irte); |
| 3921 | } |
| 3922 | |
| 3923 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, |
| 3924 | u8 vector, u32 dest_apicid) |
| 3925 | { |
| 3926 | struct irte_ga *irte = (struct irte_ga *) entry; |
| 3927 | |
Scott Wood | 01ee04b | 2018-01-28 14:22:19 -0600 | [diff] [blame] | 3928 | if (!irte->lo.fields_remap.guest_mode) { |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 3929 | irte->hi.fields.vector = vector; |
| 3930 | irte->lo.fields_remap.destination = dest_apicid; |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 3931 | modify_irte_ga(devid, index, irte, NULL); |
| 3932 | } |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3933 | } |
| 3934 | |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 3935 | #define IRTE_ALLOCATED (~1U) |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 3936 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
| 3937 | { |
| 3938 | table->table[index] = IRTE_ALLOCATED; |
| 3939 | } |
| 3940 | |
| 3941 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) |
| 3942 | { |
| 3943 | struct irte_ga *ptr = (struct irte_ga *)table->table; |
| 3944 | struct irte_ga *irte = &ptr[index]; |
| 3945 | |
| 3946 | memset(&irte->lo.val, 0, sizeof(u64)); |
| 3947 | memset(&irte->hi.val, 0, sizeof(u64)); |
| 3948 | irte->hi.fields.vector = 0xff; |
| 3949 | } |
| 3950 | |
| 3951 | static bool irte_is_allocated(struct irq_remap_table *table, int index) |
| 3952 | { |
| 3953 | union irte *ptr = (union irte *)table->table; |
| 3954 | union irte *irte = &ptr[index]; |
| 3955 | |
| 3956 | return irte->val != 0; |
| 3957 | } |
| 3958 | |
| 3959 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) |
| 3960 | { |
| 3961 | struct irte_ga *ptr = (struct irte_ga *)table->table; |
| 3962 | struct irte_ga *irte = &ptr[index]; |
| 3963 | |
| 3964 | return irte->hi.fields.vector != 0; |
| 3965 | } |
| 3966 | |
| 3967 | static void irte_clear_allocated(struct irq_remap_table *table, int index) |
| 3968 | { |
| 3969 | table->table[index] = 0; |
| 3970 | } |
| 3971 | |
| 3972 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) |
| 3973 | { |
| 3974 | struct irte_ga *ptr = (struct irte_ga *)table->table; |
| 3975 | struct irte_ga *irte = &ptr[index]; |
| 3976 | |
| 3977 | memset(&irte->lo.val, 0, sizeof(u64)); |
| 3978 | memset(&irte->hi.val, 0, sizeof(u64)); |
| 3979 | } |
| 3980 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 3981 | static int get_devid(struct irq_alloc_info *info) |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 3982 | { |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 3983 | int devid = -1; |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 3984 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 3985 | switch (info->type) { |
| 3986 | case X86_IRQ_ALLOC_TYPE_IOAPIC: |
| 3987 | devid = get_ioapic_devid(info->ioapic_id); |
| 3988 | break; |
| 3989 | case X86_IRQ_ALLOC_TYPE_HPET: |
| 3990 | devid = get_hpet_devid(info->hpet_id); |
| 3991 | break; |
| 3992 | case X86_IRQ_ALLOC_TYPE_MSI: |
| 3993 | case X86_IRQ_ALLOC_TYPE_MSIX: |
| 3994 | devid = get_device_id(&info->msi_dev->dev); |
| 3995 | break; |
| 3996 | default: |
| 3997 | BUG_ON(1); |
| 3998 | break; |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 3999 | } |
| 4000 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4001 | return devid; |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 4002 | } |
| 4003 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4004 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 4005 | { |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4006 | struct amd_iommu *iommu; |
| 4007 | int devid; |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 4008 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4009 | if (!info) |
| 4010 | return NULL; |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 4011 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4012 | devid = get_devid(info); |
| 4013 | if (devid >= 0) { |
| 4014 | iommu = amd_iommu_rlookup_table[devid]; |
| 4015 | if (iommu) |
| 4016 | return iommu->ir_domain; |
| 4017 | } |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 4018 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4019 | return NULL; |
Joerg Roedel | 5527de7 | 2012-06-26 11:17:32 +0200 | [diff] [blame] | 4020 | } |
| 4021 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4022 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
Joerg Roedel | 0b4d48c | 2012-06-26 14:54:17 +0200 | [diff] [blame] | 4023 | { |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4024 | struct amd_iommu *iommu; |
| 4025 | int devid; |
Joerg Roedel | 0b4d48c | 2012-06-26 14:54:17 +0200 | [diff] [blame] | 4026 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4027 | if (!info) |
| 4028 | return NULL; |
Joerg Roedel | 0b4d48c | 2012-06-26 14:54:17 +0200 | [diff] [blame] | 4029 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4030 | switch (info->type) { |
| 4031 | case X86_IRQ_ALLOC_TYPE_MSI: |
| 4032 | case X86_IRQ_ALLOC_TYPE_MSIX: |
| 4033 | devid = get_device_id(&info->msi_dev->dev); |
Joerg Roedel | 9ee35e4 | 2016-04-21 18:21:31 +0200 | [diff] [blame] | 4034 | if (devid < 0) |
Wan Zongshun | 7aba6cb | 2016-04-01 09:06:02 -0400 | [diff] [blame] | 4035 | return NULL; |
| 4036 | |
Dan Carpenter | 1fb260b | 2016-01-07 12:36:06 +0300 | [diff] [blame] | 4037 | iommu = amd_iommu_rlookup_table[devid]; |
| 4038 | if (iommu) |
| 4039 | return iommu->msi_domain; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4040 | break; |
| 4041 | default: |
| 4042 | break; |
| 4043 | } |
Joerg Roedel | 0b4d48c | 2012-06-26 14:54:17 +0200 | [diff] [blame] | 4044 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4045 | return NULL; |
Joerg Roedel | d976195 | 2012-06-26 16:00:08 +0200 | [diff] [blame] | 4046 | } |
| 4047 | |
Joerg Roedel | 6b474b8 | 2012-06-26 16:46:04 +0200 | [diff] [blame] | 4048 | struct irq_remap_ops amd_iommu_irq_ops = { |
Joerg Roedel | 6b474b8 | 2012-06-26 16:46:04 +0200 | [diff] [blame] | 4049 | .prepare = amd_iommu_prepare, |
| 4050 | .enable = amd_iommu_enable, |
| 4051 | .disable = amd_iommu_disable, |
| 4052 | .reenable = amd_iommu_reenable, |
| 4053 | .enable_faulting = amd_iommu_enable_faulting, |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4054 | .get_ir_irq_domain = get_ir_irq_domain, |
| 4055 | .get_irq_domain = get_irq_domain, |
Joerg Roedel | 6b474b8 | 2012-06-26 16:46:04 +0200 | [diff] [blame] | 4056 | }; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4057 | |
| 4058 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
| 4059 | struct irq_cfg *irq_cfg, |
| 4060 | struct irq_alloc_info *info, |
| 4061 | int devid, int index, int sub_handle) |
| 4062 | { |
| 4063 | struct irq_2_irte *irte_info = &data->irq_2_irte; |
| 4064 | struct msi_msg *msg = &data->msi_entry; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4065 | struct IO_APIC_route_entry *entry; |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4066 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
| 4067 | |
| 4068 | if (!iommu) |
| 4069 | return; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4070 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4071 | data->irq_2_irte.devid = devid; |
| 4072 | data->irq_2_irte.index = index + sub_handle; |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4073 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
| 4074 | apic->irq_dest_mode, irq_cfg->vector, |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 4075 | irq_cfg->dest_apicid, devid); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4076 | |
| 4077 | switch (info->type) { |
| 4078 | case X86_IRQ_ALLOC_TYPE_IOAPIC: |
| 4079 | /* Setup IOAPIC entry */ |
| 4080 | entry = info->ioapic_entry; |
| 4081 | info->ioapic_entry = NULL; |
| 4082 | memset(entry, 0, sizeof(*entry)); |
| 4083 | entry->vector = index; |
| 4084 | entry->mask = 0; |
| 4085 | entry->trigger = info->ioapic_trigger; |
| 4086 | entry->polarity = info->ioapic_polarity; |
| 4087 | /* Mask level triggered irqs. */ |
| 4088 | if (info->ioapic_trigger) |
| 4089 | entry->mask = 1; |
| 4090 | break; |
| 4091 | |
| 4092 | case X86_IRQ_ALLOC_TYPE_HPET: |
| 4093 | case X86_IRQ_ALLOC_TYPE_MSI: |
| 4094 | case X86_IRQ_ALLOC_TYPE_MSIX: |
| 4095 | msg->address_hi = MSI_ADDR_BASE_HI; |
| 4096 | msg->address_lo = MSI_ADDR_BASE_LO; |
| 4097 | msg->data = irte_info->index; |
| 4098 | break; |
| 4099 | |
| 4100 | default: |
| 4101 | BUG_ON(1); |
| 4102 | break; |
| 4103 | } |
| 4104 | } |
| 4105 | |
Suravee Suthikulpanit | 880ac60 | 2016-08-23 13:52:34 -0500 | [diff] [blame] | 4106 | struct amd_irte_ops irte_32_ops = { |
| 4107 | .prepare = irte_prepare, |
| 4108 | .activate = irte_activate, |
| 4109 | .deactivate = irte_deactivate, |
| 4110 | .set_affinity = irte_set_affinity, |
| 4111 | .set_allocated = irte_set_allocated, |
| 4112 | .is_allocated = irte_is_allocated, |
| 4113 | .clear_allocated = irte_clear_allocated, |
| 4114 | }; |
| 4115 | |
| 4116 | struct amd_irte_ops irte_128_ops = { |
| 4117 | .prepare = irte_ga_prepare, |
| 4118 | .activate = irte_ga_activate, |
| 4119 | .deactivate = irte_ga_deactivate, |
| 4120 | .set_affinity = irte_ga_set_affinity, |
| 4121 | .set_allocated = irte_ga_set_allocated, |
| 4122 | .is_allocated = irte_ga_is_allocated, |
| 4123 | .clear_allocated = irte_ga_clear_allocated, |
| 4124 | }; |
| 4125 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4126 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
| 4127 | unsigned int nr_irqs, void *arg) |
| 4128 | { |
| 4129 | struct irq_alloc_info *info = arg; |
| 4130 | struct irq_data *irq_data; |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4131 | struct amd_ir_data *data = NULL; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4132 | struct irq_cfg *cfg; |
| 4133 | int i, ret, devid; |
Sebastian Andrzej Siewior | 29d049b | 2018-03-22 16:22:42 +0100 | [diff] [blame] | 4134 | int index; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4135 | |
| 4136 | if (!info) |
| 4137 | return -EINVAL; |
| 4138 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && |
| 4139 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) |
| 4140 | return -EINVAL; |
| 4141 | |
| 4142 | /* |
| 4143 | * With IRQ remapping enabled, don't need contiguous CPU vectors |
| 4144 | * to support multiple MSI interrupts. |
| 4145 | */ |
| 4146 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) |
| 4147 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; |
| 4148 | |
| 4149 | devid = get_devid(info); |
| 4150 | if (devid < 0) |
| 4151 | return -EINVAL; |
| 4152 | |
| 4153 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
| 4154 | if (ret < 0) |
| 4155 | return ret; |
| 4156 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4157 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
Sebastian Andrzej Siewior | fde65dd | 2018-03-22 16:22:37 +0100 | [diff] [blame] | 4158 | struct irq_remap_table *table; |
| 4159 | struct amd_iommu *iommu; |
| 4160 | |
| 4161 | table = alloc_irq_table(devid); |
| 4162 | if (table) { |
| 4163 | if (!table->min_index) { |
| 4164 | /* |
| 4165 | * Keep the first 32 indexes free for IOAPIC |
| 4166 | * interrupts. |
| 4167 | */ |
| 4168 | table->min_index = 32; |
| 4169 | iommu = amd_iommu_rlookup_table[devid]; |
| 4170 | for (i = 0; i < 32; ++i) |
| 4171 | iommu->irte_ops->set_allocated(table, i); |
| 4172 | } |
| 4173 | WARN_ON(table->min_index != 32); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4174 | index = info->ioapic_pin; |
Sebastian Andrzej Siewior | fde65dd | 2018-03-22 16:22:37 +0100 | [diff] [blame] | 4175 | } else { |
Sebastian Andrzej Siewior | 29d049b | 2018-03-22 16:22:42 +0100 | [diff] [blame] | 4176 | index = -ENOMEM; |
Sebastian Andrzej Siewior | fde65dd | 2018-03-22 16:22:37 +0100 | [diff] [blame] | 4177 | } |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4178 | } else { |
Joerg Roedel | 53b9ec3 | 2017-10-06 12:22:06 +0200 | [diff] [blame] | 4179 | bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI); |
| 4180 | |
| 4181 | index = alloc_irq_index(devid, nr_irqs, align); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4182 | } |
| 4183 | if (index < 0) { |
| 4184 | pr_warn("Failed to allocate IRTE\n"); |
Wei Yongjun | 517abe4 | 2016-07-28 02:10:26 +0000 | [diff] [blame] | 4185 | ret = index; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4186 | goto out_free_parent; |
| 4187 | } |
| 4188 | |
| 4189 | for (i = 0; i < nr_irqs; i++) { |
| 4190 | irq_data = irq_domain_get_irq_data(domain, virq + i); |
| 4191 | cfg = irqd_cfg(irq_data); |
| 4192 | if (!irq_data || !cfg) { |
| 4193 | ret = -EINVAL; |
| 4194 | goto out_free_data; |
| 4195 | } |
| 4196 | |
Joerg Roedel | a130e69 | 2015-08-13 11:07:25 +0200 | [diff] [blame] | 4197 | ret = -ENOMEM; |
| 4198 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
| 4199 | if (!data) |
| 4200 | goto out_free_data; |
| 4201 | |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4202 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
| 4203 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); |
| 4204 | else |
| 4205 | data->entry = kzalloc(sizeof(struct irte_ga), |
| 4206 | GFP_KERNEL); |
| 4207 | if (!data->entry) { |
| 4208 | kfree(data); |
| 4209 | goto out_free_data; |
| 4210 | } |
| 4211 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4212 | irq_data->hwirq = (devid << 16) + i; |
| 4213 | irq_data->chip_data = data; |
| 4214 | irq_data->chip = &amd_ir_chip; |
| 4215 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); |
| 4216 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); |
| 4217 | } |
Joerg Roedel | a130e69 | 2015-08-13 11:07:25 +0200 | [diff] [blame] | 4218 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4219 | return 0; |
| 4220 | |
| 4221 | out_free_data: |
| 4222 | for (i--; i >= 0; i--) { |
| 4223 | irq_data = irq_domain_get_irq_data(domain, virq + i); |
| 4224 | if (irq_data) |
| 4225 | kfree(irq_data->chip_data); |
| 4226 | } |
| 4227 | for (i = 0; i < nr_irqs; i++) |
| 4228 | free_irte(devid, index + i); |
| 4229 | out_free_parent: |
| 4230 | irq_domain_free_irqs_common(domain, virq, nr_irqs); |
| 4231 | return ret; |
| 4232 | } |
| 4233 | |
| 4234 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
| 4235 | unsigned int nr_irqs) |
| 4236 | { |
| 4237 | struct irq_2_irte *irte_info; |
| 4238 | struct irq_data *irq_data; |
| 4239 | struct amd_ir_data *data; |
| 4240 | int i; |
| 4241 | |
| 4242 | for (i = 0; i < nr_irqs; i++) { |
| 4243 | irq_data = irq_domain_get_irq_data(domain, virq + i); |
| 4244 | if (irq_data && irq_data->chip_data) { |
| 4245 | data = irq_data->chip_data; |
| 4246 | irte_info = &data->irq_2_irte; |
| 4247 | free_irte(irte_info->devid, irte_info->index); |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4248 | kfree(data->entry); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4249 | kfree(data); |
| 4250 | } |
| 4251 | } |
| 4252 | irq_domain_free_irqs_common(domain, virq, nr_irqs); |
| 4253 | } |
| 4254 | |
Thomas Gleixner | 5ba204a | 2017-09-13 23:29:48 +0200 | [diff] [blame] | 4255 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
| 4256 | struct amd_ir_data *ir_data, |
| 4257 | struct irq_2_irte *irte_info, |
| 4258 | struct irq_cfg *cfg); |
| 4259 | |
Thomas Gleixner | 7249164 | 2017-09-13 23:29:10 +0200 | [diff] [blame] | 4260 | static int irq_remapping_activate(struct irq_domain *domain, |
Thomas Gleixner | 702cb0a | 2017-12-29 16:59:06 +0100 | [diff] [blame] | 4261 | struct irq_data *irq_data, bool reserve) |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4262 | { |
| 4263 | struct amd_ir_data *data = irq_data->chip_data; |
| 4264 | struct irq_2_irte *irte_info = &data->irq_2_irte; |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4265 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
Thomas Gleixner | 5ba204a | 2017-09-13 23:29:48 +0200 | [diff] [blame] | 4266 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4267 | |
Thomas Gleixner | 5ba204a | 2017-09-13 23:29:48 +0200 | [diff] [blame] | 4268 | if (!iommu) |
| 4269 | return 0; |
| 4270 | |
| 4271 | iommu->irte_ops->activate(data->entry, irte_info->devid, |
| 4272 | irte_info->index); |
| 4273 | amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); |
Thomas Gleixner | 7249164 | 2017-09-13 23:29:10 +0200 | [diff] [blame] | 4274 | return 0; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4275 | } |
| 4276 | |
| 4277 | static void irq_remapping_deactivate(struct irq_domain *domain, |
| 4278 | struct irq_data *irq_data) |
| 4279 | { |
| 4280 | struct amd_ir_data *data = irq_data->chip_data; |
| 4281 | struct irq_2_irte *irte_info = &data->irq_2_irte; |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4282 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4283 | |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4284 | if (iommu) |
| 4285 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, |
| 4286 | irte_info->index); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4287 | } |
| 4288 | |
Tobias Klauser | e2f9d45 | 2017-05-24 16:31:16 +0200 | [diff] [blame] | 4289 | static const struct irq_domain_ops amd_ir_domain_ops = { |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4290 | .alloc = irq_remapping_alloc, |
| 4291 | .free = irq_remapping_free, |
| 4292 | .activate = irq_remapping_activate, |
| 4293 | .deactivate = irq_remapping_deactivate, |
| 4294 | }; |
| 4295 | |
Suravee Suthikulpanit | b9fc6b5 | 2016-08-23 13:52:39 -0500 | [diff] [blame] | 4296 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
| 4297 | { |
| 4298 | struct amd_iommu *iommu; |
| 4299 | struct amd_iommu_pi_data *pi_data = vcpu_info; |
| 4300 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; |
| 4301 | struct amd_ir_data *ir_data = data->chip_data; |
| 4302 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; |
| 4303 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; |
Suravee Suthikulpanit | d98de49 | 2016-08-23 13:52:40 -0500 | [diff] [blame] | 4304 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); |
| 4305 | |
| 4306 | /* Note: |
| 4307 | * This device has never been set up for guest mode. |
| 4308 | * we should not modify the IRTE |
| 4309 | */ |
| 4310 | if (!dev_data || !dev_data->use_vapic) |
| 4311 | return 0; |
Suravee Suthikulpanit | b9fc6b5 | 2016-08-23 13:52:39 -0500 | [diff] [blame] | 4312 | |
| 4313 | pi_data->ir_data = ir_data; |
| 4314 | |
| 4315 | /* Note: |
| 4316 | * SVM tries to set up for VAPIC mode, but we are in |
| 4317 | * legacy mode. So, we force legacy mode instead. |
| 4318 | */ |
| 4319 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { |
| 4320 | pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", |
| 4321 | __func__); |
| 4322 | pi_data->is_guest_mode = false; |
| 4323 | } |
| 4324 | |
| 4325 | iommu = amd_iommu_rlookup_table[irte_info->devid]; |
| 4326 | if (iommu == NULL) |
| 4327 | return -EINVAL; |
| 4328 | |
| 4329 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; |
| 4330 | if (pi_data->is_guest_mode) { |
| 4331 | /* Setting */ |
| 4332 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); |
| 4333 | irte->hi.fields.vector = vcpu_pi_info->vector; |
Suravee Suthikulpanit | efe6f24 | 2017-07-05 21:29:59 -0500 | [diff] [blame] | 4334 | irte->lo.fields_vapic.ga_log_intr = 1; |
Suravee Suthikulpanit | b9fc6b5 | 2016-08-23 13:52:39 -0500 | [diff] [blame] | 4335 | irte->lo.fields_vapic.guest_mode = 1; |
| 4336 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; |
| 4337 | |
| 4338 | ir_data->cached_ga_tag = pi_data->ga_tag; |
| 4339 | } else { |
| 4340 | /* Un-Setting */ |
| 4341 | struct irq_cfg *cfg = irqd_cfg(data); |
| 4342 | |
| 4343 | irte->hi.val = 0; |
| 4344 | irte->lo.val = 0; |
| 4345 | irte->hi.fields.vector = cfg->vector; |
| 4346 | irte->lo.fields_remap.guest_mode = 0; |
| 4347 | irte->lo.fields_remap.destination = cfg->dest_apicid; |
| 4348 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; |
| 4349 | irte->lo.fields_remap.dm = apic->irq_dest_mode; |
| 4350 | |
| 4351 | /* |
| 4352 | * This communicates the ga_tag back to the caller |
| 4353 | * so that it can do all the necessary clean up. |
| 4354 | */ |
| 4355 | ir_data->cached_ga_tag = 0; |
| 4356 | } |
| 4357 | |
| 4358 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); |
| 4359 | } |
| 4360 | |
Thomas Gleixner | 5ba204a | 2017-09-13 23:29:48 +0200 | [diff] [blame] | 4361 | |
| 4362 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
| 4363 | struct amd_ir_data *ir_data, |
| 4364 | struct irq_2_irte *irte_info, |
| 4365 | struct irq_cfg *cfg) |
| 4366 | { |
| 4367 | |
| 4368 | /* |
| 4369 | * Atomically updates the IRTE with the new destination, vector |
| 4370 | * and flushes the interrupt entry cache. |
| 4371 | */ |
| 4372 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, |
| 4373 | irte_info->index, cfg->vector, |
| 4374 | cfg->dest_apicid); |
| 4375 | } |
| 4376 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4377 | static int amd_ir_set_affinity(struct irq_data *data, |
| 4378 | const struct cpumask *mask, bool force) |
| 4379 | { |
| 4380 | struct amd_ir_data *ir_data = data->chip_data; |
| 4381 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; |
| 4382 | struct irq_cfg *cfg = irqd_cfg(data); |
| 4383 | struct irq_data *parent = data->parent_data; |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4384 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4385 | int ret; |
| 4386 | |
Suravee Suthikulpanit | 77bdab4 | 2016-08-23 13:52:35 -0500 | [diff] [blame] | 4387 | if (!iommu) |
| 4388 | return -ENODEV; |
| 4389 | |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4390 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
| 4391 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) |
| 4392 | return ret; |
| 4393 | |
Thomas Gleixner | 5ba204a | 2017-09-13 23:29:48 +0200 | [diff] [blame] | 4394 | amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4395 | /* |
| 4396 | * After this point, all the interrupts will start arriving |
| 4397 | * at the new destination. So, time to cleanup the previous |
| 4398 | * vector allocation. |
| 4399 | */ |
Jiang Liu | c6c2002 | 2015-04-14 10:30:02 +0800 | [diff] [blame] | 4400 | send_cleanup_vector(cfg); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4401 | |
| 4402 | return IRQ_SET_MASK_OK_DONE; |
| 4403 | } |
| 4404 | |
| 4405 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
| 4406 | { |
| 4407 | struct amd_ir_data *ir_data = irq_data->chip_data; |
| 4408 | |
| 4409 | *msg = ir_data->msi_entry; |
| 4410 | } |
| 4411 | |
| 4412 | static struct irq_chip amd_ir_chip = { |
Thomas Gleixner | 290be19 | 2017-06-20 01:37:02 +0200 | [diff] [blame] | 4413 | .name = "AMD-IR", |
Thomas Gleixner | 8a2b7d1 | 2018-06-04 17:33:56 +0200 | [diff] [blame] | 4414 | .irq_ack = apic_ack_irq, |
Thomas Gleixner | 290be19 | 2017-06-20 01:37:02 +0200 | [diff] [blame] | 4415 | .irq_set_affinity = amd_ir_set_affinity, |
| 4416 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, |
| 4417 | .irq_compose_msi_msg = ir_compose_msi_msg, |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4418 | }; |
| 4419 | |
| 4420 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
| 4421 | { |
Thomas Gleixner | 3e49a81 | 2017-06-20 01:37:12 +0200 | [diff] [blame] | 4422 | struct fwnode_handle *fn; |
| 4423 | |
| 4424 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); |
| 4425 | if (!fn) |
| 4426 | return -ENOMEM; |
| 4427 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); |
| 4428 | irq_domain_free_fwnode(fn); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4429 | if (!iommu->ir_domain) |
| 4430 | return -ENOMEM; |
| 4431 | |
| 4432 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
Thomas Gleixner | 3e49a81 | 2017-06-20 01:37:12 +0200 | [diff] [blame] | 4433 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, |
| 4434 | "AMD-IR-MSI", |
| 4435 | iommu->index); |
Jiang Liu | 7c71d30 | 2015-04-13 14:11:33 +0800 | [diff] [blame] | 4436 | return 0; |
| 4437 | } |
Suravee Suthikulpanit | 8dbea3f | 2016-08-23 13:52:38 -0500 | [diff] [blame] | 4438 | |
| 4439 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) |
| 4440 | { |
| 4441 | unsigned long flags; |
| 4442 | struct amd_iommu *iommu; |
Sebastian Andrzej Siewior | 4fde541 | 2018-03-22 16:22:38 +0100 | [diff] [blame] | 4443 | struct irq_remap_table *table; |
Suravee Suthikulpanit | 8dbea3f | 2016-08-23 13:52:38 -0500 | [diff] [blame] | 4444 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; |
| 4445 | int devid = ir_data->irq_2_irte.devid; |
| 4446 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; |
| 4447 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; |
| 4448 | |
| 4449 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || |
| 4450 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) |
| 4451 | return 0; |
| 4452 | |
| 4453 | iommu = amd_iommu_rlookup_table[devid]; |
| 4454 | if (!iommu) |
| 4455 | return -ENODEV; |
| 4456 | |
Sebastian Andrzej Siewior | 4fde541 | 2018-03-22 16:22:38 +0100 | [diff] [blame] | 4457 | table = get_irq_table(devid); |
| 4458 | if (!table) |
Suravee Suthikulpanit | 8dbea3f | 2016-08-23 13:52:38 -0500 | [diff] [blame] | 4459 | return -ENODEV; |
| 4460 | |
Sebastian Andrzej Siewior | 4fde541 | 2018-03-22 16:22:38 +0100 | [diff] [blame] | 4461 | raw_spin_lock_irqsave(&table->lock, flags); |
Suravee Suthikulpanit | 8dbea3f | 2016-08-23 13:52:38 -0500 | [diff] [blame] | 4462 | |
| 4463 | if (ref->lo.fields_vapic.guest_mode) { |
| 4464 | if (cpu >= 0) |
| 4465 | ref->lo.fields_vapic.destination = cpu; |
| 4466 | ref->lo.fields_vapic.is_run = is_run; |
| 4467 | barrier(); |
| 4468 | } |
| 4469 | |
Sebastian Andrzej Siewior | 4fde541 | 2018-03-22 16:22:38 +0100 | [diff] [blame] | 4470 | raw_spin_unlock_irqrestore(&table->lock, flags); |
Suravee Suthikulpanit | 8dbea3f | 2016-08-23 13:52:38 -0500 | [diff] [blame] | 4471 | |
| 4472 | iommu_flush_irt(iommu, devid); |
| 4473 | iommu_completion_wait(iommu); |
| 4474 | return 0; |
| 4475 | } |
| 4476 | EXPORT_SYMBOL(amd_iommu_update_ga); |
Joerg Roedel | 2b32450 | 2012-06-21 16:29:10 +0200 | [diff] [blame] | 4477 | #endif |