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Joerg Roedelb6c02712008-06-26 21:27:53 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedel63ce3ae2015-02-04 16:12:55 +01003 * Author: Joerg Roedel <jroedel@suse.de>
Joerg Roedelb6c02712008-06-26 21:27:53 +02004 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010020#include <linux/ratelimit.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020021#include <linux/pci.h>
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -040022#include <linux/acpi.h>
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -040023#include <linux/amba/bus.h>
Wan Zongshun0076cd32016-05-10 09:21:01 -040024#include <linux/platform_device.h>
Joerg Roedelcb41ed82011-04-05 11:00:53 +020025#include <linux/pci-ats.h>
Akinobu Mitaa66022c2009-12-15 16:48:28 -080026#include <linux/bitmap.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090027#include <linux/slab.h>
Joerg Roedel7f265082008-12-12 13:50:21 +010028#include <linux/debugfs.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020029#include <linux/scatterlist.h>
FUJITA Tomonori51491362009-01-05 23:47:25 +090030#include <linux/dma-mapping.h>
Christoph Hellwigfec777c2018-03-19 11:38:15 +010031#include <linux/dma-direct.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020032#include <linux/iommu-helper.h>
Joerg Roedelc156e342008-12-02 18:13:27 +010033#include <linux/iommu.h>
Joerg Roedel815b33f2011-04-06 17:26:49 +020034#include <linux/delay.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020035#include <linux/amd-iommu.h>
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010036#include <linux/notifier.h>
37#include <linux/export.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020038#include <linux/irq.h>
39#include <linux/msi.h>
Joerg Roedel3b839a52015-04-01 14:58:47 +020040#include <linux/dma-contiguous.h>
Jiang Liu7c71d302015-04-13 14:11:33 +080041#include <linux/irqdomain.h>
Joerg Roedel5f6bed52015-12-22 13:34:22 +010042#include <linux/percpu.h>
Joerg Roedel307d5852016-07-05 11:54:04 +020043#include <linux/iova.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020044#include <asm/irq_remapping.h>
45#include <asm/io_apic.h>
46#include <asm/apic.h>
47#include <asm/hw_irq.h>
Joerg Roedel17f5b562011-07-06 17:14:44 +020048#include <asm/msidef.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020049#include <asm/proto.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090050#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010051#include <asm/gart.h>
Joerg Roedel27c21272011-05-30 15:56:24 +020052#include <asm/dma.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020053
54#include "amd_iommu_proto.h"
55#include "amd_iommu_types.h"
Joerg Roedel6b474b82012-06-26 16:46:04 +020056#include "irq_remapping.h"
Joerg Roedelb6c02712008-06-26 21:27:53 +020057
Christoph Hellwiga8695722017-05-21 13:26:45 +020058#define AMD_IOMMU_MAPPING_ERROR 0
59
Joerg Roedelb6c02712008-06-26 21:27:53 +020060#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61
Joerg Roedel815b33f2011-04-06 17:26:49 +020062#define LOOP_TIMEOUT 100000
Joerg Roedel136f78a2008-07-11 17:14:27 +020063
Joerg Roedel307d5852016-07-05 11:54:04 +020064/* IO virtual address start page frame number */
65#define IOVA_START_PFN (1)
66#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
Joerg Roedel307d5852016-07-05 11:54:04 +020067
Joerg Roedel81cd07b2016-07-07 18:01:10 +020068/* Reserved IOVA ranges */
69#define MSI_RANGE_START (0xfee00000)
70#define MSI_RANGE_END (0xfeefffff)
71#define HT_RANGE_START (0xfd00000000ULL)
72#define HT_RANGE_END (0xffffffffffULL)
73
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020074/*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
Joerg Roedel954e3dd2012-12-02 15:35:37 +010080 * 512GB Pages are not supported due to a hardware bug
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020081 */
Joerg Roedel954e3dd2012-12-02 15:35:37 +010082#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020083
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +010084static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +010085static DEFINE_SPINLOCK(pd_bitmap_lock);
Joerg Roedelb6c02712008-06-26 21:27:53 +020086
Joerg Roedel8fa5f802011-06-09 12:24:45 +020087/* List of all available dev_data structures */
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +010088static LLIST_HEAD(dev_data_list);
Joerg Roedel8fa5f802011-06-09 12:24:45 +020089
Joerg Roedel6efed632012-06-14 15:52:58 +020090LIST_HEAD(ioapic_map);
91LIST_HEAD(hpet_map);
Wan Zongshun2a0cb4e2016-04-01 09:06:00 -040092LIST_HEAD(acpihid_map);
Joerg Roedel6efed632012-06-14 15:52:58 +020093
Joerg Roedel0feae532009-08-26 15:26:30 +020094/*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
Joerg Roedelb0119e82017-02-01 13:23:08 +010098const struct iommu_ops amd_iommu_ops;
Joerg Roedel26961ef2008-12-03 17:00:17 +010099
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100100static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
Joerg Roedel52815b72011-11-17 17:24:28 +0100101int amd_iommu_max_glx_val = -1;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100102
Bart Van Assche52997092017-01-20 13:04:01 -0800103static const struct dma_map_ops amd_iommu_dma_ops;
Joerg Roedelac1534a2012-06-21 14:52:40 +0200104
Joerg Roedel431b2a22008-07-11 17:14:22 +0200105/*
106 * general struct to manage commands send to an IOMMU
107 */
Joerg Roedeld6449532008-07-11 17:14:28 +0200108struct iommu_cmd {
Joerg Roedelb6c02712008-06-26 21:27:53 +0200109 u32 data[4];
110};
111
Joerg Roedel05152a02012-06-15 16:53:51 +0200112struct kmem_cache *amd_iommu_irq_cache;
113
Joerg Roedel04bfdd82009-09-02 16:00:23 +0200114static void update_domain(struct protection_domain *domain);
Joerg Roedel7a5a5662015-06-30 08:56:11 +0200115static int protection_domain_init(struct protection_domain *domain);
Joerg Roedelb6809ee2016-02-26 16:48:59 +0100116static void detach_device(struct device *dev);
Joerg Roedel9003d612017-08-10 17:19:13 +0200117static void iova_domain_flush_tlb(struct iova_domain *iovad);
Joerg Roedeld4241a22017-06-02 14:55:56 +0200118
Joerg Roedel007b74b2015-12-21 12:53:54 +0100119/*
Joerg Roedel007b74b2015-12-21 12:53:54 +0100120 * Data container for a dma_ops specific protection domain
121 */
122struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
Joerg Roedel307d5852016-07-05 11:54:04 +0200126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
Joerg Roedel007b74b2015-12-21 12:53:54 +0100128};
129
Joerg Roedel81cd07b2016-07-07 18:01:10 +0200130static struct iova_domain reserved_iova_ranges;
131static struct lock_class_key reserved_rbtree_key;
132
Joerg Roedel15898bb2009-11-24 15:39:42 +0100133/****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400139static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
Joerg Roedel3f4b87b2015-03-26 13:43:07 +0100141{
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
Joerg Roedel3f4b87b2015-03-26 13:43:07 +0100157}
158
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400159static inline u16 get_pci_device_id(struct device *dev)
Joerg Roedele3156042016-04-08 15:12:24 +0200160{
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164}
165
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400166static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168{
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179}
180
181static inline int get_device_id(struct device *dev)
182{
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191}
192
Joerg Roedel15898bb2009-11-24 15:39:42 +0100193static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194{
195 return container_of(dom, struct protection_domain, domain);
196}
197
Joerg Roedelb3311b02016-07-08 13:31:31 +0200198static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199{
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202}
203
Joerg Roedelf62dda62011-06-09 12:55:35 +0200204static struct iommu_dev_data *alloc_dev_data(u16 devid)
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200205{
206 struct iommu_dev_data *dev_data;
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200207
208 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
209 if (!dev_data)
210 return NULL;
211
Joerg Roedelf62dda62011-06-09 12:55:35 +0200212 dev_data->devid = devid;
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200213 ratelimit_default_init(&dev_data->rs);
214
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100215 llist_add(&dev_data->dev_data_list, &dev_data_list);
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200216 return dev_data;
217}
218
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200219static struct iommu_dev_data *search_dev_data(u16 devid)
220{
221 struct iommu_dev_data *dev_data;
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100222 struct llist_node *node;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200223
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100224 if (llist_empty(&dev_data_list))
225 return NULL;
226
227 node = dev_data_list.first;
228 llist_for_each_entry(dev_data, node, dev_data_list) {
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200229 if (dev_data->devid == devid)
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100230 return dev_data;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200231 }
232
Sebastian Andrzej Siewior779da732018-03-22 16:22:34 +0100233 return NULL;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200234}
235
Joerg Roedele3156042016-04-08 15:12:24 +0200236static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
237{
238 *(u16 *)data = alias;
239 return 0;
240}
241
242static u16 get_alias(struct device *dev)
243{
244 struct pci_dev *pdev = to_pci_dev(dev);
245 u16 devid, ivrs_alias, pci_alias;
246
Joerg Roedel6c0b43d2016-05-09 19:39:17 +0200247 /* The callers make sure that get_device_id() does not fail here */
Joerg Roedele3156042016-04-08 15:12:24 +0200248 devid = get_device_id(dev);
249 ivrs_alias = amd_iommu_alias_table[devid];
250 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
251
252 if (ivrs_alias == pci_alias)
253 return ivrs_alias;
254
255 /*
256 * DMA alias showdown
257 *
258 * The IVRS is fairly reliable in telling us about aliases, but it
259 * can't know about every screwy device. If we don't have an IVRS
260 * reported alias, use the PCI reported alias. In that case we may
261 * still need to initialize the rlookup and dev_table entries if the
262 * alias is to a non-existent device.
263 */
264 if (ivrs_alias == devid) {
265 if (!amd_iommu_rlookup_table[pci_alias]) {
266 amd_iommu_rlookup_table[pci_alias] =
267 amd_iommu_rlookup_table[devid];
268 memcpy(amd_iommu_dev_table[pci_alias].data,
269 amd_iommu_dev_table[devid].data,
270 sizeof(amd_iommu_dev_table[pci_alias].data));
271 }
272
273 return pci_alias;
274 }
275
276 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
277 "for device %s[%04x:%04x], kernel reported alias "
278 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
279 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
280 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
281 PCI_FUNC(pci_alias));
282
283 /*
284 * If we don't have a PCI DMA alias and the IVRS alias is on the same
285 * bus, then the IVRS table may know about a quirk that we don't.
286 */
287 if (pci_alias == devid &&
288 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
Linus Torvalds7afd16f2016-05-19 13:10:54 -0700289 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
Joerg Roedele3156042016-04-08 15:12:24 +0200290 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
291 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
292 dev_name(dev));
293 }
294
295 return ivrs_alias;
296}
297
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200298static struct iommu_dev_data *find_dev_data(u16 devid)
299{
300 struct iommu_dev_data *dev_data;
Baoquan Hedf3f7a62017-08-09 16:33:41 +0800301 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200302
303 dev_data = search_dev_data(devid);
304
Baoquan Hedf3f7a62017-08-09 16:33:41 +0800305 if (dev_data == NULL) {
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200306 dev_data = alloc_dev_data(devid);
Sebastian Andrzej Siewior39ffe392018-03-22 16:22:33 +0100307 if (!dev_data)
308 return NULL;
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200309
Baoquan Hedf3f7a62017-08-09 16:33:41 +0800310 if (translation_pre_enabled(iommu))
311 dev_data->defer_attach = true;
312 }
313
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200314 return dev_data;
315}
316
Baoquan Hedaae2d22017-08-09 16:33:43 +0800317struct iommu_dev_data *get_dev_data(struct device *dev)
Joerg Roedel657cbb62009-11-23 15:26:46 +0100318{
319 return dev->archdata.iommu;
320}
Baoquan Hedaae2d22017-08-09 16:33:43 +0800321EXPORT_SYMBOL(get_dev_data);
Joerg Roedel657cbb62009-11-23 15:26:46 +0100322
Wan Zongshunb097d112016-04-01 09:06:04 -0400323/*
324* Find or create an IOMMU group for a acpihid device.
325*/
326static struct iommu_group *acpihid_device_group(struct device *dev)
327{
328 struct acpihid_map_entry *p, *entry = NULL;
Dan Carpenter2d8e1f02016-04-11 10:14:46 +0300329 int devid;
Wan Zongshunb097d112016-04-01 09:06:04 -0400330
331 devid = get_acpihid_device_id(dev, &entry);
332 if (devid < 0)
333 return ERR_PTR(devid);
334
335 list_for_each_entry(p, &acpihid_map, list) {
336 if ((devid == p->devid) && p->group)
337 entry->group = p->group;
338 }
339
340 if (!entry->group)
341 entry->group = generic_device_group(dev);
Robin Murphyf2f101f2016-11-11 17:59:23 +0000342 else
343 iommu_group_ref_get(entry->group);
Wan Zongshunb097d112016-04-01 09:06:04 -0400344
345 return entry->group;
346}
347
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100348static bool pci_iommuv2_capable(struct pci_dev *pdev)
349{
350 static const int caps[] = {
351 PCI_EXT_CAP_ID_ATS,
Joerg Roedel46277b72011-12-07 14:34:02 +0100352 PCI_EXT_CAP_ID_PRI,
353 PCI_EXT_CAP_ID_PASID,
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100354 };
355 int i, pos;
356
Gil Kupfercef74402018-05-10 17:56:02 -0500357 if (pci_ats_disabled())
358 return false;
359
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100360 for (i = 0; i < 3; ++i) {
361 pos = pci_find_ext_capability(pdev, caps[i]);
362 if (pos == 0)
363 return false;
364 }
365
366 return true;
367}
368
Joerg Roedel6a113dd2011-12-01 12:04:58 +0100369static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
370{
371 struct iommu_dev_data *dev_data;
372
373 dev_data = get_dev_data(&pdev->dev);
374
375 return dev_data->errata & (1 << erratum) ? true : false;
376}
377
Joerg Roedel71c70982009-11-24 16:43:06 +0100378/*
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100379 * This function checks if the driver got a valid device from the caller to
380 * avoid dereferencing invalid pointers.
381 */
382static bool check_device(struct device *dev)
383{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400384 int devid;
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100385
386 if (!dev || !dev->dma_mask)
387 return false;
388
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100389 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200390 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400391 return false;
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100392
393 /* Out of our scope? */
394 if (devid > amd_iommu_last_bdf)
395 return false;
396
397 if (amd_iommu_rlookup_table[devid] == NULL)
398 return false;
399
400 return true;
401}
402
Alex Williamson25b11ce2014-09-19 10:03:13 -0600403static void init_iommu_group(struct device *dev)
Alex Williamson2851db22012-10-08 22:49:41 -0600404{
Alex Williamson2851db22012-10-08 22:49:41 -0600405 struct iommu_group *group;
Alex Williamson2851db22012-10-08 22:49:41 -0600406
Alex Williamson65d53522014-07-03 09:51:30 -0600407 group = iommu_group_get_for_dev(dev);
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200408 if (IS_ERR(group))
409 return;
410
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200411 iommu_group_put(group);
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600412}
413
414static int iommu_init_device(struct device *dev)
415{
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600416 struct iommu_dev_data *dev_data;
Joerg Roedel39ab9552017-02-01 16:56:46 +0100417 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400418 int devid;
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600419
420 if (dev->archdata.iommu)
421 return 0;
422
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400423 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200424 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400425 return devid;
426
Joerg Roedel39ab9552017-02-01 16:56:46 +0100427 iommu = amd_iommu_rlookup_table[devid];
428
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400429 dev_data = find_dev_data(devid);
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600430 if (!dev_data)
431 return -ENOMEM;
432
Joerg Roedele3156042016-04-08 15:12:24 +0200433 dev_data->alias = get_alias(dev);
434
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400435 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100436 struct amd_iommu *iommu;
437
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -0400438 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100439 dev_data->iommu_v2 = iommu->is_iommu_v2;
440 }
441
Joerg Roedel657cbb62009-11-23 15:26:46 +0100442 dev->archdata.iommu = dev_data;
443
Joerg Roedele3d10af2017-02-01 17:23:22 +0100444 iommu_device_link(&iommu->iommu, dev);
Alex Williamson066f2e92014-06-12 16:12:37 -0600445
Joerg Roedel657cbb62009-11-23 15:26:46 +0100446 return 0;
447}
448
Joerg Roedel26018872011-06-06 16:50:14 +0200449static void iommu_ignore_device(struct device *dev)
450{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400451 u16 alias;
452 int devid;
Joerg Roedel26018872011-06-06 16:50:14 +0200453
454 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200455 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400456 return;
457
Joerg Roedele3156042016-04-08 15:12:24 +0200458 alias = get_alias(dev);
Joerg Roedel26018872011-06-06 16:50:14 +0200459
460 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
461 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
462
463 amd_iommu_rlookup_table[devid] = NULL;
464 amd_iommu_rlookup_table[alias] = NULL;
465}
466
Joerg Roedel657cbb62009-11-23 15:26:46 +0100467static void iommu_uninit_device(struct device *dev)
468{
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400469 struct iommu_dev_data *dev_data;
Joerg Roedel39ab9552017-02-01 16:56:46 +0100470 struct amd_iommu *iommu;
471 int devid;
Alex Williamsonc1931092014-07-03 09:51:24 -0600472
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400473 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +0200474 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400475 return;
476
Joerg Roedel39ab9552017-02-01 16:56:46 +0100477 iommu = amd_iommu_rlookup_table[devid];
478
Wan Zongshun7aba6cb2016-04-01 09:06:02 -0400479 dev_data = search_dev_data(devid);
Alex Williamsonc1931092014-07-03 09:51:24 -0600480 if (!dev_data)
481 return;
482
Joerg Roedelb6809ee2016-02-26 16:48:59 +0100483 if (dev_data->domain)
484 detach_device(dev);
485
Joerg Roedele3d10af2017-02-01 17:23:22 +0100486 iommu_device_unlink(&iommu->iommu, dev);
Alex Williamson066f2e92014-06-12 16:12:37 -0600487
Alex Williamson9dcd6132012-05-30 14:19:07 -0600488 iommu_group_remove_device(dev);
489
Joerg Roedelaafd8ba2015-05-28 18:41:39 +0200490 /* Remove dma-ops */
Bart Van Assche56579332017-01-20 13:04:02 -0800491 dev->dma_ops = NULL;
Joerg Roedelaafd8ba2015-05-28 18:41:39 +0200492
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200493 /*
Alex Williamsonc1931092014-07-03 09:51:24 -0600494 * We keep dev_data around for unplugged devices and reuse it when the
495 * device is re-plugged - not doing so would introduce a ton of races.
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200496 */
Joerg Roedel657cbb62009-11-23 15:26:46 +0100497}
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100498
Joerg Roedel431b2a22008-07-11 17:14:22 +0200499/****************************************************************************
500 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200501 * Interrupt handling functions
502 *
503 ****************************************************************************/
504
Joerg Roedele3e59872009-09-03 14:02:10 +0200505static void dump_dte_entry(u16 devid)
506{
507 int i;
508
Joerg Roedelee6c2862011-11-09 12:06:03 +0100509 for (i = 0; i < 4; ++i)
510 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
Joerg Roedele3e59872009-09-03 14:02:10 +0200511 amd_iommu_dev_table[devid].data[i]);
512}
513
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200514static void dump_command(unsigned long phys_addr)
515{
Tom Lendacky2543a782017-07-17 16:10:24 -0500516 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200517 int i;
518
519 for (i = 0; i < 4; ++i)
520 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
521}
522
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200523static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
524 u64 address, int flags)
525{
526 struct iommu_dev_data *dev_data = NULL;
527 struct pci_dev *pdev;
528
Sinan Kayad5bf0f42017-12-19 00:37:47 -0500529 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
530 devid & 0xff);
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200531 if (pdev)
532 dev_data = get_dev_data(&pdev->dev);
533
534 if (dev_data && __ratelimit(&dev_data->rs)) {
535 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 domain_id, address, flags);
537 } else if (printk_ratelimit()) {
538 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
540 domain_id, address, flags);
541 }
542
543 if (pdev)
544 pci_dev_put(pdev);
545}
546
Joerg Roedela345b232009-09-03 15:01:43 +0200547static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
Joerg Roedel90008ee2008-09-09 16:41:05 +0200548{
Gary R Hook90ca3852018-03-08 18:34:41 -0600549 struct device *dev = iommu->iommu.dev;
Gary R Hooke7f63ff2018-05-01 14:53:00 -0500550 int type, devid, pasid, flags, tag;
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
Gary R Hookd64c0482018-05-01 14:52:52 -0500558 pasid = PPR_PASID(*(u64 *)&event[0]);
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200571
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200572 if (type == EVENT_TYPE_IO_FAULT) {
Gary R Hookd64c0482018-05-01 14:52:52 -0500573 amd_iommu_report_page_fault(devid, pasid, address, flags);
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200574 return;
575 } else {
Gary R Hook90ca3852018-03-08 18:34:41 -0600576 dev_err(dev, "AMD-Vi: Event logged [");
Joerg Roedel30bf2df2017-05-15 16:25:03 +0200577 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200578
579 switch (type) {
580 case EVENT_TYPE_ILL_DEV:
Gary R Hookd64c0482018-05-01 14:52:52 -0500581 dev_err(dev, "ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600582 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Gary R Hookd64c0482018-05-01 14:52:52 -0500583 pasid, address, flags);
Joerg Roedele3e59872009-09-03 14:02:10 +0200584 dump_dte_entry(devid);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200585 break;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200586 case EVENT_TYPE_DEV_TAB_ERR:
Gary R Hook90ca3852018-03-08 18:34:41 -0600587 dev_err(dev, "DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
588 "address=0x%016llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
590 address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200591 break;
592 case EVENT_TYPE_PAGE_TAB_ERR:
Gary R Hookd64c0482018-05-01 14:52:52 -0500593 dev_err(dev, "PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600594 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Gary R Hookd64c0482018-05-01 14:52:52 -0500595 pasid, address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200596 break;
597 case EVENT_TYPE_ILL_CMD:
Gary R Hook90ca3852018-03-08 18:34:41 -0600598 dev_err(dev, "ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200599 dump_command(address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200600 break;
601 case EVENT_TYPE_CMD_HARD_ERR:
Gary R Hookd64c0482018-05-01 14:52:52 -0500602 dev_err(dev, "COMMAND_HARDWARE_ERROR address=0x%016llx flags=0x%04x]\n",
603 address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200604 break;
605 case EVENT_TYPE_IOTLB_INV_TO:
Gary R Hookd64c0482018-05-01 14:52:52 -0500606 dev_err(dev, "IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%016llx]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600607 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
608 address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200609 break;
610 case EVENT_TYPE_INV_DEV_REQ:
Gary R Hookd64c0482018-05-01 14:52:52 -0500611 dev_err(dev, "INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600612 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Gary R Hookd64c0482018-05-01 14:52:52 -0500613 pasid, address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200614 break;
Gary R Hooke7f63ff2018-05-01 14:53:00 -0500615 case EVENT_TYPE_INV_PPR_REQ:
616 pasid = ((event[0] >> 16) & 0xFFFF)
617 | ((event[1] << 6) & 0xF0000);
618 tag = event[1] & 0x03FF;
619 dev_err(dev, "INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 pasid, address, flags);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200622 break;
623 default:
Gary R Hookd64c0482018-05-01 14:52:52 -0500624 dev_err(dev, "UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
Gary R Hook90ca3852018-03-08 18:34:41 -0600625 event[0], event[1], event[2], event[3]);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200626 }
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200627
628 memset(__evt, 0, 4 * sizeof(u32));
Joerg Roedel90008ee2008-09-09 16:41:05 +0200629}
630
631static void iommu_poll_events(struct amd_iommu *iommu)
632{
633 u32 head, tail;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200634
635 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
636 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
637
638 while (head != tail) {
Joerg Roedela345b232009-09-03 15:01:43 +0200639 iommu_print_event(iommu, iommu->evt_buf + head);
Joerg Roedeldeba4bc2015-10-20 17:33:41 +0200640 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200641 }
642
643 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200644}
645
Joerg Roedeleee53532012-06-01 15:20:23 +0200646static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100647{
648 struct amd_iommu_fault fault;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100649
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100650 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
651 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
652 return;
653 }
654
655 fault.address = raw[1];
656 fault.pasid = PPR_PASID(raw[0]);
657 fault.device_id = PPR_DEVID(raw[0]);
658 fault.tag = PPR_TAG(raw[0]);
659 fault.flags = PPR_FLAGS(raw[0]);
660
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100661 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
662}
663
664static void iommu_poll_ppr_log(struct amd_iommu *iommu)
665{
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100666 u32 head, tail;
667
668 if (iommu->ppr_log == NULL)
669 return;
670
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100671 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
672 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
673
674 while (head != tail) {
Joerg Roedeleee53532012-06-01 15:20:23 +0200675 volatile u64 *raw;
676 u64 entry[2];
677 int i;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100678
Joerg Roedeleee53532012-06-01 15:20:23 +0200679 raw = (u64 *)(iommu->ppr_log + head);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100680
Joerg Roedeleee53532012-06-01 15:20:23 +0200681 /*
682 * Hardware bug: Interrupt may arrive before the entry is
683 * written to memory. If this happens we need to wait for the
684 * entry to arrive.
685 */
686 for (i = 0; i < LOOP_TIMEOUT; ++i) {
687 if (PPR_REQ_TYPE(raw[0]) != 0)
688 break;
689 udelay(1);
690 }
691
692 /* Avoid memcpy function-call overhead */
693 entry[0] = raw[0];
694 entry[1] = raw[1];
695
696 /*
697 * To detect the hardware bug we need to clear the entry
698 * back to zero.
699 */
700 raw[0] = raw[1] = 0UL;
701
702 /* Update head pointer of hardware ring-buffer */
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100703 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
704 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedeleee53532012-06-01 15:20:23 +0200705
Joerg Roedeleee53532012-06-01 15:20:23 +0200706 /* Handle PPR entry */
707 iommu_handle_ppr_entry(iommu, entry);
708
Joerg Roedeleee53532012-06-01 15:20:23 +0200709 /* Refresh ring-buffer information */
710 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100711 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
712 }
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100713}
714
Suravee Suthikulpanitbd6fcef2016-08-23 13:52:37 -0500715#ifdef CONFIG_IRQ_REMAP
716static int (*iommu_ga_log_notifier)(u32);
717
718int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
719{
720 iommu_ga_log_notifier = notifier;
721
722 return 0;
723}
724EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
725
726static void iommu_poll_ga_log(struct amd_iommu *iommu)
727{
728 u32 head, tail, cnt = 0;
729
730 if (iommu->ga_log == NULL)
731 return;
732
733 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
734 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
735
736 while (head != tail) {
737 volatile u64 *raw;
738 u64 log_entry;
739
740 raw = (u64 *)(iommu->ga_log + head);
741 cnt++;
742
743 /* Avoid memcpy function-call overhead */
744 log_entry = *raw;
745
746 /* Update head pointer of hardware ring-buffer */
747 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
748 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
749
750 /* Handle GA entry */
751 switch (GA_REQ_TYPE(log_entry)) {
752 case GA_GUEST_NR:
753 if (!iommu_ga_log_notifier)
754 break;
755
756 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
757 __func__, GA_DEVID(log_entry),
758 GA_TAG(log_entry));
759
760 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
761 pr_err("AMD-Vi: GA log notifier failed.\n");
762 break;
763 default:
764 break;
765 }
766 }
767}
768#endif /* CONFIG_IRQ_REMAP */
769
770#define AMD_IOMMU_INT_MASK \
771 (MMIO_STATUS_EVT_INT_MASK | \
772 MMIO_STATUS_PPR_INT_MASK | \
773 MMIO_STATUS_GALOG_INT_MASK)
774
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200775irqreturn_t amd_iommu_int_thread(int irq, void *data)
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200776{
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500777 struct amd_iommu *iommu = (struct amd_iommu *) data;
778 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200779
Suravee Suthikulpanitbd6fcef2016-08-23 13:52:37 -0500780 while (status & AMD_IOMMU_INT_MASK) {
781 /* Enable EVT and PPR and GA interrupts again */
782 writel(AMD_IOMMU_INT_MASK,
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500783 iommu->mmio_base + MMIO_STATUS_OFFSET);
784
785 if (status & MMIO_STATUS_EVT_INT_MASK) {
786 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
787 iommu_poll_events(iommu);
788 }
789
790 if (status & MMIO_STATUS_PPR_INT_MASK) {
791 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
792 iommu_poll_ppr_log(iommu);
793 }
794
Suravee Suthikulpanitbd6fcef2016-08-23 13:52:37 -0500795#ifdef CONFIG_IRQ_REMAP
796 if (status & MMIO_STATUS_GALOG_INT_MASK) {
797 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
798 iommu_poll_ga_log(iommu);
799 }
800#endif
801
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500802 /*
803 * Hardware bug: ERBT1312
804 * When re-enabling interrupt (by writing 1
805 * to clear the bit), the hardware might also try to set
806 * the interrupt bit in the event status register.
807 * In this scenario, the bit will be set, and disable
808 * subsequent interrupts.
809 *
810 * Workaround: The IOMMU driver should read back the
811 * status register and check if the interrupt bits are cleared.
812 * If not, driver will need to go through the interrupt handler
813 * again and re-clear the bits
814 */
815 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100816 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200817 return IRQ_HANDLED;
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200818}
819
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200820irqreturn_t amd_iommu_int_handler(int irq, void *data)
821{
822 return IRQ_WAKE_THREAD;
823}
824
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200825/****************************************************************************
826 *
Joerg Roedel431b2a22008-07-11 17:14:22 +0200827 * IOMMU command queuing functions
828 *
829 ****************************************************************************/
830
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200831static int wait_on_sem(volatile u64 *sem)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200832{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200833 int i = 0;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200834
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200835 while (*sem == 0 && i < LOOP_TIMEOUT) {
836 udelay(1);
837 i += 1;
838 }
839
840 if (i == LOOP_TIMEOUT) {
841 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
842 return -EIO;
843 }
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200844
845 return 0;
846}
847
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200848static void copy_cmd_to_buffer(struct amd_iommu *iommu,
Tom Lendackyd334a562017-06-05 14:52:12 -0500849 struct iommu_cmd *cmd)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200850{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200851 u8 *target;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200852
Tom Lendackyd334a562017-06-05 14:52:12 -0500853 target = iommu->cmd_buf + iommu->cmd_buf_tail;
854
855 iommu->cmd_buf_tail += sizeof(*cmd);
856 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200857
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200858 /* Copy command to buffer */
859 memcpy(target, cmd, sizeof(*cmd));
860
861 /* Tell the IOMMU about it */
Tom Lendackyd334a562017-06-05 14:52:12 -0500862 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200863}
864
Joerg Roedel815b33f2011-04-06 17:26:49 +0200865static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
Joerg Roedelded46732011-04-06 10:53:48 +0200866{
Tom Lendacky2543a782017-07-17 16:10:24 -0500867 u64 paddr = iommu_virt_to_phys((void *)address);
868
Joerg Roedel815b33f2011-04-06 17:26:49 +0200869 WARN_ON(address & 0x7ULL);
870
Joerg Roedelded46732011-04-06 10:53:48 +0200871 memset(cmd, 0, sizeof(*cmd));
Tom Lendacky2543a782017-07-17 16:10:24 -0500872 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
873 cmd->data[1] = upper_32_bits(paddr);
Joerg Roedel815b33f2011-04-06 17:26:49 +0200874 cmd->data[2] = 1;
Joerg Roedelded46732011-04-06 10:53:48 +0200875 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
876}
877
Joerg Roedel94fe79e2011-04-06 11:07:21 +0200878static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
879{
880 memset(cmd, 0, sizeof(*cmd));
881 cmd->data[0] = devid;
882 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
883}
884
Joerg Roedel11b64022011-04-06 11:49:28 +0200885static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
886 size_t size, u16 domid, int pde)
887{
888 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100889 bool s;
Joerg Roedel11b64022011-04-06 11:49:28 +0200890
891 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100892 s = false;
Joerg Roedel11b64022011-04-06 11:49:28 +0200893
894 if (pages > 1) {
895 /*
896 * If we have to flush more than one page, flush all
897 * TLB entries for this domain
898 */
899 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100900 s = true;
Joerg Roedel11b64022011-04-06 11:49:28 +0200901 }
902
903 address &= PAGE_MASK;
904
905 memset(cmd, 0, sizeof(*cmd));
906 cmd->data[1] |= domid;
907 cmd->data[2] = lower_32_bits(address);
908 cmd->data[3] = upper_32_bits(address);
909 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
910 if (s) /* size bit - we flush more than one 4kb page */
911 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
Frank Arnolddf805ab2012-08-27 19:21:04 +0200912 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
Joerg Roedel11b64022011-04-06 11:49:28 +0200913 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
914}
915
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200916static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
917 u64 address, size_t size)
918{
919 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100920 bool s;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200921
922 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100923 s = false;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200924
925 if (pages > 1) {
926 /*
927 * If we have to flush more than one page, flush all
928 * TLB entries for this domain
929 */
930 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100931 s = true;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200932 }
933
934 address &= PAGE_MASK;
935
936 memset(cmd, 0, sizeof(*cmd));
937 cmd->data[0] = devid;
938 cmd->data[0] |= (qdep & 0xff) << 24;
939 cmd->data[1] = devid;
940 cmd->data[2] = lower_32_bits(address);
941 cmd->data[3] = upper_32_bits(address);
942 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
943 if (s)
944 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
945}
946
Joerg Roedel22e266c2011-11-21 15:59:08 +0100947static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
948 u64 address, bool size)
949{
950 memset(cmd, 0, sizeof(*cmd));
951
952 address &= ~(0xfffULL);
953
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600954 cmd->data[0] = pasid;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100955 cmd->data[1] = domid;
956 cmd->data[2] = lower_32_bits(address);
957 cmd->data[3] = upper_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
960 if (size)
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
963}
964
965static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
966 int qdep, u64 address, bool size)
967{
968 memset(cmd, 0, sizeof(*cmd));
969
970 address &= ~(0xfffULL);
971
972 cmd->data[0] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600973 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100974 cmd->data[0] |= (qdep & 0xff) << 24;
975 cmd->data[1] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600976 cmd->data[1] |= (pasid & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100977 cmd->data[2] = lower_32_bits(address);
978 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
979 cmd->data[3] = upper_32_bits(address);
980 if (size)
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
982 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
983}
984
Joerg Roedelc99afa22011-11-21 18:19:25 +0100985static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
986 int status, int tag, bool gn)
987{
988 memset(cmd, 0, sizeof(*cmd));
989
990 cmd->data[0] = devid;
991 if (gn) {
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600992 cmd->data[1] = pasid;
Joerg Roedelc99afa22011-11-21 18:19:25 +0100993 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
994 }
995 cmd->data[3] = tag & 0x1ff;
996 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
997
998 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
999}
1000
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001001static void build_inv_all(struct iommu_cmd *cmd)
1002{
1003 memset(cmd, 0, sizeof(*cmd));
1004 CMD_SET_TYPE(cmd, CMD_INV_ALL);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001005}
1006
Joerg Roedel7ef27982012-06-21 16:46:04 +02001007static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1008{
1009 memset(cmd, 0, sizeof(*cmd));
1010 cmd->data[0] = devid;
1011 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1012}
1013
Joerg Roedel431b2a22008-07-11 17:14:22 +02001014/*
Joerg Roedelb6c02712008-06-26 21:27:53 +02001015 * Writes the command to the IOMMUs command buffer and informs the
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001016 * hardware about the new command.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001017 */
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001018static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1019 struct iommu_cmd *cmd,
1020 bool sync)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001021{
Tom Lendacky23e967e2017-06-05 14:52:26 -05001022 unsigned int count = 0;
Tom Lendackyd334a562017-06-05 14:52:12 -05001023 u32 left, next_tail;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001024
Tom Lendackyd334a562017-06-05 14:52:12 -05001025 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001026again:
Tom Lendackyd334a562017-06-05 14:52:12 -05001027 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001028
Huang Rui432abf62016-12-12 07:28:26 -05001029 if (left <= 0x20) {
Tom Lendacky23e967e2017-06-05 14:52:26 -05001030 /* Skip udelay() the first time around */
1031 if (count++) {
1032 if (count == LOOP_TIMEOUT) {
1033 pr_err("AMD-Vi: Command buffer timeout\n");
1034 return -EIO;
1035 }
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001036
Tom Lendacky23e967e2017-06-05 14:52:26 -05001037 udelay(1);
Tom Lendackyd334a562017-06-05 14:52:12 -05001038 }
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001039
Tom Lendacky23e967e2017-06-05 14:52:26 -05001040 /* Update head and recheck remaining space */
1041 iommu->cmd_buf_head = readl(iommu->mmio_base +
1042 MMIO_CMD_HEAD_OFFSET);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001043
1044 goto again;
Joerg Roedel136f78a2008-07-11 17:14:27 +02001045 }
1046
Tom Lendackyd334a562017-06-05 14:52:12 -05001047 copy_cmd_to_buffer(iommu, cmd);
Joerg Roedel519c31b2008-08-14 19:55:15 +02001048
Tom Lendacky23e967e2017-06-05 14:52:26 -05001049 /* Do we need to make sure all commands are processed? */
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001050 iommu->need_sync = sync;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001051
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001052 return 0;
1053}
1054
1055static int iommu_queue_command_sync(struct amd_iommu *iommu,
1056 struct iommu_cmd *cmd,
1057 bool sync)
1058{
1059 unsigned long flags;
1060 int ret;
1061
Scott Wood27790392018-01-21 03:28:54 -06001062 raw_spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001063 ret = __iommu_queue_command_sync(iommu, cmd, sync);
Scott Wood27790392018-01-21 03:28:54 -06001064 raw_spin_unlock_irqrestore(&iommu->lock, flags);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001065
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001066 return ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001067}
1068
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001069static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1070{
1071 return iommu_queue_command_sync(iommu, cmd, true);
1072}
1073
Joerg Roedel8d201962008-12-02 20:34:41 +01001074/*
1075 * This function queues a completion wait command into the command
1076 * buffer of an IOMMU
1077 */
Joerg Roedel8d201962008-12-02 20:34:41 +01001078static int iommu_completion_wait(struct amd_iommu *iommu)
1079{
Joerg Roedel815b33f2011-04-06 17:26:49 +02001080 struct iommu_cmd cmd;
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001081 unsigned long flags;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001082 int ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001083
1084 if (!iommu->need_sync)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001085 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +01001086
Joerg Roedel8d201962008-12-02 20:34:41 +01001087
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001088 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1089
Scott Wood27790392018-01-21 03:28:54 -06001090 raw_spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001091
1092 iommu->cmd_sem = 0;
1093
1094 ret = __iommu_queue_command_sync(iommu, &cmd, false);
Joerg Roedel8d201962008-12-02 20:34:41 +01001095 if (ret)
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001096 goto out_unlock;
Joerg Roedel8d201962008-12-02 20:34:41 +01001097
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001098 ret = wait_on_sem(&iommu->cmd_sem);
1099
1100out_unlock:
Scott Wood27790392018-01-21 03:28:54 -06001101 raw_spin_unlock_irqrestore(&iommu->lock, flags);
Joerg Roedel4bf5bee2016-09-14 11:41:59 +02001102
1103 return ret;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001104}
1105
Joerg Roedeld8c13082011-04-06 18:51:26 +02001106static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001107{
1108 struct iommu_cmd cmd;
1109
Joerg Roedeld8c13082011-04-06 18:51:26 +02001110 build_inv_dte(&cmd, devid);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001111
Joerg Roedeld8c13082011-04-06 18:51:26 +02001112 return iommu_queue_command(iommu, &cmd);
1113}
1114
Joerg Roedel0688a092017-08-23 15:50:03 +02001115static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001116{
1117 u32 devid;
1118
1119 for (devid = 0; devid <= 0xffff; ++devid)
1120 iommu_flush_dte(iommu, devid);
1121
1122 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001123}
1124
1125/*
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001126 * This function uses heavy locking and may disable irqs for some time. But
1127 * this is no issue because it is only called during resume.
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001128 */
Joerg Roedel0688a092017-08-23 15:50:03 +02001129static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001130{
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001131 u32 dom_id;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001132
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001133 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1134 struct iommu_cmd cmd;
1135 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1136 dom_id, 1);
1137 iommu_queue_command(iommu, &cmd);
1138 }
Joerg Roedel431b2a22008-07-11 17:14:22 +02001139
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001140 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001141}
1142
Joerg Roedel0688a092017-08-23 15:50:03 +02001143static void amd_iommu_flush_all(struct amd_iommu *iommu)
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001144{
1145 struct iommu_cmd cmd;
1146
1147 build_inv_all(&cmd);
1148
1149 iommu_queue_command(iommu, &cmd);
1150 iommu_completion_wait(iommu);
1151}
1152
Joerg Roedel7ef27982012-06-21 16:46:04 +02001153static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1154{
1155 struct iommu_cmd cmd;
1156
1157 build_inv_irt(&cmd, devid);
1158
1159 iommu_queue_command(iommu, &cmd);
1160}
1161
Joerg Roedel0688a092017-08-23 15:50:03 +02001162static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
Joerg Roedel7ef27982012-06-21 16:46:04 +02001163{
1164 u32 devid;
1165
1166 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1167 iommu_flush_irt(iommu, devid);
1168
1169 iommu_completion_wait(iommu);
1170}
1171
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001172void iommu_flush_all_caches(struct amd_iommu *iommu)
1173{
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001174 if (iommu_feature(iommu, FEATURE_IA)) {
Joerg Roedel0688a092017-08-23 15:50:03 +02001175 amd_iommu_flush_all(iommu);
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001176 } else {
Joerg Roedel0688a092017-08-23 15:50:03 +02001177 amd_iommu_flush_dte_all(iommu);
1178 amd_iommu_flush_irt_all(iommu);
1179 amd_iommu_flush_tlb_all(iommu);
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001180 }
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001181}
1182
Joerg Roedel431b2a22008-07-11 17:14:22 +02001183/*
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001184 * Command send function for flushing on-device TLB
1185 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001186static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1187 u64 address, size_t size)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001188{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001189 struct amd_iommu *iommu;
1190 struct iommu_cmd cmd;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001191 int qdep;
1192
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001193 qdep = dev_data->ats.qdep;
1194 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001195
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001196 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001197
1198 return iommu_queue_command(iommu, &cmd);
1199}
1200
1201/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001202 * Command send function for invalidating a device table entry
1203 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001204static int device_flush_dte(struct iommu_dev_data *dev_data)
Joerg Roedel3fa43652009-11-26 15:04:38 +01001205{
1206 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02001207 u16 alias;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001208 int ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001209
Joerg Roedel6c542042011-06-09 17:07:31 +02001210 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02001211 alias = dev_data->alias;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001212
Joerg Roedelf62dda62011-06-09 12:55:35 +02001213 ret = iommu_flush_dte(iommu, dev_data->devid);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001214 if (!ret && alias != dev_data->devid)
1215 ret = iommu_flush_dte(iommu, alias);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001216 if (ret)
1217 return ret;
1218
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001219 if (dev_data->ats.enabled)
Joerg Roedel6c542042011-06-09 17:07:31 +02001220 ret = device_flush_iotlb(dev_data, 0, ~0UL);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001221
1222 return ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001223}
1224
Joerg Roedel431b2a22008-07-11 17:14:22 +02001225/*
1226 * TLB invalidation function which is called from the mapping functions.
1227 * It invalidates a single PTE if the range to flush is within a single
1228 * page. Otherwise it flushes the whole TLB of the IOMMU.
1229 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001230static void __domain_flush_pages(struct protection_domain *domain,
1231 u64 address, size_t size, int pde)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001232{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001233 struct iommu_dev_data *dev_data;
Joerg Roedel11b64022011-04-06 11:49:28 +02001234 struct iommu_cmd cmd;
1235 int ret = 0, i;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001236
Joerg Roedel11b64022011-04-06 11:49:28 +02001237 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
Joerg Roedel999ba412008-07-03 19:35:08 +02001238
Suravee Suthikulpanit6b9376e2017-02-24 02:48:17 -06001239 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001240 if (!domain->dev_iommu[i])
1241 continue;
1242
1243 /*
1244 * Devices of this domain are behind this IOMMU
1245 * We need a TLB flush
1246 */
Joerg Roedel11b64022011-04-06 11:49:28 +02001247 ret |= iommu_queue_command(amd_iommus[i], &cmd);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001248 }
1249
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001250 list_for_each_entry(dev_data, &domain->dev_list, list) {
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001251
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001252 if (!dev_data->ats.enabled)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001253 continue;
1254
Joerg Roedel6c542042011-06-09 17:07:31 +02001255 ret |= device_flush_iotlb(dev_data, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001256 }
1257
Joerg Roedel11b64022011-04-06 11:49:28 +02001258 WARN_ON(ret);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001259}
1260
Joerg Roedel17b124b2011-04-06 18:01:35 +02001261static void domain_flush_pages(struct protection_domain *domain,
1262 u64 address, size_t size)
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001263{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001264 __domain_flush_pages(domain, address, size, 0);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001265}
Joerg Roedelb6c02712008-06-26 21:27:53 +02001266
Joerg Roedel1c655772008-09-04 18:40:05 +02001267/* Flush the whole IO/TLB for a given protection domain */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001268static void domain_flush_tlb(struct protection_domain *domain)
Joerg Roedel1c655772008-09-04 18:40:05 +02001269{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001270 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001271}
1272
Chris Wright42a49f92009-06-15 15:42:00 +02001273/* Flush the whole IO/TLB for a given protection domain - including PDE */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001274static void domain_flush_tlb_pde(struct protection_domain *domain)
Chris Wright42a49f92009-06-15 15:42:00 +02001275{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001276 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1277}
1278
1279static void domain_flush_complete(struct protection_domain *domain)
Joerg Roedelb6c02712008-06-26 21:27:53 +02001280{
1281 int i;
1282
Suravee Suthikulpanit6b9376e2017-02-24 02:48:17 -06001283 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
Joerg Roedelf1eae7c2016-07-06 12:50:35 +02001284 if (domain && !domain->dev_iommu[i])
Joerg Roedelb6c02712008-06-26 21:27:53 +02001285 continue;
1286
1287 /*
1288 * Devices of this domain are behind this IOMMU
1289 * We need to wait for completion of all commands.
1290 */
1291 iommu_completion_wait(amd_iommus[i]);
1292 }
1293}
1294
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001295
Joerg Roedel43f49602008-12-02 21:01:12 +01001296/*
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001297 * This function flushes the DTEs for all devices in domain
Joerg Roedel43f49602008-12-02 21:01:12 +01001298 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001299static void domain_flush_devices(struct protection_domain *domain)
Joerg Roedelbfd1be12009-05-05 15:33:57 +02001300{
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001301 struct iommu_dev_data *dev_data;
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001302
1303 list_for_each_entry(dev_data, &domain->dev_list, list)
Joerg Roedel6c542042011-06-09 17:07:31 +02001304 device_flush_dte(dev_data);
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001305}
1306
Joerg Roedel431b2a22008-07-11 17:14:22 +02001307/****************************************************************************
1308 *
1309 * The functions below are used the create the page table mappings for
1310 * unity mapped regions.
1311 *
1312 ****************************************************************************/
1313
1314/*
Joerg Roedel308973d2009-11-24 17:43:32 +01001315 * This function is used to add another level to an IO page table. Adding
1316 * another level increases the size of the address space by 9 bits to a size up
1317 * to 64 bits.
1318 */
1319static bool increase_address_space(struct protection_domain *domain,
1320 gfp_t gfp)
1321{
1322 u64 *pte;
1323
1324 if (domain->mode == PAGE_MODE_6_LEVEL)
1325 /* address space already 64 bit large */
1326 return false;
1327
1328 pte = (void *)get_zeroed_page(gfp);
1329 if (!pte)
1330 return false;
1331
1332 *pte = PM_LEVEL_PDE(domain->mode,
Tom Lendacky2543a782017-07-17 16:10:24 -05001333 iommu_virt_to_phys(domain->pt_root));
Joerg Roedel308973d2009-11-24 17:43:32 +01001334 domain->pt_root = pte;
1335 domain->mode += 1;
1336 domain->updated = true;
1337
1338 return true;
1339}
1340
1341static u64 *alloc_pte(struct protection_domain *domain,
1342 unsigned long address,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001343 unsigned long page_size,
Joerg Roedel308973d2009-11-24 17:43:32 +01001344 u64 **pte_page,
1345 gfp_t gfp)
1346{
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001347 int level, end_lvl;
Joerg Roedel308973d2009-11-24 17:43:32 +01001348 u64 *pte, *page;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001349
1350 BUG_ON(!is_power_of_2(page_size));
Joerg Roedel308973d2009-11-24 17:43:32 +01001351
1352 while (address > PM_LEVEL_SIZE(domain->mode))
1353 increase_address_space(domain, gfp);
1354
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001355 level = domain->mode - 1;
1356 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1357 address = PAGE_SIZE_ALIGN(address, page_size);
1358 end_lvl = PAGE_SIZE_LEVEL(page_size);
Joerg Roedel308973d2009-11-24 17:43:32 +01001359
1360 while (level > end_lvl) {
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001361 u64 __pte, __npte;
1362
1363 __pte = *pte;
1364
1365 if (!IOMMU_PTE_PRESENT(__pte)) {
Joerg Roedel308973d2009-11-24 17:43:32 +01001366 page = (u64 *)get_zeroed_page(gfp);
1367 if (!page)
1368 return NULL;
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001369
Tom Lendacky2543a782017-07-17 16:10:24 -05001370 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001371
Baoquan He134414f2016-09-15 16:50:50 +08001372 /* pte could have been changed somewhere. */
1373 if (cmpxchg64(pte, __pte, __npte) != __pte) {
Joerg Roedel7bfa5bd2015-12-21 19:07:50 +01001374 free_page((unsigned long)page);
1375 continue;
1376 }
Joerg Roedel308973d2009-11-24 17:43:32 +01001377 }
1378
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001379 /* No level skipping support yet */
1380 if (PM_PTE_LEVEL(*pte) != level)
1381 return NULL;
1382
Joerg Roedel308973d2009-11-24 17:43:32 +01001383 level -= 1;
1384
1385 pte = IOMMU_PTE_PAGE(*pte);
1386
1387 if (pte_page && level == end_lvl)
1388 *pte_page = pte;
1389
1390 pte = &pte[PM_LEVEL_INDEX(level, address)];
1391 }
1392
1393 return pte;
1394}
1395
1396/*
1397 * This function checks if there is a PTE for a given dma address. If
1398 * there is one, it returns the pointer to it.
1399 */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001400static u64 *fetch_pte(struct protection_domain *domain,
1401 unsigned long address,
1402 unsigned long *page_size)
Joerg Roedel308973d2009-11-24 17:43:32 +01001403{
1404 int level;
1405 u64 *pte;
1406
Joerg Roedel24cd7722010-01-19 17:27:39 +01001407 if (address > PM_LEVEL_SIZE(domain->mode))
1408 return NULL;
Joerg Roedel308973d2009-11-24 17:43:32 +01001409
Joerg Roedel3039ca12015-04-01 14:58:48 +02001410 level = domain->mode - 1;
1411 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1412 *page_size = PTE_LEVEL_PAGE_SIZE(level);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001413
1414 while (level > 0) {
1415
1416 /* Not Present */
Joerg Roedel308973d2009-11-24 17:43:32 +01001417 if (!IOMMU_PTE_PRESENT(*pte))
1418 return NULL;
1419
Joerg Roedel24cd7722010-01-19 17:27:39 +01001420 /* Large PTE */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001421 if (PM_PTE_LEVEL(*pte) == 7 ||
1422 PM_PTE_LEVEL(*pte) == 0)
1423 break;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001424
1425 /* No level skipping support yet */
1426 if (PM_PTE_LEVEL(*pte) != level)
1427 return NULL;
1428
Joerg Roedel308973d2009-11-24 17:43:32 +01001429 level -= 1;
1430
Joerg Roedel24cd7722010-01-19 17:27:39 +01001431 /* Walk to the next level */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001432 pte = IOMMU_PTE_PAGE(*pte);
1433 pte = &pte[PM_LEVEL_INDEX(level, address)];
1434 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1435 }
1436
1437 if (PM_PTE_LEVEL(*pte) == 0x07) {
1438 unsigned long pte_mask;
1439
1440 /*
1441 * If we have a series of large PTEs, make
1442 * sure to return a pointer to the first one.
1443 */
1444 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1445 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1446 pte = (u64 *)(((unsigned long)pte) & pte_mask);
Joerg Roedel308973d2009-11-24 17:43:32 +01001447 }
1448
1449 return pte;
1450}
1451
1452/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001453 * Generic mapping functions. It maps a physical address into a DMA
1454 * address space. It allocates the page table pages if necessary.
1455 * In the future it can be extended to a generic mapping function
1456 * supporting all features of AMD IOMMU page tables like level skipping
1457 * and full 64 bit address spaces.
1458 */
Joerg Roedel38e817f2008-12-02 17:27:52 +01001459static int iommu_map_page(struct protection_domain *dom,
1460 unsigned long bus_addr,
1461 unsigned long phys_addr,
Joerg Roedelb911b892016-07-05 14:29:11 +02001462 unsigned long page_size,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001463 int prot,
Joerg Roedelb911b892016-07-05 14:29:11 +02001464 gfp_t gfp)
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001465{
Joerg Roedel8bda3092009-05-12 12:02:46 +02001466 u64 __pte, *pte;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001467 int i, count;
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001468
Joerg Roedeld4b03662015-04-01 14:58:52 +02001469 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1470 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1471
Joerg Roedelbad1cac2009-09-02 16:52:23 +02001472 if (!(prot & IOMMU_PROT_MASK))
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001473 return -EINVAL;
1474
Joerg Roedeld4b03662015-04-01 14:58:52 +02001475 count = PAGE_SIZE_PTE_COUNT(page_size);
Joerg Roedelb911b892016-07-05 14:29:11 +02001476 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001477
Maurizio Lombardi63eaa752014-09-11 12:28:03 +02001478 if (!pte)
1479 return -ENOMEM;
1480
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001481 for (i = 0; i < count; ++i)
1482 if (IOMMU_PTE_PRESENT(pte[i]))
1483 return -EBUSY;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001484
Joerg Roedeld4b03662015-04-01 14:58:52 +02001485 if (count > 1) {
Tom Lendacky2543a782017-07-17 16:10:24 -05001486 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
Baoquan He07a80a62017-08-09 16:33:36 +08001487 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001488 } else
Linus Torvalds4dfc2782017-09-09 15:03:24 -07001489 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001490
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001491 if (prot & IOMMU_PROT_IR)
1492 __pte |= IOMMU_PTE_IR;
1493 if (prot & IOMMU_PROT_IW)
1494 __pte |= IOMMU_PTE_IW;
1495
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001496 for (i = 0; i < count; ++i)
1497 pte[i] = __pte;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001498
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001499 update_domain(dom);
1500
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001501 return 0;
1502}
1503
Joerg Roedel24cd7722010-01-19 17:27:39 +01001504static unsigned long iommu_unmap_page(struct protection_domain *dom,
1505 unsigned long bus_addr,
1506 unsigned long page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001507{
Joerg Roedel71b390e2015-04-01 14:58:49 +02001508 unsigned long long unmapped;
1509 unsigned long unmap_size;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001510 u64 *pte;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001511
Joerg Roedel24cd7722010-01-19 17:27:39 +01001512 BUG_ON(!is_power_of_2(page_size));
1513
1514 unmapped = 0;
1515
1516 while (unmapped < page_size) {
1517
Joerg Roedel71b390e2015-04-01 14:58:49 +02001518 pte = fetch_pte(dom, bus_addr, &unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001519
Joerg Roedel71b390e2015-04-01 14:58:49 +02001520 if (pte) {
1521 int i, count;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001522
Joerg Roedel71b390e2015-04-01 14:58:49 +02001523 count = PAGE_SIZE_PTE_COUNT(unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001524 for (i = 0; i < count; i++)
1525 pte[i] = 0ULL;
1526 }
1527
1528 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1529 unmapped += unmap_size;
1530 }
1531
Alex Williamson60d0ca32013-06-21 14:33:19 -06001532 BUG_ON(unmapped && !is_power_of_2(unmapped));
Joerg Roedel24cd7722010-01-19 17:27:39 +01001533
1534 return unmapped;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001535}
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001536
Joerg Roedel431b2a22008-07-11 17:14:22 +02001537/****************************************************************************
1538 *
1539 * The next functions belong to the address allocator for the dma_ops
Joerg Roedel2d4c5152016-07-05 16:21:32 +02001540 * interface functions.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001541 *
1542 ****************************************************************************/
Joerg Roedeld3086442008-06-26 21:27:57 +02001543
Joerg Roedel9cabe892009-05-18 16:38:55 +02001544
Joerg Roedel256e4622016-07-05 14:23:01 +02001545static unsigned long dma_ops_alloc_iova(struct device *dev,
1546 struct dma_ops_domain *dma_dom,
1547 unsigned int pages, u64 dma_mask)
Joerg Roedela0f51442015-12-21 16:20:09 +01001548{
Joerg Roedel256e4622016-07-05 14:23:01 +02001549 unsigned long pfn = 0;
Joerg Roedela0f51442015-12-21 16:20:09 +01001550
Joerg Roedel256e4622016-07-05 14:23:01 +02001551 pages = __roundup_pow_of_two(pages);
Joerg Roedela0f51442015-12-21 16:20:09 +01001552
Joerg Roedel256e4622016-07-05 14:23:01 +02001553 if (dma_mask > DMA_BIT_MASK(32))
1554 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
Tomasz Nowicki538d5b32017-09-20 10:52:02 +02001555 IOVA_PFN(DMA_BIT_MASK(32)), false);
Joerg Roedel7b5e25b2015-12-22 13:38:12 +01001556
Joerg Roedel256e4622016-07-05 14:23:01 +02001557 if (!pfn)
Tomasz Nowicki538d5b32017-09-20 10:52:02 +02001558 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1559 IOVA_PFN(dma_mask), true);
Joerg Roedel60e6a7c2015-12-21 16:53:17 +01001560
Joerg Roedel256e4622016-07-05 14:23:01 +02001561 return (pfn << PAGE_SHIFT);
Joerg Roedela0f51442015-12-21 16:20:09 +01001562}
1563
Joerg Roedel256e4622016-07-05 14:23:01 +02001564static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1565 unsigned long address,
1566 unsigned int pages)
Joerg Roedel384de722009-05-15 12:30:05 +02001567{
Joerg Roedel256e4622016-07-05 14:23:01 +02001568 pages = __roundup_pow_of_two(pages);
1569 address >>= PAGE_SHIFT;
Joerg Roedel5f6bed52015-12-22 13:34:22 +01001570
Joerg Roedel256e4622016-07-05 14:23:01 +02001571 free_iova_fast(&dma_dom->iovad, address, pages);
Joerg Roedeld3086442008-06-26 21:27:57 +02001572}
1573
Joerg Roedel431b2a22008-07-11 17:14:22 +02001574/****************************************************************************
1575 *
1576 * The next functions belong to the domain allocation. A domain is
1577 * allocated for every IOMMU as the default domain. If device isolation
1578 * is enabled, every device get its own domain. The most important thing
1579 * about domains is the page table mapping the DMA address space they
1580 * contain.
1581 *
1582 ****************************************************************************/
1583
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001584/*
1585 * This function adds a protection domain to the global protection domain list
1586 */
1587static void add_domain_to_list(struct protection_domain *domain)
1588{
1589 unsigned long flags;
1590
1591 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1592 list_add(&domain->list, &amd_iommu_pd_list);
1593 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1594}
1595
1596/*
1597 * This function removes a protection domain to the global
1598 * protection domain list
1599 */
1600static void del_domain_from_list(struct protection_domain *domain)
1601{
1602 unsigned long flags;
1603
1604 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1605 list_del(&domain->list);
1606 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1607}
1608
Joerg Roedelec487d12008-06-26 21:27:58 +02001609static u16 domain_id_alloc(void)
1610{
Joerg Roedelec487d12008-06-26 21:27:58 +02001611 int id;
1612
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001613 spin_lock(&pd_bitmap_lock);
Joerg Roedelec487d12008-06-26 21:27:58 +02001614 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1615 BUG_ON(id == 0);
1616 if (id > 0 && id < MAX_DOMAIN_ID)
1617 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1618 else
1619 id = 0;
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001620 spin_unlock(&pd_bitmap_lock);
Joerg Roedelec487d12008-06-26 21:27:58 +02001621
1622 return id;
1623}
1624
Joerg Roedela2acfb72008-12-02 18:28:53 +01001625static void domain_id_free(int id)
1626{
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001627 spin_lock(&pd_bitmap_lock);
Joerg Roedela2acfb72008-12-02 18:28:53 +01001628 if (id > 0 && id < MAX_DOMAIN_ID)
1629 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
Sebastian Andrzej Siewior2bc00182018-03-22 16:22:35 +01001630 spin_unlock(&pd_bitmap_lock);
Joerg Roedela2acfb72008-12-02 18:28:53 +01001631}
Joerg Roedela2acfb72008-12-02 18:28:53 +01001632
Joerg Roedel5c34c402013-06-20 20:22:58 +02001633#define DEFINE_FREE_PT_FN(LVL, FN) \
1634static void free_pt_##LVL (unsigned long __pt) \
1635{ \
1636 unsigned long p; \
1637 u64 *pt; \
1638 int i; \
1639 \
1640 pt = (u64 *)__pt; \
1641 \
1642 for (i = 0; i < 512; ++i) { \
Joerg Roedel0b3fff52015-06-18 10:48:34 +02001643 /* PTE present? */ \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001644 if (!IOMMU_PTE_PRESENT(pt[i])) \
1645 continue; \
1646 \
Joerg Roedel0b3fff52015-06-18 10:48:34 +02001647 /* Large PTE? */ \
1648 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1649 PM_PTE_LEVEL(pt[i]) == 7) \
1650 continue; \
1651 \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001652 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1653 FN(p); \
1654 } \
1655 free_page((unsigned long)pt); \
1656}
1657
1658DEFINE_FREE_PT_FN(l2, free_page)
1659DEFINE_FREE_PT_FN(l3, free_pt_l2)
1660DEFINE_FREE_PT_FN(l4, free_pt_l3)
1661DEFINE_FREE_PT_FN(l5, free_pt_l4)
1662DEFINE_FREE_PT_FN(l6, free_pt_l5)
1663
Joerg Roedel86db2e52008-12-02 18:20:21 +01001664static void free_pagetable(struct protection_domain *domain)
Joerg Roedelec487d12008-06-26 21:27:58 +02001665{
Joerg Roedel5c34c402013-06-20 20:22:58 +02001666 unsigned long root = (unsigned long)domain->pt_root;
Joerg Roedelec487d12008-06-26 21:27:58 +02001667
Joerg Roedel5c34c402013-06-20 20:22:58 +02001668 switch (domain->mode) {
1669 case PAGE_MODE_NONE:
1670 break;
1671 case PAGE_MODE_1_LEVEL:
1672 free_page(root);
1673 break;
1674 case PAGE_MODE_2_LEVEL:
1675 free_pt_l2(root);
1676 break;
1677 case PAGE_MODE_3_LEVEL:
1678 free_pt_l3(root);
1679 break;
1680 case PAGE_MODE_4_LEVEL:
1681 free_pt_l4(root);
1682 break;
1683 case PAGE_MODE_5_LEVEL:
1684 free_pt_l5(root);
1685 break;
1686 case PAGE_MODE_6_LEVEL:
1687 free_pt_l6(root);
1688 break;
1689 default:
1690 BUG();
Joerg Roedelec487d12008-06-26 21:27:58 +02001691 }
Joerg Roedelec487d12008-06-26 21:27:58 +02001692}
1693
Joerg Roedelb16137b2011-11-21 16:50:23 +01001694static void free_gcr3_tbl_level1(u64 *tbl)
1695{
1696 u64 *ptr;
1697 int i;
1698
1699 for (i = 0; i < 512; ++i) {
1700 if (!(tbl[i] & GCR3_VALID))
1701 continue;
1702
Tom Lendacky2543a782017-07-17 16:10:24 -05001703 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001704
1705 free_page((unsigned long)ptr);
1706 }
1707}
1708
1709static void free_gcr3_tbl_level2(u64 *tbl)
1710{
1711 u64 *ptr;
1712 int i;
1713
1714 for (i = 0; i < 512; ++i) {
1715 if (!(tbl[i] & GCR3_VALID))
1716 continue;
1717
Tom Lendacky2543a782017-07-17 16:10:24 -05001718 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001719
1720 free_gcr3_tbl_level1(ptr);
1721 }
1722}
1723
Joerg Roedel52815b72011-11-17 17:24:28 +01001724static void free_gcr3_table(struct protection_domain *domain)
1725{
Joerg Roedelb16137b2011-11-21 16:50:23 +01001726 if (domain->glx == 2)
1727 free_gcr3_tbl_level2(domain->gcr3_tbl);
1728 else if (domain->glx == 1)
1729 free_gcr3_tbl_level1(domain->gcr3_tbl);
Joerg Roedel23d3a982015-08-13 11:15:13 +02001730 else
1731 BUG_ON(domain->glx != 0);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001732
Joerg Roedel52815b72011-11-17 17:24:28 +01001733 free_page((unsigned long)domain->gcr3_tbl);
1734}
1735
Joerg Roedelfca6af62017-06-02 18:13:37 +02001736static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1737{
Joerg Roedelfca6af62017-06-02 18:13:37 +02001738 domain_flush_tlb(&dom->domain);
1739 domain_flush_complete(&dom->domain);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001740}
1741
Joerg Roedel9003d612017-08-10 17:19:13 +02001742static void iova_domain_flush_tlb(struct iova_domain *iovad)
Joerg Roedelfd621902017-06-02 15:37:26 +02001743{
Joerg Roedel9003d612017-08-10 17:19:13 +02001744 struct dma_ops_domain *dom;
Joerg Roedele241f8e762017-06-02 15:44:57 +02001745
Joerg Roedel9003d612017-08-10 17:19:13 +02001746 dom = container_of(iovad, struct dma_ops_domain, iovad);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001747
1748 dma_ops_domain_flush_tlb(dom);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001749}
1750
Joerg Roedel431b2a22008-07-11 17:14:22 +02001751/*
1752 * Free a domain, only used if something went wrong in the
1753 * allocation path and we need to free an already allocated page table
1754 */
Joerg Roedelec487d12008-06-26 21:27:58 +02001755static void dma_ops_domain_free(struct dma_ops_domain *dom)
1756{
1757 if (!dom)
1758 return;
1759
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001760 del_domain_from_list(&dom->domain);
1761
Joerg Roedel2d4c5152016-07-05 16:21:32 +02001762 put_iova_domain(&dom->iovad);
1763
Joerg Roedel86db2e52008-12-02 18:20:21 +01001764 free_pagetable(&dom->domain);
Joerg Roedelec487d12008-06-26 21:27:58 +02001765
Baoquan Hec3db9012016-09-15 16:50:52 +08001766 if (dom->domain.id)
1767 domain_id_free(dom->domain.id);
1768
Joerg Roedelec487d12008-06-26 21:27:58 +02001769 kfree(dom);
1770}
1771
Joerg Roedel431b2a22008-07-11 17:14:22 +02001772/*
1773 * Allocates a new protection domain usable for the dma_ops functions.
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001774 * It also initializes the page table and the address allocator data
Joerg Roedel431b2a22008-07-11 17:14:22 +02001775 * structures required for the dma_ops interface
1776 */
Joerg Roedel87a64d52009-11-24 17:26:43 +01001777static struct dma_ops_domain *dma_ops_domain_alloc(void)
Joerg Roedelec487d12008-06-26 21:27:58 +02001778{
1779 struct dma_ops_domain *dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001780
1781 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1782 if (!dma_dom)
1783 return NULL;
1784
Joerg Roedel7a5a5662015-06-30 08:56:11 +02001785 if (protection_domain_init(&dma_dom->domain))
Joerg Roedelec487d12008-06-26 21:27:58 +02001786 goto free_dma_dom;
Joerg Roedel7a5a5662015-06-30 08:56:11 +02001787
Joerg Roedelffec2192016-07-26 15:31:23 +02001788 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
Joerg Roedelec487d12008-06-26 21:27:58 +02001789 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
Joerg Roedel9fdb19d2008-12-02 17:46:25 +01001790 dma_dom->domain.flags = PD_DMA_OPS_MASK;
Joerg Roedelec487d12008-06-26 21:27:58 +02001791 if (!dma_dom->domain.pt_root)
1792 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001793
Zhen Leiaa3ac942017-09-21 16:52:45 +01001794 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
Joerg Roedel307d5852016-07-05 11:54:04 +02001795
Joerg Roedel9003d612017-08-10 17:19:13 +02001796 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
Joerg Roedeld4241a22017-06-02 14:55:56 +02001797 goto free_dma_dom;
1798
Joerg Roedel9003d612017-08-10 17:19:13 +02001799 /* Initialize reserved ranges */
1800 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
Joerg Roedelfca6af62017-06-02 18:13:37 +02001801
Joerg Roedel2d4c5152016-07-05 16:21:32 +02001802 add_domain_to_list(&dma_dom->domain);
1803
Joerg Roedelec487d12008-06-26 21:27:58 +02001804 return dma_dom;
1805
1806free_dma_dom:
1807 dma_ops_domain_free(dma_dom);
1808
1809 return NULL;
1810}
1811
Joerg Roedel431b2a22008-07-11 17:14:22 +02001812/*
Joerg Roedel5b28df62008-12-02 17:49:42 +01001813 * little helper function to check whether a given protection domain is a
1814 * dma_ops domain
1815 */
1816static bool dma_ops_domain(struct protection_domain *domain)
1817{
1818 return domain->flags & PD_DMA_OPS_MASK;
1819}
1820
Gary R Hookff18c4e2017-12-20 09:47:08 -07001821static void set_dte_entry(u16 devid, struct protection_domain *domain,
1822 bool ats, bool ppr)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001823{
Joerg Roedel132bd682011-11-17 14:18:46 +01001824 u64 pte_root = 0;
Joerg Roedelee6c2862011-11-09 12:06:03 +01001825 u64 flags = 0;
Joerg Roedel863c74e2008-12-02 17:56:36 +01001826
Joerg Roedel132bd682011-11-17 14:18:46 +01001827 if (domain->mode != PAGE_MODE_NONE)
Tom Lendacky2543a782017-07-17 16:10:24 -05001828 pte_root = iommu_virt_to_phys(domain->pt_root);
Joerg Roedel132bd682011-11-17 14:18:46 +01001829
Joerg Roedel38ddf412008-09-11 10:38:32 +02001830 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1831 << DEV_ENTRY_MODE_SHIFT;
Baoquan He07a80a62017-08-09 16:33:36 +08001832 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001833
Joerg Roedelee6c2862011-11-09 12:06:03 +01001834 flags = amd_iommu_dev_table[devid].data[1];
1835
Joerg Roedelfd7b5532011-04-05 15:31:08 +02001836 if (ats)
1837 flags |= DTE_FLAG_IOTLB;
1838
Gary R Hookff18c4e2017-12-20 09:47:08 -07001839 if (ppr) {
1840 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1841
1842 if (iommu_feature(iommu, FEATURE_EPHSUP))
1843 pte_root |= 1ULL << DEV_ENTRY_PPR;
1844 }
1845
Joerg Roedel52815b72011-11-17 17:24:28 +01001846 if (domain->flags & PD_IOMMUV2_MASK) {
Tom Lendacky2543a782017-07-17 16:10:24 -05001847 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
Joerg Roedel52815b72011-11-17 17:24:28 +01001848 u64 glx = domain->glx;
1849 u64 tmp;
1850
1851 pte_root |= DTE_FLAG_GV;
1852 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1853
1854 /* First mask out possible old values for GCR3 table */
1855 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1856 flags &= ~tmp;
1857
1858 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1859 flags &= ~tmp;
1860
1861 /* Encode GCR3 table into DTE */
1862 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1863 pte_root |= tmp;
1864
1865 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1866 flags |= tmp;
1867
1868 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1869 flags |= tmp;
1870 }
1871
Baoquan He45a01c42017-08-09 16:33:37 +08001872 flags &= ~DEV_DOMID_MASK;
Joerg Roedelee6c2862011-11-09 12:06:03 +01001873 flags |= domain->id;
1874
1875 amd_iommu_dev_table[devid].data[1] = flags;
1876 amd_iommu_dev_table[devid].data[0] = pte_root;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001877}
1878
Joerg Roedel15898bb2009-11-24 15:39:42 +01001879static void clear_dte_entry(u16 devid)
Joerg Roedel355bf552008-12-08 12:02:41 +01001880{
Joerg Roedel355bf552008-12-08 12:02:41 +01001881 /* remove entry from the device table seen by the hardware */
Baoquan He07a80a62017-08-09 16:33:36 +08001882 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
Joerg Roedelcbf3ccd2015-10-20 14:59:36 +02001883 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
Joerg Roedel355bf552008-12-08 12:02:41 +01001884
Joerg Roedelc5cca142009-10-09 18:31:20 +02001885 amd_iommu_apply_erratum_63(devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001886}
1887
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001888static void do_attach(struct iommu_dev_data *dev_data,
1889 struct protection_domain *domain)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001890{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001891 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02001892 u16 alias;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001893 bool ats;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001894
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001895 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02001896 alias = dev_data->alias;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001897 ats = dev_data->ats.enabled;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001898
1899 /* Update data structures */
1900 dev_data->domain = domain;
1901 list_add(&dev_data->list, &domain->dev_list);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001902
1903 /* Do reference counting */
1904 domain->dev_iommu[iommu->index] += 1;
1905 domain->dev_cnt += 1;
1906
Joerg Roedele25bfb52015-10-20 17:33:38 +02001907 /* Update device table */
Gary R Hookff18c4e2017-12-20 09:47:08 -07001908 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001909 if (alias != dev_data->devid)
Gary R Hookff18c4e2017-12-20 09:47:08 -07001910 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001911
Joerg Roedel6c542042011-06-09 17:07:31 +02001912 device_flush_dte(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001913}
1914
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001915static void do_detach(struct iommu_dev_data *dev_data)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001916{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001917 struct amd_iommu *iommu;
Joerg Roedele25bfb52015-10-20 17:33:38 +02001918 u16 alias;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001919
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001920 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedele3156042016-04-08 15:12:24 +02001921 alias = dev_data->alias;
Joerg Roedelc5cca142009-10-09 18:31:20 +02001922
Joerg Roedelc4596112009-11-20 14:57:32 +01001923 /* decrease reference counters */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001924 dev_data->domain->dev_iommu[iommu->index] -= 1;
1925 dev_data->domain->dev_cnt -= 1;
Joerg Roedel355bf552008-12-08 12:02:41 +01001926
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001927 /* Update data structures */
1928 dev_data->domain = NULL;
1929 list_del(&dev_data->list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02001930 clear_dte_entry(dev_data->devid);
Joerg Roedele25bfb52015-10-20 17:33:38 +02001931 if (alias != dev_data->devid)
1932 clear_dte_entry(alias);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001933
1934 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02001935 device_flush_dte(dev_data);
Joerg Roedel15898bb2009-11-24 15:39:42 +01001936}
1937
1938/*
Anna-Maria Gleixner29a0c412018-05-07 14:53:26 +02001939 * If a device is not yet associated with a domain, this function makes the
1940 * device visible in the domain
Joerg Roedel15898bb2009-11-24 15:39:42 +01001941 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001942static int __attach_device(struct iommu_dev_data *dev_data,
Joerg Roedel15898bb2009-11-24 15:39:42 +01001943 struct protection_domain *domain)
1944{
Julia Lawall84fe6c12010-05-27 12:31:51 +02001945 int ret;
Joerg Roedel657cbb62009-11-23 15:26:46 +01001946
Joerg Roedel272e4f92015-10-20 17:33:37 +02001947 /*
1948 * Must be called with IRQs disabled. Warn here to detect early
1949 * when its not.
1950 */
1951 WARN_ON(!irqs_disabled());
1952
Joerg Roedel15898bb2009-11-24 15:39:42 +01001953 /* lock domain */
1954 spin_lock(&domain->lock);
1955
Joerg Roedel397111a2014-08-05 17:31:51 +02001956 ret = -EBUSY;
Joerg Roedel150952f2015-10-20 17:33:35 +02001957 if (dev_data->domain != NULL)
Joerg Roedel397111a2014-08-05 17:31:51 +02001958 goto out_unlock;
Joerg Roedel24100052009-11-25 15:59:57 +01001959
Joerg Roedel397111a2014-08-05 17:31:51 +02001960 /* Attach alias group root */
Joerg Roedel150952f2015-10-20 17:33:35 +02001961 do_attach(dev_data, domain);
Joerg Roedel24100052009-11-25 15:59:57 +01001962
Julia Lawall84fe6c12010-05-27 12:31:51 +02001963 ret = 0;
1964
1965out_unlock:
1966
Joerg Roedel355bf552008-12-08 12:02:41 +01001967 /* ready */
1968 spin_unlock(&domain->lock);
Joerg Roedel21129f72009-09-01 11:59:42 +02001969
Julia Lawall84fe6c12010-05-27 12:31:51 +02001970 return ret;
Joerg Roedel15898bb2009-11-24 15:39:42 +01001971}
1972
Joerg Roedel52815b72011-11-17 17:24:28 +01001973
1974static void pdev_iommuv2_disable(struct pci_dev *pdev)
1975{
1976 pci_disable_ats(pdev);
1977 pci_disable_pri(pdev);
1978 pci_disable_pasid(pdev);
1979}
1980
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001981/* FIXME: Change generic reset-function to do the same */
1982static int pri_reset_while_enabled(struct pci_dev *pdev)
1983{
1984 u16 control;
1985 int pos;
1986
Joerg Roedel46277b72011-12-07 14:34:02 +01001987 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001988 if (!pos)
1989 return -EINVAL;
1990
Joerg Roedel46277b72011-12-07 14:34:02 +01001991 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1992 control |= PCI_PRI_CTRL_RESET;
1993 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01001994
1995 return 0;
1996}
1997
Joerg Roedel52815b72011-11-17 17:24:28 +01001998static int pdev_iommuv2_enable(struct pci_dev *pdev)
1999{
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002000 bool reset_enable;
2001 int reqs, ret;
2002
2003 /* FIXME: Hardcode number of outstanding requests for now */
2004 reqs = 32;
2005 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2006 reqs = 1;
2007 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
Joerg Roedel52815b72011-11-17 17:24:28 +01002008
2009 /* Only allow access to user-accessible pages */
2010 ret = pci_enable_pasid(pdev, 0);
2011 if (ret)
2012 goto out_err;
2013
2014 /* First reset the PRI state of the device */
2015 ret = pci_reset_pri(pdev);
2016 if (ret)
2017 goto out_err;
2018
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002019 /* Enable PRI */
2020 ret = pci_enable_pri(pdev, reqs);
Joerg Roedel52815b72011-11-17 17:24:28 +01002021 if (ret)
2022 goto out_err;
2023
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002024 if (reset_enable) {
2025 ret = pri_reset_while_enabled(pdev);
2026 if (ret)
2027 goto out_err;
2028 }
2029
Joerg Roedel52815b72011-11-17 17:24:28 +01002030 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2031 if (ret)
2032 goto out_err;
2033
2034 return 0;
2035
2036out_err:
2037 pci_disable_pri(pdev);
2038 pci_disable_pasid(pdev);
2039
2040 return ret;
2041}
2042
Joerg Roedelc99afa22011-11-21 18:19:25 +01002043/* FIXME: Move this to PCI code */
Joerg Roedela3b93122012-04-12 12:49:26 +02002044#define PCI_PRI_TLP_OFF (1 << 15)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002045
Joerg Roedel98f1ad22012-07-06 13:28:37 +02002046static bool pci_pri_tlp_required(struct pci_dev *pdev)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002047{
Joerg Roedela3b93122012-04-12 12:49:26 +02002048 u16 status;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002049 int pos;
2050
Joerg Roedel46277b72011-12-07 14:34:02 +01002051 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002052 if (!pos)
2053 return false;
2054
Joerg Roedela3b93122012-04-12 12:49:26 +02002055 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002056
Joerg Roedela3b93122012-04-12 12:49:26 +02002057 return (status & PCI_PRI_TLP_OFF) ? true : false;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002058}
2059
Joerg Roedel15898bb2009-11-24 15:39:42 +01002060/*
Anna-Maria Gleixner29a0c412018-05-07 14:53:26 +02002061 * If a device is not yet associated with a domain, this function makes the
2062 * device visible in the domain
Joerg Roedel15898bb2009-11-24 15:39:42 +01002063 */
2064static int attach_device(struct device *dev,
2065 struct protection_domain *domain)
2066{
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002067 struct pci_dev *pdev;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002068 struct iommu_dev_data *dev_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002069 unsigned long flags;
2070 int ret;
2071
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002072 dev_data = get_dev_data(dev);
2073
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002074 if (!dev_is_pci(dev))
2075 goto skip_ats_check;
2076
2077 pdev = to_pci_dev(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002078 if (domain->flags & PD_IOMMUV2_MASK) {
Joerg Roedel02ca2022015-07-28 16:58:49 +02002079 if (!dev_data->passthrough)
Joerg Roedel52815b72011-11-17 17:24:28 +01002080 return -EINVAL;
2081
Joerg Roedel02ca2022015-07-28 16:58:49 +02002082 if (dev_data->iommu_v2) {
2083 if (pdev_iommuv2_enable(pdev) != 0)
2084 return -EINVAL;
Joerg Roedel52815b72011-11-17 17:24:28 +01002085
Joerg Roedel02ca2022015-07-28 16:58:49 +02002086 dev_data->ats.enabled = true;
2087 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2088 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2089 }
Joerg Roedel52815b72011-11-17 17:24:28 +01002090 } else if (amd_iommu_iotlb_sup &&
2091 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002092 dev_data->ats.enabled = true;
2093 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2094 }
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002095
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002096skip_ats_check:
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002097 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002098 ret = __attach_device(dev_data, domain);
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002099 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002100
2101 /*
2102 * We might boot into a crash-kernel here. The crashed kernel
2103 * left the caches in the IOMMU dirty. So we have to flush
2104 * here to evict all dirty stuff.
2105 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02002106 domain_flush_tlb_pde(domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002107
2108 return ret;
2109}
2110
2111/*
2112 * Removes a device from a protection domain (unlocked)
2113 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002114static void __detach_device(struct iommu_dev_data *dev_data)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002115{
Joerg Roedel2ca76272010-01-22 16:45:31 +01002116 struct protection_domain *domain;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002117
Joerg Roedel272e4f92015-10-20 17:33:37 +02002118 /*
2119 * Must be called with IRQs disabled. Warn here to detect early
2120 * when its not.
2121 */
2122 WARN_ON(!irqs_disabled());
2123
Joerg Roedel2ca76272010-01-22 16:45:31 +01002124 domain = dev_data->domain;
2125
Joerg Roedelf1dd0a82015-10-20 17:33:36 +02002126 spin_lock(&domain->lock);
Joerg Roedel24100052009-11-25 15:59:57 +01002127
Joerg Roedel150952f2015-10-20 17:33:35 +02002128 do_detach(dev_data);
Joerg Roedel71f77582011-06-09 19:03:15 +02002129
Joerg Roedelf1dd0a82015-10-20 17:33:36 +02002130 spin_unlock(&domain->lock);
Joerg Roedel355bf552008-12-08 12:02:41 +01002131}
2132
2133/*
2134 * Removes a device from a protection domain (with devtable_lock held)
2135 */
Joerg Roedel15898bb2009-11-24 15:39:42 +01002136static void detach_device(struct device *dev)
Joerg Roedel355bf552008-12-08 12:02:41 +01002137{
Joerg Roedel52815b72011-11-17 17:24:28 +01002138 struct protection_domain *domain;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002139 struct iommu_dev_data *dev_data;
Joerg Roedel355bf552008-12-08 12:02:41 +01002140 unsigned long flags;
2141
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002142 dev_data = get_dev_data(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002143 domain = dev_data->domain;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002144
Anna-Maria Gleixnerea3fd042018-05-07 14:53:27 +02002145 /*
2146 * First check if the device is still attached. It might already
2147 * be detached from its domain because the generic
2148 * iommu_detach_group code detached it and we try again here in
2149 * our alias handling.
2150 */
2151 if (WARN_ON(!dev_data->domain))
2152 return;
2153
Joerg Roedel355bf552008-12-08 12:02:41 +01002154 /* lock device table */
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002155 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002156 __detach_device(dev_data);
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002157 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002158
Wan Zongshun2bf9a0a2016-04-01 09:06:03 -04002159 if (!dev_is_pci(dev))
2160 return;
2161
Joerg Roedel02ca2022015-07-28 16:58:49 +02002162 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
Joerg Roedel52815b72011-11-17 17:24:28 +01002163 pdev_iommuv2_disable(to_pci_dev(dev));
2164 else if (dev_data->ats.enabled)
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002165 pci_disable_ats(to_pci_dev(dev));
Joerg Roedel52815b72011-11-17 17:24:28 +01002166
2167 dev_data->ats.enabled = false;
Joerg Roedel355bf552008-12-08 12:02:41 +01002168}
Joerg Roedele275a2a2008-12-10 18:27:25 +01002169
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002170static int amd_iommu_add_device(struct device *dev)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002171{
Joerg Roedel71f77582011-06-09 19:03:15 +02002172 struct iommu_dev_data *dev_data;
Joerg Roedel07ee8692015-05-28 18:41:42 +02002173 struct iommu_domain *domain;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002174 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002175 int ret, devid;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002176
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002177 if (!check_device(dev) || get_dev_data(dev))
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002178 return 0;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002179
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002180 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002181 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002182 return devid;
2183
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002184 iommu = amd_iommu_rlookup_table[devid];
Joerg Roedele275a2a2008-12-10 18:27:25 +01002185
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002186 ret = iommu_init_device(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002187 if (ret) {
2188 if (ret != -ENOTSUPP)
2189 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2190 dev_name(dev));
Joerg Roedel657cbb62009-11-23 15:26:46 +01002191
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002192 iommu_ignore_device(dev);
Christoph Hellwigfec777c2018-03-19 11:38:15 +01002193 dev->dma_ops = &dma_direct_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002194 goto out;
2195 }
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002196 init_iommu_group(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002197
Joerg Roedel07ee8692015-05-28 18:41:42 +02002198 dev_data = get_dev_data(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002199
2200 BUG_ON(!dev_data);
2201
Joerg Roedel1e6a7b02015-07-28 16:58:48 +02002202 if (iommu_pass_through || dev_data->iommu_v2)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002203 iommu_request_dm_for_dev(dev);
2204
2205 /* Domains are initialized for this device - have a look what we ended up with */
2206 domain = iommu_get_domain_for_dev(dev);
Joerg Roedel32302322015-07-28 16:58:50 +02002207 if (domain->type == IOMMU_DOMAIN_IDENTITY)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002208 dev_data->passthrough = true;
Joerg Roedel32302322015-07-28 16:58:50 +02002209 else
Bart Van Assche56579332017-01-20 13:04:02 -08002210 dev->dma_ops = &amd_iommu_dma_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002211
2212out:
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002213 iommu_completion_wait(iommu);
2214
Joerg Roedele275a2a2008-12-10 18:27:25 +01002215 return 0;
2216}
2217
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002218static void amd_iommu_remove_device(struct device *dev)
Joerg Roedel8638c492009-12-10 11:12:25 +01002219{
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002220 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002221 int devid;
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002222
2223 if (!check_device(dev))
2224 return;
2225
2226 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002227 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002228 return;
2229
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002230 iommu = amd_iommu_rlookup_table[devid];
2231
2232 iommu_uninit_device(dev);
2233 iommu_completion_wait(iommu);
Joerg Roedel8638c492009-12-10 11:12:25 +01002234}
2235
Wan Zongshunb097d112016-04-01 09:06:04 -04002236static struct iommu_group *amd_iommu_device_group(struct device *dev)
2237{
2238 if (dev_is_pci(dev))
2239 return pci_device_group(dev);
2240
2241 return acpihid_device_group(dev);
2242}
2243
Joerg Roedel431b2a22008-07-11 17:14:22 +02002244/*****************************************************************************
2245 *
2246 * The next functions belong to the dma_ops mapping/unmapping code.
2247 *
2248 *****************************************************************************/
2249
2250/*
2251 * In the dma_ops path we only have the struct device. This function
2252 * finds the corresponding IOMMU, the protection domain and the
2253 * requestor id for a given device.
2254 * If the device is not yet associated with a domain this is also done
2255 * in this function.
2256 */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002257static struct protection_domain *get_domain(struct device *dev)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002258{
Joerg Roedel94f6d192009-11-24 16:40:02 +01002259 struct protection_domain *domain;
Baoquan Hedf3f7a62017-08-09 16:33:41 +08002260 struct iommu_domain *io_domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002261
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002262 if (!check_device(dev))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002263 return ERR_PTR(-EINVAL);
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002264
Joerg Roedeld26592a2016-07-07 15:31:13 +02002265 domain = get_dev_data(dev)->domain;
Baoquan Hedf3f7a62017-08-09 16:33:41 +08002266 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2267 get_dev_data(dev)->defer_attach = false;
2268 io_domain = iommu_get_domain_for_dev(dev);
2269 domain = to_pdomain(io_domain);
2270 attach_device(dev, domain);
2271 }
Baoquan Heec62b1a2017-08-24 21:13:57 +08002272 if (domain == NULL)
2273 return ERR_PTR(-EBUSY);
2274
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002275 if (!dma_ops_domain(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002276 return ERR_PTR(-EBUSY);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002277
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002278 return domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002279}
2280
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002281static void update_device_table(struct protection_domain *domain)
2282{
Joerg Roedel492667d2009-11-27 13:25:47 +01002283 struct iommu_dev_data *dev_data;
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002284
Joerg Roedel3254de62016-07-26 15:18:54 +02002285 list_for_each_entry(dev_data, &domain->dev_list, list) {
Gary R Hookff18c4e2017-12-20 09:47:08 -07002286 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2287 dev_data->iommu_v2);
Joerg Roedel3254de62016-07-26 15:18:54 +02002288
2289 if (dev_data->devid == dev_data->alias)
2290 continue;
2291
2292 /* There is an alias, update device table entry for it */
Gary R Hookff18c4e2017-12-20 09:47:08 -07002293 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2294 dev_data->iommu_v2);
Joerg Roedel3254de62016-07-26 15:18:54 +02002295 }
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002296}
2297
2298static void update_domain(struct protection_domain *domain)
2299{
2300 if (!domain->updated)
2301 return;
2302
2303 update_device_table(domain);
Joerg Roedel17b124b2011-04-06 18:01:35 +02002304
2305 domain_flush_devices(domain);
2306 domain_flush_tlb_pde(domain);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002307
2308 domain->updated = false;
2309}
2310
Joerg Roedelf37f7f32016-07-08 11:47:22 +02002311static int dir2prot(enum dma_data_direction direction)
2312{
2313 if (direction == DMA_TO_DEVICE)
2314 return IOMMU_PROT_IR;
2315 else if (direction == DMA_FROM_DEVICE)
2316 return IOMMU_PROT_IW;
2317 else if (direction == DMA_BIDIRECTIONAL)
2318 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2319 else
2320 return 0;
2321}
Baoquan Hedaae2d22017-08-09 16:33:43 +08002322
Joerg Roedel431b2a22008-07-11 17:14:22 +02002323/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002324 * This function contains common code for mapping of a physically
Joerg Roedel24f81162008-12-08 14:25:39 +01002325 * contiguous memory region into DMA address space. It is used by all
2326 * mapping functions provided with this IOMMU driver.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002327 * Must be called with the domain lock held.
2328 */
Joerg Roedelcb76c322008-06-26 21:28:00 +02002329static dma_addr_t __map_single(struct device *dev,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002330 struct dma_ops_domain *dma_dom,
2331 phys_addr_t paddr,
2332 size_t size,
Joerg Roedelf37f7f32016-07-08 11:47:22 +02002333 enum dma_data_direction direction,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002334 u64 dma_mask)
Joerg Roedelcb76c322008-06-26 21:28:00 +02002335{
2336 dma_addr_t offset = paddr & ~PAGE_MASK;
Joerg Roedel53812c12009-05-12 12:17:38 +02002337 dma_addr_t address, start, ret;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002338 unsigned int pages;
Joerg Roedel518d9b42016-07-05 14:39:47 +02002339 int prot = 0;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002340 int i;
2341
Joerg Roedele3c449f2008-10-15 22:02:11 -07002342 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002343 paddr &= PAGE_MASK;
2344
Joerg Roedel256e4622016-07-05 14:23:01 +02002345 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
Christoph Hellwiga8695722017-05-21 13:26:45 +02002346 if (address == AMD_IOMMU_MAPPING_ERROR)
Joerg Roedel266a3bd2015-12-21 18:54:24 +01002347 goto out;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002348
Joerg Roedelf37f7f32016-07-08 11:47:22 +02002349 prot = dir2prot(direction);
Joerg Roedel518d9b42016-07-05 14:39:47 +02002350
Joerg Roedelcb76c322008-06-26 21:28:00 +02002351 start = address;
2352 for (i = 0; i < pages; ++i) {
Joerg Roedel518d9b42016-07-05 14:39:47 +02002353 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2354 PAGE_SIZE, prot, GFP_ATOMIC);
2355 if (ret)
Joerg Roedel53812c12009-05-12 12:17:38 +02002356 goto out_unmap;
2357
Joerg Roedelcb76c322008-06-26 21:28:00 +02002358 paddr += PAGE_SIZE;
2359 start += PAGE_SIZE;
2360 }
2361 address += offset;
2362
Joerg Roedelab7032b2015-12-21 18:47:11 +01002363 if (unlikely(amd_iommu_np_cache)) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002364 domain_flush_pages(&dma_dom->domain, address, size);
Joerg Roedelab7032b2015-12-21 18:47:11 +01002365 domain_flush_complete(&dma_dom->domain);
2366 }
Joerg Roedel270cab242008-09-04 15:49:46 +02002367
Joerg Roedelcb76c322008-06-26 21:28:00 +02002368out:
2369 return address;
Joerg Roedel53812c12009-05-12 12:17:38 +02002370
2371out_unmap:
2372
2373 for (--i; i >= 0; --i) {
2374 start -= PAGE_SIZE;
Joerg Roedel518d9b42016-07-05 14:39:47 +02002375 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
Joerg Roedel53812c12009-05-12 12:17:38 +02002376 }
2377
Joerg Roedel256e4622016-07-05 14:23:01 +02002378 domain_flush_tlb(&dma_dom->domain);
2379 domain_flush_complete(&dma_dom->domain);
2380
2381 dma_ops_free_iova(dma_dom, address, pages);
Joerg Roedel53812c12009-05-12 12:17:38 +02002382
Christoph Hellwiga8695722017-05-21 13:26:45 +02002383 return AMD_IOMMU_MAPPING_ERROR;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002384}
2385
Joerg Roedel431b2a22008-07-11 17:14:22 +02002386/*
2387 * Does the reverse of the __map_single function. Must be called with
2388 * the domain lock held too
2389 */
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002390static void __unmap_single(struct dma_ops_domain *dma_dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002391 dma_addr_t dma_addr,
2392 size_t size,
2393 int dir)
2394{
2395 dma_addr_t i, start;
2396 unsigned int pages;
2397
Joerg Roedele3c449f2008-10-15 22:02:11 -07002398 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002399 dma_addr &= PAGE_MASK;
2400 start = dma_addr;
2401
2402 for (i = 0; i < pages; ++i) {
Joerg Roedel518d9b42016-07-05 14:39:47 +02002403 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002404 start += PAGE_SIZE;
2405 }
2406
Joerg Roedelb1516a12016-07-06 13:07:22 +02002407 if (amd_iommu_unmap_flush) {
2408 dma_ops_free_iova(dma_dom, dma_addr, pages);
2409 domain_flush_tlb(&dma_dom->domain);
2410 domain_flush_complete(&dma_dom->domain);
2411 } else {
Joerg Roedel9003d612017-08-10 17:19:13 +02002412 pages = __roundup_pow_of_two(pages);
2413 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
Joerg Roedelb1516a12016-07-06 13:07:22 +02002414 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002415}
2416
Joerg Roedel431b2a22008-07-11 17:14:22 +02002417/*
2418 * The exported map_single function for dma_ops.
2419 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002420static dma_addr_t map_page(struct device *dev, struct page *page,
2421 unsigned long offset, size_t size,
2422 enum dma_data_direction dir,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002423 unsigned long attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002424{
FUJITA Tomonori51491362009-01-05 23:47:25 +09002425 phys_addr_t paddr = page_to_phys(page) + offset;
Joerg Roedel92d420e2015-12-21 19:31:33 +01002426 struct protection_domain *domain;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002427 struct dma_ops_domain *dma_dom;
Joerg Roedel92d420e2015-12-21 19:31:33 +01002428 u64 dma_mask;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002429
Joerg Roedel94f6d192009-11-24 16:40:02 +01002430 domain = get_domain(dev);
2431 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002432 return (dma_addr_t)paddr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002433 else if (IS_ERR(domain))
Christoph Hellwiga8695722017-05-21 13:26:45 +02002434 return AMD_IOMMU_MAPPING_ERROR;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002435
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002436 dma_mask = *dev->dma_mask;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002437 dma_dom = to_dma_ops_domain(domain);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002438
Joerg Roedelb3311b02016-07-08 13:31:31 +02002439 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002440}
2441
Joerg Roedel431b2a22008-07-11 17:14:22 +02002442/*
2443 * The exported unmap_single function for dma_ops.
2444 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002445static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002446 enum dma_data_direction dir, unsigned long attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002447{
Joerg Roedel4da70b92008-06-26 21:28:01 +02002448 struct protection_domain *domain;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002449 struct dma_ops_domain *dma_dom;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002450
Joerg Roedel94f6d192009-11-24 16:40:02 +01002451 domain = get_domain(dev);
2452 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002453 return;
2454
Joerg Roedelb3311b02016-07-08 13:31:31 +02002455 dma_dom = to_dma_ops_domain(domain);
2456
2457 __unmap_single(dma_dom, dma_addr, size, dir);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002458}
2459
Joerg Roedel80187fd2016-07-06 17:20:54 +02002460static int sg_num_pages(struct device *dev,
2461 struct scatterlist *sglist,
2462 int nelems)
2463{
2464 unsigned long mask, boundary_size;
2465 struct scatterlist *s;
2466 int i, npages = 0;
2467
2468 mask = dma_get_seg_boundary(dev);
2469 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2470 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2471
2472 for_each_sg(sglist, s, nelems, i) {
2473 int p, n;
2474
2475 s->dma_address = npages << PAGE_SHIFT;
2476 p = npages % boundary_size;
2477 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2478 if (p + n > boundary_size)
2479 npages += boundary_size - p;
2480 npages += n;
2481 }
2482
2483 return npages;
2484}
2485
Joerg Roedel431b2a22008-07-11 17:14:22 +02002486/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002487 * The exported map_sg function for dma_ops (handles scatter-gather
2488 * lists).
2489 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002490static int map_sg(struct device *dev, struct scatterlist *sglist,
Joerg Roedel80187fd2016-07-06 17:20:54 +02002491 int nelems, enum dma_data_direction direction,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002492 unsigned long attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002493{
Joerg Roedel80187fd2016-07-06 17:20:54 +02002494 int mapped_pages = 0, npages = 0, prot = 0, i;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002495 struct protection_domain *domain;
Joerg Roedel80187fd2016-07-06 17:20:54 +02002496 struct dma_ops_domain *dma_dom;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002497 struct scatterlist *s;
Joerg Roedel80187fd2016-07-06 17:20:54 +02002498 unsigned long address;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002499 u64 dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002500
Joerg Roedel94f6d192009-11-24 16:40:02 +01002501 domain = get_domain(dev);
Joerg Roedela0e191b2013-04-09 15:04:36 +02002502 if (IS_ERR(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002503 return 0;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002504
Joerg Roedelb3311b02016-07-08 13:31:31 +02002505 dma_dom = to_dma_ops_domain(domain);
Joerg Roedel832a90c2008-09-18 15:54:23 +02002506 dma_mask = *dev->dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002507
Joerg Roedel80187fd2016-07-06 17:20:54 +02002508 npages = sg_num_pages(dev, sglist, nelems);
2509
2510 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
Christoph Hellwiga8695722017-05-21 13:26:45 +02002511 if (address == AMD_IOMMU_MAPPING_ERROR)
Joerg Roedel80187fd2016-07-06 17:20:54 +02002512 goto out_err;
2513
2514 prot = dir2prot(direction);
2515
2516 /* Map all sg entries */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002517 for_each_sg(sglist, s, nelems, i) {
Joerg Roedel80187fd2016-07-06 17:20:54 +02002518 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002519
Joerg Roedel80187fd2016-07-06 17:20:54 +02002520 for (j = 0; j < pages; ++j) {
2521 unsigned long bus_addr, phys_addr;
2522 int ret;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002523
Joerg Roedel80187fd2016-07-06 17:20:54 +02002524 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2525 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2526 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2527 if (ret)
2528 goto out_unmap;
2529
2530 mapped_pages += 1;
2531 }
Joerg Roedel65b050a2008-06-26 21:28:02 +02002532 }
2533
Joerg Roedel80187fd2016-07-06 17:20:54 +02002534 /* Everything is mapped - write the right values into s->dma_address */
2535 for_each_sg(sglist, s, nelems, i) {
2536 s->dma_address += address + s->offset;
2537 s->dma_length = s->length;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002538 }
2539
Joerg Roedel80187fd2016-07-06 17:20:54 +02002540 return nelems;
2541
2542out_unmap:
2543 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2544 dev_name(dev), npages);
2545
2546 for_each_sg(sglist, s, nelems, i) {
2547 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2548
2549 for (j = 0; j < pages; ++j) {
2550 unsigned long bus_addr;
2551
2552 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2553 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2554
2555 if (--mapped_pages)
2556 goto out_free_iova;
2557 }
2558 }
2559
2560out_free_iova:
2561 free_iova_fast(&dma_dom->iovad, address, npages);
2562
2563out_err:
Joerg Roedel92d420e2015-12-21 19:31:33 +01002564 return 0;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002565}
2566
Joerg Roedel431b2a22008-07-11 17:14:22 +02002567/*
2568 * The exported map_sg function for dma_ops (handles scatter-gather
2569 * lists).
2570 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002571static void unmap_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002572 int nelems, enum dma_data_direction dir,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002573 unsigned long attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002574{
Joerg Roedel65b050a2008-06-26 21:28:02 +02002575 struct protection_domain *domain;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002576 struct dma_ops_domain *dma_dom;
Joerg Roedel80187fd2016-07-06 17:20:54 +02002577 unsigned long startaddr;
2578 int npages = 2;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002579
Joerg Roedel94f6d192009-11-24 16:40:02 +01002580 domain = get_domain(dev);
2581 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002582 return;
2583
Joerg Roedel80187fd2016-07-06 17:20:54 +02002584 startaddr = sg_dma_address(sglist) & PAGE_MASK;
Joerg Roedelb3311b02016-07-08 13:31:31 +02002585 dma_dom = to_dma_ops_domain(domain);
Joerg Roedel80187fd2016-07-06 17:20:54 +02002586 npages = sg_num_pages(dev, sglist, nelems);
2587
Joerg Roedelb3311b02016-07-08 13:31:31 +02002588 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002589}
2590
Joerg Roedel431b2a22008-07-11 17:14:22 +02002591/*
2592 * The exported alloc_coherent function for dma_ops.
2593 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002594static void *alloc_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002595 dma_addr_t *dma_addr, gfp_t flag,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002596 unsigned long attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002597{
Joerg Roedel832a90c2008-09-18 15:54:23 +02002598 u64 dma_mask = dev->coherent_dma_mask;
Linus Torvaldse16c4792018-06-11 12:22:12 -07002599 struct protection_domain *domain;
2600 struct dma_ops_domain *dma_dom;
2601 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002602
Linus Torvaldse16c4792018-06-11 12:22:12 -07002603 domain = get_domain(dev);
2604 if (PTR_ERR(domain) == -EINVAL) {
2605 page = alloc_pages(flag, get_order(size));
2606 *dma_addr = page_to_phys(page);
2607 return page_address(page);
2608 } else if (IS_ERR(domain))
2609 return NULL;
2610
2611 dma_dom = to_dma_ops_domain(domain);
2612 size = PAGE_ALIGN(size);
2613 dma_mask = dev->coherent_dma_mask;
2614 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2615 flag |= __GFP_ZERO;
2616
2617 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2618 if (!page) {
2619 if (!gfpflags_allow_blocking(flag))
Joerg Roedel3b839a52015-04-01 14:58:47 +02002620 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002621
Linus Torvaldse16c4792018-06-11 12:22:12 -07002622 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2623 get_order(size), flag);
2624 if (!page)
2625 return NULL;
2626 }
Christoph Hellwigb4686202018-03-19 11:38:19 +01002627
Joerg Roedel832a90c2008-09-18 15:54:23 +02002628 if (!dma_mask)
2629 dma_mask = *dev->dma_mask;
2630
Linus Torvaldse16c4792018-06-11 12:22:12 -07002631 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2632 size, DMA_BIDIRECTIONAL, dma_mask);
2633
Christoph Hellwiga8695722017-05-21 13:26:45 +02002634 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
Joerg Roedel5b28df62008-12-02 17:49:42 +01002635 goto out_free;
Linus Torvaldse16c4792018-06-11 12:22:12 -07002636
2637 return page_address(page);
Joerg Roedel5b28df62008-12-02 17:49:42 +01002638
2639out_free:
Linus Torvaldse16c4792018-06-11 12:22:12 -07002640
2641 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2642 __free_pages(page, get_order(size));
2643
Joerg Roedel5b28df62008-12-02 17:49:42 +01002644 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002645}
2646
Joerg Roedel431b2a22008-07-11 17:14:22 +02002647/*
2648 * The exported free_coherent function for dma_ops.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002649 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002650static void free_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002651 void *virt_addr, dma_addr_t dma_addr,
Krzysztof Kozlowski00085f12016-08-03 13:46:00 -07002652 unsigned long attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002653{
Linus Torvaldse16c4792018-06-11 12:22:12 -07002654 struct protection_domain *domain;
2655 struct dma_ops_domain *dma_dom;
2656 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002657
Linus Torvaldse16c4792018-06-11 12:22:12 -07002658 page = virt_to_page(virt_addr);
Joerg Roedel3b839a52015-04-01 14:58:47 +02002659 size = PAGE_ALIGN(size);
2660
Linus Torvaldse16c4792018-06-11 12:22:12 -07002661 domain = get_domain(dev);
2662 if (IS_ERR(domain))
2663 goto free_mem;
Joerg Roedel5b28df62008-12-02 17:49:42 +01002664
Linus Torvaldse16c4792018-06-11 12:22:12 -07002665 dma_dom = to_dma_ops_domain(domain);
Joerg Roedelb3311b02016-07-08 13:31:31 +02002666
Linus Torvaldse16c4792018-06-11 12:22:12 -07002667 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2668
2669free_mem:
2670 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2671 __free_pages(page, get_order(size));
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002672}
2673
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002674/*
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002675 * This function is called by the DMA layer to find out if we can handle a
2676 * particular device. It is part of the dma_ops.
2677 */
2678static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2679{
Christoph Hellwigfec777c2018-03-19 11:38:15 +01002680 if (!dma_direct_supported(dev, mask))
Christoph Hellwig5860acc2017-05-22 11:38:27 +02002681 return 0;
Joerg Roedel420aef82009-11-23 16:14:57 +01002682 return check_device(dev);
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002683}
2684
Christoph Hellwiga8695722017-05-21 13:26:45 +02002685static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2686{
2687 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2688}
2689
Bart Van Assche52997092017-01-20 13:04:01 -08002690static const struct dma_map_ops amd_iommu_dma_ops = {
Joerg Roedela639a8e2015-12-22 16:06:49 +01002691 .alloc = alloc_coherent,
2692 .free = free_coherent,
2693 .map_page = map_page,
2694 .unmap_page = unmap_page,
2695 .map_sg = map_sg,
2696 .unmap_sg = unmap_sg,
2697 .dma_supported = amd_iommu_dma_supported,
Christoph Hellwiga8695722017-05-21 13:26:45 +02002698 .mapping_error = amd_iommu_mapping_error,
Joerg Roedel6631ee92008-06-26 21:28:05 +02002699};
2700
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002701static int init_reserved_iova_ranges(void)
2702{
2703 struct pci_dev *pdev = NULL;
2704 struct iova *val;
2705
Zhen Leiaa3ac942017-09-21 16:52:45 +01002706 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002707
2708 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2709 &reserved_rbtree_key);
2710
2711 /* MSI memory range */
2712 val = reserve_iova(&reserved_iova_ranges,
2713 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2714 if (!val) {
2715 pr_err("Reserving MSI range failed\n");
2716 return -ENOMEM;
2717 }
2718
2719 /* HT memory range */
2720 val = reserve_iova(&reserved_iova_ranges,
2721 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2722 if (!val) {
2723 pr_err("Reserving HT range failed\n");
2724 return -ENOMEM;
2725 }
2726
2727 /*
2728 * Memory used for PCI resources
2729 * FIXME: Check whether we can reserve the PCI-hole completly
2730 */
2731 for_each_pci_dev(pdev) {
2732 int i;
2733
2734 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2735 struct resource *r = &pdev->resource[i];
2736
2737 if (!(r->flags & IORESOURCE_MEM))
2738 continue;
2739
2740 val = reserve_iova(&reserved_iova_ranges,
2741 IOVA_PFN(r->start),
2742 IOVA_PFN(r->end));
2743 if (!val) {
2744 pr_err("Reserve pci-resource range failed\n");
2745 return -ENOMEM;
2746 }
2747 }
2748 }
2749
2750 return 0;
2751}
2752
Joerg Roedel3a18404c2015-05-28 18:41:45 +02002753int __init amd_iommu_init_api(void)
Joerg Roedel27c21272011-05-30 15:56:24 +02002754{
Joerg Roedel460c26d2017-06-02 14:28:01 +02002755 int ret, err = 0;
Joerg Roedel307d5852016-07-05 11:54:04 +02002756
2757 ret = iova_cache_get();
2758 if (ret)
2759 return ret;
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04002760
Joerg Roedel81cd07b2016-07-07 18:01:10 +02002761 ret = init_reserved_iova_ranges();
2762 if (ret)
2763 return ret;
2764
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04002765 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2766 if (err)
2767 return err;
2768#ifdef CONFIG_ARM_AMBA
2769 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2770 if (err)
2771 return err;
2772#endif
Wan Zongshun0076cd32016-05-10 09:21:01 -04002773 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2774 if (err)
2775 return err;
Joerg Roedel460c26d2017-06-02 14:28:01 +02002776
Wan Zongshun9a4d3bf52016-04-01 09:06:05 -04002777 return 0;
Joerg Roedelf5325092010-01-22 17:44:35 +01002778}
2779
Joerg Roedel6631ee92008-06-26 21:28:05 +02002780int __init amd_iommu_init_dma_ops(void)
2781{
Tom Lendackyaba2d9a2017-10-06 16:35:40 -05002782 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002783 iommu_detected = 1;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002784
Joerg Roedel52717822015-07-28 16:58:51 +02002785 /*
2786 * In case we don't initialize SWIOTLB (actually the common case
Tom Lendackyaba2d9a2017-10-06 16:35:40 -05002787 * when AMD IOMMU is enabled and SME is not active), make sure there
2788 * are global dma_ops set as a fall-back for devices not handled by
2789 * this driver (for example non-PCI devices). When SME is active,
2790 * make sure that swiotlb variable remains set so the global dma_ops
2791 * continue to be SWIOTLB.
Joerg Roedel52717822015-07-28 16:58:51 +02002792 */
2793 if (!swiotlb)
Christoph Hellwigfec777c2018-03-19 11:38:15 +01002794 dma_ops = &dma_direct_ops;
Joerg Roedel52717822015-07-28 16:58:51 +02002795
Joerg Roedel62410ee2012-06-12 16:42:43 +02002796 if (amd_iommu_unmap_flush)
2797 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2798 else
2799 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2800
Joerg Roedel6631ee92008-06-26 21:28:05 +02002801 return 0;
Joerg Roedelc5b5da92016-07-06 11:55:37 +02002802
Joerg Roedel6631ee92008-06-26 21:28:05 +02002803}
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002804
2805/*****************************************************************************
2806 *
2807 * The following functions belong to the exported interface of AMD IOMMU
2808 *
2809 * This interface allows access to lower level functions of the IOMMU
2810 * like protection domain handling and assignement of devices to domains
2811 * which is not possible with the dma_ops interface.
2812 *
2813 *****************************************************************************/
2814
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002815static void cleanup_domain(struct protection_domain *domain)
2816{
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002817 struct iommu_dev_data *entry;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002818 unsigned long flags;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002819
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002820 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002821
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002822 while (!list_empty(&domain->dev_list)) {
2823 entry = list_first_entry(&domain->dev_list,
2824 struct iommu_dev_data, list);
Anna-Maria Gleixnerea3fd042018-05-07 14:53:27 +02002825 BUG_ON(!entry->domain);
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002826 __detach_device(entry);
Joerg Roedel492667d2009-11-27 13:25:47 +01002827 }
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002828
Sebastian Andrzej Siewior2cd10832018-03-22 16:22:41 +01002829 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002830}
2831
Joerg Roedel26508152009-08-26 16:52:40 +02002832static void protection_domain_free(struct protection_domain *domain)
2833{
2834 if (!domain)
2835 return;
2836
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002837 del_domain_from_list(domain);
2838
Joerg Roedel26508152009-08-26 16:52:40 +02002839 if (domain->id)
2840 domain_id_free(domain->id);
2841
2842 kfree(domain);
2843}
2844
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002845static int protection_domain_init(struct protection_domain *domain)
2846{
2847 spin_lock_init(&domain->lock);
2848 mutex_init(&domain->api_lock);
2849 domain->id = domain_id_alloc();
2850 if (!domain->id)
2851 return -ENOMEM;
2852 INIT_LIST_HEAD(&domain->dev_list);
2853
2854 return 0;
2855}
2856
Joerg Roedel26508152009-08-26 16:52:40 +02002857static struct protection_domain *protection_domain_alloc(void)
Joerg Roedelc156e342008-12-02 18:13:27 +01002858{
2859 struct protection_domain *domain;
2860
2861 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2862 if (!domain)
Joerg Roedel26508152009-08-26 16:52:40 +02002863 return NULL;
Joerg Roedelc156e342008-12-02 18:13:27 +01002864
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002865 if (protection_domain_init(domain))
Joerg Roedel26508152009-08-26 16:52:40 +02002866 goto out_err;
2867
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002868 add_domain_to_list(domain);
2869
Joerg Roedel26508152009-08-26 16:52:40 +02002870 return domain;
2871
2872out_err:
2873 kfree(domain);
2874
2875 return NULL;
2876}
2877
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002878static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2879{
2880 struct protection_domain *pdomain;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002881 struct dma_ops_domain *dma_domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002882
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002883 switch (type) {
2884 case IOMMU_DOMAIN_UNMANAGED:
2885 pdomain = protection_domain_alloc();
2886 if (!pdomain)
2887 return NULL;
2888
2889 pdomain->mode = PAGE_MODE_3_LEVEL;
2890 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2891 if (!pdomain->pt_root) {
2892 protection_domain_free(pdomain);
2893 return NULL;
2894 }
2895
2896 pdomain->domain.geometry.aperture_start = 0;
2897 pdomain->domain.geometry.aperture_end = ~0ULL;
2898 pdomain->domain.geometry.force_aperture = true;
2899
2900 break;
2901 case IOMMU_DOMAIN_DMA:
2902 dma_domain = dma_ops_domain_alloc();
2903 if (!dma_domain) {
2904 pr_err("AMD-Vi: Failed to allocate\n");
2905 return NULL;
2906 }
2907 pdomain = &dma_domain->domain;
2908 break;
Joerg Roedel07f643a2015-05-28 18:41:41 +02002909 case IOMMU_DOMAIN_IDENTITY:
2910 pdomain = protection_domain_alloc();
2911 if (!pdomain)
2912 return NULL;
2913
2914 pdomain->mode = PAGE_MODE_NONE;
2915 break;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002916 default:
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002917 return NULL;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002918 }
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002919
2920 return &pdomain->domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002921}
2922
2923static void amd_iommu_domain_free(struct iommu_domain *dom)
Joerg Roedel26508152009-08-26 16:52:40 +02002924{
2925 struct protection_domain *domain;
Joerg Roedelcda70052016-07-07 15:57:04 +02002926 struct dma_ops_domain *dma_dom;
Joerg Roedel98383fc2008-12-02 18:34:12 +01002927
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002928 domain = to_pdomain(dom);
2929
Joerg Roedel98383fc2008-12-02 18:34:12 +01002930 if (domain->dev_cnt > 0)
2931 cleanup_domain(domain);
2932
2933 BUG_ON(domain->dev_cnt != 0);
2934
Joerg Roedelcda70052016-07-07 15:57:04 +02002935 if (!dom)
2936 return;
Joerg Roedel98383fc2008-12-02 18:34:12 +01002937
Joerg Roedelcda70052016-07-07 15:57:04 +02002938 switch (dom->type) {
2939 case IOMMU_DOMAIN_DMA:
Joerg Roedel281e8cc2016-07-07 16:12:02 +02002940 /* Now release the domain */
Joerg Roedelb3311b02016-07-08 13:31:31 +02002941 dma_dom = to_dma_ops_domain(domain);
Joerg Roedelcda70052016-07-07 15:57:04 +02002942 dma_ops_domain_free(dma_dom);
2943 break;
2944 default:
2945 if (domain->mode != PAGE_MODE_NONE)
2946 free_pagetable(domain);
Joerg Roedel52815b72011-11-17 17:24:28 +01002947
Joerg Roedelcda70052016-07-07 15:57:04 +02002948 if (domain->flags & PD_IOMMUV2_MASK)
2949 free_gcr3_table(domain);
2950
2951 protection_domain_free(domain);
2952 break;
2953 }
Joerg Roedel98383fc2008-12-02 18:34:12 +01002954}
2955
Joerg Roedel684f2882008-12-08 12:07:44 +01002956static void amd_iommu_detach_device(struct iommu_domain *dom,
2957 struct device *dev)
2958{
Joerg Roedel657cbb62009-11-23 15:26:46 +01002959 struct iommu_dev_data *dev_data = dev->archdata.iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01002960 struct amd_iommu *iommu;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002961 int devid;
Joerg Roedel684f2882008-12-08 12:07:44 +01002962
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002963 if (!check_device(dev))
Joerg Roedel684f2882008-12-08 12:07:44 +01002964 return;
2965
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002966 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02002967 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04002968 return;
Joerg Roedel684f2882008-12-08 12:07:44 +01002969
Joerg Roedel657cbb62009-11-23 15:26:46 +01002970 if (dev_data->domain != NULL)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002971 detach_device(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01002972
2973 iommu = amd_iommu_rlookup_table[devid];
2974 if (!iommu)
2975 return;
2976
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05002977#ifdef CONFIG_IRQ_REMAP
2978 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2979 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2980 dev_data->use_vapic = 0;
2981#endif
2982
Joerg Roedel684f2882008-12-08 12:07:44 +01002983 iommu_completion_wait(iommu);
2984}
2985
Joerg Roedel01106062008-12-02 19:34:11 +01002986static int amd_iommu_attach_device(struct iommu_domain *dom,
2987 struct device *dev)
2988{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002989 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel657cbb62009-11-23 15:26:46 +01002990 struct iommu_dev_data *dev_data;
Joerg Roedel01106062008-12-02 19:34:11 +01002991 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002992 int ret;
Joerg Roedel01106062008-12-02 19:34:11 +01002993
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002994 if (!check_device(dev))
Joerg Roedel01106062008-12-02 19:34:11 +01002995 return -EINVAL;
2996
Joerg Roedel657cbb62009-11-23 15:26:46 +01002997 dev_data = dev->archdata.iommu;
2998
Joerg Roedelf62dda62011-06-09 12:55:35 +02002999 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel01106062008-12-02 19:34:11 +01003000 if (!iommu)
3001 return -EINVAL;
3002
Joerg Roedel657cbb62009-11-23 15:26:46 +01003003 if (dev_data->domain)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003004 detach_device(dev);
Joerg Roedel01106062008-12-02 19:34:11 +01003005
Joerg Roedel15898bb2009-11-24 15:39:42 +01003006 ret = attach_device(dev, domain);
Joerg Roedel01106062008-12-02 19:34:11 +01003007
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003008#ifdef CONFIG_IRQ_REMAP
3009 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3010 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3011 dev_data->use_vapic = 1;
3012 else
3013 dev_data->use_vapic = 0;
3014 }
3015#endif
3016
Joerg Roedel01106062008-12-02 19:34:11 +01003017 iommu_completion_wait(iommu);
3018
Joerg Roedel15898bb2009-11-24 15:39:42 +01003019 return ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003020}
3021
Joerg Roedel468e2362010-01-21 16:37:36 +01003022static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003023 phys_addr_t paddr, size_t page_size, int iommu_prot)
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003024{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003025 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003026 int prot = 0;
3027 int ret;
3028
Joerg Roedel132bd682011-11-17 14:18:46 +01003029 if (domain->mode == PAGE_MODE_NONE)
3030 return -EINVAL;
3031
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003032 if (iommu_prot & IOMMU_READ)
3033 prot |= IOMMU_PROT_IR;
3034 if (iommu_prot & IOMMU_WRITE)
3035 prot |= IOMMU_PROT_IW;
3036
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003037 mutex_lock(&domain->api_lock);
Joerg Roedelb911b892016-07-05 14:29:11 +02003038 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003039 mutex_unlock(&domain->api_lock);
3040
Joerg Roedel795e74f72010-05-11 17:40:57 +02003041 return ret;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003042}
3043
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003044static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3045 size_t page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003046{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003047 struct protection_domain *domain = to_pdomain(dom);
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003048 size_t unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003049
Joerg Roedel132bd682011-11-17 14:18:46 +01003050 if (domain->mode == PAGE_MODE_NONE)
Suravee Suthikulpanitc5611a82018-02-05 05:45:53 -05003051 return 0;
Joerg Roedel132bd682011-11-17 14:18:46 +01003052
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003053 mutex_lock(&domain->api_lock);
Joerg Roedel468e2362010-01-21 16:37:36 +01003054 unmap_size = iommu_unmap_page(domain, iova, page_size);
Joerg Roedel795e74f72010-05-11 17:40:57 +02003055 mutex_unlock(&domain->api_lock);
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003056
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003057 return unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003058}
3059
Joerg Roedel645c4c82008-12-02 20:05:50 +01003060static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
Varun Sethibb5547a2013-03-29 01:23:58 +05303061 dma_addr_t iova)
Joerg Roedel645c4c82008-12-02 20:05:50 +01003062{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003063 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel3039ca12015-04-01 14:58:48 +02003064 unsigned long offset_mask, pte_pgsize;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003065 u64 *pte, __pte;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003066
Joerg Roedel132bd682011-11-17 14:18:46 +01003067 if (domain->mode == PAGE_MODE_NONE)
3068 return iova;
3069
Joerg Roedel3039ca12015-04-01 14:58:48 +02003070 pte = fetch_pte(domain, iova, &pte_pgsize);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003071
Joerg Roedela6d41a42009-09-02 17:08:55 +02003072 if (!pte || !IOMMU_PTE_PRESENT(*pte))
Joerg Roedel645c4c82008-12-02 20:05:50 +01003073 return 0;
3074
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003075 offset_mask = pte_pgsize - 1;
3076 __pte = *pte & PM_ADDR_MASK;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003077
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003078 return (__pte & ~offset_mask) | (iova & offset_mask);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003079}
3080
Joerg Roedelab636482014-09-05 10:48:21 +02003081static bool amd_iommu_capable(enum iommu_cap cap)
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003082{
Joerg Roedel80a506b2010-07-27 17:14:24 +02003083 switch (cap) {
3084 case IOMMU_CAP_CACHE_COHERENCY:
Joerg Roedelab636482014-09-05 10:48:21 +02003085 return true;
Joerg Roedelbdddadc2012-07-02 18:38:13 +02003086 case IOMMU_CAP_INTR_REMAP:
Joerg Roedelab636482014-09-05 10:48:21 +02003087 return (irq_remapping_enabled == 1);
Will Deaconcfdeec22014-10-27 11:24:48 +00003088 case IOMMU_CAP_NOEXEC:
3089 return false;
Joerg Roedel80a506b2010-07-27 17:14:24 +02003090 }
3091
Joerg Roedelab636482014-09-05 10:48:21 +02003092 return false;
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003093}
3094
Eric Augere5b52342017-01-19 20:57:47 +00003095static void amd_iommu_get_resv_regions(struct device *dev,
3096 struct list_head *head)
Joerg Roedel35cf2482015-05-28 18:41:37 +02003097{
Eric Auger4397f322017-01-19 20:57:54 +00003098 struct iommu_resv_region *region;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003099 struct unity_map_entry *entry;
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003100 int devid;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003101
3102 devid = get_device_id(dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02003103 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04003104 return;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003105
3106 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
Eric Auger4397f322017-01-19 20:57:54 +00003107 size_t length;
3108 int prot = 0;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003109
3110 if (devid < entry->devid_start || devid > entry->devid_end)
3111 continue;
3112
Eric Auger4397f322017-01-19 20:57:54 +00003113 length = entry->address_end - entry->address_start;
3114 if (entry->prot & IOMMU_PROT_IR)
3115 prot |= IOMMU_READ;
3116 if (entry->prot & IOMMU_PROT_IW)
3117 prot |= IOMMU_WRITE;
3118
3119 region = iommu_alloc_resv_region(entry->address_start,
3120 length, prot,
3121 IOMMU_RESV_DIRECT);
Joerg Roedel35cf2482015-05-28 18:41:37 +02003122 if (!region) {
3123 pr_err("Out of memory allocating dm-regions for %s\n",
3124 dev_name(dev));
3125 return;
3126 }
Joerg Roedel35cf2482015-05-28 18:41:37 +02003127 list_add_tail(&region->list, head);
3128 }
Eric Auger4397f322017-01-19 20:57:54 +00003129
3130 region = iommu_alloc_resv_region(MSI_RANGE_START,
3131 MSI_RANGE_END - MSI_RANGE_START + 1,
Robin Murphy9d3a4de2017-03-16 17:00:16 +00003132 0, IOMMU_RESV_MSI);
Eric Auger4397f322017-01-19 20:57:54 +00003133 if (!region)
3134 return;
3135 list_add_tail(&region->list, head);
3136
3137 region = iommu_alloc_resv_region(HT_RANGE_START,
3138 HT_RANGE_END - HT_RANGE_START + 1,
3139 0, IOMMU_RESV_RESERVED);
3140 if (!region)
3141 return;
3142 list_add_tail(&region->list, head);
Joerg Roedel35cf2482015-05-28 18:41:37 +02003143}
3144
Eric Augere5b52342017-01-19 20:57:47 +00003145static void amd_iommu_put_resv_regions(struct device *dev,
Joerg Roedel35cf2482015-05-28 18:41:37 +02003146 struct list_head *head)
3147{
Eric Augere5b52342017-01-19 20:57:47 +00003148 struct iommu_resv_region *entry, *next;
Joerg Roedel35cf2482015-05-28 18:41:37 +02003149
3150 list_for_each_entry_safe(entry, next, head, list)
3151 kfree(entry);
3152}
3153
Eric Augere5b52342017-01-19 20:57:47 +00003154static void amd_iommu_apply_resv_region(struct device *dev,
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003155 struct iommu_domain *domain,
Eric Augere5b52342017-01-19 20:57:47 +00003156 struct iommu_resv_region *region)
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003157{
Joerg Roedelb3311b02016-07-08 13:31:31 +02003158 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003159 unsigned long start, end;
3160
3161 start = IOVA_PFN(region->start);
Gary R Hookb92b4fb2017-11-03 10:50:34 -06003162 end = IOVA_PFN(region->start + region->length - 1);
Joerg Roedel8d54d6c2016-07-05 13:32:20 +02003163
3164 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3165}
3166
Baoquan Hedf3f7a62017-08-09 16:33:41 +08003167static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3168 struct device *dev)
3169{
3170 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3171 return dev_data->defer_attach;
3172}
3173
Suravee Suthikulpaniteb5ecd12018-02-21 14:19:45 +07003174static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3175{
3176 struct protection_domain *dom = to_pdomain(domain);
3177
3178 domain_flush_tlb_pde(dom);
3179 domain_flush_complete(dom);
3180}
3181
3182static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3183 unsigned long iova, size_t size)
3184{
3185}
3186
Joerg Roedelb0119e82017-02-01 13:23:08 +01003187const struct iommu_ops amd_iommu_ops = {
Joerg Roedelab636482014-09-05 10:48:21 +02003188 .capable = amd_iommu_capable,
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003189 .domain_alloc = amd_iommu_domain_alloc,
3190 .domain_free = amd_iommu_domain_free,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003191 .attach_dev = amd_iommu_attach_device,
3192 .detach_dev = amd_iommu_detach_device,
Joerg Roedel468e2362010-01-21 16:37:36 +01003193 .map = amd_iommu_map,
3194 .unmap = amd_iommu_unmap,
Olav Haugan315786e2014-10-25 09:55:16 -07003195 .map_sg = default_iommu_map_sg,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003196 .iova_to_phys = amd_iommu_iova_to_phys,
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02003197 .add_device = amd_iommu_add_device,
3198 .remove_device = amd_iommu_remove_device,
Wan Zongshunb097d112016-04-01 09:06:04 -04003199 .device_group = amd_iommu_device_group,
Eric Augere5b52342017-01-19 20:57:47 +00003200 .get_resv_regions = amd_iommu_get_resv_regions,
3201 .put_resv_regions = amd_iommu_put_resv_regions,
3202 .apply_resv_region = amd_iommu_apply_resv_region,
Baoquan Hedf3f7a62017-08-09 16:33:41 +08003203 .is_attach_deferred = amd_iommu_is_attach_deferred,
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +02003204 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
Suravee Suthikulpaniteb5ecd12018-02-21 14:19:45 +07003205 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3206 .iotlb_range_add = amd_iommu_iotlb_range_add,
3207 .iotlb_sync = amd_iommu_flush_iotlb_all,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003208};
3209
Joerg Roedel0feae532009-08-26 15:26:30 +02003210/*****************************************************************************
3211 *
3212 * The next functions do a basic initialization of IOMMU for pass through
3213 * mode
3214 *
3215 * In passthrough mode the IOMMU is initialized and enabled but not used for
3216 * DMA-API translation.
3217 *
3218 *****************************************************************************/
3219
Joerg Roedel72e1dcc2011-11-10 19:13:51 +01003220/* IOMMUv2 specific functions */
3221int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3222{
3223 return atomic_notifier_chain_register(&ppr_notifier, nb);
3224}
3225EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3226
3227int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3228{
3229 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3230}
3231EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
Joerg Roedel132bd682011-11-17 14:18:46 +01003232
3233void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3234{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003235 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel132bd682011-11-17 14:18:46 +01003236 unsigned long flags;
3237
3238 spin_lock_irqsave(&domain->lock, flags);
3239
3240 /* Update data structure */
3241 domain->mode = PAGE_MODE_NONE;
3242 domain->updated = true;
3243
3244 /* Make changes visible to IOMMUs */
3245 update_domain(domain);
3246
3247 /* Page-table is not visible to IOMMU anymore, so free it */
3248 free_pagetable(domain);
3249
3250 spin_unlock_irqrestore(&domain->lock, flags);
3251}
3252EXPORT_SYMBOL(amd_iommu_domain_direct_map);
Joerg Roedel52815b72011-11-17 17:24:28 +01003253
3254int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3255{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003256 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel52815b72011-11-17 17:24:28 +01003257 unsigned long flags;
3258 int levels, ret;
3259
3260 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3261 return -EINVAL;
3262
3263 /* Number of GCR3 table levels required */
3264 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3265 levels += 1;
3266
3267 if (levels > amd_iommu_max_glx_val)
3268 return -EINVAL;
3269
3270 spin_lock_irqsave(&domain->lock, flags);
3271
3272 /*
3273 * Save us all sanity checks whether devices already in the
3274 * domain support IOMMUv2. Just force that the domain has no
3275 * devices attached when it is switched into IOMMUv2 mode.
3276 */
3277 ret = -EBUSY;
3278 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3279 goto out;
3280
3281 ret = -ENOMEM;
3282 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3283 if (domain->gcr3_tbl == NULL)
3284 goto out;
3285
3286 domain->glx = levels;
3287 domain->flags |= PD_IOMMUV2_MASK;
3288 domain->updated = true;
3289
3290 update_domain(domain);
3291
3292 ret = 0;
3293
3294out:
3295 spin_unlock_irqrestore(&domain->lock, flags);
3296
3297 return ret;
3298}
3299EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003300
3301static int __flush_pasid(struct protection_domain *domain, int pasid,
3302 u64 address, bool size)
3303{
3304 struct iommu_dev_data *dev_data;
3305 struct iommu_cmd cmd;
3306 int i, ret;
3307
3308 if (!(domain->flags & PD_IOMMUV2_MASK))
3309 return -EINVAL;
3310
3311 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3312
3313 /*
3314 * IOMMU TLB needs to be flushed before Device TLB to
3315 * prevent device TLB refill from IOMMU TLB
3316 */
Suravee Suthikulpanit6b9376e2017-02-24 02:48:17 -06003317 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
Joerg Roedel22e266c2011-11-21 15:59:08 +01003318 if (domain->dev_iommu[i] == 0)
3319 continue;
3320
3321 ret = iommu_queue_command(amd_iommus[i], &cmd);
3322 if (ret != 0)
3323 goto out;
3324 }
3325
3326 /* Wait until IOMMU TLB flushes are complete */
3327 domain_flush_complete(domain);
3328
3329 /* Now flush device TLBs */
3330 list_for_each_entry(dev_data, &domain->dev_list, list) {
3331 struct amd_iommu *iommu;
3332 int qdep;
3333
Joerg Roedel1c1cc452015-07-30 11:24:45 +02003334 /*
3335 There might be non-IOMMUv2 capable devices in an IOMMUv2
3336 * domain.
3337 */
3338 if (!dev_data->ats.enabled)
3339 continue;
Joerg Roedel22e266c2011-11-21 15:59:08 +01003340
3341 qdep = dev_data->ats.qdep;
3342 iommu = amd_iommu_rlookup_table[dev_data->devid];
3343
3344 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3345 qdep, address, size);
3346
3347 ret = iommu_queue_command(iommu, &cmd);
3348 if (ret != 0)
3349 goto out;
3350 }
3351
3352 /* Wait until all device TLBs are flushed */
3353 domain_flush_complete(domain);
3354
3355 ret = 0;
3356
3357out:
3358
3359 return ret;
3360}
3361
3362static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3363 u64 address)
3364{
3365 return __flush_pasid(domain, pasid, address, false);
3366}
3367
3368int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3369 u64 address)
3370{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003371 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003372 unsigned long flags;
3373 int ret;
3374
3375 spin_lock_irqsave(&domain->lock, flags);
3376 ret = __amd_iommu_flush_page(domain, pasid, address);
3377 spin_unlock_irqrestore(&domain->lock, flags);
3378
3379 return ret;
3380}
3381EXPORT_SYMBOL(amd_iommu_flush_page);
3382
3383static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3384{
3385 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3386 true);
3387}
3388
3389int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3390{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003391 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003392 unsigned long flags;
3393 int ret;
3394
3395 spin_lock_irqsave(&domain->lock, flags);
3396 ret = __amd_iommu_flush_tlb(domain, pasid);
3397 spin_unlock_irqrestore(&domain->lock, flags);
3398
3399 return ret;
3400}
3401EXPORT_SYMBOL(amd_iommu_flush_tlb);
3402
Joerg Roedelb16137b2011-11-21 16:50:23 +01003403static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3404{
3405 int index;
3406 u64 *pte;
3407
3408 while (true) {
3409
3410 index = (pasid >> (9 * level)) & 0x1ff;
3411 pte = &root[index];
3412
3413 if (level == 0)
3414 break;
3415
3416 if (!(*pte & GCR3_VALID)) {
3417 if (!alloc)
3418 return NULL;
3419
3420 root = (void *)get_zeroed_page(GFP_ATOMIC);
3421 if (root == NULL)
3422 return NULL;
3423
Tom Lendacky2543a782017-07-17 16:10:24 -05003424 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
Joerg Roedelb16137b2011-11-21 16:50:23 +01003425 }
3426
Tom Lendacky2543a782017-07-17 16:10:24 -05003427 root = iommu_phys_to_virt(*pte & PAGE_MASK);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003428
3429 level -= 1;
3430 }
3431
3432 return pte;
3433}
3434
3435static int __set_gcr3(struct protection_domain *domain, int pasid,
3436 unsigned long cr3)
3437{
3438 u64 *pte;
3439
3440 if (domain->mode != PAGE_MODE_NONE)
3441 return -EINVAL;
3442
3443 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3444 if (pte == NULL)
3445 return -ENOMEM;
3446
3447 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3448
3449 return __amd_iommu_flush_tlb(domain, pasid);
3450}
3451
3452static int __clear_gcr3(struct protection_domain *domain, int pasid)
3453{
3454 u64 *pte;
3455
3456 if (domain->mode != PAGE_MODE_NONE)
3457 return -EINVAL;
3458
3459 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3460 if (pte == NULL)
3461 return 0;
3462
3463 *pte = 0;
3464
3465 return __amd_iommu_flush_tlb(domain, pasid);
3466}
3467
3468int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3469 unsigned long cr3)
3470{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003471 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003472 unsigned long flags;
3473 int ret;
3474
3475 spin_lock_irqsave(&domain->lock, flags);
3476 ret = __set_gcr3(domain, pasid, cr3);
3477 spin_unlock_irqrestore(&domain->lock, flags);
3478
3479 return ret;
3480}
3481EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3482
3483int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3484{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003485 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003486 unsigned long flags;
3487 int ret;
3488
3489 spin_lock_irqsave(&domain->lock, flags);
3490 ret = __clear_gcr3(domain, pasid);
3491 spin_unlock_irqrestore(&domain->lock, flags);
3492
3493 return ret;
3494}
3495EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
Joerg Roedelc99afa22011-11-21 18:19:25 +01003496
3497int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3498 int status, int tag)
3499{
3500 struct iommu_dev_data *dev_data;
3501 struct amd_iommu *iommu;
3502 struct iommu_cmd cmd;
3503
3504 dev_data = get_dev_data(&pdev->dev);
3505 iommu = amd_iommu_rlookup_table[dev_data->devid];
3506
3507 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3508 tag, dev_data->pri_tlp);
3509
3510 return iommu_queue_command(iommu, &cmd);
3511}
3512EXPORT_SYMBOL(amd_iommu_complete_ppr);
Joerg Roedelf3572db2011-11-23 12:36:25 +01003513
3514struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3515{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003516 struct protection_domain *pdomain;
Joerg Roedelf3572db2011-11-23 12:36:25 +01003517
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003518 pdomain = get_domain(&pdev->dev);
3519 if (IS_ERR(pdomain))
Joerg Roedelf3572db2011-11-23 12:36:25 +01003520 return NULL;
3521
3522 /* Only return IOMMUv2 domains */
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003523 if (!(pdomain->flags & PD_IOMMUV2_MASK))
Joerg Roedelf3572db2011-11-23 12:36:25 +01003524 return NULL;
3525
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003526 return &pdomain->domain;
Joerg Roedelf3572db2011-11-23 12:36:25 +01003527}
3528EXPORT_SYMBOL(amd_iommu_get_v2_domain);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01003529
3530void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3531{
3532 struct iommu_dev_data *dev_data;
3533
3534 if (!amd_iommu_v2_supported())
3535 return;
3536
3537 dev_data = get_dev_data(&pdev->dev);
3538 dev_data->errata |= (1 << erratum);
3539}
3540EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
Joerg Roedel52efdb82011-12-07 12:01:36 +01003541
3542int amd_iommu_device_info(struct pci_dev *pdev,
3543 struct amd_iommu_device_info *info)
3544{
3545 int max_pasids;
3546 int pos;
3547
3548 if (pdev == NULL || info == NULL)
3549 return -EINVAL;
3550
3551 if (!amd_iommu_v2_supported())
3552 return -EINVAL;
3553
3554 memset(info, 0, sizeof(*info));
3555
Gil Kupfercef74402018-05-10 17:56:02 -05003556 if (!pci_ats_disabled()) {
3557 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3558 if (pos)
3559 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3560 }
Joerg Roedel52efdb82011-12-07 12:01:36 +01003561
3562 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3563 if (pos)
3564 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3565
3566 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3567 if (pos) {
3568 int features;
3569
3570 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3571 max_pasids = min(max_pasids, (1 << 20));
3572
3573 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3574 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3575
3576 features = pci_pasid_features(pdev);
3577 if (features & PCI_PASID_CAP_EXEC)
3578 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3579 if (features & PCI_PASID_CAP_PRIV)
3580 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3581 }
3582
3583 return 0;
3584}
3585EXPORT_SYMBOL(amd_iommu_device_info);
Joerg Roedel2b324502012-06-21 16:29:10 +02003586
3587#ifdef CONFIG_IRQ_REMAP
3588
3589/*****************************************************************************
3590 *
3591 * Interrupt Remapping Implementation
3592 *
3593 *****************************************************************************/
3594
Jiang Liu7c71d302015-04-13 14:11:33 +08003595static struct irq_chip amd_ir_chip;
Arnd Bergmann94c793a2018-04-04 12:56:59 +02003596static DEFINE_SPINLOCK(iommu_table_lock);
Jiang Liu7c71d302015-04-13 14:11:33 +08003597
Joerg Roedel2b324502012-06-21 16:29:10 +02003598static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3599{
3600 u64 dte;
3601
3602 dte = amd_iommu_dev_table[devid].data[2];
3603 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
Tom Lendacky2543a782017-07-17 16:10:24 -05003604 dte |= iommu_virt_to_phys(table->table);
Joerg Roedel2b324502012-06-21 16:29:10 +02003605 dte |= DTE_IRQ_REMAP_INTCTL;
3606 dte |= DTE_IRQ_TABLE_LEN;
3607 dte |= DTE_IRQ_REMAP_ENABLE;
3608
3609 amd_iommu_dev_table[devid].data[2] = dte;
3610}
3611
Scott Wooddf42a042018-02-14 17:36:28 -06003612static struct irq_remap_table *get_irq_table(u16 devid)
3613{
3614 struct irq_remap_table *table;
3615
3616 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3617 "%s: no iommu for devid %x\n", __func__, devid))
3618 return NULL;
3619
3620 table = irq_lookup_table[devid];
3621 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3622 return NULL;
3623
3624 return table;
3625}
3626
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003627static struct irq_remap_table *__alloc_irq_table(void)
3628{
3629 struct irq_remap_table *table;
3630
3631 table = kzalloc(sizeof(*table), GFP_KERNEL);
3632 if (!table)
3633 return NULL;
3634
3635 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3636 if (!table->table) {
3637 kfree(table);
3638 return NULL;
3639 }
3640 raw_spin_lock_init(&table->lock);
3641
3642 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3643 memset(table->table, 0,
3644 MAX_IRQS_PER_TABLE * sizeof(u32));
3645 else
3646 memset(table->table, 0,
3647 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3648 return table;
3649}
3650
Sebastian Andrzej Siewior2fcc1e82018-03-22 16:22:39 +01003651static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3652 struct irq_remap_table *table)
3653{
3654 irq_lookup_table[devid] = table;
3655 set_dte_irq_entry(devid, table);
3656 iommu_flush_dte(iommu, devid);
3657}
3658
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01003659static struct irq_remap_table *alloc_irq_table(u16 devid)
Joerg Roedel2b324502012-06-21 16:29:10 +02003660{
3661 struct irq_remap_table *table = NULL;
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003662 struct irq_remap_table *new_table = NULL;
Joerg Roedel2b324502012-06-21 16:29:10 +02003663 struct amd_iommu *iommu;
3664 unsigned long flags;
3665 u16 alias;
3666
Sebastian Andrzej Siewiorea6166f2018-03-22 16:22:36 +01003667 spin_lock_irqsave(&iommu_table_lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003668
3669 iommu = amd_iommu_rlookup_table[devid];
3670 if (!iommu)
3671 goto out_unlock;
3672
3673 table = irq_lookup_table[devid];
3674 if (table)
Baoquan He09284b92016-09-20 09:05:34 +08003675 goto out_unlock;
Joerg Roedel2b324502012-06-21 16:29:10 +02003676
3677 alias = amd_iommu_alias_table[devid];
3678 table = irq_lookup_table[alias];
3679 if (table) {
Sebastian Andrzej Siewior2fcc1e82018-03-22 16:22:39 +01003680 set_remap_table_entry(iommu, devid, table);
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003681 goto out_wait;
Joerg Roedel2b324502012-06-21 16:29:10 +02003682 }
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003683 spin_unlock_irqrestore(&iommu_table_lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003684
3685 /* Nothing there yet, allocate new irq remapping table */
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003686 new_table = __alloc_irq_table();
3687 if (!new_table)
3688 return NULL;
3689
3690 spin_lock_irqsave(&iommu_table_lock, flags);
3691
3692 table = irq_lookup_table[devid];
3693 if (table)
Baoquan He09284b92016-09-20 09:05:34 +08003694 goto out_unlock;
Joerg Roedel2b324502012-06-21 16:29:10 +02003695
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003696 table = irq_lookup_table[alias];
3697 if (table) {
3698 set_remap_table_entry(iommu, devid, table);
3699 goto out_wait;
Joerg Roedel2b324502012-06-21 16:29:10 +02003700 }
3701
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003702 table = new_table;
3703 new_table = NULL;
Joerg Roedel2b324502012-06-21 16:29:10 +02003704
Sebastian Andrzej Siewior2fcc1e82018-03-22 16:22:39 +01003705 set_remap_table_entry(iommu, devid, table);
3706 if (devid != alias)
3707 set_remap_table_entry(iommu, alias, table);
Joerg Roedel2b324502012-06-21 16:29:10 +02003708
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003709out_wait:
Joerg Roedel2b324502012-06-21 16:29:10 +02003710 iommu_completion_wait(iommu);
3711
3712out_unlock:
Sebastian Andrzej Siewiorea6166f2018-03-22 16:22:36 +01003713 spin_unlock_irqrestore(&iommu_table_lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003714
Sebastian Andrzej Siewior993ca6e2018-03-22 16:22:40 +01003715 if (new_table) {
3716 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3717 kfree(new_table);
3718 }
Joerg Roedel2b324502012-06-21 16:29:10 +02003719 return table;
3720}
3721
Joerg Roedel37946d92017-10-06 12:16:39 +02003722static int alloc_irq_index(u16 devid, int count, bool align)
Joerg Roedel2b324502012-06-21 16:29:10 +02003723{
3724 struct irq_remap_table *table;
Joerg Roedel37946d92017-10-06 12:16:39 +02003725 int index, c, alignment = 1;
Joerg Roedel2b324502012-06-21 16:29:10 +02003726 unsigned long flags;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003727 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3728
3729 if (!iommu)
3730 return -ENODEV;
Joerg Roedel2b324502012-06-21 16:29:10 +02003731
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01003732 table = alloc_irq_table(devid);
Joerg Roedel2b324502012-06-21 16:29:10 +02003733 if (!table)
3734 return -ENODEV;
3735
Joerg Roedel37946d92017-10-06 12:16:39 +02003736 if (align)
3737 alignment = roundup_pow_of_two(count);
3738
Scott Wood27790392018-01-21 03:28:54 -06003739 raw_spin_lock_irqsave(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003740
3741 /* Scan table for free entries */
Joerg Roedel37946d92017-10-06 12:16:39 +02003742 for (index = ALIGN(table->min_index, alignment), c = 0;
Alex Williamson07d1c912017-11-03 10:50:31 -06003743 index < MAX_IRQS_PER_TABLE;) {
Joerg Roedel37946d92017-10-06 12:16:39 +02003744 if (!iommu->irte_ops->is_allocated(table, index)) {
Joerg Roedel2b324502012-06-21 16:29:10 +02003745 c += 1;
Joerg Roedel37946d92017-10-06 12:16:39 +02003746 } else {
3747 c = 0;
Alex Williamson07d1c912017-11-03 10:50:31 -06003748 index = ALIGN(index + 1, alignment);
Joerg Roedel37946d92017-10-06 12:16:39 +02003749 continue;
3750 }
Joerg Roedel2b324502012-06-21 16:29:10 +02003751
3752 if (c == count) {
Joerg Roedel2b324502012-06-21 16:29:10 +02003753 for (; c != 0; --c)
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003754 iommu->irte_ops->set_allocated(table, index - c + 1);
Joerg Roedel2b324502012-06-21 16:29:10 +02003755
3756 index -= count - 1;
Joerg Roedel2b324502012-06-21 16:29:10 +02003757 goto out;
3758 }
Alex Williamson07d1c912017-11-03 10:50:31 -06003759
3760 index++;
Joerg Roedel2b324502012-06-21 16:29:10 +02003761 }
3762
3763 index = -ENOSPC;
3764
3765out:
Scott Wood27790392018-01-21 03:28:54 -06003766 raw_spin_unlock_irqrestore(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003767
3768 return index;
3769}
3770
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003771static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3772 struct amd_ir_data *data)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003773{
3774 struct irq_remap_table *table;
3775 struct amd_iommu *iommu;
3776 unsigned long flags;
3777 struct irte_ga *entry;
3778
3779 iommu = amd_iommu_rlookup_table[devid];
3780 if (iommu == NULL)
3781 return -EINVAL;
3782
Scott Wooddf42a042018-02-14 17:36:28 -06003783 table = get_irq_table(devid);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003784 if (!table)
3785 return -ENOMEM;
3786
Scott Wood27790392018-01-21 03:28:54 -06003787 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003788
3789 entry = (struct irte_ga *)table->table;
3790 entry = &entry[index];
3791 entry->lo.fields_remap.valid = 0;
3792 entry->hi.val = irte->hi.val;
3793 entry->lo.val = irte->lo.val;
3794 entry->lo.fields_remap.valid = 1;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003795 if (data)
3796 data->ref = entry;
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003797
Scott Wood27790392018-01-21 03:28:54 -06003798 raw_spin_unlock_irqrestore(&table->lock, flags);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003799
3800 iommu_flush_irt(iommu, devid);
3801 iommu_completion_wait(iommu);
3802
3803 return 0;
3804}
3805
3806static int modify_irte(u16 devid, int index, union irte *irte)
Joerg Roedel2b324502012-06-21 16:29:10 +02003807{
3808 struct irq_remap_table *table;
3809 struct amd_iommu *iommu;
3810 unsigned long flags;
3811
3812 iommu = amd_iommu_rlookup_table[devid];
3813 if (iommu == NULL)
3814 return -EINVAL;
3815
Scott Wooddf42a042018-02-14 17:36:28 -06003816 table = get_irq_table(devid);
Joerg Roedel2b324502012-06-21 16:29:10 +02003817 if (!table)
3818 return -ENOMEM;
3819
Scott Wood27790392018-01-21 03:28:54 -06003820 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003821 table->table[index] = irte->val;
Scott Wood27790392018-01-21 03:28:54 -06003822 raw_spin_unlock_irqrestore(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003823
3824 iommu_flush_irt(iommu, devid);
3825 iommu_completion_wait(iommu);
3826
3827 return 0;
3828}
3829
3830static void free_irte(u16 devid, int index)
3831{
3832 struct irq_remap_table *table;
3833 struct amd_iommu *iommu;
3834 unsigned long flags;
3835
3836 iommu = amd_iommu_rlookup_table[devid];
3837 if (iommu == NULL)
3838 return;
3839
Scott Wooddf42a042018-02-14 17:36:28 -06003840 table = get_irq_table(devid);
Joerg Roedel2b324502012-06-21 16:29:10 +02003841 if (!table)
3842 return;
3843
Scott Wood27790392018-01-21 03:28:54 -06003844 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003845 iommu->irte_ops->clear_allocated(table, index);
Scott Wood27790392018-01-21 03:28:54 -06003846 raw_spin_unlock_irqrestore(&table->lock, flags);
Joerg Roedel2b324502012-06-21 16:29:10 +02003847
3848 iommu_flush_irt(iommu, devid);
3849 iommu_completion_wait(iommu);
3850}
3851
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003852static void irte_prepare(void *entry,
3853 u32 delivery_mode, u32 dest_mode,
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003854 u8 vector, u32 dest_apicid, int devid)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003855{
3856 union irte *irte = (union irte *) entry;
3857
3858 irte->val = 0;
3859 irte->fields.vector = vector;
3860 irte->fields.int_type = delivery_mode;
3861 irte->fields.destination = dest_apicid;
3862 irte->fields.dm = dest_mode;
3863 irte->fields.valid = 1;
3864}
3865
3866static void irte_ga_prepare(void *entry,
3867 u32 delivery_mode, u32 dest_mode,
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003868 u8 vector, u32 dest_apicid, int devid)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003869{
3870 struct irte_ga *irte = (struct irte_ga *) entry;
3871
3872 irte->lo.val = 0;
3873 irte->hi.val = 0;
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003874 irte->lo.fields_remap.int_type = delivery_mode;
3875 irte->lo.fields_remap.dm = dest_mode;
3876 irte->hi.fields.vector = vector;
3877 irte->lo.fields_remap.destination = dest_apicid;
3878 irte->lo.fields_remap.valid = 1;
3879}
3880
3881static void irte_activate(void *entry, u16 devid, u16 index)
3882{
3883 union irte *irte = (union irte *) entry;
3884
3885 irte->fields.valid = 1;
3886 modify_irte(devid, index, irte);
3887}
3888
3889static void irte_ga_activate(void *entry, u16 devid, u16 index)
3890{
3891 struct irte_ga *irte = (struct irte_ga *) entry;
3892
3893 irte->lo.fields_remap.valid = 1;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003894 modify_irte_ga(devid, index, irte, NULL);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003895}
3896
3897static void irte_deactivate(void *entry, u16 devid, u16 index)
3898{
3899 union irte *irte = (union irte *) entry;
3900
3901 irte->fields.valid = 0;
3902 modify_irte(devid, index, irte);
3903}
3904
3905static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3906{
3907 struct irte_ga *irte = (struct irte_ga *) entry;
3908
3909 irte->lo.fields_remap.valid = 0;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05003910 modify_irte_ga(devid, index, irte, NULL);
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003911}
3912
3913static void irte_set_affinity(void *entry, u16 devid, u16 index,
3914 u8 vector, u32 dest_apicid)
3915{
3916 union irte *irte = (union irte *) entry;
3917
3918 irte->fields.vector = vector;
3919 irte->fields.destination = dest_apicid;
3920 modify_irte(devid, index, irte);
3921}
3922
3923static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3924 u8 vector, u32 dest_apicid)
3925{
3926 struct irte_ga *irte = (struct irte_ga *) entry;
3927
Scott Wood01ee04b2018-01-28 14:22:19 -06003928 if (!irte->lo.fields_remap.guest_mode) {
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003929 irte->hi.fields.vector = vector;
3930 irte->lo.fields_remap.destination = dest_apicid;
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05003931 modify_irte_ga(devid, index, irte, NULL);
3932 }
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003933}
3934
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05003935#define IRTE_ALLOCATED (~1U)
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05003936static void irte_set_allocated(struct irq_remap_table *table, int index)
3937{
3938 table->table[index] = IRTE_ALLOCATED;
3939}
3940
3941static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3942{
3943 struct irte_ga *ptr = (struct irte_ga *)table->table;
3944 struct irte_ga *irte = &ptr[index];
3945
3946 memset(&irte->lo.val, 0, sizeof(u64));
3947 memset(&irte->hi.val, 0, sizeof(u64));
3948 irte->hi.fields.vector = 0xff;
3949}
3950
3951static bool irte_is_allocated(struct irq_remap_table *table, int index)
3952{
3953 union irte *ptr = (union irte *)table->table;
3954 union irte *irte = &ptr[index];
3955
3956 return irte->val != 0;
3957}
3958
3959static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3960{
3961 struct irte_ga *ptr = (struct irte_ga *)table->table;
3962 struct irte_ga *irte = &ptr[index];
3963
3964 return irte->hi.fields.vector != 0;
3965}
3966
3967static void irte_clear_allocated(struct irq_remap_table *table, int index)
3968{
3969 table->table[index] = 0;
3970}
3971
3972static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3973{
3974 struct irte_ga *ptr = (struct irte_ga *)table->table;
3975 struct irte_ga *irte = &ptr[index];
3976
3977 memset(&irte->lo.val, 0, sizeof(u64));
3978 memset(&irte->hi.val, 0, sizeof(u64));
3979}
3980
Jiang Liu7c71d302015-04-13 14:11:33 +08003981static int get_devid(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02003982{
Jiang Liu7c71d302015-04-13 14:11:33 +08003983 int devid = -1;
Joerg Roedel5527de72012-06-26 11:17:32 +02003984
Jiang Liu7c71d302015-04-13 14:11:33 +08003985 switch (info->type) {
3986 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3987 devid = get_ioapic_devid(info->ioapic_id);
3988 break;
3989 case X86_IRQ_ALLOC_TYPE_HPET:
3990 devid = get_hpet_devid(info->hpet_id);
3991 break;
3992 case X86_IRQ_ALLOC_TYPE_MSI:
3993 case X86_IRQ_ALLOC_TYPE_MSIX:
3994 devid = get_device_id(&info->msi_dev->dev);
3995 break;
3996 default:
3997 BUG_ON(1);
3998 break;
Joerg Roedel5527de72012-06-26 11:17:32 +02003999 }
4000
Jiang Liu7c71d302015-04-13 14:11:33 +08004001 return devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02004002}
4003
Jiang Liu7c71d302015-04-13 14:11:33 +08004004static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02004005{
Jiang Liu7c71d302015-04-13 14:11:33 +08004006 struct amd_iommu *iommu;
4007 int devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02004008
Jiang Liu7c71d302015-04-13 14:11:33 +08004009 if (!info)
4010 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02004011
Jiang Liu7c71d302015-04-13 14:11:33 +08004012 devid = get_devid(info);
4013 if (devid >= 0) {
4014 iommu = amd_iommu_rlookup_table[devid];
4015 if (iommu)
4016 return iommu->ir_domain;
4017 }
Joerg Roedel5527de72012-06-26 11:17:32 +02004018
Jiang Liu7c71d302015-04-13 14:11:33 +08004019 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02004020}
4021
Jiang Liu7c71d302015-04-13 14:11:33 +08004022static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004023{
Jiang Liu7c71d302015-04-13 14:11:33 +08004024 struct amd_iommu *iommu;
4025 int devid;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004026
Jiang Liu7c71d302015-04-13 14:11:33 +08004027 if (!info)
4028 return NULL;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004029
Jiang Liu7c71d302015-04-13 14:11:33 +08004030 switch (info->type) {
4031 case X86_IRQ_ALLOC_TYPE_MSI:
4032 case X86_IRQ_ALLOC_TYPE_MSIX:
4033 devid = get_device_id(&info->msi_dev->dev);
Joerg Roedel9ee35e42016-04-21 18:21:31 +02004034 if (devid < 0)
Wan Zongshun7aba6cb2016-04-01 09:06:02 -04004035 return NULL;
4036
Dan Carpenter1fb260b2016-01-07 12:36:06 +03004037 iommu = amd_iommu_rlookup_table[devid];
4038 if (iommu)
4039 return iommu->msi_domain;
Jiang Liu7c71d302015-04-13 14:11:33 +08004040 break;
4041 default:
4042 break;
4043 }
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02004044
Jiang Liu7c71d302015-04-13 14:11:33 +08004045 return NULL;
Joerg Roedeld9761952012-06-26 16:00:08 +02004046}
4047
Joerg Roedel6b474b82012-06-26 16:46:04 +02004048struct irq_remap_ops amd_iommu_irq_ops = {
Joerg Roedel6b474b82012-06-26 16:46:04 +02004049 .prepare = amd_iommu_prepare,
4050 .enable = amd_iommu_enable,
4051 .disable = amd_iommu_disable,
4052 .reenable = amd_iommu_reenable,
4053 .enable_faulting = amd_iommu_enable_faulting,
Jiang Liu7c71d302015-04-13 14:11:33 +08004054 .get_ir_irq_domain = get_ir_irq_domain,
4055 .get_irq_domain = get_irq_domain,
Joerg Roedel6b474b82012-06-26 16:46:04 +02004056};
Jiang Liu7c71d302015-04-13 14:11:33 +08004057
4058static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4059 struct irq_cfg *irq_cfg,
4060 struct irq_alloc_info *info,
4061 int devid, int index, int sub_handle)
4062{
4063 struct irq_2_irte *irte_info = &data->irq_2_irte;
4064 struct msi_msg *msg = &data->msi_entry;
Jiang Liu7c71d302015-04-13 14:11:33 +08004065 struct IO_APIC_route_entry *entry;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004066 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4067
4068 if (!iommu)
4069 return;
Jiang Liu7c71d302015-04-13 14:11:33 +08004070
Jiang Liu7c71d302015-04-13 14:11:33 +08004071 data->irq_2_irte.devid = devid;
4072 data->irq_2_irte.index = index + sub_handle;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004073 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4074 apic->irq_dest_mode, irq_cfg->vector,
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05004075 irq_cfg->dest_apicid, devid);
Jiang Liu7c71d302015-04-13 14:11:33 +08004076
4077 switch (info->type) {
4078 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4079 /* Setup IOAPIC entry */
4080 entry = info->ioapic_entry;
4081 info->ioapic_entry = NULL;
4082 memset(entry, 0, sizeof(*entry));
4083 entry->vector = index;
4084 entry->mask = 0;
4085 entry->trigger = info->ioapic_trigger;
4086 entry->polarity = info->ioapic_polarity;
4087 /* Mask level triggered irqs. */
4088 if (info->ioapic_trigger)
4089 entry->mask = 1;
4090 break;
4091
4092 case X86_IRQ_ALLOC_TYPE_HPET:
4093 case X86_IRQ_ALLOC_TYPE_MSI:
4094 case X86_IRQ_ALLOC_TYPE_MSIX:
4095 msg->address_hi = MSI_ADDR_BASE_HI;
4096 msg->address_lo = MSI_ADDR_BASE_LO;
4097 msg->data = irte_info->index;
4098 break;
4099
4100 default:
4101 BUG_ON(1);
4102 break;
4103 }
4104}
4105
Suravee Suthikulpanit880ac602016-08-23 13:52:34 -05004106struct amd_irte_ops irte_32_ops = {
4107 .prepare = irte_prepare,
4108 .activate = irte_activate,
4109 .deactivate = irte_deactivate,
4110 .set_affinity = irte_set_affinity,
4111 .set_allocated = irte_set_allocated,
4112 .is_allocated = irte_is_allocated,
4113 .clear_allocated = irte_clear_allocated,
4114};
4115
4116struct amd_irte_ops irte_128_ops = {
4117 .prepare = irte_ga_prepare,
4118 .activate = irte_ga_activate,
4119 .deactivate = irte_ga_deactivate,
4120 .set_affinity = irte_ga_set_affinity,
4121 .set_allocated = irte_ga_set_allocated,
4122 .is_allocated = irte_ga_is_allocated,
4123 .clear_allocated = irte_ga_clear_allocated,
4124};
4125
Jiang Liu7c71d302015-04-13 14:11:33 +08004126static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4127 unsigned int nr_irqs, void *arg)
4128{
4129 struct irq_alloc_info *info = arg;
4130 struct irq_data *irq_data;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004131 struct amd_ir_data *data = NULL;
Jiang Liu7c71d302015-04-13 14:11:33 +08004132 struct irq_cfg *cfg;
4133 int i, ret, devid;
Sebastian Andrzej Siewior29d049b2018-03-22 16:22:42 +01004134 int index;
Jiang Liu7c71d302015-04-13 14:11:33 +08004135
4136 if (!info)
4137 return -EINVAL;
4138 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4139 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4140 return -EINVAL;
4141
4142 /*
4143 * With IRQ remapping enabled, don't need contiguous CPU vectors
4144 * to support multiple MSI interrupts.
4145 */
4146 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4147 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4148
4149 devid = get_devid(info);
4150 if (devid < 0)
4151 return -EINVAL;
4152
4153 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4154 if (ret < 0)
4155 return ret;
4156
Jiang Liu7c71d302015-04-13 14:11:33 +08004157 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01004158 struct irq_remap_table *table;
4159 struct amd_iommu *iommu;
4160
4161 table = alloc_irq_table(devid);
4162 if (table) {
4163 if (!table->min_index) {
4164 /*
4165 * Keep the first 32 indexes free for IOAPIC
4166 * interrupts.
4167 */
4168 table->min_index = 32;
4169 iommu = amd_iommu_rlookup_table[devid];
4170 for (i = 0; i < 32; ++i)
4171 iommu->irte_ops->set_allocated(table, i);
4172 }
4173 WARN_ON(table->min_index != 32);
Jiang Liu7c71d302015-04-13 14:11:33 +08004174 index = info->ioapic_pin;
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01004175 } else {
Sebastian Andrzej Siewior29d049b2018-03-22 16:22:42 +01004176 index = -ENOMEM;
Sebastian Andrzej Siewiorfde65dd2018-03-22 16:22:37 +01004177 }
Jiang Liu7c71d302015-04-13 14:11:33 +08004178 } else {
Joerg Roedel53b9ec32017-10-06 12:22:06 +02004179 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4180
4181 index = alloc_irq_index(devid, nr_irqs, align);
Jiang Liu7c71d302015-04-13 14:11:33 +08004182 }
4183 if (index < 0) {
4184 pr_warn("Failed to allocate IRTE\n");
Wei Yongjun517abe42016-07-28 02:10:26 +00004185 ret = index;
Jiang Liu7c71d302015-04-13 14:11:33 +08004186 goto out_free_parent;
4187 }
4188
4189 for (i = 0; i < nr_irqs; i++) {
4190 irq_data = irq_domain_get_irq_data(domain, virq + i);
4191 cfg = irqd_cfg(irq_data);
4192 if (!irq_data || !cfg) {
4193 ret = -EINVAL;
4194 goto out_free_data;
4195 }
4196
Joerg Roedela130e692015-08-13 11:07:25 +02004197 ret = -ENOMEM;
4198 data = kzalloc(sizeof(*data), GFP_KERNEL);
4199 if (!data)
4200 goto out_free_data;
4201
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004202 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4203 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4204 else
4205 data->entry = kzalloc(sizeof(struct irte_ga),
4206 GFP_KERNEL);
4207 if (!data->entry) {
4208 kfree(data);
4209 goto out_free_data;
4210 }
4211
Jiang Liu7c71d302015-04-13 14:11:33 +08004212 irq_data->hwirq = (devid << 16) + i;
4213 irq_data->chip_data = data;
4214 irq_data->chip = &amd_ir_chip;
4215 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4216 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4217 }
Joerg Roedela130e692015-08-13 11:07:25 +02004218
Jiang Liu7c71d302015-04-13 14:11:33 +08004219 return 0;
4220
4221out_free_data:
4222 for (i--; i >= 0; i--) {
4223 irq_data = irq_domain_get_irq_data(domain, virq + i);
4224 if (irq_data)
4225 kfree(irq_data->chip_data);
4226 }
4227 for (i = 0; i < nr_irqs; i++)
4228 free_irte(devid, index + i);
4229out_free_parent:
4230 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4231 return ret;
4232}
4233
4234static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4235 unsigned int nr_irqs)
4236{
4237 struct irq_2_irte *irte_info;
4238 struct irq_data *irq_data;
4239 struct amd_ir_data *data;
4240 int i;
4241
4242 for (i = 0; i < nr_irqs; i++) {
4243 irq_data = irq_domain_get_irq_data(domain, virq + i);
4244 if (irq_data && irq_data->chip_data) {
4245 data = irq_data->chip_data;
4246 irte_info = &data->irq_2_irte;
4247 free_irte(irte_info->devid, irte_info->index);
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004248 kfree(data->entry);
Jiang Liu7c71d302015-04-13 14:11:33 +08004249 kfree(data);
4250 }
4251 }
4252 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4253}
4254
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004255static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4256 struct amd_ir_data *ir_data,
4257 struct irq_2_irte *irte_info,
4258 struct irq_cfg *cfg);
4259
Thomas Gleixner72491642017-09-13 23:29:10 +02004260static int irq_remapping_activate(struct irq_domain *domain,
Thomas Gleixner702cb0a2017-12-29 16:59:06 +01004261 struct irq_data *irq_data, bool reserve)
Jiang Liu7c71d302015-04-13 14:11:33 +08004262{
4263 struct amd_ir_data *data = irq_data->chip_data;
4264 struct irq_2_irte *irte_info = &data->irq_2_irte;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004265 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004266 struct irq_cfg *cfg = irqd_cfg(irq_data);
Jiang Liu7c71d302015-04-13 14:11:33 +08004267
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004268 if (!iommu)
4269 return 0;
4270
4271 iommu->irte_ops->activate(data->entry, irte_info->devid,
4272 irte_info->index);
4273 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
Thomas Gleixner72491642017-09-13 23:29:10 +02004274 return 0;
Jiang Liu7c71d302015-04-13 14:11:33 +08004275}
4276
4277static void irq_remapping_deactivate(struct irq_domain *domain,
4278 struct irq_data *irq_data)
4279{
4280 struct amd_ir_data *data = irq_data->chip_data;
4281 struct irq_2_irte *irte_info = &data->irq_2_irte;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004282 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
Jiang Liu7c71d302015-04-13 14:11:33 +08004283
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004284 if (iommu)
4285 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4286 irte_info->index);
Jiang Liu7c71d302015-04-13 14:11:33 +08004287}
4288
Tobias Klausere2f9d452017-05-24 16:31:16 +02004289static const struct irq_domain_ops amd_ir_domain_ops = {
Jiang Liu7c71d302015-04-13 14:11:33 +08004290 .alloc = irq_remapping_alloc,
4291 .free = irq_remapping_free,
4292 .activate = irq_remapping_activate,
4293 .deactivate = irq_remapping_deactivate,
4294};
4295
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05004296static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4297{
4298 struct amd_iommu *iommu;
4299 struct amd_iommu_pi_data *pi_data = vcpu_info;
4300 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4301 struct amd_ir_data *ir_data = data->chip_data;
4302 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4303 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
Suravee Suthikulpanitd98de492016-08-23 13:52:40 -05004304 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4305
4306 /* Note:
4307 * This device has never been set up for guest mode.
4308 * we should not modify the IRTE
4309 */
4310 if (!dev_data || !dev_data->use_vapic)
4311 return 0;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05004312
4313 pi_data->ir_data = ir_data;
4314
4315 /* Note:
4316 * SVM tries to set up for VAPIC mode, but we are in
4317 * legacy mode. So, we force legacy mode instead.
4318 */
4319 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4320 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4321 __func__);
4322 pi_data->is_guest_mode = false;
4323 }
4324
4325 iommu = amd_iommu_rlookup_table[irte_info->devid];
4326 if (iommu == NULL)
4327 return -EINVAL;
4328
4329 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4330 if (pi_data->is_guest_mode) {
4331 /* Setting */
4332 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4333 irte->hi.fields.vector = vcpu_pi_info->vector;
Suravee Suthikulpanitefe6f242017-07-05 21:29:59 -05004334 irte->lo.fields_vapic.ga_log_intr = 1;
Suravee Suthikulpanitb9fc6b52016-08-23 13:52:39 -05004335 irte->lo.fields_vapic.guest_mode = 1;
4336 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4337
4338 ir_data->cached_ga_tag = pi_data->ga_tag;
4339 } else {
4340 /* Un-Setting */
4341 struct irq_cfg *cfg = irqd_cfg(data);
4342
4343 irte->hi.val = 0;
4344 irte->lo.val = 0;
4345 irte->hi.fields.vector = cfg->vector;
4346 irte->lo.fields_remap.guest_mode = 0;
4347 irte->lo.fields_remap.destination = cfg->dest_apicid;
4348 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4349 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4350
4351 /*
4352 * This communicates the ga_tag back to the caller
4353 * so that it can do all the necessary clean up.
4354 */
4355 ir_data->cached_ga_tag = 0;
4356 }
4357
4358 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4359}
4360
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004361
4362static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4363 struct amd_ir_data *ir_data,
4364 struct irq_2_irte *irte_info,
4365 struct irq_cfg *cfg)
4366{
4367
4368 /*
4369 * Atomically updates the IRTE with the new destination, vector
4370 * and flushes the interrupt entry cache.
4371 */
4372 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4373 irte_info->index, cfg->vector,
4374 cfg->dest_apicid);
4375}
4376
Jiang Liu7c71d302015-04-13 14:11:33 +08004377static int amd_ir_set_affinity(struct irq_data *data,
4378 const struct cpumask *mask, bool force)
4379{
4380 struct amd_ir_data *ir_data = data->chip_data;
4381 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4382 struct irq_cfg *cfg = irqd_cfg(data);
4383 struct irq_data *parent = data->parent_data;
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004384 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
Jiang Liu7c71d302015-04-13 14:11:33 +08004385 int ret;
4386
Suravee Suthikulpanit77bdab42016-08-23 13:52:35 -05004387 if (!iommu)
4388 return -ENODEV;
4389
Jiang Liu7c71d302015-04-13 14:11:33 +08004390 ret = parent->chip->irq_set_affinity(parent, mask, force);
4391 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4392 return ret;
4393
Thomas Gleixner5ba204a2017-09-13 23:29:48 +02004394 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
Jiang Liu7c71d302015-04-13 14:11:33 +08004395 /*
4396 * After this point, all the interrupts will start arriving
4397 * at the new destination. So, time to cleanup the previous
4398 * vector allocation.
4399 */
Jiang Liuc6c20022015-04-14 10:30:02 +08004400 send_cleanup_vector(cfg);
Jiang Liu7c71d302015-04-13 14:11:33 +08004401
4402 return IRQ_SET_MASK_OK_DONE;
4403}
4404
4405static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4406{
4407 struct amd_ir_data *ir_data = irq_data->chip_data;
4408
4409 *msg = ir_data->msi_entry;
4410}
4411
4412static struct irq_chip amd_ir_chip = {
Thomas Gleixner290be192017-06-20 01:37:02 +02004413 .name = "AMD-IR",
Thomas Gleixner8a2b7d12018-06-04 17:33:56 +02004414 .irq_ack = apic_ack_irq,
Thomas Gleixner290be192017-06-20 01:37:02 +02004415 .irq_set_affinity = amd_ir_set_affinity,
4416 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4417 .irq_compose_msi_msg = ir_compose_msi_msg,
Jiang Liu7c71d302015-04-13 14:11:33 +08004418};
4419
4420int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4421{
Thomas Gleixner3e49a812017-06-20 01:37:12 +02004422 struct fwnode_handle *fn;
4423
4424 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4425 if (!fn)
4426 return -ENOMEM;
4427 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4428 irq_domain_free_fwnode(fn);
Jiang Liu7c71d302015-04-13 14:11:33 +08004429 if (!iommu->ir_domain)
4430 return -ENOMEM;
4431
4432 iommu->ir_domain->parent = arch_get_ir_parent_domain();
Thomas Gleixner3e49a812017-06-20 01:37:12 +02004433 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4434 "AMD-IR-MSI",
4435 iommu->index);
Jiang Liu7c71d302015-04-13 14:11:33 +08004436 return 0;
4437}
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004438
4439int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4440{
4441 unsigned long flags;
4442 struct amd_iommu *iommu;
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004443 struct irq_remap_table *table;
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004444 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4445 int devid = ir_data->irq_2_irte.devid;
4446 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4447 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4448
4449 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4450 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4451 return 0;
4452
4453 iommu = amd_iommu_rlookup_table[devid];
4454 if (!iommu)
4455 return -ENODEV;
4456
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004457 table = get_irq_table(devid);
4458 if (!table)
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004459 return -ENODEV;
4460
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004461 raw_spin_lock_irqsave(&table->lock, flags);
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004462
4463 if (ref->lo.fields_vapic.guest_mode) {
4464 if (cpu >= 0)
4465 ref->lo.fields_vapic.destination = cpu;
4466 ref->lo.fields_vapic.is_run = is_run;
4467 barrier();
4468 }
4469
Sebastian Andrzej Siewior4fde5412018-03-22 16:22:38 +01004470 raw_spin_unlock_irqrestore(&table->lock, flags);
Suravee Suthikulpanit8dbea3f2016-08-23 13:52:38 -05004471
4472 iommu_flush_irt(iommu, devid);
4473 iommu_completion_wait(iommu);
4474 return 0;
4475}
4476EXPORT_SYMBOL(amd_iommu_update_ga);
Joerg Roedel2b324502012-06-21 16:29:10 +02004477#endif