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Jayachandran C65040e22011-11-16 00:21:28 +00001/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/kernel.h>
37#include <linux/mm.h>
38#include <linux/delay.h>
39
40#include <asm/mipsregs.h>
41#include <asm/time.h>
42
Jayachandran C77ae7982012-10-31 12:01:39 +000043#include <asm/netlogic/common.h>
Jayachandran C65040e22011-11-16 00:21:28 +000044#include <asm/netlogic/haldefs.h>
45#include <asm/netlogic/xlp-hal/iomap.h>
46#include <asm/netlogic/xlp-hal/xlp.h>
47#include <asm/netlogic/xlp-hal/pic.h>
48#include <asm/netlogic/xlp-hal/sys.h>
49
Jayachandran C65040e22011-11-16 00:21:28 +000050/* Main initialization */
Jayachandran C77ae7982012-10-31 12:01:39 +000051void nlm_node_init(int node)
Jayachandran C65040e22011-11-16 00:21:28 +000052{
Jayachandran C77ae7982012-10-31 12:01:39 +000053 struct nlm_soc_info *nodep;
54
55 nodep = nlm_get_node(node);
56 nodep->sysbase = nlm_get_sys_regbase(node);
57 nodep->picbase = nlm_get_pic_regbase(node);
58 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
59 spin_lock_init(&nodep->piclock);
Jayachandran C65040e22011-11-16 00:21:28 +000060}
61
62int nlm_irq_to_irt(int irq)
63{
Jayachandran C3c0553e2013-03-23 17:27:56 +000064 uint64_t pcibase;
65 int devoff, irt;
Jayachandran C65040e22011-11-16 00:21:28 +000066
67 switch (irq) {
68 case PIC_UART_0_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000069 devoff = XLP_IO_UART0_OFFSET(0);
70 break;
Jayachandran C65040e22011-11-16 00:21:28 +000071 case PIC_UART_1_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000072 devoff = XLP_IO_UART1_OFFSET(0);
73 break;
Ganesan Ramalingam10041652012-07-24 17:28:54 +020074 case PIC_EHCI_0_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000075 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
76 break;
Ganesan Ramalingam10041652012-07-24 17:28:54 +020077 case PIC_EHCI_1_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000078 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
79 break;
Ganesan Ramalingam10041652012-07-24 17:28:54 +020080 case PIC_OHCI_0_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000081 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
82 break;
Ganesan Ramalingam10041652012-07-24 17:28:54 +020083 case PIC_OHCI_1_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000084 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
85 break;
Ganesan Ramalingam10041652012-07-24 17:28:54 +020086 case PIC_OHCI_2_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000087 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
88 break;
Ganesan Ramalingam10041652012-07-24 17:28:54 +020089 case PIC_OHCI_3_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000090 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
91 break;
Jayachandran C57d7cdb2012-07-24 17:28:54 +020092 case PIC_MMC_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000093 devoff = XLP_IO_SD_OFFSET(0);
94 break;
Jayachandran C57d7cdb2012-07-24 17:28:54 +020095 case PIC_I2C_0_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000096 devoff = XLP_IO_I2C0_OFFSET(0);
97 break;
Jayachandran C57d7cdb2012-07-24 17:28:54 +020098 case PIC_I2C_1_IRQ:
Jayachandran C3c0553e2013-03-23 17:27:56 +000099 devoff = XLP_IO_I2C1_OFFSET(0);
100 break;
Jayachandran C65040e22011-11-16 00:21:28 +0000101 default:
Jayachandran C3c0553e2013-03-23 17:27:56 +0000102 devoff = 0;
103 break;
Jayachandran C65040e22011-11-16 00:21:28 +0000104 }
Jayachandran C3c0553e2013-03-23 17:27:56 +0000105
106 if (devoff != 0) {
107 pcibase = nlm_pcicfg_base(devoff);
108 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
109 /* HW bug, I2C 1 irt entry is off by one */
110 if (irq == PIC_I2C_1_IRQ)
111 irt = irt + 1;
112 } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
113 /* HW bug, PCI IRT entries are bad on early silicon, fix */
114 irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);
115 } else {
116 irt = -1;
117 }
118 return irt;
Jayachandran C65040e22011-11-16 00:21:28 +0000119}
120
Jayachandran C77ae7982012-10-31 12:01:39 +0000121unsigned int nlm_get_core_frequency(int node, int core)
Jayachandran C65040e22011-11-16 00:21:28 +0000122{
Jayachandran C2aa54b22011-11-16 00:21:29 +0000123 unsigned int pll_divf, pll_divr, dfs_div, ext_div;
124 unsigned int rstval, dfsval, denom;
Jayachandran C77ae7982012-10-31 12:01:39 +0000125 uint64_t num, sysbase;
Jayachandran C65040e22011-11-16 00:21:28 +0000126
Jayachandran C77ae7982012-10-31 12:01:39 +0000127 sysbase = nlm_get_node(node)->sysbase;
128 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
129 dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
Jayachandran C2aa54b22011-11-16 00:21:29 +0000130 pll_divf = ((rstval >> 10) & 0x7f) + 1;
131 pll_divr = ((rstval >> 8) & 0x3) + 1;
Ralf Baechle70342282013-01-22 12:59:30 +0100132 ext_div = ((rstval >> 30) & 0x3) + 1;
133 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
Jayachandran C65040e22011-11-16 00:21:28 +0000134
Jayachandran C2aa54b22011-11-16 00:21:29 +0000135 num = 800000000ULL * pll_divf;
136 denom = 3 * pll_divr * ext_div * dfs_div;
Jayachandran C65040e22011-11-16 00:21:28 +0000137 do_div(num, denom);
138 return (unsigned int)num;
139}
Jayachandran C2aa54b22011-11-16 00:21:29 +0000140
141unsigned int nlm_get_cpu_frequency(void)
142{
Jayachandran C77ae7982012-10-31 12:01:39 +0000143 return nlm_get_core_frequency(0, 0);
Jayachandran C2aa54b22011-11-16 00:21:29 +0000144}