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review.shift-gmbh.com / SHIFTPHONES / kernel / common / dccb6e8d02d44407ab2d673732bc4ec0c0766713 / . / include / acpi / cppc_acpi.h
blob: a6a9373ab8634ec737b39f6061d4d7140778240c [file] [log] [blame]
Thomas Gleixnerb886d832019-06-01 10:08:55 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]2/*
3 * CPPC (Collaborative Processor Performance Control) methods used
4 * by CPUfreq drivers.
5 *
6 * (C) Copyright 2014, 2015 Linaro Ltd.
7 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]8 */
9
10#ifndef _CPPC_ACPI_H
11#define _CPPC_ACPI_H
12
13#include <linux/acpi.h>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]14#include <linux/types.h>
15
Hoan Tran866ae692016-06-16 14:09:38 -0700[diff] [blame]16#include <acpi/pcc.h>
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]17#include <acpi/processor.h>
18
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]19/* Support CPPCv2 and CPPCv3 */
20#define CPPC_V2_REV 2
21#define CPPC_V3_REV 3
22#define CPPC_V2_NUM_ENT 21
23#define CPPC_V3_NUM_ENT 23
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]24
Prakash, Prashanth139aee72016-08-16 14:39:44 -0600[diff] [blame]25#define PCC_CMD_COMPLETE_MASK (1 << 0)
26#define PCC_ERROR_MASK (1 << 2)
27
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]28#define MAX_CPC_REG_ENT 21
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]29
30/* CPPC specific PCC commands. */
31#define CMD_READ 0
32#define CMD_WRITE 1
33
34/* Each register has the folowing format. */
35struct cpc_reg {
36 u8 descriptor;
37 u16 length;
38 u8 space_id;
39 u8 bit_width;
40 u8 bit_offset;
41 u8 access_width;
42 u64 __iomem address;
43} __packed;
44
45/*
46 * Each entry in the CPC table is either
47 * of type ACPI_TYPE_BUFFER or
48 * ACPI_TYPE_INTEGER.
49 */
50struct cpc_register_resource {
51 acpi_object_type type;
Ashwin Chaugule5bbb86a2016-08-16 14:39:38 -0600[diff] [blame]52 u64 __iomem *sys_mem_vaddr;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]53 union {
54 struct cpc_reg reg;
55 u64 int_value;
56 } cpc_entry;
57};
58
59/* Container to hold the CPC details for each CPU */
60struct cpc_desc {
61 int num_entries;
62 int version;
63 int cpu_id;
Prakash, Prashanth80b82862016-08-16 14:39:40 -0600[diff] [blame]64 int write_cmd_status;
65 int write_cmd_id;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]66 struct cpc_register_resource cpc_regs[MAX_CPC_REG_ENT];
67 struct acpi_psd_package domain_info;
Ashwin Chaugule158c9982016-08-16 14:39:42 -0600[diff] [blame]68 struct kobject kobj;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]69};
70
71/* These are indexes into the per-cpu cpc_regs[]. Order is important. */
72enum cppc_regs {
73 HIGHEST_PERF,
74 NOMINAL_PERF,
75 LOW_NON_LINEAR_PERF,
76 LOWEST_PERF,
77 GUARANTEED_PERF,
78 DESIRED_PERF,
79 MIN_PERF,
80 MAX_PERF,
81 PERF_REDUC_TOLERANCE,
82 TIME_WINDOW,
83 CTR_WRAP_TIME,
84 REFERENCE_CTR,
85 DELIVERED_CTR,
86 PERF_LIMITED,
87 ENABLE,
88 AUTO_SEL_ENABLE,
89 AUTO_ACT_WINDOW,
90 ENERGY_PERF,
91 REFERENCE_PERF,
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]92 LOWEST_FREQ,
93 NOMINAL_FREQ,
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]94};
95
96/*
97 * Categorization of registers as described
98 * in the ACPI v.5.1 spec.
99 * XXX: Only filling up ones which are used by governors
100 * today.
101 */
102struct cppc_perf_caps {
Srinivas Pandruvada29523f02018-10-15 10:37:19 -0700[diff] [blame]103 u32 guaranteed_perf;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]104 u32 highest_perf;
105 u32 nominal_perf;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]106 u32 lowest_perf;
Prakash, Prashanth368520a2017-03-29 13:49:59 -0600[diff] [blame]107 u32 lowest_nonlinear_perf;
Prashanth Prakash4773e772018-04-04 12:14:50 -0600[diff] [blame]108 u32 lowest_freq;
109 u32 nominal_freq;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]110};
111
112struct cppc_perf_ctrls {
113 u32 max_perf;
114 u32 min_perf;
115 u32 desired_perf;
116};
117
118struct cppc_perf_fb_ctrs {
119 u64 reference;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]120 u64 delivered;
Ashwin Chaugule158c9982016-08-16 14:39:42 -0600[diff] [blame]121 u64 reference_perf;
Prakash, Prashanth2c74d842017-03-29 13:50:00 -0600[diff] [blame]122 u64 wraparound_time;
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]123};
124
125/* Per CPU container for runtime CPPC management. */
Srinivas Pandruvada41dd6402016-09-01 13:37:11 -0700[diff] [blame]126struct cppc_cpudata {
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]127 int cpu;
128 struct cppc_perf_caps perf_caps;
129 struct cppc_perf_ctrls perf_ctrls;
130 struct cppc_perf_fb_ctrs perf_fb_ctrs;
131 struct cpufreq_policy *cur_policy;
132 unsigned int shared_type;
133 cpumask_var_t shared_cpu_map;
134};
135
Xiongfeng Wang1757d052019-02-17 11:54:14 +0800[diff] [blame]136extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf);
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]137extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs);
138extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
139extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps);
Srinivas Pandruvada41dd6402016-09-01 13:37:11 -0700[diff] [blame]140extern int acpi_get_psd_map(struct cppc_cpudata **);
Prakash, Prashanthbe8b88d2016-08-16 14:39:41 -0600[diff] [blame]141extern unsigned int cppc_get_transition_latency(int cpu);
Borislav Petkovad3bc252018-12-05 00:34:56 +0100[diff] [blame]142extern bool cpc_ffh_supported(void);
143extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
144extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]145
Ashwin Chaugule337aadf2015-10-02 10:01:19 -0400[diff] [blame]146#endif /* _CPPC_ACPI_H*/