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Thomas Gleixnercaab2772019-06-03 07:44:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Marc Zyngier092bd142012-12-17 17:07:52 +00002/*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
Marc Zyngier092bd142012-12-17 17:07:52 +00005 */
6
Andrew Scull04e4caa2020-09-15 11:46:42 +01007#include <linux/arm-smccc.h>
Marc Zyngier092bd142012-12-17 17:07:52 +00008#include <linux/linkage.h>
9
Will Deacon5f1f7f62020-06-30 13:53:07 +010010#include <asm/alternative.h>
Marc Zyngier092bd142012-12-17 17:07:52 +000011#include <asm/assembler.h>
12#include <asm/kvm_arm.h>
Andrew Scull04e4caa2020-09-15 11:46:42 +010013#include <asm/kvm_asm.h>
Marc Zyngier092bd142012-12-17 17:07:52 +000014#include <asm/kvm_mmu.h>
Ard Biesheuvele4c5a682015-03-19 16:42:28 +000015#include <asm/pgtable-hwdef.h>
Geoff Levande7227d02016-04-27 17:47:01 +010016#include <asm/sysreg.h>
Marc Zyngierfb1b4e02017-04-03 19:37:40 +010017#include <asm/virt.h>
Marc Zyngier092bd142012-12-17 17:07:52 +000018
19 .text
20 .pushsection .hyp.idmap.text, "ax"
21
22 .align 11
23
Mark Brown617a2f32020-02-18 19:58:37 +000024SYM_CODE_START(__kvm_hyp_init)
Marc Zyngier092bd142012-12-17 17:07:52 +000025 ventry __invalid // Synchronous EL2t
26 ventry __invalid // IRQ EL2t
27 ventry __invalid // FIQ EL2t
28 ventry __invalid // Error EL2t
29
30 ventry __invalid // Synchronous EL2h
31 ventry __invalid // IRQ EL2h
32 ventry __invalid // FIQ EL2h
33 ventry __invalid // Error EL2h
34
35 ventry __do_hyp_init // Synchronous 64-bit EL1
36 ventry __invalid // IRQ 64-bit EL1
37 ventry __invalid // FIQ 64-bit EL1
38 ventry __invalid // Error 64-bit EL1
39
40 ventry __invalid // Synchronous 32-bit EL1
41 ventry __invalid // IRQ 32-bit EL1
42 ventry __invalid // FIQ 32-bit EL1
43 ventry __invalid // Error 32-bit EL1
44
45__invalid:
46 b .
47
48 /*
Andrew Scull04e4caa2020-09-15 11:46:42 +010049 * x0: SMCCC function ID
50 * x1: HYP pgd
51 * x2: per-CPU offset
52 * x3: HYP stack
53 * x4: HYP vectors
Marc Zyngier092bd142012-12-17 17:07:52 +000054 */
55__do_hyp_init:
Marc Zyngierfb1b4e02017-04-03 19:37:40 +010056 /* Check for a stub HVC call */
57 cmp x0, #HVC_STUB_HCALL_NR
58 b.lo __kvm_handle_stub_hvc
Marc Zyngier092bd142012-12-17 17:07:52 +000059
Marc Zyngier28e81c62020-10-26 09:51:09 +000060 // We only actively check bits [24:31], and everything
61 // else has to be zero, which we check at build time.
62#if (KVM_HOST_SMCCC_FUNC(__kvm_hyp_init) & 0xFFFFFFFF00FFFFFF)
63#error Unexpected __KVM_HOST_SMCCC_FUNC___kvm_hyp_init value
64#endif
Marc Zyngier092bd142012-12-17 17:07:52 +000065
Marc Zyngier28e81c62020-10-26 09:51:09 +000066 ror x0, x0, #24
67 eor x0, x0, #((KVM_HOST_SMCCC_FUNC(__kvm_hyp_init) >> 24) & 0xF)
68 ror x0, x0, #4
69 eor x0, x0, #((KVM_HOST_SMCCC_FUNC(__kvm_hyp_init) >> 28) & 0xF)
70 cbz x0, 1f
Andrew Scull04e4caa2020-09-15 11:46:42 +010071 mov x0, #SMCCC_RET_NOT_SUPPORTED
72 eret
73
Marc Zyngier28e81c62020-10-26 09:51:09 +0000741:
75 /* Set tpidr_el2 for use by HYP to free a register */
76 msr tpidr_el2, x2
77
78 phys_to_ttbr x0, x1
Andrew Scull04e4caa2020-09-15 11:46:42 +010079alternative_if ARM64_HAS_CNP
80 orr x0, x0, #TTBR_CNP_BIT
81alternative_else_nop_endif
82 msr ttbr0_el2, x0
83
84 mrs x0, tcr_el1
85 mov_q x1, TCR_EL2_MASK
86 and x0, x0, x1
87 mov x1, #TCR_EL2_RES1
88 orr x0, x0, x1
Ard Biesheuvele4c5a682015-03-19 16:42:28 +000089
Ard Biesheuvele4c5a682015-03-19 16:42:28 +000090 /*
Kristina Martsenkofa2a8442017-12-13 17:07:24 +000091 * The ID map may be configured to use an extended virtual address
92 * range. This is only the case if system RAM is out of range for the
93 * currently configured page size and VA_BITS, in which case we will
94 * also need the extended virtual range for the HYP ID map, or we won't
95 * be able to enable the EL2 MMU.
Ard Biesheuvele4c5a682015-03-19 16:42:28 +000096 *
97 * However, at EL2, there is only one TTBR register, and we can't switch
98 * between translation tables *and* update TCR_EL2.T0SZ at the same
Kristina Martsenkofa2a8442017-12-13 17:07:24 +000099 * time. Bottom line: we need to use the extended range with *both* our
100 * translation tables.
Ard Biesheuvele4c5a682015-03-19 16:42:28 +0000101 *
102 * So use the same T0SZ value we use for the ID map.
103 */
Andrew Scull04e4caa2020-09-15 11:46:42 +0100104 ldr_l x1, idmap_t0sz
105 bfi x0, x1, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
Kristina Martsenkofa2a8442017-12-13 17:07:24 +0000106
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -0800107 /*
Kristina Martsenko787fd1d2017-12-13 17:07:17 +0000108 * Set the PS bits in TCR_EL2.
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -0800109 */
Andrew Scull04e4caa2020-09-15 11:46:42 +0100110 tcr_compute_pa_size x0, #TCR_EL2_PS_SHIFT, x1, x2
Tirumalesh Chalamarla3c5b1d92016-02-10 10:46:53 -0800111
Andrew Scull04e4caa2020-09-15 11:46:42 +0100112 msr tcr_el2, x0
Marc Zyngier092bd142012-12-17 17:07:52 +0000113
Andrew Scull04e4caa2020-09-15 11:46:42 +0100114 mrs x0, mair_el1
115 msr mair_el2, x0
Marc Zyngier092bd142012-12-17 17:07:52 +0000116 isb
117
Pranavkumar Sawargaonkarf6edbbf2014-07-31 12:23:23 +0530118 /* Invalidate the stale TLBs from Bootloader */
119 tlbi alle2
120 dsb sy
121
Marc Zyngierd68c1f7f2017-06-06 19:08:33 +0100122 /*
123 * Preserve all the RES1 bits while setting the default flags,
Marc Zyngier78fd6dc2017-06-06 19:08:34 +0100124 * as well as the EE bit on BE. Drop the A flag since the compiler
125 * is allowed to generate unaligned accesses.
Marc Zyngierd68c1f7f2017-06-06 19:08:33 +0100126 */
Andrew Scull04e4caa2020-09-15 11:46:42 +0100127 mov_q x0, (SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))
128CPU_BE( orr x0, x0, #SCTLR_ELx_EE)
Marc Zyngier4a95a1b2020-06-11 11:54:01 +0100129alternative_if ARM64_HAS_ADDRESS_AUTH
Andrew Scull04e4caa2020-09-15 11:46:42 +0100130 mov_q x1, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | \
Marc Zyngier4a95a1b2020-06-11 11:54:01 +0100131 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB)
Andrew Scull04e4caa2020-09-15 11:46:42 +0100132 orr x0, x0, x1
Marc Zyngier4a95a1b2020-06-11 11:54:01 +0100133alternative_else_nop_endif
Andrew Scull04e4caa2020-09-15 11:46:42 +0100134 msr sctlr_el2, x0
Marc Zyngier092bd142012-12-17 17:07:52 +0000135 isb
136
Marc Zyngier092bd142012-12-17 17:07:52 +0000137 /* Set the stack and new vectors */
Andrew Scull04e4caa2020-09-15 11:46:42 +0100138 mov sp, x3
139 msr vbar_el2, x4
James Morse1f742672018-01-08 15:38:07 +0000140
Marc Zyngier092bd142012-12-17 17:07:52 +0000141 /* Hello, World! */
Andrew Scull04e4caa2020-09-15 11:46:42 +0100142 mov x0, #SMCCC_RET_SUCCESS
Marc Zyngier092bd142012-12-17 17:07:52 +0000143 eret
Mark Brown617a2f32020-02-18 19:58:37 +0000144SYM_CODE_END(__kvm_hyp_init)
Marc Zyngier092bd142012-12-17 17:07:52 +0000145
Mark Brown617a2f32020-02-18 19:58:37 +0000146SYM_CODE_START(__kvm_handle_stub_hvc)
Marc Zyngier0b51c542017-04-03 19:38:04 +0100147 cmp x0, #HVC_SOFT_RESTART
Marc Zyngier506c3722017-04-03 19:37:44 +0100148 b.ne 1f
149
150 /* This is where we're about to jump, staying at EL2 */
151 msr elr_el2, x1
152 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT | PSR_MODE_EL2h)
153 msr spsr_el2, x0
154
155 /* Shuffle the arguments, and don't come back */
156 mov x0, x2
157 mov x1, x3
158 mov x2, x4
159 b reset
160
Marc Zyngier82529d92017-04-03 19:37:41 +01001611: cmp x0, #HVC_RESET_VECTORS
Marc Zyngierfb1b4e02017-04-03 19:37:40 +0100162 b.ne 1f
Andrew Scullb9e10d42020-07-06 10:52:59 +0100163
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100164 /*
Andrew Scullb9e10d42020-07-06 10:52:59 +0100165 * Set the HVC_RESET_VECTORS return code before entering the common
166 * path so that we do not clobber x0-x2 in case we are coming via
167 * HVC_SOFT_RESTART.
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100168 */
Andrew Scullb9e10d42020-07-06 10:52:59 +0100169 mov x0, xzr
170reset:
171 /* Reset kvm back to the hyp stub. */
Marc Zyngier506c3722017-04-03 19:37:44 +0100172 mrs x5, sctlr_el2
Remi Denis-Courmontdc374b42020-03-04 11:36:31 +0200173 mov_q x6, SCTLR_ELx_FLAGS
Marc Zyngier506c3722017-04-03 19:37:44 +0100174 bic x5, x5, x6 // Clear SCTL_M and etc
Shanker Donthineni3060e9f2018-01-29 11:59:52 +0000175 pre_disable_mmu_workaround
Marc Zyngier506c3722017-04-03 19:37:44 +0100176 msr sctlr_el2, x5
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100177 isb
178
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100179 /* Install stub vectors */
Marc Zyngier506c3722017-04-03 19:37:44 +0100180 adr_l x5, __hyp_stub_vectors
181 msr vbar_el2, x5
Marc Zyngieraf42f202017-04-03 19:38:05 +0100182 eret
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100183
Marc Zyngierfb1b4e02017-04-03 19:37:40 +01001841: /* Bad stub call */
Remi Denis-Courmontdc374b42020-03-04 11:36:31 +0200185 mov_q x0, HVC_STUB_ERR
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100186 eret
Marc Zyngieraf42f202017-04-03 19:38:05 +0100187
Mark Brown617a2f32020-02-18 19:58:37 +0000188SYM_CODE_END(__kvm_handle_stub_hvc)
AKASHI Takahiro67f69192016-04-27 17:47:05 +0100189
Marc Zyngier092bd142012-12-17 17:07:52 +0000190 .popsection