Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * intelfb |
| 3 | * |
| 4 | * Linux framebuffer driver for Intel(R) 865G integrated graphics chips. |
| 5 | * |
| 6 | * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org> |
| 7 | * 2004 Sylvain Meyer |
| 8 | * |
| 9 | * This driver consists of two parts. The first part (intelfbdrv.c) provides |
| 10 | * the basic fbdev interfaces, is derived in part from the radeonfb and |
| 11 | * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c) |
| 12 | * provides the code to program the hardware. Most of it is derived from |
| 13 | * the i810/i830 XFree86 driver. The HW-specific code is covered here |
| 14 | * under a dual license (GPL and MIT/XFree86 license). |
| 15 | * |
| 16 | * Author: David Dawes |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */ |
| 21 | |
| 22 | #include <linux/config.h> |
| 23 | #include <linux/module.h> |
| 24 | #include <linux/kernel.h> |
| 25 | #include <linux/errno.h> |
| 26 | #include <linux/string.h> |
| 27 | #include <linux/mm.h> |
| 28 | #include <linux/tty.h> |
| 29 | #include <linux/slab.h> |
| 30 | #include <linux/delay.h> |
| 31 | #include <linux/fb.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <linux/ioport.h> |
| 33 | #include <linux/init.h> |
| 34 | #include <linux/pci.h> |
| 35 | #include <linux/vmalloc.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | #include <linux/pagemap.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
| 38 | #include <asm/io.h> |
| 39 | |
| 40 | #include "intelfb.h" |
| 41 | #include "intelfbhw.h" |
| 42 | |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 43 | struct pll_min_max { |
| 44 | int min_m, max_m; |
| 45 | int min_m1, max_m1; |
| 46 | int min_m2, max_m2; |
| 47 | int min_n, max_n; |
| 48 | int min_p, max_p; |
| 49 | int min_p1, max_p1; |
| 50 | int min_vco_freq, max_vco_freq; |
| 51 | int p_transition_clock; |
| 52 | }; |
| 53 | |
| 54 | #define PLLS_I8xx 0 |
| 55 | #define PLLS_I9xx 1 |
| 56 | #define PLLS_MAX 2 |
| 57 | |
| 58 | struct pll_min_max plls[PLLS_MAX] = { |
| 59 | { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000 }, //I8xx |
| 60 | { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000 } //I9xx |
| 61 | }; |
| 62 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 63 | int |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 64 | intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 65 | { |
| 66 | u32 tmp; |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 67 | if (!pdev || !dinfo) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | return 1; |
| 69 | |
| 70 | switch (pdev->device) { |
| 71 | case PCI_DEVICE_ID_INTEL_830M: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 72 | dinfo->name = "Intel(R) 830M"; |
| 73 | dinfo->chipset = INTEL_830M; |
| 74 | dinfo->mobile = 1; |
| 75 | dinfo->pll_index = PLLS_I8xx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 76 | return 0; |
| 77 | case PCI_DEVICE_ID_INTEL_845G: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 78 | dinfo->name = "Intel(R) 845G"; |
| 79 | dinfo->chipset = INTEL_845G; |
| 80 | dinfo->mobile = 0; |
| 81 | dinfo->pll_index = PLLS_I8xx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 82 | return 0; |
| 83 | case PCI_DEVICE_ID_INTEL_85XGM: |
| 84 | tmp = 0; |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 85 | dinfo->mobile = 1; |
| 86 | dinfo->pll_index = PLLS_I8xx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp); |
| 88 | switch ((tmp >> INTEL_85X_VARIANT_SHIFT) & |
| 89 | INTEL_85X_VARIANT_MASK) { |
| 90 | case INTEL_VAR_855GME: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 91 | dinfo->name = "Intel(R) 855GME"; |
| 92 | dinfo->chipset = INTEL_855GME; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | return 0; |
| 94 | case INTEL_VAR_855GM: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 95 | dinfo->name = "Intel(R) 855GM"; |
| 96 | dinfo->chipset = INTEL_855GM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | return 0; |
| 98 | case INTEL_VAR_852GME: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 99 | dinfo->name = "Intel(R) 852GME"; |
| 100 | dinfo->chipset = INTEL_852GME; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 101 | return 0; |
| 102 | case INTEL_VAR_852GM: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 103 | dinfo->name = "Intel(R) 852GM"; |
| 104 | dinfo->chipset = INTEL_852GM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | return 0; |
| 106 | default: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 107 | dinfo->name = "Intel(R) 852GM/855GM"; |
| 108 | dinfo->chipset = INTEL_85XGM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | return 0; |
| 110 | } |
| 111 | break; |
| 112 | case PCI_DEVICE_ID_INTEL_865G: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 113 | dinfo->name = "Intel(R) 865G"; |
| 114 | dinfo->chipset = INTEL_865G; |
| 115 | dinfo->mobile = 0; |
| 116 | dinfo->pll_index = PLLS_I8xx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | return 0; |
| 118 | case PCI_DEVICE_ID_INTEL_915G: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 119 | dinfo->name = "Intel(R) 915G"; |
| 120 | dinfo->chipset = INTEL_915G; |
| 121 | dinfo->mobile = 0; |
| 122 | dinfo->pll_index = PLLS_I9xx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 123 | return 0; |
Scott MacKenzie | 3a59026 | 2005-11-07 01:00:33 -0800 | [diff] [blame] | 124 | case PCI_DEVICE_ID_INTEL_915GM: |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 125 | dinfo->name = "Intel(R) 915GM"; |
| 126 | dinfo->chipset = INTEL_915GM; |
| 127 | dinfo->mobile = 1; |
| 128 | dinfo->pll_index = PLLS_I9xx; |
Scott MacKenzie | 3a59026 | 2005-11-07 01:00:33 -0800 | [diff] [blame] | 129 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | default: |
| 131 | return 1; |
| 132 | } |
| 133 | } |
| 134 | |
| 135 | int |
| 136 | intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size, |
| 137 | int *stolen_size) |
| 138 | { |
| 139 | struct pci_dev *bridge_dev; |
| 140 | u16 tmp; |
| 141 | |
| 142 | if (!pdev || !aperture_size || !stolen_size) |
| 143 | return 1; |
| 144 | |
| 145 | /* Find the bridge device. It is always 0:0.0 */ |
| 146 | if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) { |
| 147 | ERR_MSG("cannot find bridge device\n"); |
| 148 | return 1; |
| 149 | } |
| 150 | |
| 151 | /* Get the fb aperture size and "stolen" memory amount. */ |
| 152 | tmp = 0; |
| 153 | pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); |
| 154 | switch (pdev->device) { |
| 155 | case PCI_DEVICE_ID_INTEL_830M: |
| 156 | case PCI_DEVICE_ID_INTEL_845G: |
| 157 | if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) |
| 158 | *aperture_size = MB(64); |
| 159 | else |
| 160 | *aperture_size = MB(128); |
| 161 | switch (tmp & INTEL_830_GMCH_GMS_MASK) { |
| 162 | case INTEL_830_GMCH_GMS_STOLEN_512: |
| 163 | *stolen_size = KB(512) - KB(132); |
| 164 | return 0; |
| 165 | case INTEL_830_GMCH_GMS_STOLEN_1024: |
| 166 | *stolen_size = MB(1) - KB(132); |
| 167 | return 0; |
| 168 | case INTEL_830_GMCH_GMS_STOLEN_8192: |
| 169 | *stolen_size = MB(8) - KB(132); |
| 170 | return 0; |
| 171 | case INTEL_830_GMCH_GMS_LOCAL: |
| 172 | ERR_MSG("only local memory found\n"); |
| 173 | return 1; |
| 174 | case INTEL_830_GMCH_GMS_DISABLED: |
| 175 | ERR_MSG("video memory is disabled\n"); |
| 176 | return 1; |
| 177 | default: |
| 178 | ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n", |
| 179 | tmp & INTEL_830_GMCH_GMS_MASK); |
| 180 | return 1; |
| 181 | } |
| 182 | break; |
| 183 | default: |
| 184 | *aperture_size = MB(128); |
| 185 | switch (tmp & INTEL_855_GMCH_GMS_MASK) { |
| 186 | case INTEL_855_GMCH_GMS_STOLEN_1M: |
| 187 | *stolen_size = MB(1) - KB(132); |
| 188 | return 0; |
| 189 | case INTEL_855_GMCH_GMS_STOLEN_4M: |
| 190 | *stolen_size = MB(4) - KB(132); |
| 191 | return 0; |
| 192 | case INTEL_855_GMCH_GMS_STOLEN_8M: |
| 193 | *stolen_size = MB(8) - KB(132); |
| 194 | return 0; |
| 195 | case INTEL_855_GMCH_GMS_STOLEN_16M: |
| 196 | *stolen_size = MB(16) - KB(132); |
| 197 | return 0; |
| 198 | case INTEL_855_GMCH_GMS_STOLEN_32M: |
| 199 | *stolen_size = MB(32) - KB(132); |
| 200 | return 0; |
| 201 | case INTEL_915G_GMCH_GMS_STOLEN_48M: |
| 202 | *stolen_size = MB(48) - KB(132); |
| 203 | return 0; |
| 204 | case INTEL_915G_GMCH_GMS_STOLEN_64M: |
| 205 | *stolen_size = MB(64) - KB(132); |
| 206 | return 0; |
| 207 | case INTEL_855_GMCH_GMS_DISABLED: |
| 208 | ERR_MSG("video memory is disabled\n"); |
| 209 | return 0; |
| 210 | default: |
| 211 | ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n", |
| 212 | tmp & INTEL_855_GMCH_GMS_MASK); |
| 213 | return 1; |
| 214 | } |
| 215 | } |
| 216 | } |
| 217 | |
| 218 | int |
| 219 | intelfbhw_check_non_crt(struct intelfb_info *dinfo) |
| 220 | { |
| 221 | int dvo = 0; |
| 222 | |
| 223 | if (INREG(LVDS) & PORT_ENABLE) |
| 224 | dvo |= LVDS_PORT; |
| 225 | if (INREG(DVOA) & PORT_ENABLE) |
| 226 | dvo |= DVOA_PORT; |
| 227 | if (INREG(DVOB) & PORT_ENABLE) |
| 228 | dvo |= DVOB_PORT; |
| 229 | if (INREG(DVOC) & PORT_ENABLE) |
| 230 | dvo |= DVOC_PORT; |
| 231 | |
| 232 | return dvo; |
| 233 | } |
| 234 | |
| 235 | const char * |
| 236 | intelfbhw_dvo_to_string(int dvo) |
| 237 | { |
| 238 | if (dvo & DVOA_PORT) |
| 239 | return "DVO port A"; |
| 240 | else if (dvo & DVOB_PORT) |
| 241 | return "DVO port B"; |
| 242 | else if (dvo & DVOC_PORT) |
| 243 | return "DVO port C"; |
| 244 | else if (dvo & LVDS_PORT) |
| 245 | return "LVDS port"; |
| 246 | else |
| 247 | return NULL; |
| 248 | } |
| 249 | |
| 250 | |
| 251 | int |
| 252 | intelfbhw_validate_mode(struct intelfb_info *dinfo, |
| 253 | struct fb_var_screeninfo *var) |
| 254 | { |
| 255 | int bytes_per_pixel; |
| 256 | int tmp; |
| 257 | |
| 258 | #if VERBOSE > 0 |
| 259 | DBG_MSG("intelfbhw_validate_mode\n"); |
| 260 | #endif |
| 261 | |
| 262 | bytes_per_pixel = var->bits_per_pixel / 8; |
| 263 | if (bytes_per_pixel == 3) |
| 264 | bytes_per_pixel = 4; |
| 265 | |
| 266 | /* Check if enough video memory. */ |
| 267 | tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel; |
| 268 | if (tmp > dinfo->fb.size) { |
| 269 | WRN_MSG("Not enough video ram for mode " |
| 270 | "(%d KByte vs %d KByte).\n", |
| 271 | BtoKB(tmp), BtoKB(dinfo->fb.size)); |
| 272 | return 1; |
| 273 | } |
| 274 | |
| 275 | /* Check if x/y limits are OK. */ |
| 276 | if (var->xres - 1 > HACTIVE_MASK) { |
| 277 | WRN_MSG("X resolution too large (%d vs %d).\n", |
| 278 | var->xres, HACTIVE_MASK + 1); |
| 279 | return 1; |
| 280 | } |
| 281 | if (var->yres - 1 > VACTIVE_MASK) { |
| 282 | WRN_MSG("Y resolution too large (%d vs %d).\n", |
| 283 | var->yres, VACTIVE_MASK + 1); |
| 284 | return 1; |
| 285 | } |
| 286 | |
| 287 | /* Check for interlaced/doublescan modes. */ |
| 288 | if (var->vmode & FB_VMODE_INTERLACED) { |
| 289 | WRN_MSG("Mode is interlaced.\n"); |
| 290 | return 1; |
| 291 | } |
| 292 | if (var->vmode & FB_VMODE_DOUBLE) { |
| 293 | WRN_MSG("Mode is double-scan.\n"); |
| 294 | return 1; |
| 295 | } |
| 296 | |
| 297 | /* Check if clock is OK. */ |
| 298 | tmp = 1000000000 / var->pixclock; |
| 299 | if (tmp < MIN_CLOCK) { |
| 300 | WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n", |
| 301 | (tmp + 500) / 1000, MIN_CLOCK / 1000); |
| 302 | return 1; |
| 303 | } |
| 304 | if (tmp > MAX_CLOCK) { |
| 305 | WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n", |
| 306 | (tmp + 500) / 1000, MAX_CLOCK / 1000); |
| 307 | return 1; |
| 308 | } |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
| 313 | int |
| 314 | intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) |
| 315 | { |
| 316 | struct intelfb_info *dinfo = GET_DINFO(info); |
| 317 | u32 offset, xoffset, yoffset; |
| 318 | |
| 319 | #if VERBOSE > 0 |
| 320 | DBG_MSG("intelfbhw_pan_display\n"); |
| 321 | #endif |
| 322 | |
| 323 | xoffset = ROUND_DOWN_TO(var->xoffset, 8); |
| 324 | yoffset = var->yoffset; |
| 325 | |
| 326 | if ((xoffset + var->xres > var->xres_virtual) || |
| 327 | (yoffset + var->yres > var->yres_virtual)) |
| 328 | return -EINVAL; |
| 329 | |
| 330 | offset = (yoffset * dinfo->pitch) + |
| 331 | (xoffset * var->bits_per_pixel) / 8; |
| 332 | |
| 333 | offset += dinfo->fb.offset << 12; |
| 334 | |
| 335 | OUTREG(DSPABASE, offset); |
| 336 | |
| 337 | return 0; |
| 338 | } |
| 339 | |
| 340 | /* Blank the screen. */ |
| 341 | void |
| 342 | intelfbhw_do_blank(int blank, struct fb_info *info) |
| 343 | { |
| 344 | struct intelfb_info *dinfo = GET_DINFO(info); |
| 345 | u32 tmp; |
| 346 | |
| 347 | #if VERBOSE > 0 |
| 348 | DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank); |
| 349 | #endif |
| 350 | |
| 351 | /* Turn plane A on or off */ |
| 352 | tmp = INREG(DSPACNTR); |
| 353 | if (blank) |
| 354 | tmp &= ~DISPPLANE_PLANE_ENABLE; |
| 355 | else |
| 356 | tmp |= DISPPLANE_PLANE_ENABLE; |
| 357 | OUTREG(DSPACNTR, tmp); |
| 358 | /* Flush */ |
| 359 | tmp = INREG(DSPABASE); |
| 360 | OUTREG(DSPABASE, tmp); |
| 361 | |
| 362 | /* Turn off/on the HW cursor */ |
| 363 | #if VERBOSE > 0 |
| 364 | DBG_MSG("cursor_on is %d\n", dinfo->cursor_on); |
| 365 | #endif |
| 366 | if (dinfo->cursor_on) { |
| 367 | if (blank) { |
| 368 | intelfbhw_cursor_hide(dinfo); |
| 369 | } else { |
| 370 | intelfbhw_cursor_show(dinfo); |
| 371 | } |
| 372 | dinfo->cursor_on = 1; |
| 373 | } |
| 374 | dinfo->cursor_blanked = blank; |
| 375 | |
| 376 | /* Set DPMS level */ |
| 377 | tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; |
| 378 | switch (blank) { |
| 379 | case FB_BLANK_UNBLANK: |
| 380 | case FB_BLANK_NORMAL: |
| 381 | tmp |= ADPA_DPMS_D0; |
| 382 | break; |
| 383 | case FB_BLANK_VSYNC_SUSPEND: |
| 384 | tmp |= ADPA_DPMS_D1; |
| 385 | break; |
| 386 | case FB_BLANK_HSYNC_SUSPEND: |
| 387 | tmp |= ADPA_DPMS_D2; |
| 388 | break; |
| 389 | case FB_BLANK_POWERDOWN: |
| 390 | tmp |= ADPA_DPMS_D3; |
| 391 | break; |
| 392 | } |
| 393 | OUTREG(ADPA, tmp); |
| 394 | |
| 395 | return; |
| 396 | } |
| 397 | |
| 398 | |
| 399 | void |
| 400 | intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno, |
| 401 | unsigned red, unsigned green, unsigned blue, |
| 402 | unsigned transp) |
| 403 | { |
| 404 | #if VERBOSE > 0 |
| 405 | DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n", |
| 406 | regno, red, green, blue); |
| 407 | #endif |
| 408 | |
| 409 | u32 palette_reg = (dinfo->pipe == PIPE_A) ? |
| 410 | PALETTE_A : PALETTE_B; |
| 411 | |
| 412 | OUTREG(palette_reg + (regno << 2), |
| 413 | (red << PALETTE_8_RED_SHIFT) | |
| 414 | (green << PALETTE_8_GREEN_SHIFT) | |
| 415 | (blue << PALETTE_8_BLUE_SHIFT)); |
| 416 | } |
| 417 | |
| 418 | |
| 419 | int |
| 420 | intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, |
| 421 | int flag) |
| 422 | { |
| 423 | int i; |
| 424 | |
| 425 | #if VERBOSE > 0 |
| 426 | DBG_MSG("intelfbhw_read_hw_state\n"); |
| 427 | #endif |
| 428 | |
| 429 | if (!hw || !dinfo) |
| 430 | return -1; |
| 431 | |
| 432 | /* Read in as much of the HW state as possible. */ |
| 433 | hw->vga0_divisor = INREG(VGA0_DIVISOR); |
| 434 | hw->vga1_divisor = INREG(VGA1_DIVISOR); |
| 435 | hw->vga_pd = INREG(VGAPD); |
| 436 | hw->dpll_a = INREG(DPLL_A); |
| 437 | hw->dpll_b = INREG(DPLL_B); |
| 438 | hw->fpa0 = INREG(FPA0); |
| 439 | hw->fpa1 = INREG(FPA1); |
| 440 | hw->fpb0 = INREG(FPB0); |
| 441 | hw->fpb1 = INREG(FPB1); |
| 442 | |
| 443 | if (flag == 1) |
| 444 | return flag; |
| 445 | |
| 446 | #if 0 |
| 447 | /* This seems to be a problem with the 852GM/855GM */ |
| 448 | for (i = 0; i < PALETTE_8_ENTRIES; i++) { |
| 449 | hw->palette_a[i] = INREG(PALETTE_A + (i << 2)); |
| 450 | hw->palette_b[i] = INREG(PALETTE_B + (i << 2)); |
| 451 | } |
| 452 | #endif |
| 453 | |
| 454 | if (flag == 2) |
| 455 | return flag; |
| 456 | |
| 457 | hw->htotal_a = INREG(HTOTAL_A); |
| 458 | hw->hblank_a = INREG(HBLANK_A); |
| 459 | hw->hsync_a = INREG(HSYNC_A); |
| 460 | hw->vtotal_a = INREG(VTOTAL_A); |
| 461 | hw->vblank_a = INREG(VBLANK_A); |
| 462 | hw->vsync_a = INREG(VSYNC_A); |
| 463 | hw->src_size_a = INREG(SRC_SIZE_A); |
| 464 | hw->bclrpat_a = INREG(BCLRPAT_A); |
| 465 | hw->htotal_b = INREG(HTOTAL_B); |
| 466 | hw->hblank_b = INREG(HBLANK_B); |
| 467 | hw->hsync_b = INREG(HSYNC_B); |
| 468 | hw->vtotal_b = INREG(VTOTAL_B); |
| 469 | hw->vblank_b = INREG(VBLANK_B); |
| 470 | hw->vsync_b = INREG(VSYNC_B); |
| 471 | hw->src_size_b = INREG(SRC_SIZE_B); |
| 472 | hw->bclrpat_b = INREG(BCLRPAT_B); |
| 473 | |
| 474 | if (flag == 3) |
| 475 | return flag; |
| 476 | |
| 477 | hw->adpa = INREG(ADPA); |
| 478 | hw->dvoa = INREG(DVOA); |
| 479 | hw->dvob = INREG(DVOB); |
| 480 | hw->dvoc = INREG(DVOC); |
| 481 | hw->dvoa_srcdim = INREG(DVOA_SRCDIM); |
| 482 | hw->dvob_srcdim = INREG(DVOB_SRCDIM); |
| 483 | hw->dvoc_srcdim = INREG(DVOC_SRCDIM); |
| 484 | hw->lvds = INREG(LVDS); |
| 485 | |
| 486 | if (flag == 4) |
| 487 | return flag; |
| 488 | |
| 489 | hw->pipe_a_conf = INREG(PIPEACONF); |
| 490 | hw->pipe_b_conf = INREG(PIPEBCONF); |
| 491 | hw->disp_arb = INREG(DISPARB); |
| 492 | |
| 493 | if (flag == 5) |
| 494 | return flag; |
| 495 | |
| 496 | hw->cursor_a_control = INREG(CURSOR_A_CONTROL); |
| 497 | hw->cursor_b_control = INREG(CURSOR_B_CONTROL); |
| 498 | hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); |
| 499 | hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); |
| 500 | |
| 501 | if (flag == 6) |
| 502 | return flag; |
| 503 | |
| 504 | for (i = 0; i < 4; i++) { |
| 505 | hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); |
| 506 | hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); |
| 507 | } |
| 508 | |
| 509 | if (flag == 7) |
| 510 | return flag; |
| 511 | |
| 512 | hw->cursor_size = INREG(CURSOR_SIZE); |
| 513 | |
| 514 | if (flag == 8) |
| 515 | return flag; |
| 516 | |
| 517 | hw->disp_a_ctrl = INREG(DSPACNTR); |
| 518 | hw->disp_b_ctrl = INREG(DSPBCNTR); |
| 519 | hw->disp_a_base = INREG(DSPABASE); |
| 520 | hw->disp_b_base = INREG(DSPBBASE); |
| 521 | hw->disp_a_stride = INREG(DSPASTRIDE); |
| 522 | hw->disp_b_stride = INREG(DSPBSTRIDE); |
| 523 | |
| 524 | if (flag == 9) |
| 525 | return flag; |
| 526 | |
| 527 | hw->vgacntrl = INREG(VGACNTRL); |
| 528 | |
| 529 | if (flag == 10) |
| 530 | return flag; |
| 531 | |
| 532 | hw->add_id = INREG(ADD_ID); |
| 533 | |
| 534 | if (flag == 11) |
| 535 | return flag; |
| 536 | |
| 537 | for (i = 0; i < 7; i++) { |
| 538 | hw->swf0x[i] = INREG(SWF00 + (i << 2)); |
| 539 | hw->swf1x[i] = INREG(SWF10 + (i << 2)); |
| 540 | if (i < 3) |
| 541 | hw->swf3x[i] = INREG(SWF30 + (i << 2)); |
| 542 | } |
| 543 | |
| 544 | for (i = 0; i < 8; i++) |
| 545 | hw->fence[i] = INREG(FENCE + (i << 2)); |
| 546 | |
| 547 | hw->instpm = INREG(INSTPM); |
| 548 | hw->mem_mode = INREG(MEM_MODE); |
| 549 | hw->fw_blc_0 = INREG(FW_BLC_0); |
| 550 | hw->fw_blc_1 = INREG(FW_BLC_1); |
| 551 | |
| 552 | return 0; |
| 553 | } |
| 554 | |
| 555 | |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 556 | static int calc_vclock3(int index, int m, int n, int p) |
| 557 | { |
| 558 | return PLL_REFCLK * m / n / p; |
| 559 | } |
| 560 | |
| 561 | static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2) |
| 562 | { |
| 563 | switch(index) |
| 564 | { |
| 565 | case PLLS_I9xx: |
| 566 | return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / |
| 567 | ((p1)) * (p2 ? 10 : 5))); |
| 568 | case PLLS_I8xx: |
| 569 | default: |
| 570 | return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / |
| 571 | ((p1+2) * (1 << (p2 + 1))))); |
| 572 | } |
| 573 | } |
| 574 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | void |
| 576 | intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw) |
| 577 | { |
| 578 | #if REGDUMP |
| 579 | int i, m1, m2, n, p1, p2; |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 580 | int index = dinfo->pll_index; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 581 | DBG_MSG("intelfbhw_print_hw_state\n"); |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 582 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | if (!hw || !dinfo) |
| 584 | return; |
| 585 | /* Read in as much of the HW state as possible. */ |
| 586 | printk("hw state dump start\n"); |
| 587 | printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor); |
| 588 | printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor); |
| 589 | printk(" VGAPD: 0x%08x\n", hw->vga_pd); |
| 590 | n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 591 | m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 592 | m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 593 | if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2) |
| 594 | p1 = 0; |
| 595 | else |
| 596 | p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK; |
| 597 | p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK; |
| 598 | printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 599 | m1, m2, n, p1, p2); |
| 600 | printk(" VGA0: clock is %d\n", |
| 601 | calc_vclock(index, m1, m2, n, p1, p2)); |
| 602 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 603 | n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 604 | m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 605 | m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 606 | if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2) |
| 607 | p1 = 0; |
| 608 | else |
| 609 | p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK; |
| 610 | p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK; |
| 611 | printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 612 | m1, m2, n, p1, p2); |
| 613 | printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); |
| 614 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | printk(" DPLL_A: 0x%08x\n", hw->dpll_a); |
| 616 | printk(" DPLL_B: 0x%08x\n", hw->dpll_b); |
| 617 | printk(" FPA0: 0x%08x\n", hw->fpa0); |
| 618 | printk(" FPA1: 0x%08x\n", hw->fpa1); |
| 619 | printk(" FPB0: 0x%08x\n", hw->fpb0); |
| 620 | printk(" FPB1: 0x%08x\n", hw->fpb1); |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 621 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 623 | m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 624 | m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 625 | if (hw->dpll_a & DPLL_P1_FORCE_DIV2) |
| 626 | p1 = 0; |
| 627 | else |
| 628 | p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; |
| 629 | p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; |
| 630 | printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 631 | m1, m2, n, p1, p2); |
| 632 | printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); |
| 633 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 635 | m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 636 | m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; |
| 637 | if (hw->dpll_a & DPLL_P1_FORCE_DIV2) |
| 638 | p1 = 0; |
| 639 | else |
| 640 | p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK; |
| 641 | p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK; |
| 642 | printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 643 | m1, m2, n, p1, p2); |
| 644 | printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2)); |
| 645 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | #if 0 |
| 647 | printk(" PALETTE_A:\n"); |
| 648 | for (i = 0; i < PALETTE_8_ENTRIES) |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 649 | printk(" %3d: 0x%08x\n", i, hw->palette_a[i]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | printk(" PALETTE_B:\n"); |
| 651 | for (i = 0; i < PALETTE_8_ENTRIES) |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 652 | printk(" %3d: 0x%08x\n", i, hw->palette_b[i]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | #endif |
| 654 | |
| 655 | printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); |
| 656 | printk(" HBLANK_A: 0x%08x\n", hw->hblank_a); |
| 657 | printk(" HSYNC_A: 0x%08x\n", hw->hsync_a); |
| 658 | printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a); |
| 659 | printk(" VBLANK_A: 0x%08x\n", hw->vblank_a); |
| 660 | printk(" VSYNC_A: 0x%08x\n", hw->vsync_a); |
| 661 | printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a); |
| 662 | printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a); |
| 663 | printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b); |
| 664 | printk(" HBLANK_B: 0x%08x\n", hw->hblank_b); |
| 665 | printk(" HSYNC_B: 0x%08x\n", hw->hsync_b); |
| 666 | printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b); |
| 667 | printk(" VBLANK_B: 0x%08x\n", hw->vblank_b); |
| 668 | printk(" VSYNC_B: 0x%08x\n", hw->vsync_b); |
| 669 | printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b); |
| 670 | printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b); |
| 671 | |
| 672 | printk(" ADPA: 0x%08x\n", hw->adpa); |
| 673 | printk(" DVOA: 0x%08x\n", hw->dvoa); |
| 674 | printk(" DVOB: 0x%08x\n", hw->dvob); |
| 675 | printk(" DVOC: 0x%08x\n", hw->dvoc); |
| 676 | printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim); |
| 677 | printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim); |
| 678 | printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim); |
| 679 | printk(" LVDS: 0x%08x\n", hw->lvds); |
| 680 | |
| 681 | printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf); |
| 682 | printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf); |
| 683 | printk(" DISPARB: 0x%08x\n", hw->disp_arb); |
| 684 | |
| 685 | printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control); |
| 686 | printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control); |
| 687 | printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base); |
| 688 | printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base); |
| 689 | |
| 690 | printk(" CURSOR_A_PALETTE: "); |
| 691 | for (i = 0; i < 4; i++) { |
| 692 | printk("0x%08x", hw->cursor_a_palette[i]); |
| 693 | if (i < 3) |
| 694 | printk(", "); |
| 695 | } |
| 696 | printk("\n"); |
| 697 | printk(" CURSOR_B_PALETTE: "); |
| 698 | for (i = 0; i < 4; i++) { |
| 699 | printk("0x%08x", hw->cursor_b_palette[i]); |
| 700 | if (i < 3) |
| 701 | printk(", "); |
| 702 | } |
| 703 | printk("\n"); |
| 704 | |
| 705 | printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size); |
| 706 | |
| 707 | printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl); |
| 708 | printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl); |
| 709 | printk(" DSPABASE: 0x%08x\n", hw->disp_a_base); |
| 710 | printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base); |
| 711 | printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride); |
| 712 | printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride); |
| 713 | |
| 714 | printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl); |
| 715 | printk(" ADD_ID: 0x%08x\n", hw->add_id); |
| 716 | |
| 717 | for (i = 0; i < 7; i++) { |
| 718 | printk(" SWF0%d 0x%08x\n", i, |
| 719 | hw->swf0x[i]); |
| 720 | } |
| 721 | for (i = 0; i < 7; i++) { |
| 722 | printk(" SWF1%d 0x%08x\n", i, |
| 723 | hw->swf1x[i]); |
| 724 | } |
| 725 | for (i = 0; i < 3; i++) { |
| 726 | printk(" SWF3%d 0x%08x\n", i, |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 727 | hw->swf3x[i]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 728 | } |
| 729 | for (i = 0; i < 8; i++) |
| 730 | printk(" FENCE%d 0x%08x\n", i, |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 731 | hw->fence[i]); |
| 732 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | printk(" INSTPM 0x%08x\n", hw->instpm); |
| 734 | printk(" MEM_MODE 0x%08x\n", hw->mem_mode); |
| 735 | printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); |
| 736 | printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1); |
| 737 | |
| 738 | printk("hw state dump end\n"); |
| 739 | #endif |
| 740 | } |
| 741 | |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 742 | |
| 743 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 744 | /* Split the M parameter into M1 and M2. */ |
| 745 | static int |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 746 | splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | { |
| 748 | int m1, m2; |
| 749 | |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 750 | m1 = (m - 2 - (plls[index].min_m1 + plls[index].max_m2) / 2) / 5 - 2; |
| 751 | if (m1 < plls[index].min_m1) |
| 752 | m1 = plls[index].min_m1; |
| 753 | if (m1 > plls[index].max_m1) |
| 754 | m1 = plls[index].max_m1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | m2 = m - 5 * (m1 + 2) - 2; |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 756 | if (m2 < plls[index].min_m2 || m2 > plls[index].max_m2 || m2 >= m1) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 757 | return 1; |
| 758 | } else { |
| 759 | *retm1 = (unsigned int)m1; |
| 760 | *retm2 = (unsigned int)m2; |
| 761 | return 0; |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | /* Split the P parameter into P1 and P2. */ |
| 766 | static int |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 767 | splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 768 | { |
| 769 | int p1, p2; |
| 770 | |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 771 | if (index == PLLS_I9xx) |
| 772 | { |
| 773 | p1 = (p / 10) + 1; |
| 774 | p2 = 0; |
| 775 | |
| 776 | *retp1 = (unsigned int)p1; |
| 777 | *retp2 = (unsigned int)p2; |
| 778 | return 0; |
| 779 | } |
| 780 | |
| 781 | if (index == PLLS_I8xx) |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 782 | { |
| 783 | if (p % 4 == 0) |
| 784 | p2 = 1; |
| 785 | else |
| 786 | p2 = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | p1 = (p / (1 << (p2 + 1))) - 2; |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 788 | if (p % 4 == 0 && p1 < plls[index].min_p1) { |
| 789 | p2 = 0; |
| 790 | p1 = (p / (1 << (p2 + 1))) - 2; |
| 791 | } |
| 792 | if (p1 < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) { |
| 793 | return 1; |
| 794 | } else { |
| 795 | *retp1 = (unsigned int)p1; |
| 796 | *retp2 = (unsigned int)p2; |
| 797 | return 0; |
| 798 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | } |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 800 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | } |
| 802 | |
| 803 | static int |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 804 | calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 805 | u32 *retp2, u32 *retclock) |
| 806 | { |
| 807 | u32 m1, m2, n, p1, p2, n1; |
| 808 | u32 f_vco, p, p_best = 0, m, f_out; |
| 809 | u32 err_max, err_target, err_best = 10000000; |
| 810 | u32 n_best = 0, m_best = 0, f_best, f_err; |
| 811 | u32 p_min, p_max, p_inc, div_min, div_max; |
| 812 | |
| 813 | /* Accept 0.5% difference, but aim for 0.1% */ |
| 814 | err_max = 5 * clock / 1000; |
| 815 | err_target = clock / 1000; |
| 816 | |
| 817 | DBG_MSG("Clock is %d\n", clock); |
| 818 | |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 819 | div_max = plls[index].max_vco_freq / clock; |
| 820 | div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 821 | |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 822 | if (clock <= plls[index].p_transition_clock) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | p_inc = 4; |
| 824 | else |
| 825 | p_inc = 2; |
| 826 | p_min = ROUND_UP_TO(div_min, p_inc); |
| 827 | p_max = ROUND_DOWN_TO(div_max, p_inc); |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 828 | if (p_min < plls[index].min_p) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 829 | p_min = 4; |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 830 | if (p_max > plls[index].max_p) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 831 | p_max = 128; |
| 832 | |
| 833 | DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc); |
| 834 | |
| 835 | p = p_min; |
| 836 | do { |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 837 | if (splitp(index, p, &p1, &p2)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 838 | WRN_MSG("cannot split p = %d\n", p); |
| 839 | p += p_inc; |
| 840 | continue; |
| 841 | } |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 842 | n = plls[index].min_n; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 843 | f_vco = clock * p; |
| 844 | |
| 845 | do { |
| 846 | m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK; |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 847 | if (m < plls[index].min_m) |
| 848 | m = plls[index].min_m; |
| 849 | if (m > plls[index].max_m) |
| 850 | m = plls[index].max_m; |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 851 | f_out = calc_vclock3(index, m, n, p); |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 852 | if (splitm(index, m, &m1, &m2)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 853 | WRN_MSG("cannot split m = %d\n", m); |
| 854 | n++; |
| 855 | continue; |
| 856 | } |
| 857 | if (clock > f_out) |
| 858 | f_err = clock - f_out; |
| 859 | else |
| 860 | f_err = f_out - clock; |
| 861 | |
| 862 | if (f_err < err_best) { |
| 863 | m_best = m; |
| 864 | n_best = n; |
| 865 | p_best = p; |
| 866 | f_best = f_out; |
| 867 | err_best = f_err; |
| 868 | } |
| 869 | n++; |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 870 | } while ((n <= plls[index].max_n) && (f_out >= clock)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | p += p_inc; |
| 872 | } while ((p <= p_max)); |
| 873 | |
| 874 | if (!m_best) { |
| 875 | WRN_MSG("cannot find parameters for clock %d\n", clock); |
| 876 | return 1; |
| 877 | } |
| 878 | m = m_best; |
| 879 | n = n_best; |
| 880 | p = p_best; |
Dave Airlie | 7258b11 | 2006-03-20 20:02:24 +1100 | [diff] [blame] | 881 | splitm(index, m, &m1, &m2); |
| 882 | splitp(index, p, &p1, &p2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 883 | n1 = n - 2; |
| 884 | |
| 885 | DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), " |
| 886 | "f: %d (%d), VCO: %d\n", |
| 887 | m, m1, m2, n, n1, p, p1, p2, |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 888 | calc_vclock3(index, m, n, p), |
| 889 | calc_vclock(index, m1, m2, n1, p1, p2), |
| 890 | calc_vclock3(index, m, n, p) * p); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | *retm1 = m1; |
| 892 | *retm2 = m2; |
| 893 | *retn = n1; |
| 894 | *retp1 = p1; |
| 895 | *retp2 = p2; |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 896 | *retclock = calc_vclock(index, m1, m2, n1, p1, p2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 897 | |
| 898 | return 0; |
| 899 | } |
| 900 | |
| 901 | static __inline__ int |
| 902 | check_overflow(u32 value, u32 limit, const char *description) |
| 903 | { |
| 904 | if (value > limit) { |
| 905 | WRN_MSG("%s value %d exceeds limit %d\n", |
| 906 | description, value, limit); |
| 907 | return 1; |
| 908 | } |
| 909 | return 0; |
| 910 | } |
| 911 | |
| 912 | /* It is assumed that hw is filled in with the initial state information. */ |
| 913 | int |
| 914 | intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw, |
| 915 | struct fb_var_screeninfo *var) |
| 916 | { |
| 917 | int pipe = PIPE_A; |
| 918 | u32 *dpll, *fp0, *fp1; |
| 919 | u32 m1, m2, n, p1, p2, clock_target, clock; |
| 920 | u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive; |
| 921 | u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive; |
| 922 | u32 vsync_pol, hsync_pol; |
| 923 | u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf; |
| 924 | |
| 925 | DBG_MSG("intelfbhw_mode_to_hw\n"); |
| 926 | |
| 927 | /* Disable VGA */ |
| 928 | hw->vgacntrl |= VGA_DISABLE; |
| 929 | |
| 930 | /* Check whether pipe A or pipe B is enabled. */ |
| 931 | if (hw->pipe_a_conf & PIPECONF_ENABLE) |
| 932 | pipe = PIPE_A; |
| 933 | else if (hw->pipe_b_conf & PIPECONF_ENABLE) |
| 934 | pipe = PIPE_B; |
| 935 | |
| 936 | /* Set which pipe's registers will be set. */ |
| 937 | if (pipe == PIPE_B) { |
| 938 | dpll = &hw->dpll_b; |
| 939 | fp0 = &hw->fpb0; |
| 940 | fp1 = &hw->fpb1; |
| 941 | hs = &hw->hsync_b; |
| 942 | hb = &hw->hblank_b; |
| 943 | ht = &hw->htotal_b; |
| 944 | vs = &hw->vsync_b; |
| 945 | vb = &hw->vblank_b; |
| 946 | vt = &hw->vtotal_b; |
| 947 | ss = &hw->src_size_b; |
| 948 | pipe_conf = &hw->pipe_b_conf; |
| 949 | } else { |
| 950 | dpll = &hw->dpll_a; |
| 951 | fp0 = &hw->fpa0; |
| 952 | fp1 = &hw->fpa1; |
| 953 | hs = &hw->hsync_a; |
| 954 | hb = &hw->hblank_a; |
| 955 | ht = &hw->htotal_a; |
| 956 | vs = &hw->vsync_a; |
| 957 | vb = &hw->vblank_a; |
| 958 | vt = &hw->vtotal_a; |
| 959 | ss = &hw->src_size_a; |
| 960 | pipe_conf = &hw->pipe_a_conf; |
| 961 | } |
| 962 | |
| 963 | /* Use ADPA register for sync control. */ |
| 964 | hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY; |
| 965 | |
| 966 | /* sync polarity */ |
| 967 | hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ? |
| 968 | ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW; |
| 969 | vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ? |
| 970 | ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW; |
| 971 | hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) | |
| 972 | (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT)); |
| 973 | hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) | |
| 974 | (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT); |
| 975 | |
| 976 | /* Connect correct pipe to the analog port DAC */ |
| 977 | hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT); |
| 978 | hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT); |
| 979 | |
| 980 | /* Set DPMS state to D0 (on) */ |
| 981 | hw->adpa &= ~ADPA_DPMS_CONTROL_MASK; |
| 982 | hw->adpa |= ADPA_DPMS_D0; |
| 983 | |
| 984 | hw->adpa |= ADPA_DAC_ENABLE; |
| 985 | |
| 986 | *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); |
| 987 | *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK); |
| 988 | *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0); |
| 989 | |
| 990 | /* Desired clock in kHz */ |
| 991 | clock_target = 1000000000 / var->pixclock; |
| 992 | |
Dave Airlie | d024960 | 2006-03-20 20:26:45 +1100 | [diff] [blame^] | 993 | if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 994 | WRN_MSG("calc_pll_params failed\n"); |
| 995 | return 1; |
| 996 | } |
| 997 | |
| 998 | /* Check for overflow. */ |
| 999 | if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter")) |
| 1000 | return 1; |
| 1001 | if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter")) |
| 1002 | return 1; |
| 1003 | if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter")) |
| 1004 | return 1; |
| 1005 | if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter")) |
| 1006 | return 1; |
| 1007 | if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter")) |
| 1008 | return 1; |
| 1009 | |
| 1010 | *dpll &= ~DPLL_P1_FORCE_DIV2; |
| 1011 | *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) | |
| 1012 | (DPLL_P1_MASK << DPLL_P1_SHIFT)); |
| 1013 | *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT); |
| 1014 | *fp0 = (n << FP_N_DIVISOR_SHIFT) | |
| 1015 | (m1 << FP_M1_DIVISOR_SHIFT) | |
| 1016 | (m2 << FP_M2_DIVISOR_SHIFT); |
| 1017 | *fp1 = *fp0; |
| 1018 | |
| 1019 | hw->dvob &= ~PORT_ENABLE; |
| 1020 | hw->dvoc &= ~PORT_ENABLE; |
| 1021 | |
| 1022 | /* Use display plane A. */ |
| 1023 | hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE; |
| 1024 | hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE; |
| 1025 | hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK; |
| 1026 | switch (intelfb_var_to_depth(var)) { |
| 1027 | case 8: |
| 1028 | hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE; |
| 1029 | break; |
| 1030 | case 15: |
| 1031 | hw->disp_a_ctrl |= DISPPLANE_15_16BPP; |
| 1032 | break; |
| 1033 | case 16: |
| 1034 | hw->disp_a_ctrl |= DISPPLANE_16BPP; |
| 1035 | break; |
| 1036 | case 24: |
| 1037 | hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA; |
| 1038 | break; |
| 1039 | } |
| 1040 | hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT); |
| 1041 | hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT); |
| 1042 | |
| 1043 | /* Set CRTC registers. */ |
| 1044 | hactive = var->xres; |
| 1045 | hsync_start = hactive + var->right_margin; |
| 1046 | hsync_end = hsync_start + var->hsync_len; |
| 1047 | htotal = hsync_end + var->left_margin; |
| 1048 | hblank_start = hactive; |
| 1049 | hblank_end = htotal; |
| 1050 | |
| 1051 | DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n", |
| 1052 | hactive, hsync_start, hsync_end, htotal, hblank_start, |
| 1053 | hblank_end); |
| 1054 | |
| 1055 | vactive = var->yres; |
| 1056 | vsync_start = vactive + var->lower_margin; |
| 1057 | vsync_end = vsync_start + var->vsync_len; |
| 1058 | vtotal = vsync_end + var->upper_margin; |
| 1059 | vblank_start = vactive; |
| 1060 | vblank_end = vtotal; |
| 1061 | vblank_end = vsync_end + 1; |
| 1062 | |
| 1063 | DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n", |
| 1064 | vactive, vsync_start, vsync_end, vtotal, vblank_start, |
| 1065 | vblank_end); |
| 1066 | |
| 1067 | /* Adjust for register values, and check for overflow. */ |
| 1068 | hactive--; |
| 1069 | if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive")) |
| 1070 | return 1; |
| 1071 | hsync_start--; |
| 1072 | if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start")) |
| 1073 | return 1; |
| 1074 | hsync_end--; |
| 1075 | if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end")) |
| 1076 | return 1; |
| 1077 | htotal--; |
| 1078 | if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal")) |
| 1079 | return 1; |
| 1080 | hblank_start--; |
| 1081 | if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start")) |
| 1082 | return 1; |
| 1083 | hblank_end--; |
| 1084 | if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end")) |
| 1085 | return 1; |
| 1086 | |
| 1087 | vactive--; |
| 1088 | if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive")) |
| 1089 | return 1; |
| 1090 | vsync_start--; |
| 1091 | if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start")) |
| 1092 | return 1; |
| 1093 | vsync_end--; |
| 1094 | if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end")) |
| 1095 | return 1; |
| 1096 | vtotal--; |
| 1097 | if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal")) |
| 1098 | return 1; |
| 1099 | vblank_start--; |
| 1100 | if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start")) |
| 1101 | return 1; |
| 1102 | vblank_end--; |
| 1103 | if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end")) |
| 1104 | return 1; |
| 1105 | |
| 1106 | *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT); |
| 1107 | *hb = (hblank_start << HBLANKSTART_SHIFT) | |
| 1108 | (hblank_end << HSYNCEND_SHIFT); |
| 1109 | *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT); |
| 1110 | |
| 1111 | *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT); |
| 1112 | *vb = (vblank_start << VBLANKSTART_SHIFT) | |
| 1113 | (vblank_end << VSYNCEND_SHIFT); |
| 1114 | *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT); |
| 1115 | *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) | |
| 1116 | (vactive << SRC_SIZE_VERT_SHIFT); |
| 1117 | |
| 1118 | hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8; |
| 1119 | DBG_MSG("pitch is %d\n", hw->disp_a_stride); |
| 1120 | |
| 1121 | hw->disp_a_base = hw->disp_a_stride * var->yoffset + |
| 1122 | var->xoffset * var->bits_per_pixel / 8; |
| 1123 | |
| 1124 | hw->disp_a_base += dinfo->fb.offset << 12; |
| 1125 | |
| 1126 | /* Check stride alignment. */ |
| 1127 | if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) { |
| 1128 | WRN_MSG("display stride %d has bad alignment %d\n", |
| 1129 | hw->disp_a_stride, STRIDE_ALIGNMENT); |
| 1130 | return 1; |
| 1131 | } |
| 1132 | |
| 1133 | /* Set the palette to 8-bit mode. */ |
| 1134 | *pipe_conf &= ~PIPECONF_GAMMA; |
| 1135 | return 0; |
| 1136 | } |
| 1137 | |
| 1138 | /* Program a (non-VGA) video mode. */ |
| 1139 | int |
| 1140 | intelfbhw_program_mode(struct intelfb_info *dinfo, |
| 1141 | const struct intelfb_hwstate *hw, int blank) |
| 1142 | { |
| 1143 | int pipe = PIPE_A; |
| 1144 | u32 tmp; |
| 1145 | const u32 *dpll, *fp0, *fp1, *pipe_conf; |
| 1146 | const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss; |
| 1147 | u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg; |
| 1148 | u32 hsync_reg, htotal_reg, hblank_reg; |
| 1149 | u32 vsync_reg, vtotal_reg, vblank_reg; |
| 1150 | u32 src_size_reg; |
| 1151 | |
| 1152 | /* Assume single pipe, display plane A, analog CRT. */ |
| 1153 | |
| 1154 | #if VERBOSE > 0 |
| 1155 | DBG_MSG("intelfbhw_program_mode\n"); |
| 1156 | #endif |
| 1157 | |
| 1158 | /* Disable VGA */ |
| 1159 | tmp = INREG(VGACNTRL); |
| 1160 | tmp |= VGA_DISABLE; |
| 1161 | OUTREG(VGACNTRL, tmp); |
| 1162 | |
| 1163 | /* Check whether pipe A or pipe B is enabled. */ |
| 1164 | if (hw->pipe_a_conf & PIPECONF_ENABLE) |
| 1165 | pipe = PIPE_A; |
| 1166 | else if (hw->pipe_b_conf & PIPECONF_ENABLE) |
| 1167 | pipe = PIPE_B; |
| 1168 | |
| 1169 | dinfo->pipe = pipe; |
| 1170 | |
| 1171 | if (pipe == PIPE_B) { |
| 1172 | dpll = &hw->dpll_b; |
| 1173 | fp0 = &hw->fpb0; |
| 1174 | fp1 = &hw->fpb1; |
| 1175 | pipe_conf = &hw->pipe_b_conf; |
| 1176 | hs = &hw->hsync_b; |
| 1177 | hb = &hw->hblank_b; |
| 1178 | ht = &hw->htotal_b; |
| 1179 | vs = &hw->vsync_b; |
| 1180 | vb = &hw->vblank_b; |
| 1181 | vt = &hw->vtotal_b; |
| 1182 | ss = &hw->src_size_b; |
| 1183 | dpll_reg = DPLL_B; |
| 1184 | fp0_reg = FPB0; |
| 1185 | fp1_reg = FPB1; |
| 1186 | pipe_conf_reg = PIPEBCONF; |
| 1187 | hsync_reg = HSYNC_B; |
| 1188 | htotal_reg = HTOTAL_B; |
| 1189 | hblank_reg = HBLANK_B; |
| 1190 | vsync_reg = VSYNC_B; |
| 1191 | vtotal_reg = VTOTAL_B; |
| 1192 | vblank_reg = VBLANK_B; |
| 1193 | src_size_reg = SRC_SIZE_B; |
| 1194 | } else { |
| 1195 | dpll = &hw->dpll_a; |
| 1196 | fp0 = &hw->fpa0; |
| 1197 | fp1 = &hw->fpa1; |
| 1198 | pipe_conf = &hw->pipe_a_conf; |
| 1199 | hs = &hw->hsync_a; |
| 1200 | hb = &hw->hblank_a; |
| 1201 | ht = &hw->htotal_a; |
| 1202 | vs = &hw->vsync_a; |
| 1203 | vb = &hw->vblank_a; |
| 1204 | vt = &hw->vtotal_a; |
| 1205 | ss = &hw->src_size_a; |
| 1206 | dpll_reg = DPLL_A; |
| 1207 | fp0_reg = FPA0; |
| 1208 | fp1_reg = FPA1; |
| 1209 | pipe_conf_reg = PIPEACONF; |
| 1210 | hsync_reg = HSYNC_A; |
| 1211 | htotal_reg = HTOTAL_A; |
| 1212 | hblank_reg = HBLANK_A; |
| 1213 | vsync_reg = VSYNC_A; |
| 1214 | vtotal_reg = VTOTAL_A; |
| 1215 | vblank_reg = VBLANK_A; |
| 1216 | src_size_reg = SRC_SIZE_A; |
| 1217 | } |
| 1218 | |
| 1219 | /* Disable planes A and B. */ |
| 1220 | tmp = INREG(DSPACNTR); |
| 1221 | tmp &= ~DISPPLANE_PLANE_ENABLE; |
| 1222 | OUTREG(DSPACNTR, tmp); |
| 1223 | tmp = INREG(DSPBCNTR); |
| 1224 | tmp &= ~DISPPLANE_PLANE_ENABLE; |
| 1225 | OUTREG(DSPBCNTR, tmp); |
| 1226 | |
| 1227 | /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */ |
| 1228 | mdelay(20); |
| 1229 | |
| 1230 | /* Disable Sync */ |
| 1231 | tmp = INREG(ADPA); |
| 1232 | tmp &= ~ADPA_DPMS_CONTROL_MASK; |
| 1233 | tmp |= ADPA_DPMS_D3; |
| 1234 | OUTREG(ADPA, tmp); |
| 1235 | |
| 1236 | /* turn off pipe */ |
| 1237 | tmp = INREG(pipe_conf_reg); |
| 1238 | tmp &= ~PIPECONF_ENABLE; |
| 1239 | OUTREG(pipe_conf_reg, tmp); |
| 1240 | |
| 1241 | /* turn off PLL */ |
| 1242 | tmp = INREG(dpll_reg); |
| 1243 | dpll_reg &= ~DPLL_VCO_ENABLE; |
| 1244 | OUTREG(dpll_reg, tmp); |
| 1245 | |
| 1246 | /* Set PLL parameters */ |
| 1247 | OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE); |
| 1248 | OUTREG(fp0_reg, *fp0); |
| 1249 | OUTREG(fp1_reg, *fp1); |
| 1250 | |
| 1251 | /* Set pipe parameters */ |
| 1252 | OUTREG(hsync_reg, *hs); |
| 1253 | OUTREG(hblank_reg, *hb); |
| 1254 | OUTREG(htotal_reg, *ht); |
| 1255 | OUTREG(vsync_reg, *vs); |
| 1256 | OUTREG(vblank_reg, *vb); |
| 1257 | OUTREG(vtotal_reg, *vt); |
| 1258 | OUTREG(src_size_reg, *ss); |
| 1259 | |
| 1260 | /* Set DVOs B/C */ |
| 1261 | OUTREG(DVOB, hw->dvob); |
| 1262 | OUTREG(DVOC, hw->dvoc); |
| 1263 | |
| 1264 | /* Set ADPA */ |
| 1265 | OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); |
| 1266 | |
| 1267 | /* Enable PLL */ |
| 1268 | tmp = INREG(dpll_reg); |
| 1269 | tmp |= DPLL_VCO_ENABLE; |
| 1270 | OUTREG(dpll_reg, tmp); |
| 1271 | |
| 1272 | /* Enable pipe */ |
| 1273 | OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE); |
| 1274 | |
| 1275 | /* Enable sync */ |
| 1276 | tmp = INREG(ADPA); |
| 1277 | tmp &= ~ADPA_DPMS_CONTROL_MASK; |
| 1278 | tmp |= ADPA_DPMS_D0; |
| 1279 | OUTREG(ADPA, tmp); |
| 1280 | |
| 1281 | /* setup display plane */ |
| 1282 | if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) { |
| 1283 | /* |
| 1284 | * i830M errata: the display plane must be enabled |
| 1285 | * to allow writes to the other bits in the plane |
| 1286 | * control register. |
| 1287 | */ |
| 1288 | tmp = INREG(DSPACNTR); |
| 1289 | if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) { |
| 1290 | tmp |= DISPPLANE_PLANE_ENABLE; |
| 1291 | OUTREG(DSPACNTR, tmp); |
| 1292 | OUTREG(DSPACNTR, |
| 1293 | hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE); |
| 1294 | mdelay(1); |
| 1295 | } |
| 1296 | } |
| 1297 | |
| 1298 | OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); |
| 1299 | OUTREG(DSPASTRIDE, hw->disp_a_stride); |
| 1300 | OUTREG(DSPABASE, hw->disp_a_base); |
| 1301 | |
| 1302 | /* Enable plane */ |
| 1303 | if (!blank) { |
| 1304 | tmp = INREG(DSPACNTR); |
| 1305 | tmp |= DISPPLANE_PLANE_ENABLE; |
| 1306 | OUTREG(DSPACNTR, tmp); |
| 1307 | OUTREG(DSPABASE, hw->disp_a_base); |
| 1308 | } |
| 1309 | |
| 1310 | return 0; |
| 1311 | } |
| 1312 | |
| 1313 | /* forward declarations */ |
| 1314 | static void refresh_ring(struct intelfb_info *dinfo); |
| 1315 | static void reset_state(struct intelfb_info *dinfo); |
| 1316 | static void do_flush(struct intelfb_info *dinfo); |
| 1317 | |
| 1318 | static int |
| 1319 | wait_ring(struct intelfb_info *dinfo, int n) |
| 1320 | { |
| 1321 | int i = 0; |
| 1322 | unsigned long end; |
| 1323 | u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; |
| 1324 | |
| 1325 | #if VERBOSE > 0 |
| 1326 | DBG_MSG("wait_ring: %d\n", n); |
| 1327 | #endif |
| 1328 | |
| 1329 | end = jiffies + (HZ * 3); |
| 1330 | while (dinfo->ring_space < n) { |
| 1331 | dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) & |
| 1332 | RING_HEAD_MASK); |
| 1333 | if (dinfo->ring_tail + RING_MIN_FREE < |
| 1334 | (u32 __iomem) dinfo->ring_head) |
| 1335 | dinfo->ring_space = (u32 __iomem) dinfo->ring_head |
| 1336 | - (dinfo->ring_tail + RING_MIN_FREE); |
| 1337 | else |
| 1338 | dinfo->ring_space = (dinfo->ring.size + |
| 1339 | (u32 __iomem) dinfo->ring_head) |
| 1340 | - (dinfo->ring_tail + RING_MIN_FREE); |
| 1341 | if ((u32 __iomem) dinfo->ring_head != last_head) { |
| 1342 | end = jiffies + (HZ * 3); |
| 1343 | last_head = (u32 __iomem) dinfo->ring_head; |
| 1344 | } |
| 1345 | i++; |
| 1346 | if (time_before(end, jiffies)) { |
| 1347 | if (!i) { |
| 1348 | /* Try again */ |
| 1349 | reset_state(dinfo); |
| 1350 | refresh_ring(dinfo); |
| 1351 | do_flush(dinfo); |
| 1352 | end = jiffies + (HZ * 3); |
| 1353 | i = 1; |
| 1354 | } else { |
| 1355 | WRN_MSG("ring buffer : space: %d wanted %d\n", |
| 1356 | dinfo->ring_space, n); |
| 1357 | WRN_MSG("lockup - turning off hardware " |
| 1358 | "acceleration\n"); |
| 1359 | dinfo->ring_lockup = 1; |
| 1360 | break; |
| 1361 | } |
| 1362 | } |
| 1363 | udelay(1); |
| 1364 | } |
| 1365 | return i; |
| 1366 | } |
| 1367 | |
| 1368 | static void |
| 1369 | do_flush(struct intelfb_info *dinfo) { |
| 1370 | START_RING(2); |
| 1371 | OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); |
| 1372 | OUT_RING(MI_NOOP); |
| 1373 | ADVANCE_RING(); |
| 1374 | } |
| 1375 | |
| 1376 | void |
| 1377 | intelfbhw_do_sync(struct intelfb_info *dinfo) |
| 1378 | { |
| 1379 | #if VERBOSE > 0 |
| 1380 | DBG_MSG("intelfbhw_do_sync\n"); |
| 1381 | #endif |
| 1382 | |
| 1383 | if (!dinfo->accel) |
| 1384 | return; |
| 1385 | |
| 1386 | /* |
| 1387 | * Send a flush, then wait until the ring is empty. This is what |
| 1388 | * the XFree86 driver does, and actually it doesn't seem a lot worse |
| 1389 | * than the recommended method (both have problems). |
| 1390 | */ |
| 1391 | do_flush(dinfo); |
| 1392 | wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE); |
| 1393 | dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE; |
| 1394 | } |
| 1395 | |
| 1396 | static void |
| 1397 | refresh_ring(struct intelfb_info *dinfo) |
| 1398 | { |
| 1399 | #if VERBOSE > 0 |
| 1400 | DBG_MSG("refresh_ring\n"); |
| 1401 | #endif |
| 1402 | |
| 1403 | dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) & |
| 1404 | RING_HEAD_MASK); |
| 1405 | dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; |
| 1406 | if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head) |
| 1407 | dinfo->ring_space = (u32 __iomem) dinfo->ring_head |
| 1408 | - (dinfo->ring_tail + RING_MIN_FREE); |
| 1409 | else |
| 1410 | dinfo->ring_space = (dinfo->ring.size + |
| 1411 | (u32 __iomem) dinfo->ring_head) |
| 1412 | - (dinfo->ring_tail + RING_MIN_FREE); |
| 1413 | } |
| 1414 | |
| 1415 | static void |
| 1416 | reset_state(struct intelfb_info *dinfo) |
| 1417 | { |
| 1418 | int i; |
| 1419 | u32 tmp; |
| 1420 | |
| 1421 | #if VERBOSE > 0 |
| 1422 | DBG_MSG("reset_state\n"); |
| 1423 | #endif |
| 1424 | |
| 1425 | for (i = 0; i < FENCE_NUM; i++) |
| 1426 | OUTREG(FENCE + (i << 2), 0); |
| 1427 | |
| 1428 | /* Flush the ring buffer if it's enabled. */ |
| 1429 | tmp = INREG(PRI_RING_LENGTH); |
| 1430 | if (tmp & RING_ENABLE) { |
| 1431 | #if VERBOSE > 0 |
| 1432 | DBG_MSG("reset_state: ring was enabled\n"); |
| 1433 | #endif |
| 1434 | refresh_ring(dinfo); |
| 1435 | intelfbhw_do_sync(dinfo); |
| 1436 | DO_RING_IDLE(); |
| 1437 | } |
| 1438 | |
| 1439 | OUTREG(PRI_RING_LENGTH, 0); |
| 1440 | OUTREG(PRI_RING_HEAD, 0); |
| 1441 | OUTREG(PRI_RING_TAIL, 0); |
| 1442 | OUTREG(PRI_RING_START, 0); |
| 1443 | } |
| 1444 | |
| 1445 | /* Stop the 2D engine, and turn off the ring buffer. */ |
| 1446 | void |
| 1447 | intelfbhw_2d_stop(struct intelfb_info *dinfo) |
| 1448 | { |
| 1449 | #if VERBOSE > 0 |
| 1450 | DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel, |
| 1451 | dinfo->ring_active); |
| 1452 | #endif |
| 1453 | |
| 1454 | if (!dinfo->accel) |
| 1455 | return; |
| 1456 | |
| 1457 | dinfo->ring_active = 0; |
| 1458 | reset_state(dinfo); |
| 1459 | } |
| 1460 | |
| 1461 | /* |
| 1462 | * Enable the ring buffer, and initialise the 2D engine. |
| 1463 | * It is assumed that the graphics engine has been stopped by previously |
| 1464 | * calling intelfb_2d_stop(). |
| 1465 | */ |
| 1466 | void |
| 1467 | intelfbhw_2d_start(struct intelfb_info *dinfo) |
| 1468 | { |
| 1469 | #if VERBOSE > 0 |
| 1470 | DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n", |
| 1471 | dinfo->accel, dinfo->ring_active); |
| 1472 | #endif |
| 1473 | |
| 1474 | if (!dinfo->accel) |
| 1475 | return; |
| 1476 | |
| 1477 | /* Initialise the primary ring buffer. */ |
| 1478 | OUTREG(PRI_RING_LENGTH, 0); |
| 1479 | OUTREG(PRI_RING_TAIL, 0); |
| 1480 | OUTREG(PRI_RING_HEAD, 0); |
| 1481 | |
| 1482 | OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK); |
| 1483 | OUTREG(PRI_RING_LENGTH, |
| 1484 | ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) | |
| 1485 | RING_NO_REPORT | RING_ENABLE); |
| 1486 | refresh_ring(dinfo); |
| 1487 | dinfo->ring_active = 1; |
| 1488 | } |
| 1489 | |
| 1490 | /* 2D fillrect (solid fill or invert) */ |
| 1491 | void |
| 1492 | intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h, |
| 1493 | u32 color, u32 pitch, u32 bpp, u32 rop) |
| 1494 | { |
| 1495 | u32 br00, br09, br13, br14, br16; |
| 1496 | |
| 1497 | #if VERBOSE > 0 |
| 1498 | DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, " |
| 1499 | "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop); |
| 1500 | #endif |
| 1501 | |
| 1502 | br00 = COLOR_BLT_CMD; |
| 1503 | br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8)); |
| 1504 | br13 = (rop << ROP_SHIFT) | pitch; |
| 1505 | br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT); |
| 1506 | br16 = color; |
| 1507 | |
| 1508 | switch (bpp) { |
| 1509 | case 8: |
| 1510 | br13 |= COLOR_DEPTH_8; |
| 1511 | break; |
| 1512 | case 16: |
| 1513 | br13 |= COLOR_DEPTH_16; |
| 1514 | break; |
| 1515 | case 32: |
| 1516 | br13 |= COLOR_DEPTH_32; |
| 1517 | br00 |= WRITE_ALPHA | WRITE_RGB; |
| 1518 | break; |
| 1519 | } |
| 1520 | |
| 1521 | START_RING(6); |
| 1522 | OUT_RING(br00); |
| 1523 | OUT_RING(br13); |
| 1524 | OUT_RING(br14); |
| 1525 | OUT_RING(br09); |
| 1526 | OUT_RING(br16); |
| 1527 | OUT_RING(MI_NOOP); |
| 1528 | ADVANCE_RING(); |
| 1529 | |
| 1530 | #if VERBOSE > 0 |
| 1531 | DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head, |
| 1532 | dinfo->ring_tail, dinfo->ring_space); |
| 1533 | #endif |
| 1534 | } |
| 1535 | |
| 1536 | void |
| 1537 | intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury, |
| 1538 | u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp) |
| 1539 | { |
| 1540 | u32 br00, br09, br11, br12, br13, br22, br23, br26; |
| 1541 | |
| 1542 | #if VERBOSE > 0 |
| 1543 | DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n", |
| 1544 | curx, cury, dstx, dsty, w, h, pitch, bpp); |
| 1545 | #endif |
| 1546 | |
| 1547 | br00 = XY_SRC_COPY_BLT_CMD; |
| 1548 | br09 = dinfo->fb_start; |
| 1549 | br11 = (pitch << PITCH_SHIFT); |
| 1550 | br12 = dinfo->fb_start; |
| 1551 | br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT); |
| 1552 | br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT); |
| 1553 | br23 = ((dstx + w) << WIDTH_SHIFT) | |
| 1554 | ((dsty + h) << HEIGHT_SHIFT); |
| 1555 | br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT); |
| 1556 | |
| 1557 | switch (bpp) { |
| 1558 | case 8: |
| 1559 | br13 |= COLOR_DEPTH_8; |
| 1560 | break; |
| 1561 | case 16: |
| 1562 | br13 |= COLOR_DEPTH_16; |
| 1563 | break; |
| 1564 | case 32: |
| 1565 | br13 |= COLOR_DEPTH_32; |
| 1566 | br00 |= WRITE_ALPHA | WRITE_RGB; |
| 1567 | break; |
| 1568 | } |
| 1569 | |
| 1570 | START_RING(8); |
| 1571 | OUT_RING(br00); |
| 1572 | OUT_RING(br13); |
| 1573 | OUT_RING(br22); |
| 1574 | OUT_RING(br23); |
| 1575 | OUT_RING(br09); |
| 1576 | OUT_RING(br26); |
| 1577 | OUT_RING(br11); |
| 1578 | OUT_RING(br12); |
| 1579 | ADVANCE_RING(); |
| 1580 | } |
| 1581 | |
| 1582 | int |
| 1583 | intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w, |
| 1584 | u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp) |
| 1585 | { |
| 1586 | int nbytes, ndwords, pad, tmp; |
| 1587 | u32 br00, br09, br13, br18, br19, br22, br23; |
| 1588 | int dat, ix, iy, iw; |
| 1589 | int i, j; |
| 1590 | |
| 1591 | #if VERBOSE > 0 |
| 1592 | DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h); |
| 1593 | #endif |
| 1594 | |
| 1595 | /* size in bytes of a padded scanline */ |
| 1596 | nbytes = ROUND_UP_TO(w, 16) / 8; |
| 1597 | |
| 1598 | /* Total bytes of padded scanline data to write out. */ |
| 1599 | nbytes = nbytes * h; |
| 1600 | |
| 1601 | /* |
| 1602 | * Check if the glyph data exceeds the immediate mode limit. |
| 1603 | * It would take a large font (1K pixels) to hit this limit. |
| 1604 | */ |
| 1605 | if (nbytes > MAX_MONO_IMM_SIZE) |
| 1606 | return 0; |
| 1607 | |
| 1608 | /* Src data is packaged a dword (32-bit) at a time. */ |
| 1609 | ndwords = ROUND_UP_TO(nbytes, 4) / 4; |
| 1610 | |
| 1611 | /* |
| 1612 | * Ring has to be padded to a quad word. But because the command starts |
| 1613 | with 7 bytes, pad only if there is an even number of ndwords |
| 1614 | */ |
| 1615 | pad = !(ndwords % 2); |
| 1616 | |
| 1617 | tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords; |
| 1618 | br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp; |
| 1619 | br09 = dinfo->fb_start; |
| 1620 | br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT); |
| 1621 | br18 = bg; |
| 1622 | br19 = fg; |
| 1623 | br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT); |
| 1624 | br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT); |
| 1625 | |
| 1626 | switch (bpp) { |
| 1627 | case 8: |
| 1628 | br13 |= COLOR_DEPTH_8; |
| 1629 | break; |
| 1630 | case 16: |
| 1631 | br13 |= COLOR_DEPTH_16; |
| 1632 | break; |
| 1633 | case 32: |
| 1634 | br13 |= COLOR_DEPTH_32; |
| 1635 | br00 |= WRITE_ALPHA | WRITE_RGB; |
| 1636 | break; |
| 1637 | } |
| 1638 | |
| 1639 | START_RING(8 + ndwords); |
| 1640 | OUT_RING(br00); |
| 1641 | OUT_RING(br13); |
| 1642 | OUT_RING(br22); |
| 1643 | OUT_RING(br23); |
| 1644 | OUT_RING(br09); |
| 1645 | OUT_RING(br18); |
| 1646 | OUT_RING(br19); |
| 1647 | ix = iy = 0; |
| 1648 | iw = ROUND_UP_TO(w, 8) / 8; |
| 1649 | while (ndwords--) { |
| 1650 | dat = 0; |
| 1651 | for (j = 0; j < 2; ++j) { |
| 1652 | for (i = 0; i < 2; ++i) { |
| 1653 | if (ix != iw || i == 0) |
| 1654 | dat |= cdat[iy*iw + ix++] << (i+j*2)*8; |
| 1655 | } |
| 1656 | if (ix == iw && iy != (h-1)) { |
| 1657 | ix = 0; |
| 1658 | ++iy; |
| 1659 | } |
| 1660 | } |
| 1661 | OUT_RING(dat); |
| 1662 | } |
| 1663 | if (pad) |
| 1664 | OUT_RING(MI_NOOP); |
| 1665 | ADVANCE_RING(); |
| 1666 | |
| 1667 | return 1; |
| 1668 | } |
| 1669 | |
| 1670 | /* HW cursor functions. */ |
| 1671 | void |
| 1672 | intelfbhw_cursor_init(struct intelfb_info *dinfo) |
| 1673 | { |
| 1674 | u32 tmp; |
| 1675 | |
| 1676 | #if VERBOSE > 0 |
| 1677 | DBG_MSG("intelfbhw_cursor_init\n"); |
| 1678 | #endif |
| 1679 | |
| 1680 | if (dinfo->mobile) { |
| 1681 | if (!dinfo->cursor.physical) |
| 1682 | return; |
| 1683 | tmp = INREG(CURSOR_A_CONTROL); |
| 1684 | tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE | |
| 1685 | CURSOR_MEM_TYPE_LOCAL | |
| 1686 | (1 << CURSOR_PIPE_SELECT_SHIFT)); |
| 1687 | tmp |= CURSOR_MODE_DISABLE; |
| 1688 | OUTREG(CURSOR_A_CONTROL, tmp); |
| 1689 | OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); |
| 1690 | } else { |
| 1691 | tmp = INREG(CURSOR_CONTROL); |
| 1692 | tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE | |
| 1693 | CURSOR_ENABLE | CURSOR_STRIDE_MASK); |
| 1694 | tmp = CURSOR_FORMAT_3C; |
| 1695 | OUTREG(CURSOR_CONTROL, tmp); |
| 1696 | OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12); |
| 1697 | tmp = (64 << CURSOR_SIZE_H_SHIFT) | |
| 1698 | (64 << CURSOR_SIZE_V_SHIFT); |
| 1699 | OUTREG(CURSOR_SIZE, tmp); |
| 1700 | } |
| 1701 | } |
| 1702 | |
| 1703 | void |
| 1704 | intelfbhw_cursor_hide(struct intelfb_info *dinfo) |
| 1705 | { |
| 1706 | u32 tmp; |
| 1707 | |
| 1708 | #if VERBOSE > 0 |
| 1709 | DBG_MSG("intelfbhw_cursor_hide\n"); |
| 1710 | #endif |
| 1711 | |
| 1712 | dinfo->cursor_on = 0; |
| 1713 | if (dinfo->mobile) { |
| 1714 | if (!dinfo->cursor.physical) |
| 1715 | return; |
| 1716 | tmp = INREG(CURSOR_A_CONTROL); |
| 1717 | tmp &= ~CURSOR_MODE_MASK; |
| 1718 | tmp |= CURSOR_MODE_DISABLE; |
| 1719 | OUTREG(CURSOR_A_CONTROL, tmp); |
| 1720 | /* Flush changes */ |
| 1721 | OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); |
| 1722 | } else { |
| 1723 | tmp = INREG(CURSOR_CONTROL); |
| 1724 | tmp &= ~CURSOR_ENABLE; |
| 1725 | OUTREG(CURSOR_CONTROL, tmp); |
| 1726 | } |
| 1727 | } |
| 1728 | |
| 1729 | void |
| 1730 | intelfbhw_cursor_show(struct intelfb_info *dinfo) |
| 1731 | { |
| 1732 | u32 tmp; |
| 1733 | |
| 1734 | #if VERBOSE > 0 |
| 1735 | DBG_MSG("intelfbhw_cursor_show\n"); |
| 1736 | #endif |
| 1737 | |
| 1738 | dinfo->cursor_on = 1; |
| 1739 | |
| 1740 | if (dinfo->cursor_blanked) |
| 1741 | return; |
| 1742 | |
| 1743 | if (dinfo->mobile) { |
| 1744 | if (!dinfo->cursor.physical) |
| 1745 | return; |
| 1746 | tmp = INREG(CURSOR_A_CONTROL); |
| 1747 | tmp &= ~CURSOR_MODE_MASK; |
| 1748 | tmp |= CURSOR_MODE_64_4C_AX; |
| 1749 | OUTREG(CURSOR_A_CONTROL, tmp); |
| 1750 | /* Flush changes */ |
| 1751 | OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); |
| 1752 | } else { |
| 1753 | tmp = INREG(CURSOR_CONTROL); |
| 1754 | tmp |= CURSOR_ENABLE; |
| 1755 | OUTREG(CURSOR_CONTROL, tmp); |
| 1756 | } |
| 1757 | } |
| 1758 | |
| 1759 | void |
| 1760 | intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y) |
| 1761 | { |
| 1762 | u32 tmp; |
| 1763 | |
| 1764 | #if VERBOSE > 0 |
| 1765 | DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y); |
| 1766 | #endif |
| 1767 | |
| 1768 | /* |
| 1769 | * Sets the position. The coordinates are assumed to already |
| 1770 | * have any offset adjusted. Assume that the cursor is never |
| 1771 | * completely off-screen, and that x, y are always >= 0. |
| 1772 | */ |
| 1773 | |
| 1774 | tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) | |
| 1775 | ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); |
| 1776 | OUTREG(CURSOR_A_POSITION, tmp); |
| 1777 | } |
| 1778 | |
| 1779 | void |
| 1780 | intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg) |
| 1781 | { |
| 1782 | #if VERBOSE > 0 |
| 1783 | DBG_MSG("intelfbhw_cursor_setcolor\n"); |
| 1784 | #endif |
| 1785 | |
| 1786 | OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK); |
| 1787 | OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK); |
| 1788 | OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK); |
| 1789 | OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK); |
| 1790 | } |
| 1791 | |
| 1792 | void |
| 1793 | intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height, |
| 1794 | u8 *data) |
| 1795 | { |
| 1796 | u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; |
| 1797 | int i, j, w = width / 8; |
| 1798 | int mod = width % 8, t_mask, d_mask; |
| 1799 | |
| 1800 | #if VERBOSE > 0 |
| 1801 | DBG_MSG("intelfbhw_cursor_load\n"); |
| 1802 | #endif |
| 1803 | |
| 1804 | if (!dinfo->cursor.virtual) |
| 1805 | return; |
| 1806 | |
| 1807 | t_mask = 0xff >> mod; |
| 1808 | d_mask = ~(0xff >> mod); |
| 1809 | for (i = height; i--; ) { |
| 1810 | for (j = 0; j < w; j++) { |
| 1811 | writeb(0x00, addr + j); |
| 1812 | writeb(*(data++), addr + j+8); |
| 1813 | } |
| 1814 | if (mod) { |
| 1815 | writeb(t_mask, addr + j); |
| 1816 | writeb(*(data++) & d_mask, addr + j+8); |
| 1817 | } |
| 1818 | addr += 16; |
| 1819 | } |
| 1820 | } |
| 1821 | |
| 1822 | void |
| 1823 | intelfbhw_cursor_reset(struct intelfb_info *dinfo) { |
| 1824 | u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; |
| 1825 | int i, j; |
| 1826 | |
| 1827 | #if VERBOSE > 0 |
| 1828 | DBG_MSG("intelfbhw_cursor_reset\n"); |
| 1829 | #endif |
| 1830 | |
| 1831 | if (!dinfo->cursor.virtual) |
| 1832 | return; |
| 1833 | |
| 1834 | for (i = 64; i--; ) { |
| 1835 | for (j = 0; j < 8; j++) { |
| 1836 | writeb(0xff, addr + j+0); |
| 1837 | writeb(0x00, addr + j+8); |
| 1838 | } |
| 1839 | addr += 16; |
| 1840 | } |
| 1841 | } |