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Zhou Yanjie6835ad52019-07-14 11:53:53 +08001Ingenic XBurst pin controller
Paul Cercueil8bd137d2017-05-12 18:52:54 +02002
3Please refer to pinctrl-bindings.txt in this directory for details of the
4common pinctrl bindings used by client devices, including the meaning of the
5phrase "pin configuration node".
6
Zhou Yanjie6835ad52019-07-14 11:53:53 +08007For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
Paul Cercueil8bd137d2017-05-12 18:52:54 +02008be used as GPIOs, multiplexed device functions are configured within the
9GPIO port configuration registers and it is typical to refer to pins using the
10naming scheme "PxN" where x is a character identifying the GPIO port with
11which the pin is associated and N is an integer from 0 to 31 identifying the
12pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
周琰杰 (Zhou Yanjie)8bc49f42019-12-16 00:21:03 +080013PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
14contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
15jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
Paul Cercueil8bd137d2017-05-12 18:52:54 +020016
17
18Required properties:
19--------------------
20
21 - compatible: One of:
22 - "ingenic,jz4740-pinctrl"
Paul Cercueil890e48b2018-08-21 18:42:29 +020023 - "ingenic,jz4725b-pinctrl"
Zhou Yanjied0d6d832019-07-14 11:53:51 +080024 - "ingenic,jz4760-pinctrl"
25 - "ingenic,jz4760b-pinctrl"
Paul Cercueil8bd137d2017-05-12 18:52:54 +020026 - "ingenic,jz4770-pinctrl"
27 - "ingenic,jz4780-pinctrl"
Zhou Yanjie6835ad52019-07-14 11:53:53 +080028 - "ingenic,x1000-pinctrl"
29 - "ingenic,x1000e-pinctrl"
Zhou Yanjie9b6084d2019-07-14 11:53:55 +080030 - "ingenic,x1500-pinctrl"
周琰杰 (Zhou Yanjie)8bc49f42019-12-16 00:21:03 +080031 - "ingenic,x1830-pinctrl"
Paul Cercueil8bd137d2017-05-12 18:52:54 +020032 - reg: Address range of the pinctrl registers.
33
34
Paul Cercueil890e48b2018-08-21 18:42:29 +020035Required properties for sub-nodes (GPIO chips):
36-----------------------------------------------
Paul Cercueil8bd137d2017-05-12 18:52:54 +020037
Paul Cercueil890e48b2018-08-21 18:42:29 +020038 - compatible: Must contain one of:
39 - "ingenic,jz4740-gpio"
Zhou Yanjied0d6d832019-07-14 11:53:51 +080040 - "ingenic,jz4760-gpio"
Paul Cercueil890e48b2018-08-21 18:42:29 +020041 - "ingenic,jz4770-gpio"
42 - "ingenic,jz4780-gpio"
Zhou Yanjie6835ad52019-07-14 11:53:53 +080043 - "ingenic,x1000-gpio"
周琰杰 (Zhou Yanjie)8bc49f42019-12-16 00:21:03 +080044 - "ingenic,x1830-gpio"
Paul Cercueil890e48b2018-08-21 18:42:29 +020045 - reg: The GPIO bank number.
46 - interrupt-controller: Marks the device node as an interrupt controller.
47 - interrupts: Interrupt specifier for the controllers interrupt.
48 - #interrupt-cells: Should be 2. Refer to
49 ../interrupt-controller/interrupts.txt for more details.
50 - gpio-controller: Marks the device node as a GPIO controller.
51 - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
52 cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
53 GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
54 - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
55 ../gpio/gpio.txt for more details.
Paul Cercueil8bd137d2017-05-12 18:52:54 +020056
57
58Example:
59--------
60
61pinctrl: pin-controller@10010000 {
62 compatible = "ingenic,jz4740-pinctrl";
63 reg = <0x10010000 0x400>;
Paul Cercueil890e48b2018-08-21 18:42:29 +020064 #address-cells = <1>;
65 #size-cells = <0>;
66
67 gpa: gpio@0 {
68 compatible = "ingenic,jz4740-gpio";
69 reg = <0>;
70
71 gpio-controller;
72 gpio-ranges = <&pinctrl 0 0 32>;
73 #gpio-cells = <2>;
74
75 interrupt-controller;
76 #interrupt-cells = <2>;
77
78 interrupt-parent = <&intc>;
79 interrupts = <28>;
80 };
Paul Cercueil8bd137d2017-05-12 18:52:54 +020081};