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review.shift-gmbh.com / SHIFTPHONES / kernel / common / ce804bf598b59427a2c930e5c1f5fe2e51f1b517 / . / arch / arm / boot / dts / imx6ul-pico-hobbit.dts
blob: 86f68faded0e8e1fac0e24867cd78bd8e5b30c1b [file] [log] [blame]
Fabio Estevam714c29e2016-04-27 01:00:21 -0300[diff] [blame]1/*
2 * Copyright 2015 Technexion Ltd.
3 *
4 * Author: Wig Cheng <wig.cheng@technexion.com>
5 * Richard Hu <richard.hu@technexion.com>
6 * Tapani Utriainen <tapani@technexion.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * version 2 as published by the Free Software Foundation.
16 *
17 * This file is distributed in the hope that it will be useful
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/dts-v1/;
47
48#include "imx6ul.dtsi"
49
50/ {
51 model = "Technexion Pico i.MX6UL Board";
52 compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul";
53
54 memory {
55 reg = <0x80000000 0x10000000>;
56 };
57
58 chosen {
59 stdout-path = &uart6;
60 };
61
62 backlight {
63 compatible = "pwm-backlight";
64 pwms = <&pwm3 0 5000000>;
65 brightness-levels = <0 4 8 16 32 64 128 255>;
66 default-brightness-level = <6>;
67 status = "okay";
68 };
69
70 reg_2p5v: regulator-2p5v {
71 compatible = "regulator-fixed";
72 regulator-name = "2P5V";
73 regulator-min-microvolt = <2500000>;
74 regulator-max-microvolt = <2500000>;
75 };
76
77 reg_3p3v: regulator-3p3v {
78 compatible = "regulator-fixed";
79 regulator-name = "3P3V";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 };
83
84 reg_sd1_vmmc: regulator-sd1-vmmc {
85 compatible = "regulator-fixed";
86 regulator-name = "VSD_3V3";
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
89 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
90 enable-active-high;
91 };
92
93 reg_usb_otg_vbus: regulator-usb-otg-vbus {
94 compatible = "regulator-fixed";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_usb_otg1>;
97 regulator-name = "usb_otg_vbus";
98 regulator-min-microvolt = <5000000>;
99 regulator-max-microvolt = <5000000>;
100 gpio = <&gpio1 6 0>;
101 };
102
103 sound {
104 compatible = "fsl,imx-audio-sgtl5000";
105 model = "imx6ul-sgtl5000";
106 audio-cpu = <&sai1>;
107 audio-codec = <&codec>;
108 audio-routing =
109 "LINE_IN", "Line In Jack",
110 "MIC_IN", "Mic Jack",
111 "Mic Jack", "Mic Bias",
112 "Headphone Jack", "HP_OUT";
113 };
114
115 sys_mclk: clock-sys-mclk {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <24576000>;
119 };
120
121 leds {
122 compatible = "gpio-leds";
123
124 hobbitled {
125 label = "hobbitled";
126 gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
127 };
128 };
129};
130
131&can1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_flexcan1>;
134 status = "okay";
135};
136
137&can2 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_flexcan2>;
140 status = "okay";
141};
142
143&clks {
144 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
145 assigned-clock-rates = <786432000>;
146};
147
148&fec2 {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_enet2>;
151 phy-mode = "rmii";
152 phy-handle = <&ethphy1>;
153 status = "okay";
Diego Dorta6b75a662016-06-15 13:34:41 -0300[diff] [blame]154 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
155 phy-reset-duration = <1>;
Fabio Estevam714c29e2016-04-27 01:00:21 -0300[diff] [blame]156
157 mdio {
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 ethphy1: ethernet-phy@1 {
162 compatible = "ethernet-phy-ieee802.3-c22";
163 reg = <1>;
164 max-speed = <100>;
165 interrupt-parent = <&gpio5>;
166 interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>;
167 };
168 };
169};
170
171&i2c1 {
172 clock-frequency = <100000>;
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c1>;
175 status = "okay";
176
177 pmic: pfuze3000@08 {
178 compatible = "fsl,pfuze3000";
179 reg = <0x08>;
180
181 regulators {
182 /* VDD_ARM_SOC_IN*/
183 sw1b_reg: sw1b {
184 regulator-min-microvolt = <700000>;
185 regulator-max-microvolt = <1475000>;
186 regulator-boot-on;
187 regulator-always-on;
188 regulator-ramp-delay = <6250>;
189 };
190
191 /* DRAM */
192 sw3a_reg: sw3 {
193 regulator-min-microvolt = <900000>;
194 regulator-max-microvolt = <1650000>;
195 regulator-boot-on;
196 regulator-always-on;
197 };
198
199 /* DRAM */
200 vref_reg: vrefddr {
201 regulator-boot-on;
202 regulator-always-on;
203 };
204 };
205 };
206};
207
208&i2c2 {
209 clock_frequency = <100000>;
210 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c2>;
212 status = "okay";
213
214 codec: sgtl5000@0a {
215 reg = <0x0a>;
216 compatible = "fsl,sgtl5000";
217 clocks = <&sys_mclk>;
218 VDDA-supply = <&reg_2p5v>;
219 VDDIO-supply = <&reg_3p3v>;
220 };
221};
222
223&i2c3 {
224 clock_frequency = <100000>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_i2c3>;
227 status = "okay";
228};
229
230&lcdif {
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
233 display = <&display0>;
234 status = "okay";
235
236 display0: display0 {
237 bits-per-pixel = <32>;
238 bus-width = <24>;
239
240 display-timings {
241 native-mode = <&timing0>;
242
243 timing0: timing0 {
244 clock-frequency = <33200000>;
245 hactive = <800>;
246 vactive = <480>;
247 hfront-porch = <210>;
248 hback-porch = <46>;
249 hsync-len = <1>;
250 vback-porch = <22>;
251 vfront-porch = <23>;
252 vsync-len = <1>;
253 hsync-active = <0>;
254 vsync-active = <0>;
255 de-active = <1>;
256 pixelclk-active = <0>;
257 };
258 };
259 };
260};
261
262&pwm3 {
263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_pwm3>;
265 status = "okay";
266};
267
268&pwm7 {
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_pwm7>;
271 status = "okay";
272};
273
274&pwm8 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_pwm8>;
277 status = "okay";
278};
279
280&sai1 {
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_sai1>;
283 status = "okay";
284};
285
286&uart3 {
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_uart3>;
Geert Uytterhoeven2e7c4162016-05-31 16:31:51 +0200[diff] [blame]289 uart-has-rtscts;
Fabio Estevam714c29e2016-04-27 01:00:21 -0300[diff] [blame]290 status = "okay";
291};
292
293&uart6 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_uart6>;
296 status = "okay";
297};
298
299&usbotg1 {
300 vbus-supply = <&reg_usb_otg_vbus>;
301 pinctrl-names = "default";
302 pinctrl-0 = <&pinctrl_usb_otg1_id>;
303 dr_mode = "otg";
304 disable-over-current;
305 status = "okay";
306};
307
308&usbotg2 {
309 dr_mode = "host";
310 disable-over-current;
311 status = "okay";
312};
313
314&usdhc1 {
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_usdhc1>;
317 bus-width = <8>;
318 no-1-8-v;
319 non-removable;
320 keep-power-in-suspend;
321 status = "okay";
322};
323
324&usdhc2 { /* Wifi SDIO */
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usdhc2>;
327 no-1-8-v;
328 keep-power-in-suspend;
329 wakeup-source;
330 status = "okay";
331};
332
333&iomuxc {
334 pinctrl_enet2: enet2grp {
335 fsl,pins = <
336 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
337 MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0
338 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
339 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
340 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
341 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
342 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
343 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
344 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
345 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
346 MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800
347 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79
348 >;
349 };
350
351 pinctrl_flexcan1: flexcan1grp {
352 fsl,pins = <
353 MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
354 MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
355 >;
356 };
357
358 pinctrl_flexcan2: flexcan2grp {
359 fsl,pins = <
360 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
361 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
362 >;
363 };
364
365 pinctrl_i2c1: i2c1grp {
366 fsl,pins = <
367 MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0
368 MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0
369 >;
370 };
371
372 pinctrl_i2c2: i2c2grp {
373 fsl,pins = <
374 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
375 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
376 >;
377 };
378
379 pinctrl_i2c3: i2c3grp {
380 fsl,pins = <
381 MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0
382 MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0
383 >;
384 };
385
386 pinctrl_lcdif_dat: lcdifdatgrp {
387 fsl,pins = <
388 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
389 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
390 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
391 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
392 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
393 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
394 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
395 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
396 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
397 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
398 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
399 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
400 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
401 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
402 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
403 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
404 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
405 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
406 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
407 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
408 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
409 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
410 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
411 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
412 >;
413 };
414
415 pinctrl_lcdif_ctrl: lcdifctrlgrp {
416 fsl,pins = <
417 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
418 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
419 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
420 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
421 /* LCD reset */
422 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
423 >;
424 };
425
426 pinctrl_pwm3: pwm3grp {
427 fsl,pins = <
428 MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0
429 >;
430 };
431
432 pinctrl_pwm7: pwm7grp {
433 fsl,pins = <
434 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0
435 >;
436 };
437
438 pinctrl_pwm8: pwm8grp {
439 fsl,pins = <
440 MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
441 >;
442 };
443
444 pinctrl_sai1: sai1grp {
445 fsl,pins = <
446 MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0
447 MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0
448 MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0
449 MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8
450 >;
451 };
452
453 pinctrl_uart3: uart3grp {
454 fsl,pins = <
455 MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
456 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
457 MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
458 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
459 >;
460 };
461
462 pinctrl_uart5: uart5grp {
463 fsl,pins = <
464 MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
465 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1
466 MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
467 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
468 >;
469 };
470
471 pinctrl_uart6: uart6grp {
472 fsl,pins = <
473 MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1
474 MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1
475 >;
476 };
477
478 pinctrl_usb_otg1: usbotg1grp {
479 fsl,pins = <
480 MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0
481 >;
482 };
483
484 pinctrl_usb_otg1_id: usbotg1idgrp {
485 fsl,pins = <
486 MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
487 >;
488 };
489
490 pinctrl_usdhc1: usdhc1grp {
491 fsl,pins = <
492 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
493 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
494 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
495 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
496 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
497 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
498 MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029
499 MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
500 MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
501 MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
502 MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
503 >;
504 };
505
506 pinctrl_usdhc2: usdhc2grp {
507 fsl,pins = <
508 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
509 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
510 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
511 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
512 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
513 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
514 >;
515 };
516};