Archit Taneja | acc58ca | 2016-06-13 19:37:37 +0530 | [diff] [blame] | 1 | Qualcomm adreno/snapdragon MDP4 display controller |
| 2 | |
| 3 | Description: |
| 4 | |
| 5 | This is the bindings documentation for the MDP4 display controller found in |
| 6 | SoCs like MSM8960, APQ8064 and MSM8660. |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 7 | |
| 8 | Required properties: |
| 9 | - compatible: |
Archit Taneja | d225256 | 2015-11-18 12:36:19 +0530 | [diff] [blame] | 10 | * "qcom,mdp4" - mdp4 |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 11 | - reg: Physical base address and length of the controller's registers. |
| 12 | - interrupts: The interrupt signal from the display controller. |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 13 | - clocks: device clocks |
| 14 | See ../clocks/clock-bindings.txt for details. |
Archit Taneja | d225256 | 2015-11-18 12:36:19 +0530 | [diff] [blame] | 15 | - clock-names: the following clocks are required. |
Archit Taneja | acc58ca | 2016-06-13 19:37:37 +0530 | [diff] [blame] | 16 | * "core_clk" |
| 17 | * "iface_clk" |
| 18 | * "bus_clk" |
| 19 | * "lut_clk" |
| 20 | * "hdmi_clk" |
| 21 | * "tv_clk" |
Archit Taneja | b137bb4 | 2016-06-14 17:47:26 +0530 | [diff] [blame] | 22 | - ports: contains the list of output ports from MDP. These connect to interfaces |
| 23 | that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a |
| 24 | special case since it is a part of the MDP block itself). |
| 25 | |
| 26 | Each output port contains an endpoint that describes how it is connected to an |
| 27 | external interface. These are described by the standard properties documented |
| 28 | here: |
| 29 | Documentation/devicetree/bindings/graph.txt |
| 30 | Documentation/devicetree/bindings/media/video-interfaces.txt |
| 31 | |
| 32 | The output port mappings are: |
| 33 | Port 0 -> LCDC/LVDS |
| 34 | Port 1 -> DSI1 Cmd/Video |
| 35 | Port 2 -> DSI2 Cmd/Video |
| 36 | Port 3 -> DTV |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 37 | |
| 38 | Optional properties: |
Stephane Viau | d40325b | 2015-09-15 08:41:47 -0400 | [diff] [blame] | 39 | - clock-names: the following clocks are optional: |
| 40 | * "lut_clk" |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 41 | |
| 42 | Example: |
| 43 | |
| 44 | / { |
| 45 | ... |
| 46 | |
Archit Taneja | b137bb4 | 2016-06-14 17:47:26 +0530 | [diff] [blame] | 47 | hdmi: hdmi@4a00000 { |
| 48 | ... |
| 49 | ports { |
| 50 | ... |
| 51 | port@0 { |
| 52 | reg = <0>; |
| 53 | hdmi_in: endpoint { |
| 54 | remote-endpoint = <&mdp_dtv_out>; |
| 55 | }; |
| 56 | }; |
| 57 | ... |
| 58 | }; |
| 59 | ... |
| 60 | }; |
| 61 | |
| 62 | ... |
| 63 | |
| 64 | mdp: mdp@5100000 { |
Archit Taneja | d225256 | 2015-11-18 12:36:19 +0530 | [diff] [blame] | 65 | compatible = "qcom,mdp4"; |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 66 | reg = <0x05100000 0xf0000>; |
| 67 | interrupts = <GIC_SPI 75 0>; |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 68 | clock-names = |
| 69 | "core_clk", |
| 70 | "iface_clk", |
| 71 | "lut_clk", |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 72 | "hdmi_clk", |
Archit Taneja | 1f23853 | 2016-06-10 12:01:58 +0530 | [diff] [blame] | 73 | "tv_clk"; |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 74 | clocks = |
Archit Taneja | 1f23853 | 2016-06-10 12:01:58 +0530 | [diff] [blame] | 75 | <&mmcc MDP_CLK>, |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 76 | <&mmcc MDP_AHB_CLK>, |
Archit Taneja | 1f23853 | 2016-06-10 12:01:58 +0530 | [diff] [blame] | 77 | <&mmcc MDP_AXI_CLK>, |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 78 | <&mmcc MDP_LUT_CLK>, |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 79 | <&mmcc HDMI_TV_CLK>, |
| 80 | <&mmcc MDP_TV_CLK>; |
Archit Taneja | b137bb4 | 2016-06-14 17:47:26 +0530 | [diff] [blame] | 81 | |
| 82 | ports { |
| 83 | #address-cells = <1>; |
| 84 | #size-cells = <0>; |
| 85 | |
| 86 | port@0 { |
| 87 | reg = <0>; |
| 88 | mdp_lvds_out: endpoint { |
| 89 | }; |
| 90 | }; |
| 91 | |
| 92 | port@1 { |
| 93 | reg = <1>; |
| 94 | mdp_dsi1_out: endpoint { |
| 95 | }; |
| 96 | }; |
| 97 | |
| 98 | port@2 { |
| 99 | reg = <2>; |
| 100 | mdp_dsi2_out: endpoint { |
| 101 | }; |
| 102 | }; |
| 103 | |
| 104 | port@3 { |
| 105 | reg = <3>; |
| 106 | mdp_dtv_out: endpoint { |
| 107 | remote-endpoint = <&hdmi_in>; |
| 108 | }; |
| 109 | }; |
| 110 | }; |
Rob Clark | 41e6977 | 2013-12-15 16:23:05 -0500 | [diff] [blame] | 111 | }; |
| 112 | }; |