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Archit Tanejaacc58ca2016-06-13 19:37:37 +05301Qualcomm adreno/snapdragon MDP4 display controller
2
3Description:
4
5This is the bindings documentation for the MDP4 display controller found in
6SoCs like MSM8960, APQ8064 and MSM8660.
Rob Clark41e69772013-12-15 16:23:05 -05007
8Required properties:
9- compatible:
Archit Tanejad2252562015-11-18 12:36:19 +053010 * "qcom,mdp4" - mdp4
Rob Clark41e69772013-12-15 16:23:05 -050011- reg: Physical base address and length of the controller's registers.
12- interrupts: The interrupt signal from the display controller.
Rob Clark41e69772013-12-15 16:23:05 -050013- clocks: device clocks
14 See ../clocks/clock-bindings.txt for details.
Archit Tanejad2252562015-11-18 12:36:19 +053015- clock-names: the following clocks are required.
Archit Tanejaacc58ca2016-06-13 19:37:37 +053016 * "core_clk"
17 * "iface_clk"
18 * "bus_clk"
19 * "lut_clk"
20 * "hdmi_clk"
21 * "tv_clk"
Archit Tanejab137bb42016-06-14 17:47:26 +053022- ports: contains the list of output ports from MDP. These connect to interfaces
23 that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
24 special case since it is a part of the MDP block itself).
25
26 Each output port contains an endpoint that describes how it is connected to an
27 external interface. These are described by the standard properties documented
28 here:
29 Documentation/devicetree/bindings/graph.txt
30 Documentation/devicetree/bindings/media/video-interfaces.txt
31
32 The output port mappings are:
33 Port 0 -> LCDC/LVDS
34 Port 1 -> DSI1 Cmd/Video
35 Port 2 -> DSI2 Cmd/Video
36 Port 3 -> DTV
Rob Clark41e69772013-12-15 16:23:05 -050037
38Optional properties:
Stephane Viaud40325b2015-09-15 08:41:47 -040039- clock-names: the following clocks are optional:
40 * "lut_clk"
Rob Clark41e69772013-12-15 16:23:05 -050041
42Example:
43
44/ {
45 ...
46
Archit Tanejab137bb42016-06-14 17:47:26 +053047 hdmi: hdmi@4a00000 {
48 ...
49 ports {
50 ...
51 port@0 {
52 reg = <0>;
53 hdmi_in: endpoint {
54 remote-endpoint = <&mdp_dtv_out>;
55 };
56 };
57 ...
58 };
59 ...
60 };
61
62 ...
63
64 mdp: mdp@5100000 {
Archit Tanejad2252562015-11-18 12:36:19 +053065 compatible = "qcom,mdp4";
Rob Clark41e69772013-12-15 16:23:05 -050066 reg = <0x05100000 0xf0000>;
67 interrupts = <GIC_SPI 75 0>;
Rob Clark41e69772013-12-15 16:23:05 -050068 clock-names =
69 "core_clk",
70 "iface_clk",
71 "lut_clk",
Rob Clark41e69772013-12-15 16:23:05 -050072 "hdmi_clk",
Archit Taneja1f238532016-06-10 12:01:58 +053073 "tv_clk";
Rob Clark41e69772013-12-15 16:23:05 -050074 clocks =
Archit Taneja1f238532016-06-10 12:01:58 +053075 <&mmcc MDP_CLK>,
Rob Clark41e69772013-12-15 16:23:05 -050076 <&mmcc MDP_AHB_CLK>,
Archit Taneja1f238532016-06-10 12:01:58 +053077 <&mmcc MDP_AXI_CLK>,
Rob Clark41e69772013-12-15 16:23:05 -050078 <&mmcc MDP_LUT_CLK>,
Rob Clark41e69772013-12-15 16:23:05 -050079 <&mmcc HDMI_TV_CLK>,
80 <&mmcc MDP_TV_CLK>;
Archit Tanejab137bb42016-06-14 17:47:26 +053081
82 ports {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 port@0 {
87 reg = <0>;
88 mdp_lvds_out: endpoint {
89 };
90 };
91
92 port@1 {
93 reg = <1>;
94 mdp_dsi1_out: endpoint {
95 };
96 };
97
98 port@2 {
99 reg = <2>;
100 mdp_dsi2_out: endpoint {
101 };
102 };
103
104 port@3 {
105 reg = <3>;
106 mdp_dtv_out: endpoint {
107 remote-endpoint = <&hdmi_in>;
108 };
109 };
110 };
Rob Clark41e69772013-12-15 16:23:05 -0500111 };
112};